Data processing method and device, equipment and storage medium

Abstract

The invention discloses a data processing method and device, equipment and a storage medium. The data processing method comprises the following steps: generating an original bit stream of an FPGA (Field Programmable Gate Array); carrying out lossless compression on the bit stream by adopting a compression algorithm to obtain a compressed bit stream; and storing the compressed bit stream. The data processing method and device, the equipment and the storage medium have the beneficial effects that the data processing method and device for reducing the occupation of the storage space are provided.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a data processing method, device, equipment and storage medium. Background Art

[0002] Currently, for SoC FPGAs that integrate a hard-core CPU, the process of saving and loading FPGA bitstream configurations from Flash is relatively complicated.

[0003] In particular, it will increase the occupancy of Flash and easily consume logic resources. Currently, no effective solution has been proposed for the above problems. Summary of the invention

[0004] The content of this application is used to introduce concepts in a brief form, which will be described in detail in the detailed implementation section below. The content of this application is not intended to identify the key features or essential features of the technical solution claimed for protection, nor is it intended to limit the scope of the technical solution claimed for protection.

[0005] Some embodiments of the present application propose methods, devices, electronic devices, and computer-readable media to solve the technical problems mentioned in the above background technology section.

[0006] As a first aspect of the present application, some embodiments of the present application provide a data processing method including: generating an original bit stream of an FPGA; using a compression algorithm to losslessly compress the bit stream to obtain a compressed bit stream; and storing the compressed bit stream.

[0007] Optionally, in some embodiments of the present application, the data processing method further includes: reading a compressed bit stream.

[0008] Optionally, in some embodiments of the present application, the data processing method further includes: using a decompression algorithm to losslessly decompress the compressed bit stream to obtain an original bit stream.

[0009] Optionally, in some embodiments of the present application, the data processing method further includes: loading the original bit stream into the FPGA.

[0010] Optionally, in some embodiments of the present application, storing the compressed bitstream includes: organizing the compressed bitstream and system image data.

[0011] Optionally, in some embodiments of the present application, storing the compressed bitstream further includes: storing the compressed bitstream and the system image data in different areas or partitions of the same Flash.

[0012] Optionally, in some embodiments of the present application, the system image data is stored in the Boot ROM area of ​​the Flash.

[0013] Optionally, in some embodiments of the present application, the data processing method further includes: searching for a boot loader based on system image data; initializing the system based on the boot loader; and searching for a storage location of a compressed bit stream after the system is initialized.

[0014] As a second aspect of the present application, some embodiments of the present application provide a data processing device, including: a generation module, used to generate the original bit stream of the FPGA; a compression module, which uses a compression algorithm to losslessly compress the bit stream to obtain a compressed bit stream; and a storage module, which stores the compressed bit stream.

[0015] As the third aspect of the present application, some embodiments of the present application provide an electronic device, comprising: one or more processors; a storage device on which one or more programs are stored, and when the one or more programs are executed by one or more processors, the one or more processors implement the method described in any implementation manner of the above-mentioned first aspect.

[0016] As a fourth aspect of the present application, some embodiments of the present application provide a computer-readable medium on which a computer program is stored, wherein when the program is executed by a processor, the method described in any implementation of the above-mentioned first aspect is implemented.

[0017] The beneficial effects of the present application are: providing a data processing method, device, equipment and storage medium that reduce storage space occupancy. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings constituting a part of this application are used to provide a further understanding of this application, so that other features, purposes and advantages of this application become more obvious. The illustrative embodiment drawings and their descriptions of this application are used to explain this application and do not constitute an improper limitation on this application.

[0019] In addition, throughout the drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and that the components and elements are not necessarily drawn to scale.

[0020] In the attached picture: Figure 1 is a schematic diagram of the main steps of a data processing method according to an embodiment of the present application; Figure 2 is a schematic diagram of the architecture of a data processing device according to an embodiment of the present application; Figure 3 It is a partial flow chart of a data processing method according to an embodiment of the present application; Figure 4 is another partial flow chart of a data processing method according to an embodiment of the present application; Figure 5 It is a structural schematic diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0021] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.

[0022] It should also be noted that, for ease of description, only the parts related to the invention are shown in the drawings. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other.

[0023] It should be noted that the concepts such as "first" and "second" mentioned in the present disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0024] It should be noted that the modifications of "one" and "plurality" mentioned in the present disclosure are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more".

[0025] The names of the messages or information exchanged between multiple devices in the embodiments of the present disclosure are only used for illustrative purposes and are not used to limit the scope of these messages or information.

[0026] The present disclosure will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0027] Reference Figure 1 As shown, the data processing method of the present application includes the following steps: S101: Generate an original bit stream of FPGA; S102: Using a compression algorithm to losslessly compress the bit stream to obtain a compressed bit stream; S103: Storing compressed bit stream The above solution can reduce storage space usage and reading time.

[0028] In some embodiments of the present application, step S103 specifically includes the following steps: organizing the compressed bitstream and the system image data; storing the compressed bitstream and the system image data in different areas or partitions of the same Flash, wherein the system image data is stored in the Boot ROM area of ​​the Flash.

[0029] In some embodiments of the present application, the data processing method of the present application also includes the following steps: searching for a boot loader based on system image data; initializing the system based on the boot loader; searching for the storage location of a compressed bit stream after the system is initialized; reading the compressed bit stream; using a decompression algorithm to losslessly decompress the compressed bit stream to obtain the original bit stream; and adding the original bit stream to the FPGA.

[0030] Reference Figure 3 and Figure 4 As shown, the specific scheme of the present application is described below in combination with embodiments and specific application scenarios.

[0031] Reference Figure 3 and Figure 4 As shown, the specific steps of the present application scheme when applied to a SoC FPGA integrated with a hard-core CPU are as follows: 1 Generate bitstream and system image: For this type of FPGA, in addition to generating the FPGA bitstream configuration file, you also need to generate an image file for the embedded system, including the CPU's operating system, startup code, application, etc. In this step, you need to compress the original bitstream data, define the compressed bitstream data as compressed bitstream, and define the original bitstream data before compression as raw bitstream data.

[0032] 2 Merge and partition: Organizing the FPGA bitstream (compressed bitstream) and system image in a specific format may require dividing them into different areas or partitions to be stored in the same Flash, such as the Boot ROM area for the boot loader, another area for the FPGA bitstream (compressed bitstream), and other areas for the operating system and application.

[0033] 3 Burn to Flash: Use specialized tools or processes to burn these files into different areas of the Flash. Usually, there will be specialized programming tools or firmware update tools that support this multi-partition burning.

[0034] 4 Power-on initialization and startup process: When the system is powered on, the hard-core CPU first starts to execute the built-in Boot ROM code (a part of the logic solidified inside the FPGA).

[0035] 5 The Boot ROM code is responsible for initializing the CPU and related hardware, and then finding and reading the pre-specified boot loader section in Flash.

[0036] The bootloader further initializes the system and identifies the location and format of the FPGA bitstream (compressed bitstream), and then loads the FPGA bitstream into the FPGA for configuration through the corresponding interface (such as SPI, AXI4 and other high-speed interfaces). In this step, the FPGA bitstream (compressed bitstream) is identified and then decompressed. As an optional solution, lossless compression and decompression can be used. The specific compression algorithm can use zip / rar / zlib and other similar compression algorithms.

[0037] 6. Security Verification: In advanced SoC FPGA designs, there is usually a security subsystem to ensure the secure loading of the bitstream, including encryption, signature verification and other steps to prevent illegal tampering.

[0038] 7 CPU takeover after configuration is complete: When the FPGA is successfully configured, the hard-core CPU continues to execute the subsequent startup sequence, loading the operating system and other application software to enable the entire system to operate normally.

[0039] If the FPGA bitstream is not compressed but directly stored in Flash, it will occupy a large space and take a long time to read.

[0040] The technical solution of the present application can greatly reduce the space occupied by the bit stream by storing compressed bit stream data; secondly, it can reduce the reading time, thereby saving expensive Flash space and providing better system initial startup response performance. In addition, the technical solution of the present application does not rely on FPGA decompression and does not consume logic resources; especially when selecting an algorithm with a high compression ratio, it only affects the time consumption of CPU decompression.

[0041] As shown in Reference 2, as the second aspect of the present application, the present application also provides a data processing device, including: a generation module, used to generate the original bit stream of the FPGA; a compression module, which uses a compression algorithm to losslessly compress the bit stream to obtain a compressed bit stream; and a storage module, which stores the compressed bit stream.

[0042] like Figure 5As shown, the electronic device 800 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 801, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 802 or a program loaded from a storage device 808 into a random access memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the electronic device 800 are also stored. The processing device 801, the ROM 802, and the RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0043] Typically, the following devices may be connected to the I / O interface 805: input devices 806 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; output devices 807 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; storage devices 808 including, for example, a magnetic tape, a hard disk, etc.; and communication devices 809. The communication device 809 may allow the electronic device 800 to communicate with other devices wirelessly or by wire to exchange data. Although Figure 5 The electronic device 800 is shown with various devices, but it should be understood that it is not required to implement or possess all the devices shown. More or fewer devices may be implemented or possessed instead. Figure 5 Each block shown in the figure may represent one device, or may represent multiple devices as required.

[0044] In particular, according to some embodiments of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, some embodiments of the present disclosure include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In some such embodiments, the computer program can be downloaded and installed from the network through the communication device 809, or installed from the storage device 808, or installed from the ROM 802. When the computer program is executed by the processing device 801, the above-mentioned functions defined in the method of some embodiments of the present disclosure are executed.

[0045] It should be noted that the computer-readable medium described above in some embodiments of the present disclosure may be a computer-readable signal medium or a computer-readable storage medium or any combination of the two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0046] In some embodiments of the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in combination with an instruction execution system, device, or device. In some embodiments of the present disclosure, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in combination with an instruction execution system, device, or device. The program code contained on the computer-readable medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0047] In some embodiments, the client and the server may communicate using any currently known or future developed network protocol such as HTTP (HyperTextTransferProtocol), and may be interconnected with any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network ("LAN"), a wide area network ("WAN"), an internet (e.g., the Internet), and a peer-to-peer network (e.g., an adhoc peer-to-peer network), as well as any currently known or future developed network.

[0048] The computer-readable medium may be included in the electronic device, or may exist independently without being installed in the electronic device. The computer-readable medium carries one or more programs. When the one or more programs are executed by the electronic device, the electronic device: generates the original bit stream of the FPGA; uses a compression algorithm to losslessly compress the bit stream to obtain a compressed bit stream; and stores the compressed bit stream.

[0049] Computer program code for performing the operations of some embodiments of the present disclosure may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0050] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram may represent a module, a program segment, or a part of a code, which contains one or more executable instructions for implementing a specified logical function.

[0051] It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures.

[0052] For example, two boxes shown in succession may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of boxes in the block diagram and / or flow chart, can be implemented by a dedicated hardware-based system that performs the specified function or operation, or can be implemented by a combination of dedicated hardware and computer instructions.

[0053] The units described in some embodiments of the present disclosure may be implemented by software or by hardware.

[0054] The functions described above herein may be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), and the like.

[0055] The above descriptions are only some preferred embodiments of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the embodiments of the present disclosure is not limited to the technical solutions formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above inventive concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in the embodiments of the present disclosure.

Claims

1. A data processing method, characterized in that: The data processing method comprises: Generate raw bitstream for FPGA; Using a compression algorithm to losslessly compress the bit stream to obtain a compressed bit stream; The compressed bit stream is stored.

2. The data processing method according to claim 1, characterized in that: The data processing method further includes: The compressed bit stream is read.

3. The data processing method according to claim 2, characterized in that: The data processing method further includes: The compressed bit stream is losslessly decompressed using a decompression algorithm to obtain the original bit stream.

4. The data processing method according to claim 3, characterized in that: The data processing method further includes: The raw bitstream is loaded into the FPGA.

5. The data processing method according to claim 3, characterized in that: in, The storing of the compressed bit stream comprises: The compressed bitstream and system image data are organized.

6. The data processing method according to any one of claims 1 to 4, characterized in that: in, The storing of the compressed bit stream further comprises: The compressed bit stream and the system image data are stored in different areas or partitions of the same Flash.

7. The data processing method according to claim 5, characterized in that: in, The system image data is stored in the Boot ROM area of ​​the Flash.

8. The data processing method according to claim 6, characterized in that: The data processing method further includes: searching for a boot loader based on the system image data; System initialization based on boot loader; The storage location of the compressed bit stream is searched after system initialization.

9. A data processing device, comprising: A generation module is used to generate the original bit stream of FPGA; A compression module, which uses a compression algorithm to perform lossless compression on the bit stream to obtain a compressed bit stream; A storage module stores the compressed bit stream.

10. An electronic device comprising: one or more processors; a storage device having one or more programs stored thereon; When the one or more programs are executed by the one or more processors, the processors implement the method according to any one of claims 1 to 7.

11. A computer readable medium having a computer program stored thereon, wherein: When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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