ASI receiving system based on FPGA device
By designing an ASI receiving system based on FPGA devices, and using multiple module combinations to realize the processing and recovery of ASI serial data streams, the problem of high cost of using the ASI receiving system in the prior art is solved, efficient and accurate data processing is achieved and design difficulty is reduced.
Patent Information
- Application Number
- CN202510086345.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-20
- Publication Date
- 2025-05-13
AI Technical Summary
In existing ASI receiving systems, the expensive CY7B933 decoding chip is used, resulting in high usage costs.
A ASI receiving system based on FPGA devices is designed, including an oversampling module, a change flag generation module, an asynchronous buffering module, a calculation module, a digital filtering module, a synchronous buffering module, a serial data recovery module and a byte alignment module. Through the combination of these modules, the accurate processing and recovery of ASI serial data stream is realized.
Accurate processing and recovery of ASI serial data streams is achieved, reducing the cost of use, and reducing the design difficulty and timing burden of FPGA devices through simple design logic.
Smart Images
Figure CN119996598A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of data processing, and in particular to an ASI receiving system based on FPGA devices. Background Art
[0002] ASI (Asynchronous Serial Interface) is a standard DVB interface commonly used in digital TV broadcasting. It is an asynchronous serial interface with a transmission code stream baud rate of 270Mbps. In digital TV broadcasting systems, CY7B933 is usually used as a decoding chip for the ASI receiving interface, but the chip is expensive and has high cost of use. Summary of the invention
[0003] In order to reduce costs, the present application provides an ASI receiving system based on FPGA devices.
[0004] The present application provides an ASI receiving system based on FPGA device, which adopts the following technical solution: An ASI receiving system based on FPGA device, comprising: an oversampling module, a change flag generating module, a first asynchronous buffer module, a calculating module, a synchronous buffer module, a serial data recovery module, and a byte alignment module; An oversampling module, used for converting the ASI serial data stream into parallel data P0[7:0] of a first preset bit width based on an ISERDESE resource; a change flag generating module, configured to receive the parallel data P0[7:0], use the parallel data P0[7:0] as a continuous serial data stream, generate parallel data P1[7:0] delayed by at least one beat based on the serial data stream, and simultaneously generate a change flag stream C1[7:0] synchronized with the parallel data P1[7:0]; A first asynchronous buffer module, used for converting the clock domain of the parallel data P1[7:0] and the change flag stream C1[7:0] to the clock domain clk_280m, and outputting the parallel data P2[7:0] and the change flag stream C2[7:0], and also used for outputting a PC2_VALID signal to mark whether the parallel data P2[7:0] and the change flag stream C2[7:0] are valid; A calculation module, used for calculating the duration T0[5:0] of different levels based on the change mark stream C2[7:0], converting the parallel data P2[7:0] into serial data S0 for output, and outputting a ST_VALID signal to mark whether the serial data S0 and the duration T0[5:0] are valid; A synchronous buffer module is used to receive and buffer the serial data S0 and the duration T0[5:0], output the corresponding serial data S2 and the duration T2[5:0], and output the ST2_VALID signal to mark whether the serial data S2 and the duration T2[5:0] are valid, and receive the ST_READY signal sent by the serial data recovery module to determine whether the serial data recovery module currently has the ability to receive the serial data S2 and the duration T2[5:0].
[0005] A serial data recovery module, used for recovering the baud rate of the serial data S2 to obtain serial data O, and marking whether the serial data O is valid using an O_VALID signal; The byte alignment module is used to find the K code in the serial data 0 to perform byte alignment, and convert it to obtain parallel data M with a second preset bit width.
[0006] By adopting the above technical solution and using FPGA devices, the ASI serial data stream can be accurately, efficiently and reliably processed. Compared with related technologies, the use cost is reduced, and the sampling is performed using ISERDESE resources with small errors; the overall design logic is simple, which reduces the design difficulty and the timing burden of FPGA devices.
[0007] Optionally, also include: A digital filtering module, which is arranged between the calculation module and the serial data recovery module, is used to filter out the level of the serial data S0 whose duration is less than the first preset period, integrate the duration T0[5:0], and output the serial data S1 and the duration T1[5:0] to the serial data recovery module.
[0008] By adopting the above technical solution, interference in the data transmission process is eliminated to make the signal more accurate.
[0009] Optionally, also include: The second asynchronous buffer module is used for converting the clock domain of the parallel data M, and converting the clock domain clk_280m into a customizable clock clk_user.
[0010] By adopting the above technical solution, it can be converted into a customizable clock to meet different needs, thereby improving applicability and facilitating development and use.
[0011] Optionally, also include: A decoding mapping module is used to convert the parallel data M of the second preset bit width into original data of the first preset bit width based on the encoding mapping table.
[0012] In summary, the present application includes at least one of the following beneficial technical effects: 1. Using FPGA devices, the ASI serial data stream can be accurately, efficiently and reliably processed. Compared with related technologies, the use cost is reduced, and the sampling is performed using ISERDESE resources, with small errors; the overall design logic is simple, reducing the design difficulty and the timing burden of FPGA devices. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] Figure 1 It is a block diagram showing the connection between modules of this embodiment.
[0014] Figure 2 is a schematic diagram showing oversampling in this embodiment.
[0015] Figure 3 It is a schematic diagram showing the generation of the change mark flow in this embodiment.
[0016] Figure 4 It is a schematic diagram showing the calculation module of the present embodiment for calculating the level duration.
[0017] Figure 5 It is a schematic diagram showing how the digital filter module of this embodiment filters out interference.
[0018] Figure 6 It is a schematic diagram showing the functions of the serial data recovery module of this embodiment.
[0019] Explanation of the accompanying drawings: 1. Oversampling module; 2. Change flag generation module; 3. First asynchronous buffer module; 4. Calculation module; 5. Digital filtering module; 6. Synchronous buffer module; 7. Serial data recovery module; 8. Byte alignment module; 9. Second asynchronous buffer module; 10. Decoding mapping module. DETAILED DESCRIPTION
[0020] The following is combined with Figure 1-6 This application is described in further detail.
[0021] The present application embodiment discloses an ASI receiving system based on FPGA device. Figure 1 An ASI receiving system based on FPGA device includes an oversampling module, a change flag generating module 2, a first asynchronous buffer module 3, a calculating module 4, a digital filtering module 5, a synchronous buffer module 6, a serial data recovery module 7, and a byte alignment module 8, and the above modules are connected in sequence.
[0022] Reference Figure 2The ASI serial data stream is an asynchronous signal with a baud rate of 270Mbps. First, the oversampling module 1 samples the ASI serial data stream. Specifically, the oversampling module 1 uses the ISERDESE resource to implement 1-8 serial-to-parallel conversion. The sampling clock frequency is 675MHz, and the sampling method is double-edge sampling, that is, a sampling rate of 1350MHz is achieved. Since the baud rate of the ASI serial data stream is 270Mbps, it is to achieve five times the frequency oversampling of the ASI serial data stream.
[0023] After sampling, the ASI serial data stream is converted into parallel data P0[7:0], and the bit width of the parallel data P0[7:0] is the first preset bit width. In this embodiment, the first preset bit width is 8 bits. The synchronous clock rate of the parallel data P0[7:0] is 1350 divided by 8, which is equal to 168.75 MHz, that is, the clock is clk_168d75.
[0024] During the sampling process, although the clock frequency is 675MHz, this clock frequency is only used to drive the ISERDESE resource, and is not used to drive other triggers, etc. Therefore, it does not burden the timing convergence of the FPGA device. In addition, since 5 times oversampling is adopted and the bit width of the output parallel data P0[7:0] is 8 bits, the parallel data P0[7:0] of each beat is not an integer multiple of the bit width of the ASI serial data stream. In this embodiment, the bit width of the ASI serial data stream is 5 bits.
[0025] Reference Figure 3 , the oversampling module 1 outputs the parallel data P0[7:0] to the change flag generation module 2. In the change flag generation module 2, for the parallel data P0[7:0], the lowest bit of the previous beat and the highest bit of the adjacent next beat are regarded as a continuous serial data stream, that is, the parallel data P0[7:0] are sorted in sequence to form a continuous data stream, that is, the change flag generation module 2 outputs the parallel data P1[7:0] delayed by at least one beat based on the parallel data P0[7:0]. In this embodiment, the case of delaying one beat is selected for description. Afterwards, the change flag generation module 2 generates a change flag stream C1[7:0], and the change flag stream C1[7:0] changes synchronously with the parallel data P1[7:0]. The change flag stream C1[7:0] is used to mark the changed bit, that is, the change flag stream C1[7:0] is used to indicate the bit change in the parallel data P1[7:0].
[0026] The first asynchronous buffer module 3 is used for clock domain conversion, which receives the change mark stream C1[7:0] and the parallel data P1[7:0], and converts the clock domain clk_168d75m of the change mark stream C1[7:0] and the parallel data P1[7:0] into the clock domain clk280m, thereby obtaining and outputting the corresponding change mark stream C2[7:0] and the parallel data P2[7:0]. The baud rate of the ASI serial data stream is 270Mbps. Since the clocks of the sending end and the receiving end of the ASI serial data stream are from different sources and the frequencies cannot be completely consistent, the synchronous clock frequency of the receiving end needs to be greater than 270Mbps to avoid buffer overflow on the data processing path. Therefore, the clock frequency selected in this embodiment is 280MHz, that is, the clock domain clk_280m.
[0027] At the same time, the first asynchronous buffer module 3 outputs a PC2_VALID signal for marking whether the change flag stream C2[7:0] and the parallel data P2[7:0] are valid.
[0028] Among them, the sending end is other data stream sources that can meet the ASI interface protocol, and the receiving end is the ASI receiving system based on FPGA devices disclosed in the embodiment of the present application.
[0029] Reference Figure 4 , the calculation module 4 is used to calculate the duration of different levels. In this embodiment, the calculation module 4 calculates the number of continuous cycles of the high level and the low level in the 5-fold oversampling result, that is, the duration T0[5:0] of the different levels is calculated based on the change mark stream C2[7:0]. At the same time, the calculation module 4 converts the parallel data P2[7:0] into serial data S0 and outputs it. The combination of serial data S0 and duration T0[5:0] can describe the waveform of a continuous serial signal. At the same time, the calculation module 4 outputs the STO_VALID signal to mark whether the serial data S0 and duration T0[5:0] are valid.
[0030] If the duration of a certain level exceeds the duration T0[5:0], it can be represented by multiple consecutive durations T0[5:0]. Specifically, the duration T0[5:0] is a 6-bit binary number, which represents a decimal value range of 0 to 63. Therefore, the maximum value of the duration T0[5:0] is 63. If the duration of a certain level exceeds 63, multiple cycles of T0[5:0] are required to represent it.
[0031] When the serial data S0 is at a low level, the duration T0[5:0] is 6'd5, indicating that the duration of the low level is 5 sampling cycles. When the serial data S0 is at a high level, the duration T0[5:0] is 6'd10, indicating that the duration of the high level is 10 sampling cycles.
[0032] Reference Figure 5 During data transmission, certain interference may occur due to the external environment or hardware conditions. In order to improve the anti-interference capability, a digital filter module 5 is provided in the system. The digital filter module 5 can filter out the level whose duration is less than the first preset period, that is, filter out the interference signal. Specifically, in the present embodiment, the first preset period is set to 3 sampling periods.
[0033] Figure 5 In the example, the serial data S0 contains a low level whose duration is less than the first preset period, that is, the duration T0[5:0] is the portion corresponding to 6'd2, so the digital filter module 5 is used to filter it out, thereby outputting more accurate serial data S1, and the duration T0[5:0] is re-integrated to output the duration T1[5:0]. At the same time, the ST1_VALID signal is used to mark whether the serial data S1 and the duration T1[5:0] are valid.
[0034] The synchronous buffer module 6 does not perform data conversion processing, but is only used for data buffering. That is, the serial data S1 and the duration T1[5:0] are transmitted to the synchronous buffer module 6, and the synchronous buffer module 6 buffers the serial data S1 and the duration T1[5:0], and then outputs the corresponding serial data S2 and the duration T2[5:0]. At the same time, the ST2_VALID signal is output to mark whether the serial data S2 and the duration T2[5:0] are valid.
[0035] In addition, the synchronous buffer module 6 is also used to receive the handshake signal sent by the serial data recovery module 7, that is, the serial data recovery module 7 sends a ST_READY signal to the synchronous buffer module 6, and the synchronous buffer module 6 determines whether the serial data recovery module 7 is currently ready to receive the serial data S2 and duration T2[5:0] based on the ST_READY signal.
[0036] Reference Figure 6 , the serial data S2 and the duration T2[5:0] are transmitted to the serial data recovery module 7, and the serial data recovery module 7 is used to recover the baud rate of the serial data S2 to obtain the serial data O. At the same time, the serial data recovery module 7 uses the O_VALID signal to mark whether the serial data O is valid.
[0037] Specifically, the serial data recovery module 7 is used to synchronize the serial data S2 and the duration T2[5:0] with the clock domain clk_280m, thereby obtaining the serial data O. In this embodiment, when the ST2_VALID signal and the ST2_READY signal are both at high levels, it indicates that one data exchange is completed.
[0038] The serial data O and the O_VALID signal are transmitted to the byte alignment module 8. The byte alignment module 8 searches for the K code based on the serial data SO and the O_VALID signal and performs byte alignment. After alignment, the data is converted from 1 to 10 serial to parallel, that is, the serial data is converted into parallel data with a bit width of 10 bits, that is, the serial data SO is converted into parallel data M with a second preset bit width. In this embodiment, the second preset bit width is 10 bits.
[0039] The system also includes a second asynchronous buffer module 9 and a decoding mapping module 10. The second asynchronous buffer module 9 is used for clock domain conversion, that is, for converting the clock domain clk_280m of the parallel data M into a customizable clock domain clk_user. The frequency of the clock domain clk_user can be customized according to the requirements. Regarding the value range of the frequency of the clock domain clk_user, the baud rate of the ASI serial data stream is 270Mbps, and every 10 bits corresponds to an 8-bit data. The reference clock frequency of the parallel data M outputted in the end is 270 divided by 10, which is equal to 27MHz. That is, when defining the frequency of clk_user, it only needs to be greater than 27MHz. When the frequency of clk_user is greater than 27MHz, there will be no overflow in the data path.
[0040] The decoding mapping module 10 maps and processes the coded data based on the coding mapping table and outputs it. It can map 10-bit coded data to 8-bit original data. There are 1024 combinations of 10-bit coded data. In the FPGA, a ROM with a depth of 1024 is instantiated, and each storage address is 8-bit wide, which is used to store the original data corresponding to the 10-bit code, so as to realize the decoding mapping. That is, the parallel data M output by the second asynchronous buffer module 9 is transmitted to the decoding mapping module 10 for decoding, so as to obtain the required original data.
[0041] Regarding the analysis of signal integrity, the baud rate of the ASI serial data stream is 270Mbps. In this embodiment, the ISERDESE resource is used to perform 5-fold frequency oversampling on the ASI serial data stream. Ideally, the data stream bit width is 5 sampling cycles, and in the 8B / 10B encoding method, generally, there are no more than 5 consecutive high or low levels in the ASI serial data stream. Only when the K code is K28.1, K28.5, or K28.7, there may be 5 consecutive high or low levels. Therefore, after the ASI serial data stream is oversampled, the duration of the high or low level may only be 5 / 10 / 15 / 20 / 25 sampling cycles, and only when K28.1, K28.5, or K28.7 is transmitted, the duration of 25 sampling cycles will occur.
[0042] Under non-ideal conditions, since the transmitter clock and the receiver clock are not from the same source and the ASI serial data stream is deformed during transmission, the duration of the high or low level after sampling is offset from the theoretical value of 5 / 10 / 15 / 20 / 25 sampling cycles.
[0043] Taking the theoretical value of 15 sampling cycles as an example, the duration of the high or low level after sampling is 14 / 16 sampling cycles, which is considered to be offset 1, and the duration of the high or low level after sampling is 13 / 17 sampling cycles, which is considered to be offset 2. In this way, the offset is the most direct parameter representing the signal integrity of the ASI serial data stream transmission path. The offset value ranges from 0 to 2. The smaller the offset, the better the signal integrity.
[0044] An offset of 0 is possible only under completely ideal conditions. Under normal circumstances, the offset value is 1. When the offset is 2, it indicates that the signal integrity of the transmission path is too poor and the hardware needs to be checked.
[0045] In this embodiment, the serial data recovery module also calculates the maximum value of the offset during the transmission process. When the user reads the calculated maximum value, the serial data recovery module calculates the maximum value of the next offset until the user reads the maximum value next time, that is, the above steps are repeated. The user can understand the signal integrity during the ASI serial data stream transmission process based on the read maximum value.
[0046] Using FPGA devices to receive ASI serial data streams reduces hardware costs compared to related technologies. Oversampling module 1 only requires two clocks, clk_675m and clk_168d75m, which has low demand for global clock resources and occupies less resources. Using ISERDESE resources for sampling has low error. The logic of each module is simple, which is convenient for FPGA hardware design and reduces the timing burden and logic design difficulty.
[0047] The implementation principle of an ASI receiving system based on an FPGA device in an embodiment of the present application is as follows: the reception of an ASI serial data stream is realized by an FPGA device, the ASI serial data stream is firstly oversampled by using an oversampling module 1, and then the parallel data P0[7:0] is converted and output to a change flag generation module 2. The change flag generation module 2 generates parallel data P1[7:0] delayed by at least one beat based on the parallel data P0[7:0], and simultaneously generates a change flag stream C1[7:0] synchronized with the parallel data P1[7:0]. The first asynchronous buffer module 3 converts the clock domains of the parallel data P1[7:0] and the change flag stream C1[7:0], thereby obtaining and outputting the corresponding change flag stream C2[7:0] and parallel data P2[7:0]. The calculation module 4 calculates the duration T0[5:0] of different levels based on the change mark stream C2[7:0], and converts the parallel data P2[7:0] into serial data S0. The digital filter module 5 is used to eliminate interference, thereby outputting accurate serial data S1, and integrating the duration T0[5:0] to output the duration T1[5:0]. The synchronization buffer module 6 buffers the data and outputs the serial data S2 and the duration T2[5:0]. The serial data recovery module 7 is used to recover the baud rate of the serial data S2 to obtain the serial data O. The byte alignment module 8 searches for the K code based on the serial data O and performs byte alignment. After alignment, the data is converted.
[0048] The above are all preferred embodiments of the present application, and the protection scope of the present application is not limited thereto. Therefore, any equivalent changes made according to the structure, shape, and principle of the present application should be included in the protection scope of the present application.
Claims
1. An ASI receiving system based on FPGA device, characterized in that: include: An oversampling module (1), a change flag generating module (2), a first asynchronous buffer module (3), a calculating module (4), a synchronous buffer module (6), a serial data recovery module (7), and a byte alignment module (8); An oversampling module (1) is used to convert an ASI serial data stream into parallel data P0[7:0] of a first preset bit width based on an ISERDESE resource; A change mark generation module (2) is used to receive the parallel data P0[7:0], use the parallel data P0[7:0] as a continuous serial data stream, generate parallel data P1[7:0] delayed by at least one beat based on the serial data stream, and simultaneously generate a change mark stream C1[7:0] synchronized with the parallel data P1[7:0]; A first asynchronous buffer module (3) is used to convert the clock domain of the parallel data P1[7:0] and the change mark stream C1[7:0] to the clock domain clk_280m, and output the parallel data P2[7:0] and the change mark stream C2[7:0], and is also used to output a PC2_VALID signal to mark whether the parallel data P2[7:0] and the change mark stream C2[7:0] are valid; A calculation module (4), used for calculating the duration T0[5:0] of different levels based on the change mark stream C2[7:0], converting the parallel data P2[7:0] into serial data S0 for output, and outputting a ST_VALID signal to mark whether the serial data S0 and the duration T0[5:0] are valid; The synchronous buffer module (6) is used to receive the serial data S0 and the duration T0[5:0] and perform buffering, output the corresponding serial data S2 and the duration T2[5:0], and output the ST2_VALID signal to mark whether the serial data S2 and the duration T2[5:0] are valid, and receive the ST_READY signal sent by the serial data recovery module (7) to determine whether the serial data recovery module (7) currently has the ability to receive the serial data S2 and the duration T2[5:0].
2. A serial data recovery module (7), used for recovering the baud rate of the serial data S2 to obtain serial data O, and marking whether the serial data O is valid using an O_VALID signal; The byte alignment module (8) is used to find the K code in the serial data 0 to perform byte alignment, and perform conversion to obtain parallel data M of a second preset bit width.
3. The ASI receiving system based on FPGA device according to claim 1, characterized in that: Also includes: A digital filtering module (5), the digital filtering module (5) being arranged between the calculation module (4) and the serial data recovery module (7), and being used for filtering out the level of the serial data S0 whose duration is less than a first preset period, integrating the duration T0[5:0], and outputting the serial data S1 and the duration T1[5:0] to the serial data recovery module (7).
4. The ASI receiving system based on FPGA device according to claim 1, characterized in that: Also includes: The second asynchronous buffer module (9) is used for converting the clock domain of the parallel data M, and converting the clock domain clk_280m into a customizable clock clk_user.
5. The ASI receiving system based on FPGA device according to claim 5, characterized in that: Also includes: A decoding mapping module (10) is used to convert the parallel data M of the second preset bit width into original data of the first preset bit width based on the encoding mapping table.