Self-adaptive SDI to HDMI interface based on low-power-consumption FPGA and method thereof

Abstract

The invention relates to a self-adaptive SDI-to-HDMI interface based on a low-power-consumption FPGA and a method thereof.The self-adaptive SDI-to-HDMI interface comprises an SDI interface, a cable equalizer, the FPGA, an HDMI driver and an AI chip, the SDI interface, the cable equalizer, the FPGA, the HDMI driver and the AI chip are connected in sequence, the SDI interface is used for inputting SDI signals, the cable equalizer is used for converting the SDI signals input by the SDI interface into differential signals, and the HDMI driver is used for outputting the differential signals. The FPGA is used for converting a differential signal output by the cable equalizer into an RGB signal; the HDMI driver is used for converting RGB signals of the FPGA into HDMI differential signals, and the AI chip is used for receiving the HDMI differential signals to complete input of external SDI signals. Based on the FPGA chip with low power consumption, SDI video signals are converted into HDMI signals, the HDMI signals are sent into the AI chip, video input of an SDI camera is achieved, and the AI chip reads the video signals.

Description

Technical Field

[0001] The present invention belongs to the technical field of low-power FPGA control, and in particular to an adaptive SDI to HDMI interface based on low-power FPGA and a method thereof. Background Art

[0002] With the development of AI technology, and the rapid development of artificial intelligence algorithms, artificial intelligence technology has greatly improved the performance of image recognition and target detection. AI intelligent algorithms learn target feature information from massive image data, extract target features in images, locate and classify them, and then achieve target detection. With the rise of smart driving and smart drones, edge computing devices equipped with smart target detection algorithms have gradually become a hot trend.

[0003] In modern equipment that focuses on informatization and intelligence, the integration of traditional computing systems and AI has become a trend in the development of computer technology. The target detection and recognition technology of unmanned equipment based on AI has become a key technology of the current computing system. The image acquisition interfaces of current edge computing devices are mainly SDI and Camera-Link interfaces, and AI chips do not directly lead out compatible interface pins. At present, the industry mainly uses FPGA as a communication bridge between the two, converting the SDI video interface into the external video interface of the AI ​​chip. Summary of the invention

[0004] The purpose of the present invention is to overcome the shortcomings of the prior art and propose an adaptive SDI to HDMI interface and method based on low-power FPGA. Based on the low-power FPGA chip, the SDI video signal is converted into an HDMI signal and sent to the AI ​​chip to realize the video input of the SDI camera and the reading of the video signal by the AI ​​chip.

[0005] The present invention solves the technical problem by adopting the following technical solutions:

[0006] The adaptive SDI to HDMI interface based on low-power FPGA includes an SDI interface, a cable equalizer, an FPGA, an HDMI driver and an AI chip, wherein the SDI interface, the cable equalizer, the FPGA, the HDMI driver and the AI ​​chip are connected in sequence, the SDI interface is used to input the SDI signal, the cable equalizer is used to convert the SDI signal input by the SDI interface into a differential signal, and the FPGA is used to convert the differential signal output by the cable equalizer into an RGB signal; the HDMI driver is used to convert the RGB signal of the FPGA into an HDMI differential signal, and the AI ​​chip is used to receive the HDMI differential signal to complete the input of the external SDI signal.

[0007] Moreover, the AI ​​chip uses RK3588 chip, the SDI interface uses BNC-75KYWH, and the FPGA chip uses JFMK50T4.

[0008] Moreover, the FPGA internally includes: a SMPTE SDI IP core, a YUV422 module, a YUV444 module and a RGB888 module, wherein the SMPTE SDI IP core, the YUV422 module, the YUV444 module and the RGB888 module are connected in sequence.

[0009] A working method of an adaptive SDI to HDMI interface based on a low-power FPGA, comprising the following steps:

[0010] Step 1: Input SDI signal to the cable equalizer through the SDI interface;

[0011] Step 2: The cable equalizer converts the SDI signal input from the SDI interface into a differential signal and inputs it to the FPGA;

[0012] Step 3, FPGA converts the differential signal output by the cable equalizer into RGB signal and inputs it to the HDMI driver;

[0013] Step 4: The HDMI driver converts the RGB signal of the FPGA into an HDMI differential signal and inputs it to the AI ​​chip to complete the input of the external SDI signal.

[0014] Moreover, the specific implementation method of step 2 is: after the SDI signal is processed by the equalizer, it is converted from serial data to a differential signal.

[0015] Moreover, the specific implementation method of step 3 is: after the differential signal is sent to the FPGA, it is parsed by the SDI IP core to parse out the video information, and after the video signal is converted into an RGB signal through the protocol, it is sent to the HDMI driver.

[0016] Moreover, the processing process of the FPGA is as follows: using the SMPTE SDI IP core to automatically identify the type of input video, and parse the SDI signal to complete the input of the adaptive SDI video signal; after the parsed data, according to the control timing of the rx_trs, rx_eav and rx_sav signals, the parsed video data is output; after obtaining the video data, the video signal is converted into YUV444 format data using the YUV422 module and the YUV444 module; the YUV444 format signal is converted into an RGB signal through the RGB888 module inside the FPGA, and output to the HDMI driver.

[0017] Moreover, the specific implementation method of step 4 is: after the HDMI driver receives the signal, the video signal is converted into an HDMI signal inside the chip, and the HDMI signal is sent to the AI ​​chip through the HDMI RX interface of the AI ​​chip.

[0018] The advantages and positive effects of the present invention are:

[0019] The present invention includes an SDI interface, a cable equalizer, an FPGA, an HDMI driver and an AI chip, wherein the SDI interface, the cable equalizer, the FPGA, the HDMI driver and the AI ​​chip are connected in sequence, the SDI interface is used to input an SDI signal, the cable equalizer is used to convert the SDI signal input by the SDI interface into a differential signal, and the FPGA is used to convert the differential signal output by the cable equalizer into an RGB signal; the HDMI driver is used to convert the RGB signal of the FPGA into an HDMI differential signal, and the AI ​​chip is used to receive the HDMI differential signal to complete the input of the external SDI signal. The present invention is based on a low-power FPGA chip to realize the conversion of SDI video signals into HDMI signals, and send them into the AI ​​chip, so as to realize the video input of the SDI camera and the reading of the video signal by the AI ​​chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a structural diagram of the adaptive SDI to HDMI interface based on low-power FPGA of the present invention;

[0021] Figure 2 This is a block diagram of the internal protocol conversion of the FPGA of the present invention. DETAILED DESCRIPTION

[0022] The present invention is further described in detail below with reference to the accompanying drawings.

[0023] Adaptive SDI to HDMI interface based on low power FPGA, such as Figure 1 As shown, it includes an SDI interface, a cable equalizer, an FPGA, an HDMI driver and an AI chip, wherein the SDI interface, the cable equalizer, the FPGA, the HDMI driver and the AI ​​chip are connected in sequence, the SDI interface is used to input the SDI signal, the cable equalizer is used to convert the SDI signal input by the SDI interface into a differential signal, and the FPGA is used to convert the differential signal output by the cable equalizer into an RGB signal; the HDMI driver is used to convert the RGB signal of the FPGA into an HDMI differential signal, and the AI ​​chip is used to receive the HDMI differential signal to complete the input of the external SDI signal.

[0024] The AI ​​chip uses Rockchip RK3588 chip, the SDI interface uses AVIC Optronics BNC-75KYWH, and the FPGA chip uses Fudan Microelectronics' JFMK50T4. Its size is only 19mm×19mm. While meeting the functional performance indicators, the power consumption is only about 2W.

[0025] like Figure 2 As shown, the FPGA includes: a SMPTE SDI IP core, a YUV422 module, a YUV444 module and a RGB888 module, wherein the SMPTE SDI IP core, the YUV422 module, the YUV444 module and the RGB888 module are connected in sequence.

[0026] A working method of an adaptive SDI to HDMI interface based on a low-power FPGA, comprising the following steps:

[0027] Step 1: Input the SDI signal to the cable equalizer via the SDI interface.

[0028] Step 2: The cable equalizer converts the SDI signal input from the SDI interface into a differential signal and inputs it to the FPGA.

[0029] The specific implementation method of step 2 is: after the SDI signal is processed by the equalizer, it is converted from serial data to a differential signal.

[0030] Step 3: FPGA converts the differential signal output by the cable equalizer into RGB signal and inputs it to the HDMI driver.

[0031] The specific implementation method of step 3 is as follows: after the differential signal is sent to the FPGA, it is parsed by the SDI IP core, the video information is parsed out, and the video signal is converted into an RGB signal through the protocol and sent to the HDMI driver.

[0032] like Figure 2 As shown, SDI signals can be divided into different levels such as SD-SDI, HD-SDI and 3G-SDI according to the transmission rate and video transmission quality. The present invention adopts HD-SDI (1080P@30Hz) video signal with a transmission rate of 1.485Gb / s. Using the SMPTE SDI IP core, the type of input video can be automatically identified, and the SDI signal can be parsed to complete the input of the adaptive SDI video signal. The parsed data is output according to the control timing of signals such as rx_trs, rx_eav, and rx_sav.

[0033] After acquiring the video data, the YUV422 module and YUV444 module are used to convert the video signal into data in YUV444 format. Due to the internal clock rate of the FPGA, the 1080P HDMI signal conversion cannot be completed directly inside the FPGA. Therefore, the YUV444 format signal is converted into RGB signal through the RGB888 module inside the FPGA and output to the HDMI driver. After the HDMI driver completes the HDMI signal format conversion, it is transmitted to the subsequent AI chip.

[0034] Step 4: The HDMI driver converts the RGB signal of the FPGA into an HDMI differential signal and inputs it to the AI ​​chip to complete the input of the external SDI signal.

[0035] The specific implementation method of step 4 is as follows: after the HDMI driver receives the signal, it converts the video signal into an HDMI signal inside the chip, and sends the HDMI signal to the AI ​​chip through the HDMI RX interface of the AI ​​chip.

[0036] According to the above-mentioned adaptive SDI to HDMI interface based on low-power FPGA and method thereof, it is constructed according to its interface structure, and system testing is performed according to its working method to verify the effect of the present invention.

[0037] After the program debugging is completed, the FPGA program is solidified into the configuration SPI FLASH through the bin file. After the hardware platform is powered on, the FPGA will automatically load the data in the FLASH to complete the above protocol conversion process. At this time, you can connect an external SDI camera and see the video data content transmitted by the SDI camera in the on-chip operating system interface of the AI ​​chip.

[0038] The present invention includes an SDI interface, a cable equalizer, an FPGA, an HDMI driver and an AI chip, wherein the SDI interface, the cable equalizer, the FPGA, the HDMI driver and the AI ​​chip are connected in sequence, the SDI interface is used to input an SDI signal, the cable equalizer is used to convert the SDI signal input by the SDI interface into a differential signal, and the FPGA is used to convert the differential signal output by the cable equalizer into an RGB signal; the HDMI driver is used to convert the RGB signal of the FPGA into an HDMI differential signal, and the AI ​​chip is used to receive the HDMI differential signal to complete the input of the external SDI signal. The present invention is based on a low-power FPGA chip to realize the conversion of SDI video signals into HDMI signals, and send them into the AI ​​chip, so as to realize the video input of the SDI camera and the reading of the video signal by the AI ​​chip.

[0039] It should be emphasized that the embodiments described in the present invention are illustrative rather than restrictive. Therefore, the present invention includes but is not limited to the embodiments described in the specific implementation manner. Any other implementation manners derived by those skilled in the art based on the technical solution of the present invention also fall within the scope of protection of the present invention.

Claims

1. Adaptive SDI to HDMI interface based on low power FPGA, featuring: It includes an SDI interface, a cable equalizer, an FPGA, an HDMI driver and an AI chip, wherein the SDI interface, the cable equalizer, the FPGA, the HDMI driver and the AI ​​chip are connected in sequence, the SDI interface is used to input the SDI signal, the cable equalizer is used to convert the SDI signal input by the SDI interface into a differential signal, and the FPGA is used to convert the differential signal output by the cable equalizer into an RGB signal; the HDMI driver is used to convert the RGB signal of the FPGA into an HDMI differential signal, and the AI ​​chip is used to receive the HDMI differential signal to complete the input of the external SDI signal.

2. The low-power FPGA-based adaptive SDI-to-HDMI interface according to claim 1, characterized in that: The AI ​​chip uses RK3588 chip, the SDI interface uses BNC-75KYWH, and the FPGA chip uses JFMK50T4.

3. The low-power FPGA-based adaptive SDI-to-HDMI interface according to claim 1, characterized in that: The FPGA internally comprises: a SMPTE SDI IP core, a YUV422 module, a YUV444 module and a RGB888 module, wherein the SMPTE SDI IP core, the YUV422 module, the YUV444 module and the RGB888 module are connected in sequence.

4. A working method of an adaptive SDI to HDMI interface based on a low-power FPGA according to any one of claims 1 to 3, characterized in that: The following steps are involved: Step 1: Input SDI signal to the cable equalizer through the SDI interface; Step 2: The cable equalizer converts the SDI signal input from the SDI interface into a differential signal and inputs it to the FPGA; Step 3, FPGA converts the differential signal output by the cable equalizer into RGB signal and inputs it to the HDMI driver; Step 4: The HDMI driver converts the RGB signal of the FPGA into an HDMI differential signal and inputs it to the AI ​​chip to complete the input of the external SDI signal.

5. The method for using the adaptive SDI to HDMI interface based on low power consumption FPGA according to claim 4, characterized in that: The specific implementation method of step 2 is: after the SDI signal is processed by the equalizer, it is converted from serial data to a differential signal.

6. The method for using the low-power FPGA-based adaptive SDI to HDMI interface according to claim 4, characterized in that: The specific implementation method of step 3 is as follows: after the differential signal is sent to the FPGA, it is parsed by the SDI IP core to parse out the video information, and after the video signal is converted into an RGB signal through the protocol, it is sent to the HDMI driver.

7. The method for using the adaptive SDI to HDMI interface based on low power consumption FPGA according to claim 6, characterized in that: The processing process of the FPGA is as follows: using the SMPTE SDI IP core to automatically identify the type of input video, and parse the SDI signal to complete the input of the adaptive SDI video signal; after the parsed data, according to the control timing of the rx_trs, rx_eav and rx_sav signals, the parsed video data is output; after obtaining the video data, the video signal is converted into YUV444 format data using the YUV422 module and the YUV444 module; the YUV444 format signal is converted into RGB signal through the RGB888 module inside the FPGA, and output to the HDMI driver.

8. The method for using the adaptive SDI to HDMI interface based on low power consumption FPGA according to claim 4, characterized in that: The specific implementation method of step 4 is: after the HDMI driver receives the signal, the video signal is converted into an HDMI signal inside the chip, and the HDMI signal is sent to the AI ​​chip through the HDMI RX interface of the AI ​​chip.

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