Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a manufacturing method of the semiconductor device. A semiconductor device according to one embodiment of the present disclosure includes: an upper line including an opening; a lower line located below the upper line and overlapping the opening in the first direction; and an auxiliary line located below the lower line and overlapping the opening in the first direction, where the auxiliary line contacts a lower surface of the lower line.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate generally to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly, to a semiconductor device including a wire structure and a method of manufacturing the semiconductor device. Background Art

[0002] The semiconductor device may include a nonvolatile memory device in which stored data is retained even when power is interrupted. The nonvolatile memory device may be classified into a two-dimensional structure or a three-dimensional structure according to a structure in which memory cells are arranged. The memory cells of the nonvolatile memory device having a two-dimensional structure may be arranged in a single layer on a substrate, and the memory cells of the nonvolatile memory device having a three-dimensional structure may be stacked in a vertical direction on the substrate. Since the integration degree of the nonvolatile memory device having a three-dimensional structure is higher than that of the nonvolatile memory device having a two-dimensional structure, electronic devices using the nonvolatile memory device having a three-dimensional structure have recently increased.

[0003] A semiconductor device may include a wire structure that performs various functions such as applying an electrical signal to a memory cell or supplying power to a peripheral circuit. Summary of the invention

[0004] According to one embodiment, a semiconductor device may include: an upper line, the upper line including an opening; a lower line, the lower line is located below the upper line and overlaps with the opening along a first direction; and an auxiliary line, the auxiliary line is located below the lower line and overlaps with the opening along the first direction, wherein the auxiliary line contacts a lower surface of the lower line.

[0005] According to one embodiment, a method for manufacturing a semiconductor device may include the following steps: forming a lower line; forming an auxiliary line below the lower line, the auxiliary line contacting a portion of a lower surface of the lower line; forming an upper line above the lower line; and forming an opening by etching a portion of the upper line, the opening overlapping the lower line and the auxiliary line. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a diagram illustrating a semiconductor device according to one embodiment of the present disclosure;

[0007] Figure 2A and Figure 2B is a diagram illustrating a structure of a semiconductor device including a wire structure according to an embodiment of the present disclosure;

[0008] Figures 3A to 3G is a diagram illustrating a method of manufacturing a semiconductor device including a wire structure according to an embodiment of the present disclosure;

[0009] Figure 4 and Figure 5 are diagrams illustrating various examples of a semiconductor device including a wire structure according to an embodiment of the present disclosure;

[0010] Figure 6 is a diagram illustrating a memory card system to which a memory device according to an embodiment of the present disclosure is applied; and

[0011] Figure 7 is a diagram illustrating a solid state drive (SSD) system to which a memory device according to an embodiment of the present disclosure is applied. DETAILED DESCRIPTION

[0012] The specific structural or functional descriptions disclosed herein are merely exemplified for the purpose of describing the embodiments of the concepts according to the present disclosure. The embodiments of the concepts according to the present disclosure may be implemented in various forms and should not be construed as limited to the specific embodiments set forth herein.

[0013] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical spirit of the present disclosure.

[0014] Various embodiments relate to a semiconductor device capable of reducing defects in a line structure and a method of manufacturing the semiconductor device.

[0015] Figure 1 is a diagram illustrating a semiconductor device according to one embodiment of the present disclosure.

[0016] In the present disclosure, the semiconductor device may be a memory device 100. Figures 1 to 7 , the description may be made under the assumption that the semiconductor device is the memory device 100. However, including the following Figure 2A , Figure 2B as well as Figures 3A to 3G The semiconductor device featuring the line structure described in the drawings may be a non-memory device.

[0017] Reference Figure 1 , the memory device 100 may include a memory cell array 110 , a peripheral circuit 170 , and a control circuit 180 .

[0018] The memory cell array 110 may include first to i-th memory blocks BLK1 to BLKi. Each of the first to i-th memory blocks BLK1 to BLKi may include a memory cell capable of storing data. A drain select line DSL, a word line WL, a source select line SSL, and a source line SL may be coupled to each of the first to i-th memory blocks BLK1 to BLKi, and a bit line BL may be commonly coupled to the first to i-th memory blocks BLK1 to BLKi.

[0019] The first to i-th memory blocks BLK1 to BLKi may be formed in a two-dimensional structure or a three-dimensional structure. A memory block having a two-dimensional structure may include memory cells arranged in a single layer on a substrate. A memory block having a three-dimensional structure may include memory cells stacked in a vertical direction on a substrate.

[0020] The memory cell can store one or two or more bits of data according to the programming method. For example, a method in which one bit of data is stored in one memory cell is called a single-level cell (SLC) method, and a method in which two bits of data are stored in one memory cell is called a multi-level cell (MLC) method. A method in which three bits of data are stored in one memory cell is called a three-level cell (TLC) method, and a method in which four bits of data are stored in one memory cell is called a quad-level cell (QLC) method. In addition, five or more bits of data can be stored in one memory cell.

[0021] The peripheral circuit 170 may be configured to perform a program operation for storing data, a read operation for outputting data stored in the memory cell array 110, and an erase operation for erasing data stored in the memory cell array 110. For example, the peripheral circuit 170 may include a voltage generator 120, a row decoder 130, a page buffer group 140, a column decoder 150, and an input / output circuit 160.

[0022] The voltage generator 120 may generate various operation voltages Vop for a programming operation, a reading operation, or an erasing operation in response to the operation code OPCD. For example, the voltage generator 120 may be configured to generate a programming voltage, a turn-on voltage, a turn-off voltage, a negative voltage, a precharge voltage, a verification voltage, a read voltage, a pass voltage, or an erase voltage in response to the operation code OPCD. The operation voltage Vop generated by the voltage generator 120 may be applied to the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL of the selected memory block through the row decoder 130.

[0023] The programming voltage may be applied to a selected word line among the word lines WL during a programming operation, and may be used to increase the threshold voltage of a memory cell coupled to the selected word line. A turn-on voltage may be applied to a drain select line DSL or a source select line SSL, and may be used to turn on a drain select transistor or a source select transistor. A cut-off voltage may be applied to a drain select line DSL or a source select line SSL, and may be used to turn off a drain select transistor or a source select transistor. For example, the cut-off voltage may be set to 0V. The precharge voltage may be higher than 0V and may be applied to a bit line during a read operation. A verification voltage may be used during a verification operation to determine whether the threshold voltage of a selected memory cell has been increased to a target level. The verification voltage may be set to various levels according to the target level, and may be applied to a selected word line.

[0024] The read voltage may be applied to the selected word line during a read operation of the selected memory cell. For example, the read voltage may be set to various levels according to the programming method of the selected memory cell. The pass voltage may be applied to an unselected word line among the word lines WL during a programming operation or a read operation, and may be used to turn on the memory cells connected to the unselected word lines. The erase voltage may be used during an erase operation for erasing the memory cells included in the selected memory block, and may be applied to the source line SL.

[0025] The row decoder 130 may be configured to transmit the operation voltage Vop to the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL coupled to the selected memory block according to the row address RADD. For example, the row decoder 130 may be coupled to the voltage generator 120 through the global line, and may be coupled to the first memory block BLK1 to the i-th memory block BLKi through the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL.

[0026] The page buffer group 140 may include page buffers (not shown) respectively coupled to the first to i-th memory blocks BLK1 to BLKi. Each of the page buffers (not shown) may be coupled to the first to i-th memory blocks BLK1 to BLKi through a bit line BL. During a read operation, the page buffer (not shown) may sense a current or voltage of the bit line BL that varies according to a threshold voltage of a selected memory cell, and may temporarily store the sensed data in response to a page buffer control signal PBSIG.

[0027] The column decoder 150 may be configured to transmit data between the page buffer group 140 and the input / output circuit 160 in response to the column address CADD. For example, the column decoder 150 may be coupled to the page buffer group 140 through the column line CL, and may transmit an enable signal through the column line CL. A page buffer (not shown) included in the page buffer group 140 may receive or output data through the data line DL in response to the enable signal.

[0028] The input / output circuit 160 may be configured to receive or output a command CMD, an address ADD, or data through an input / output line I / O. For example, the input / output circuit 160 may transmit a command CMD and an address ADD received from an external controller to the control circuit 180 through the input / output line I / O, and may transmit data received from the external controller to the page buffer group 140 through the input / output line I / O. Alternatively, the input / output circuit 160 may output data transmitted from the page buffer group 140 to the external controller through the input / output line I / O.

[0029] The control circuit 180 may output at least one of an operation code OPCD, a row address RADD, a page buffer control signal PBSIG, and a column address CADD in response to a command CMD and an address ADD. For example, when the command CMD input to the control circuit 180 corresponds to a program operation, the control circuit 180 may control the peripheral circuit 170 to perform a program operation of a storage block selected by the address ADD. When the command CMD input to the control circuit 180 corresponds to a read operation, the control circuit 180 may control the peripheral circuit 170 to perform a read operation of a storage block selected by the address ADD and output read data. When the command CMD input to the control circuit 180 corresponds to an erase operation, the control circuit 180 may control the peripheral circuit 170 to perform an erase operation of a selected storage block.

[0030] Figure 2A and Figure 2B is a diagram illustrating a structure of a semiconductor device including a wire structure according to an embodiment of the present disclosure.

[0031] In the present disclosure, a semiconductor device (eg, Figure 1 The memory device 100 of the present invention may include an upper line structure ULS and a lower line structure LLS. The upper line structure ULS and the lower line structure LLS may be formed on a semiconductor device (eg, Figure 1 The upper line structure ULS and the lower line structure LLS may be connected to Figure 1At least one of the memory cell array 110, the peripheral circuit 170, and the control circuit 180. For example, the upper line structure ULS and the lower line structure LLS may transmit an electrical signal applied from the peripheral circuit 170 to at least one memory cell included in the memory cell array 110. Alternatively, the upper line structure ULS and the lower line structure LLS may be used to supply power to the peripheral circuit 170. Alternatively, the upper line structure ULS and the lower line structure LLS may electrically connect the peripheral circuit 170 to the control circuit 180. In addition, the upper line structure ULS and the lower line structure LLS may be used to perform various functions. Hereinafter, the structure of the upper line structure ULS and the lower line structure LLS included in the semiconductor device according to the present disclosure will be described.

[0032] Reference Figure 2A , the semiconductor device may include an upper line structure ULS and a lower line structure LLS. The upper line structure ULS may be located on the lower line structure LLS. The upper line structure ULS may be exposed to the uppermost portion of the semiconductor device or may be located within a predetermined distance from the uppermost portion of the semiconductor device. The lower line structure LLS may be located below the upper line structure ULS and may contact the upper line structure ULS.

[0033] The upper line structure ULS may include an upper line UL. The upper line structure ULS may further include an upper plug UP. The lower line structure LLS may include a lower line LL and an auxiliary line AL. The lower line structure LLS may further include a lower plug LP. The lower plug LP may contact a target plug PL. The target plug PL may be coupled to Figure 1 The peripheral circuit contact plug of the peripheral circuit 170 shown. The upper line structure ULS, the lower line structure LLS and the target plug PL may be electrically connected to each other. The upper line structure ULS, the lower line structure LLS and the target plug PL may contact the insulating layer IL. For example, at least a portion of the upper line structure ULS may be formed in the insulating layer IL. In addition, the lower line structure LLS may be formed in the insulating layer IL.

[0034] The upper line UL may include an opening OP. The opening OP may be a region of the upper line UL from which a portion is removed. The opening OP may be filled with the insulating layer IL.

[0035] The upper plug UP may protrude downward from the upper line UL. The upper plug UP may contact the lower line LL. For example, the upper plug UP may contact an upper surface of the lower line LL. The upper plug UP may electrically couple the upper line UL to the lower line LL.

[0036] The upper line UL and the upper plug UP may be formed integrally and simultaneously. For example, the upper line UL and the upper plug UP may be formed by a damascene process. The upper line UL and the upper plug UP may include the same material. For example, the upper line UL and the upper plug UP may include aluminum (Al).

[0037] The lower line LL may overlap the opening OP of the upper line UL. The lower line LL may include a region overlapping the opening OP. A portion of the lower line LL may overlap the opening OP.

[0038] The auxiliary line AL may overlap with the opening OP of the upper line UL. The auxiliary line AL may include an area overlapping with the opening OP. A portion of the auxiliary line AL may overlap with the opening OP. For example, the plane area of ​​the auxiliary line AL may be larger than the plane area of ​​the opening OP in the upper line UL. In another example, the width of the auxiliary line AL (e.g., the width in the X direction and the width in the Y direction) may be larger than the width of the opening OP in the upper line UL (e.g., the width in the X direction and the width in the Y direction).

[0039] The auxiliary line AL may contact the lower surface of the lower line LL. For example, the auxiliary line AL may contact a portion of the lower surface of the lower line LL. The lower line LL may include an area overlapping the auxiliary line AL. For example, a portion of the lower line LL may overlap the auxiliary line AL.

[0040] The lower plug LP may protrude downward from the lower line LL. The lower plug LP may contact the target plug PL. For example, the lower plug LP may contact the upper surface of the target plug PL. The lower plug LP may electrically couple the lower line LL to the target plug PL.

[0041] The auxiliary line AL and the lower plug LP may be located below the lower line LL (e.g., in a direction opposite to the Z direction). For example, the auxiliary line AL and the lower plug LP may be located at the same height (e.g., position on the Z axis). The auxiliary line AL and the lower plug LP may have the same depth or may have different depths.

[0042] The lower line LL, the auxiliary line AL, and the lower plug LP may be formed integrally and simultaneously. For example, the lower line LL, the auxiliary line AL, and the lower plug LP may be formed by a damascene process. The lower line LL, the auxiliary line AL, and the lower plug LP may include the same material. For example, the lower line LL, the auxiliary line AL, and the lower plug LP may include copper (Cu).

[0043] Reference Figure 2A, the upper plug UP and the lower plug LP may be located on opposite sides of the auxiliary line AL along the X direction. That is, the auxiliary line AL may be located between the upper plug UP and the lower plug LP along the X direction. For example, the upper plug UP may be formed from the auxiliary line AL in the +X direction, and the lower plug LP may be formed from the auxiliary line AL in the -X direction.

[0044] Therefore, the auxiliary line AL and the lower line LL may form a current path together. For example, an electrical signal applied from the upper line UL may be transmitted to the lower line LL and the auxiliary line AL through the upper plug UP. In addition, the electrical signal transmitted to the lower line LL and the auxiliary line AL may be transmitted to the target plug PL through the lower plug LP. In another example, the electrical signal applied from the target plug PL may be transmitted to the lower line LL and the auxiliary line AL through the lower plug LP. In addition, the electrical signal transmitted to the lower line LL and the auxiliary line AL may be transmitted to the upper line UL through the upper plug UP.

[0045] Figure 2B A bypass (BP) formed in a lower line structure LLS when a defect occurs during operation of a semiconductor device is shown. When the semiconductor device is operating, a defect may occur in a first region MG of the lower line LL. The first region MG may overlap with an opening OP of an upper line UL. For example, the first region MG may include a region overlapping with the opening OP.

[0046] At least a portion of the first region MG in the lower line LL may include a defect. The defect may be migration of a material (e.g., copper) included in the lower line LL. For example, stress may be applied to the lower line LL while a portion of the upper line UL is etched to include the opening OP. Due to the stress applied to the lower line LL, migration of the material (e.g., copper) in the first region MG may occur.

[0047] When a defect such as migration occurs in the first region MG of the lower line LL, resistance may increase or a short circuit may occur in the lower line LL. However, according to one embodiment of the present disclosure, since the semiconductor device includes an auxiliary line AL in contact with the lower surface of the lower line LL, a bypass BP may be formed in the lower line structure LLS. Figure 2B , the auxiliary line AL may overlap the first region MG and may serve as a bypass for a defect occurring in the first region MG. For example, even when a defect occurs in the first region MG, the upper plug UP and the lower plug LP may be electrically coupled to each other through the bypass BP formed along the lower line LL and the auxiliary line AL.

[0048] Figure 2BThe first region MG shown may be one of many examples. In another example, the planar area of ​​the first region MG may be smaller or larger, and the depth of the first region MG may be smaller or larger.

[0049] Figures 3A to 3G is a diagram illustrating a method of manufacturing a semiconductor device including a wire structure according to an embodiment of the present disclosure.

[0050] Reference Figure 3A , a lower line structure LLS may be formed in the first insulating layer IL1. A lower line LL and an auxiliary line AL contacting a portion of a lower surface of the lower line LL may be formed in the first insulating layer IL1. In addition, a lower plug LP protruding downward from the lower line LL and contacting the target plug PL may also be simultaneously formed in the first insulating layer IL1.

[0051] The lower line structure LLS may be integrally formed. The lower line LL, the auxiliary line AL, and the lower plug LP may be formed by a damascene process. For example, the lower line structure LLS may be formed by etching a portion of the first insulating layer IL1 and then filling the corresponding region with a conductive material (eg, copper).

[0052] Reference Figure 3B , a second insulating layer IL2 may be formed on the first insulating layer IL1 and the lower line structure LLS. The first insulating layer IL1 and the second insulating layer IL2 may include the same material or different materials. The first trench TR1 may be formed by etching a portion of the second insulating layer IL2. The first trench TR1 may expose a portion of the upper surface of the lower line LL.

[0053] Reference Figure 3C , an upper line structure ULS may be formed on the lower line structure LLS. The upper line structure ULS may include a conductive material (e.g., aluminum) formed on the second insulating layer IL2. The upper line UL may be located on the lower line LL. The upper plug UP may protrude downward from the upper line UL and may be coupled to the lower line LL. The conductive material filling the first trench TR1 of the second insulating layer IL2 may correspond to the upper plug UP. The upper line UL may be coupled to the lower line LL through the upper plug UP.

[0054] Reference Figure 3D , a hard mask HM may be formed on the upper line UL. The hard mask HM may include a mask opening MO. The mask opening MO may overlap the upper line UL, the lower line LL, and the auxiliary line AL.

[0055] Reference Figure 3E, the upper line UL and the second insulating layer IL2 may be etched along the mask opening MO. By etching the hard mask HM, the upper line UL and the second insulating layer IL2 may be etched to form a second trench TR2. The second trench TR2 may penetrate the upper line UL. A portion of the upper line UL may be etched to form an opening OP. In addition, the second trench TR2 may expose a portion of the second insulating layer IL2. The second trench TR2 may be formed by using a dry etching process that etches a predetermined area using reactive ions.

[0056] The second trench TR2 may overlap the lower line LL. Therefore, when an etching process (eg, reactive ion dry etching) for forming the second trench TR2 is in progress, stress may be applied to the lower line LL. However, as described above with reference to Figure 2B As described, the second trench TR2 may also overlap the auxiliary line AL. Therefore, even when the lower line LL to which stress is applied may include a defect, the bypass BP may be formed and a short circuit of the lower line structure LLS may be avoided.

[0057] Reference Figure 3F , the hard mask HM of the upper line UL may be removed. The portion of the second trench TR2 penetrating the upper line UL may be understood as an opening OP.

[0058] Reference Figure 3G , the second trench TR2 may be filled with the insulating material. When the insulating material is filled in the second trench TR2, the opening OP may be filled with the insulating material.

[0059] Figure 4 and Figure 5 1 is a diagram illustrating various examples of a semiconductor device including a wire structure according to an embodiment of the present disclosure. Figure 4 and Figure 5 In the Figure 2A and Figure 2B The structures shown are repeated in the description of the structures.

[0060] Reference Figure 4 and Figure 5 , the semiconductor device may include a lower structure UST located below the upper line structure ULS and the lower line structure LLS. The target plug PL1 or the target plug PL2 may penetrate the lower structure UST. In addition, the semiconductor device may include a peripheral circuit (eg, Figure 1 The target plug PL1 or the target plug PL2 may be connected to the peripheral circuit. For example, the target plug PL1 or the target plug PL2 may be a peripheral circuit contact plug electrically connected to the peripheral circuit.

[0061] The target plug PL1 or PL2 may contact the lower plug LP of the lower line structure LLS. The target plug PL1 or PL2 may be electrically coupled to the lower line LL and the auxiliary line AL through the lower plug LP. The target plug PL1 or PL2 may be electrically coupled to the upper line UL through the lower line LL and the auxiliary line AL.

[0062] Reference Figure 4 , the semiconductor device may further include a stacked structure SST. The stacked structure SST may be located on the lower structure UST. The stacked structure SST may be located below the upper line structure ULS and the lower line structure LLS. The stacked structure SST may include a first material layer M1 and a second material layer M2 that are alternately stacked. The first material layer M1 may be an oxide layer, and the second material layer M2 may be a nitride layer. The target plug PL1 may penetrate the stacked structure SST. The target plug PL1 may contact a peripheral circuit located below the lower structure UST by penetrating the first material layer M1 and the second material layer M2.

[0063] Reference Figure 5 , the target plug PL2 may not penetrate the stacked structure SST. For example, the target plug PL2 may be located at a predetermined height (eg, at a height greater than the height of the stacked structure SST) where the insulating layer IL is formed in the semiconductor device. Figure 4 The height of the stacked structure SST corresponds to the height of the region). Figure 4 The target plug PL1 in Figure 5 The target plug PL2 in the middle is spaced apart, but the lower line structure LLS can also contact Figure 5 The target plug PL2 in.

[0064] Apart from Figure 4 and Figure 5 In addition to the target plugs PL1 and PL2 shown in FIG. 1 , the upper line structure ULS and the lower line structure LLS can be connected to various types of target plugs. That is, as long as the upper line structure and the lower line structure meet the above Figure 2A and Figure 2B The specifications described in the above description, the upper line structure and the lower line structure may be included within the scope of the present disclosure.

[0065] Figure 6 is a diagram illustrating a memory card system 3000 to which the memory device of the present disclosure is applied.

[0066] Reference Figure 6 , the memory card system 3000 may include a controller 3100 , a memory device 3200 , and a connector 3300 .

[0067] The controller 3100 may be coupled to the memory device 3200. The controller 3100 may be configured to access the memory device 3200. For example, the controller 3100 may control a programming operation, a read operation, an erase operation, or a background operation of the memory device 3200. The controller 3100 may be configured to provide an interface between the memory device 3200 and a host. The controller 3100 may be configured to drive firmware for controlling the memory device 3200. For example, the controller 3100 may include components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an error corrector.

[0068] The controller 3100 can communicate with an external device through the connector 3300. The controller 3100 can communicate with an external device (e.g., a host) according to a specific communication protocol. For example, the controller 3100 can be configured to communicate with an external device through at least one of various communication protocols such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), a PCI Express (PCI-E), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics device (IDE), Firewire, a universal flash memory (UFS), Wi-Fi, Bluetooth, and an NVMe protocol. For example, the connector 3300 can be defined by at least one of the above-mentioned communication protocols.

[0069] The memory device 3200 may include a plurality of memory cells and may be configured in a manner similar to that of FIG. Figure 1 The memory device 100 shown is configured in the same manner.

[0070] The controller 3100 and the memory device 3200 may be integrated into a single semiconductor device to constitute a memory card. For example, the controller 3100 and the memory device 3200 may constitute a memory card such as a personal computer (PC) card (Personal Computer Memory Card International Association (PCMCIA)), a compact flash (CF) card, a smart media card (SM and SMC), a memory stick, a multimedia card (MMC, RS-MMC, micro MMC or eMMC), an SD card (SD, mini SD, micro SD or SDHC), and a universal flash memory (UFS).

[0071] Figure 7 is a diagram illustrating a solid state drive (SSD) system 4000 to which the memory device of the present disclosure is applied.

[0072] Reference Figure 7, the SSD system 4000 may include a host 4100 and an SSD 4200. The SSD 4200 may exchange signals with the host 4100 through a signal connector 4001, and may receive power through a power connector 4002. The SSD 4200 may include a controller 4210, a plurality of memory devices 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0073] The controller 4210 may control the plurality of memory devices 4221 to 422n in response to a signal received from the host 4100. For example, the signal may be a signal based on an interface between the host 4100 and the SSD 4200. For example, the signal may be defined by at least one of an interface such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), PCI Express (PCI-E), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), a firewire, a universal flash storage (UFS), a WI-FI, a Bluetooth, and an NVMe interface.

[0074] The plurality of memory devices 4221 to 422n may include a plurality of memory cells configured to store data. Each of the plurality of memory devices 4221 to 422n may be configured to store data in a manner similar to that of FIG. Figure 1 The memory device 100 shown in FIG. 4 is configured in the same manner as the memory device 100. The plurality of memory devices 4221 to 422n may communicate with the controller 4210 through channels CH1 to CHn.

[0075] The auxiliary power supply 4230 may be connected to the host 4100 through the power connector 4002. The auxiliary power supply 4230 may receive power input from the host 4100 and charge the power. When the power supply from the host 4100 is not stable, the auxiliary power supply 4230 may provide power to the SSD 4200. For example, the auxiliary power supply 4230 may be located inside or outside the SSD 4200. For example, the auxiliary power supply 4230 may be located on the mainboard and provide auxiliary power to the SSD 4200.

[0076] The buffer memory 4240 may be used as a buffer memory of the SSD 4200. For example, the buffer memory 4240 may temporarily store data received from the host 4100 or data received from the plurality of memory devices 4221 to 422n, or may temporarily store metadata (e.g., a mapping table) of the memory devices 4221 to 422n. The buffer memory 4240 may include a volatile memory such as DRAM, SDRAM, DDR SDRAM, and LPDDR SDRAM, or a nonvolatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0077] According to an embodiment of the present disclosure, defects in a wire structure may be reduced by changing the structure of the wire structure.

[0078] CROSS-REFERENCE TO RELATED APPLICATIONS

[0079] This application claims the priority of Korean Patent Application No. 10-2023-0156341 filed on November 13, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: an upper line, the upper line comprising an opening; a lower line, the lower line being located below the upper line and overlapping the opening along a first direction; as well as An auxiliary line is located below the lower line and overlaps the opening along the first direction, wherein the auxiliary line contacts a lower surface of the lower line.

2. The semiconductor device according to claim 1, wherein The auxiliary line contacts a portion of the lower surface of the lower line.

3. The semiconductor device according to claim 1, wherein The plane area of ​​the auxiliary line is larger than the plane area of ​​the opening in the upper line.

4. The semiconductor device according to claim 1, wherein The auxiliary line has a width in a second direction intersecting the first direction greater than a width of the opening in the upper line in the second direction.

5. The semiconductor device according to claim 1, further comprising: an upper plug that protrudes downward from the upper wire and contacts the lower wire; as well as A lower plug protrudes downward from the lower line and contacts a target plug.

6. The semiconductor device according to claim 5, wherein: The upper plug and the lower plug are located on opposite sides of the auxiliary line along a second direction crossing the first direction.

7. The semiconductor device according to claim 6, wherein: The auxiliary line is located between the upper plug and the lower plug along the second direction.

8. The semiconductor device according to claim 1, wherein The auxiliary line and the lower line together form a current path.

9. The semiconductor device according to claim 1, wherein: The lower line and the auxiliary line include the same material.

10. The semiconductor device according to claim 9, wherein The lower line and the auxiliary line include copper Cu.

11. The semiconductor device according to claim 1, further comprising a stacked structure, the stacked structure being located below the upper line, the lower line and the auxiliary line, wherein: The stacked structure includes first material layers and second material layers that are alternately stacked. 12 . The semiconductor device according to claim 11 , further comprising a target plug penetrating the stacked structure.

13. The semiconductor device according to claim 12, wherein: The target plug is electrically coupled to the upper line through the lower line and the auxiliary line. 14 . The semiconductor device according to claim 12 , further comprising a peripheral circuit, wherein the peripheral circuit is located below the stacked structure.

15. The semiconductor device according to claim 14, wherein: The target plug is electrically coupled to the peripheral circuit.

16. A method for manufacturing a semiconductor device, the method comprising the steps of: Forming the lower line; forming an auxiliary line below the lower line, the auxiliary line contacting a portion of a lower surface of the lower line; forming an upper line above the lower line; as well as An opening is formed by etching a portion of the upper line, the opening overlapping the lower line and the auxiliary line.

17. The method according to claim 16, further comprising the steps of: forming a lower plug that protrudes downward from the lower line and contacts the target plug, Wherein, the lower plug, the lower line and the auxiliary line are formed simultaneously.

18. The method according to claim 17, wherein: The lower line, the auxiliary line, and the lower plug are formed by a damascene process.

19. The method according to claim 16, further comprising the steps of: forming an upper plug protruding downward from the upper wire and contacting the lower wire, Wherein, the upper plug and the upper line are formed simultaneously.

20. The method according to claim 16, wherein: The steps of forming the opening include: forming a hard mask including a mask opening on the upper line; and A trench is formed along the mask opening corresponding to the opening in the upper line.

21. The method according to claim 20, wherein: The formation of the trench is performed by a dry etching process using reactive ions.

22. The method according to claim 16, further comprising the steps of: The opening is filled with a conductive material.

23. The method according to claim 16, wherein: The plane area of ​​the auxiliary line is larger than the plane area of ​​the opening in the upper line.

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