Dynamic random access memory and manufacturing method thereof

Abstract

The invention discloses a dynamic random access memory and a manufacturing method thereof, relates to the technical field of memories, and is used for forming a multi-layer memory cell array at one time and improving the integration density of the dynamic random access memory on the premise of ensuring the electrical performance and the stability of memory cells. The dynamic random access memory comprises a plurality of memory units distributed in a three-dimensional array. Each memory cell includes a first transistor and a second transistor. The second source region, the second channel region and the second drain region are arranged in the first through hole in the first direction. The second gate is disposed within the first via. The second transistor includes a first gate disposed within the first recess. One of the first source electrode and the first drain electrode which is not electrically connected with the first gate electrode is arranged in the second through hole. And the first source region, the first channel region and the first drain region are distributed in the second notch along the third direction. The manufacturing method of the dynamic random access memory is used for manufacturing the dynamic random access memory.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a dynamic random access memory and a manufacturing method thereof. Background Art

[0002] In computer systems, memory is a key component for storing data and programs. As an important type of memory, dynamic random access memory (DRAM) plays a key role in modern computer architecture. Dynamic random access memory includes a 2T0C memory cell structure. A memory cell of this dynamic random access memory consists of two transistors, one of which is responsible for gating and the other is responsible for gating and storing charge.

[0003] In the prior art, the storage units of the dynamic random access memory are arranged in an array along the horizontal direction of the wafer, that is, a two-dimensional dynamic random access memory. However, the development of computer systems has put forward higher requirements on the density of dynamic random access memory, and the density of two-dimensional dynamic random access memory is limited by the process and cannot meet the density requirements. Summary of the invention

[0004] The object of the present invention is to provide a dynamic random access memory and a manufacturing method thereof, which are used to form a multi-layer memory cell array at one time, and to improve the integration density of the dynamic random access memory while ensuring the electrical performance and stability of the memory cell.

[0005] In order to achieve the above-mentioned object, in a first aspect, the present invention provides a dynamic random access memory, which includes: a plurality of storage cells distributed in a three-dimensional array, and a dielectric structure for isolating different storage cells. The plurality of storage cells distributed in a three-dimensional array include multiple storage layers spaced apart along a first direction, each storage layer includes multiple storage groups spaced apart along a second direction, and each storage group includes multiple storage cells spaced apart along a third direction. The first direction, the second direction and the third direction are different from each other. Each storage cell includes a first transistor and a second transistor distributed along the third direction. The second transistor is a dual-gate structure. In the same storage cell, one of the first source and the first drain included in the first transistor is electrically connected to the first gate included in the second transistor. The dielectric structure is provided with a first through hole and a second through hole spaced apart along the third direction. The second source region, the second channel region and the second drain region included in the second transistor are arranged in the first through hole along the first direction. The second gate included in the second transistor is arranged in the first through hole, and the second channel region included in the second transistor is surrounded by the periphery of the second gate. The dielectric structure is provided with a first recessed inwardly concave portion corresponding to the second channel region included in the second transistor, and the first gate included in the second transistor is provided in the first recessed portion. One of the first source and the first drain that is not electrically connected to the first gate is provided in the second through hole. The dielectric structure is provided with a second recessed inwardly concave portion corresponding to the second through hole, and the second recess is connected to the first recess. The first source region, the first channel region, and the first drain region included in the first transistor are distributed in the second recess along the third direction.

[0006] In the case of adopting the above technical solution, the dynamic random access memory provided by the present invention not only has a plurality of storage groups distributed along the second direction in the same layer, but also includes a plurality of storage layers distributed along the first direction, and the plurality of storage units are distributed in a three-dimensional array. Compared with a two-dimensional dynamic random access memory having only a single storage layer, each storage layer in the present invention can form a structure similar to the two-dimensional dynamic random access memory of the prior art, and the plurality of storage layers stacked along the first direction in the present invention can multiply the storage density of the dynamic random access memory provided by the present invention, effectively solving the problem of low density of the two-dimensional dynamic random access memory. In addition, the first through hole is connected to the first recess, and the second through hole is connected to the second recess. Since the above structures of the first transistor and the above structures of the second transistor included in the storage unit are all arranged in the first through hole, the second through hole, the first recess, and the second recess, when manufacturing the dynamic random access memory provided by the present invention, the first through hole and the second through hole can be operated to form a multi-layer storage unit array at one time, and the integration density and storage density of the dynamic random access memory are greatly improved under the premise of ensuring the electrical performance and stability of the storage unit.

[0007] In addition, the first transistor is used as a write transistor, and the second transistor is used as a read transistor. Based on this, when manufacturing the dynamic random access memory provided by the present invention, due to errors in the process, the structure and design of the storage unit, especially the second transistor, will deviate, resulting in different threshold voltages of the second transistors included in different storage units. When reading data, data errors may be caused. Based on this, the second transistor has a dual-gate structure, and the threshold voltage of the second transistor can be regulated and compensated by the second gate included in the second transistor to avoid errors in the read data, which is conducive to improving the accuracy of data storage in the dynamic random access memory provided by the present invention.

[0008] As a possible implementation scheme, the first transistor has a dual-gate structure; the third gate and the fourth gate included in the first transistor are respectively arranged on both sides of the first channel region along the third direction.

[0009] When the above technical solution is adopted, the traditional transistor has only one gate to control the current in the channel region, while the first transistor provided by the present invention has two gates. The dual-gate transistor can have twice the gate control area under the same channel region area, which can effectively improve the gate's control ability over the channel region, which makes the gate's control over the carriers in the channel region more precise and flexible, and can more effectively adjust the conduction and cutoff of the current, thereby improving the switching performance of the transistor provided by the present invention, and can effectively suppress the short channel effect, which is conducive to further reducing the size of the transistor provided by the present invention, thereby improving the storage density of the dynamic random access memory provided by the present invention. For example, under low-voltage operation, the first transistor of the dual-gate structure can control the current more accurately and achieve faster switching conversion, which is conducive to reducing the power consumption of the dynamic random access memory provided by the present invention.

[0010] As a possible implementation scheme, the gate structure included in the first transistor is arranged in the second recess and is located on at least one side of the first channel region along the first direction; one of the first source and the first drain that is not electrically connected to the first gate is isolated from the gate structure by the first gate dielectric layer included in the first transistor.

[0011] When the above technical solution is adopted, the one of the first source and the first drain that is not electrically connected to the first gate is in close contact with the gate structure, which is beneficial to reducing the area occupied by the one of the first source and the first drain that is not electrically connected to the first gate, thereby helping to reduce the area occupied by the first transistor, and is beneficial to realizing the one-time formation of a multi-layer memory cell array. Under the premise of ensuring the electrical performance and stability of the memory cell, the integration density of the dynamic random access memory is greatly improved.

[0012] As a possible implementation, the second transistor includes a second source and a second drain, which are respectively arranged in the third notch and the fourth notch. The third notch and the fourth notch are respectively arranged on both sides of the first gate along the first direction. The second source is electrically connected to the second source region; the second drain is electrically connected to the second drain region.

[0013] In the case of adopting the above technical solution, the third recess and the fourth recess are formed on both sides of the first recess in the third direction and are connected to the first through hole. The second transistor has a vertical channel structure, which reduces the area occupied by the second source region, the second channel region and the second drain region included in the second transistor while ensuring the channel length of the second transistor, thereby reducing the area occupied by the second transistor, which is conducive to improving the storage density of the dynamic random access memory. In addition, the second source electrode, the second drain electrode and the first gate electrode included in the second transistor are vertically stacked and distributed in the first direction, which reduces the area occupied by the second transistor, which is conducive to improving the storage density of the dynamic random access memory. At the same time, the second source region, the second channel region and the second drain region in the first through hole are vertically stacked and distributed, and the formation of the second source region, the second channel region and the second drain region in the same second transistor can be realized in the first through hole through only one-step deposition operation, and the formation of the second source region, the second channel region and the second drain region in different second transistors connected through the first through hole is conducive to realizing the one-time formation of a multi-layer memory cell array, and greatly improving the integration density of the dynamic random access memory under the premise of ensuring the electrical performance and stability of the memory cell.

[0014] As a possible implementation, the first transistor is an indium zinc oxide thin film transistor, a tin-doped indium oxide thin film transistor, an indium oxide thin film transistor, a zinc oxide thin film transistor or a titanium oxide thin film transistor.

[0015] In the case of adopting the above technical solution, the off current of the above-mentioned metal oxide thin film transistors is low, so that the off-state power consumption of the first transistor is low, which is conducive to reducing the power consumption of the dynamic random access memory provided by the present invention. In addition, the first transistor is used as a write tube. Based on this, due to the low off current of the above-mentioned metal oxide thin film transistors, the speed of the discharge of the gate capacitance of the second transistor through the channel of the first transistor can be greatly slowed down, thereby greatly extending the retention time of the gate capacitance of the second transistor, and then reducing the refresh frequency of the dynamic random access memory provided by the present invention, thereby reducing the power consumption of the dynamic random access memory provided by the invention. The first transistor is the above-mentioned metal oxide thin film transistor, so that the first transistor has a relatively high carrier mobility, so that the first transistor has a faster signal transmission and switching speed, thereby improving the working efficiency and response speed of the dynamic random access memory provided by the present invention. At the same time, when manufacturing the dynamic random access memory provided by the present invention, the above-mentioned metal oxide thin film transistors can be made using a low-temperature process, and the low-temperature process can reduce the demand for expensive high-temperature equipment and complex process steps, and can reduce costs. In addition, the channel regions of the above-mentioned metal oxide thin film transistors can be formed in parallel through deposition and other processes, and the first channel regions included in multiple first transistors can be formed at one time, which is conducive to the simultaneous formation of the first transistors included in multiple memory cells, and is conducive to the one-time formation of a multi-layer memory cell array. Under the premise of ensuring the electrical performance and stability of the memory cell, the integration density of the dynamic random access memory is greatly improved.

[0016] As a possible implementation, one of the first source and the first drain that is electrically connected to the first gate is integrally continuous with the first gate.

[0017] In the case of adopting the above scheme, when manufacturing the dynamic random access memory provided by the present invention, one of the first source and the first drain that is electrically connected to the first gate and the first gate can be formed in the same process step, which can reduce the process steps and is conducive to forming a multi-layer memory cell array at one time, and greatly improves the integration density of the dynamic random access memory while ensuring the electrical performance and stability of the memory cell. In addition, the above two structures are continuous as a whole, and there is no need to use an additional structure to connect them, which is conducive to reducing the area occupied by the memory cell, thereby improving the density of the dynamic random access memory provided by the present invention.

[0018] In a second aspect, the present invention also provides a method for manufacturing a dynamic random access memory, the method for manufacturing a dynamic random access memory comprising: forming a plurality of memory cells distributed in a three-dimensional array, and forming a dielectric structure for isolating different memory cells. The plurality of memory cells distributed in a three-dimensional array include multiple memory layers spaced apart along a first direction, each memory layer includes multiple memory groups spaced apart along a second direction, and each memory group includes multiple memory cells spaced apart along a third direction. The first direction, the second direction, and the third direction are different from each other. Each memory cell includes a first transistor and a second transistor spaced apart along the third direction. The second transistor is a dual-gate structure. In the same memory cell, one of the first source and the first drain included in the first transistor is electrically connected to the first gate included in the second transistor. A first through hole and a second through hole spaced apart along the third direction are provided in the dielectric structure. The second source region, the second channel region, and the second drain region included in the second transistor are provided in the first through hole along the first direction. The second gate included in the second transistor is provided in the first through hole, and the second channel region included in the second transistor is surrounded by the periphery of the second gate. The dielectric structure is provided with a first recessed inwardly concave portion corresponding to the second channel region included in the second transistor, and the first gate included in the second transistor is provided in the first recessed portion. One of the first source and the first drain that is not electrically connected to the first gate is provided in the second through hole. The dielectric structure is provided with a second recessed inwardly concave portion corresponding to the second through hole, and the second recess is connected to the first recess. The first source region, the first channel region, and the first drain region included in the first transistor are distributed in the second recess along the third direction.

[0019] Compared with the prior art, the beneficial effects of the method for manufacturing the dynamic random access memory provided by the present invention are the same as the beneficial effects of the dynamic random access memory provided by the first aspect, and are not described in detail here.

[0020] As a possible implementation scheme, forming a plurality of storage units distributed in a three-dimensional array and forming a dielectric structure for isolating different storage units includes: forming a stacking structure, and a first dielectric filling part and a second dielectric filling part that penetrate the stacking structure along a first direction; the stacking structure includes a multi-layer stacking unit stacked along the first direction. The stacking unit includes two first dielectric layers that are spaced apart along the first direction, and a stack located between the two first dielectric layers. The stack includes two metal layers that are spaced apart along the first direction, and a second dielectric layer that is located between the two metal layers. The materials of the first dielectric layer, the metal layer, and the second dielectric layer are different from each other. A third through hole and a fourth through hole that penetrate along the first direction are provided in the stacking structure, and the third through hole and the fourth through hole are spaced apart. The first dielectric filling part is filled in the third through hole, and the second dielectric filling part is filled in the fourth through hole. Next, a plurality of first through holes that penetrate the stacking structure and are spaced apart along the second direction are formed. Next, the edge portions of the two metal layers close to the first through hole are selectively etched along the third direction to form a third notch and a fourth notch. Next, a dielectric isolation layer is formed in the third notch, the fourth notch, and the first through hole. Next, a second source electrode included in the second transistor is formed in the third recess, and a second drain electrode included in the second transistor is formed in the fourth recess. Next, along the first direction, a second source region, a second channel region and a second drain region included in the second transistor are formed in the first through hole; the second source electrode is connected to the second source region; and the second drain electrode is connected to the second drain region. Next, a second gate dielectric layer included in the second transistor is formed in the first through hole. The second gate dielectric layer is formed on the second source region, the second channel region and the second drain region. Next, a second gate electrode included in the second transistor is formed in the first through hole. Next, a plurality of second through holes are formed that penetrate the stacking structure and are spaced apart along the second direction. Next, the second dielectric layer is partially removed to form the first recess and the second recess, and the remaining metal layer is formed into the gate structure included in the first transistor. Next, a first gate dielectric layer included in the first transistor is formed in the second recess and the second through hole. Next, a first gate electrode included in the second transistor and one of the first source electrode and the first drain electrode electrically connected to the first gate electrode are formed in the first recess. And a first source region, a first channel region and a first drain region included in the first transistor are formed in the second recess. Next, one of the first source electrode and the first drain electrode which is not electrically connected to the first gate electrode is formed in the second through hole.

[0021] When the above technical solution is adopted, the first through hole is connected to the first recess, the first through hole is connected to the third recess, the first through hole is connected to the fourth recess, and the second through hole is connected to the second recess. After the first through hole and the second through hole are formed, the above structures included in the first transistor and the second transistor are formed by the processing technology in the first through hole and the second through hole, thereby realizing the simultaneous manufacture of the memory cells arranged in the same first through hole, and the stacking structure includes a plurality of first through holes, so that a plurality of memory cells arranged in a plurality of first through holes can be processed at the same time, so that all the memory cells included in the dynamic random access memory can be manufactured at the same time, which is conducive to realizing the one-time formation of a multi-layer memory cell array, and greatly improving the integration density of the dynamic random access memory under the premise of ensuring the electrical performance and stability of the memory cell.

[0022] As a possible implementation, forming a stacked structure, and forming a first dielectric filling portion and a second dielectric filling portion that penetrate the stacked structure along a first direction includes: forming a stacked material layer. The stacked material layer includes a plurality of stacked units stacked along the first direction. Next, forming a third through hole and a fourth through hole that penetrate the stacked material layer. Along the second direction, the third through hole is arranged between two adjacent first through holes; along the second direction, the fourth through hole is arranged between two adjacent second through holes. Next, the first dielectric filling portion is filled in the third through hole, and the second dielectric filling portion is filled in the fourth through hole.

[0023] In the case of adopting the above technical solution, the third through hole is spaced apart from the first through hole, the fourth through hole is spaced apart from the second through hole, and the first dielectric filling part filled in the third through hole and the second dielectric filling part filled in the fourth through hole serve as an isolation layer between adjacent storage units along the second direction, which is beneficial to avoid leakage of adjacent storage units along the second direction. In addition, in the above-mentioned step of partially removing the second dielectric layer, the two metal layers in the stacking unit will be suspended, and the first dielectric filling part and the second dielectric filling part can serve as support to avoid bending of the stacking structure, which is beneficial to the regular structure of the storage unit, thereby ensuring the normal operation and stable performance of the storage unit manufactured by the manufacturing method of the dynamic random access memory provided by the present invention, thereby improving the yield.

[0024] As a possible implementation, partially removing the second dielectric layer further includes: removing a portion of the second dielectric layer located between the first through hole and the second through hole in the third direction and adjacent to the second through hole, so that the remaining second dielectric layer forms a second dielectric portion. Along the second direction, the second dielectric portion electrically isolates the first source region, the first channel region, the first drain region, and the first gate of two adjacent memory cells.

[0025] When the above technical solution is adopted, the second dielectric part isolates the first source region, the first channel region, the first drain region and the first gate region of two adjacent storage units along the second direction, so as to achieve the isolation of the data stored in the two adjacent storage units. In addition, the second dielectric part can also serve as a support to prevent the stacking structure from bending after the first notch and the second notch are formed, which is conducive to the regularity of the structure of the storage unit, thereby ensuring the normal operation and stable performance of the storage unit manufactured by the manufacturing method of the dynamic random access memory provided by the present invention, thereby improving the yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0027] FIG. 1( a ) is a front view of the structure of a dynamic random access memory provided by an embodiment of the present invention;

[0028] FIG1( b ) is a top view of the structure of a dynamic random access memory provided by an embodiment of the present invention;

[0029] Figure 2 A flow chart of a method for manufacturing a dynamic random access memory provided by an embodiment of the present invention;

[0030] FIG3( a ) is a front view of a schematic diagram of forming a stacking structure provided by an embodiment of the present invention;

[0031] FIG3( b ) is a top view of a schematic diagram of forming a stacked structure provided by an embodiment of the present invention;

[0032] Figure 4 A flowchart of forming a stacking structure in an embodiment of the present invention;

[0033] Figure 5 A front view of a schematic diagram of forming a third through hole and a fourth through hole provided in an embodiment of the present invention;

[0034] FIG6( a ) is a front view of a schematic diagram of filling a first medium filling part in a third through hole and filling a second medium filling part in a fourth through hole provided by an embodiment of the present invention;

[0035] FIG6( b ) is a top view of a schematic diagram of filling a first medium filling part in a third through hole and filling a second medium filling part in a fourth through hole provided by an embodiment of the present invention;

[0036] FIG. 7( a ) is a front view of a schematic diagram of forming a first through hole, a third recess and a fourth recess provided by an embodiment of the present invention;

[0037] FIG7( b) is a top view of a schematic diagram of forming a first through hole, a third recess and a fourth recess provided by an embodiment of the present invention;

[0038] FIG8( a ) is a front view of a schematic diagram of forming a dielectric isolation layer provided by an embodiment of the present invention;

[0039] FIG8( b ) is a top view of a schematic diagram of forming a dielectric isolation layer provided by an embodiment of the present invention;

[0040] FIG9( a) is a front view of a schematic diagram of forming a first source electrode and a first drain electrode provided by an embodiment of the present invention;

[0041] FIG9( b) is a top view of a schematic diagram of forming a first source electrode and a first drain electrode provided by an embodiment of the present invention;

[0042] FIG10( a ) is a front view of a schematic diagram of forming a second source region, a second channel region, a second drain region, a second gate dielectric layer, and a second gate provided by an embodiment of the present invention;

[0043] FIG10( b ) is a top view of a schematic diagram of forming a second source region, a second channel region, a second drain region, a second gate dielectric layer, and a second gate provided by an embodiment of the present invention;

[0044] FIG. 11( a ) is a front view of a schematic diagram of forming a second through hole provided by an embodiment of the present invention;

[0045] FIG11( b) is a top view of a schematic diagram of forming a second through hole provided by an embodiment of the present invention;

[0046] FIG12( a ) is a front view of a schematic diagram of partially removing a second dielectric layer provided by an embodiment of the present invention;

[0047] FIG12( b ) is a top view of a schematic diagram of partially removing the second dielectric layer provided by an embodiment of the present invention;

[0048] FIG12( c ) is a cross-sectional view along the AA′ direction in FIG12( a ) with the second dielectric layer partially removed provided by an embodiment of the present invention;

[0049] FIG. 13( a ) is a front view of a schematic diagram of forming a first gate dielectric layer provided in an embodiment of the present invention;

[0050] FIG13( b ) is a top view of a schematic diagram of forming a first gate dielectric layer provided by an embodiment of the present invention;

[0051] 14( a ) is a front view of a schematic diagram of forming a first source region, a first channel region, a first drain region, a first gate, and one of a first source electrode and a first drain electrode electrically connected to the first gate, provided in an embodiment of the present invention;

[0052] 14( b ) is a top view of a schematic diagram of forming a first source region, a first channel region, a first drain region, a first gate, and one of the first source and the first drain electrically connected to the first gate, provided in an embodiment of the present invention;

[0053] FIG15( a ) is a front view of a schematic diagram of forming one of the first source and the first drain that is not electrically connected to the first gate provided by an embodiment of the present invention;

[0054] FIG15( b ) is a top view of a schematic diagram of forming one of the first source and the first drain that is not electrically connected to the first gate, provided in an embodiment of the present invention.

[0055] Reference numerals:

[0056] 110 - first dielectric portion, 111 - first dielectric layer, 120 - second dielectric portion, 121 - second dielectric layer, 122 - first notch, 123 - second notch, 130 - first dielectric filling portion, 131 - third through hole, 140 - second dielectric filling portion, 141 - fourth through hole, 150 - third dielectric filling portion,

[0057] 200 - first transistor, 211 - first source region, 212 - first channel region, 213 - first drain region, 220 - gate structure, 221 - third gate, 222 - fourth gate, 223 - metal layer, 231 - first source, 232 - first drain, 240 - first gate dielectric layer, 250 - second through hole,

[0058] 300 - a second transistor, 311 - a second source region, 312 - a second channel region, 313 - a second drain region, 321 - a first gate, 322 - a second gate, 331 - a second source, 332 - a second drain, 333 - a third notch, 334 - a fourth notch, 341 - a dielectric isolation layer, 342 - a second gate dielectric layer, 340 - a first through hole,

[0059] 400 - storage unit. DETAILED DESCRIPTION

[0060] In order to make the technical problems, technical solutions and beneficial effects to be solved by the embodiments of the present invention more clearly understood, the embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the embodiments of the present invention and are not used to limit the embodiments of the present invention.

[0061] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0062] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0063] In the description of the embodiments of the present invention, it should be understood that the directions or positional relationships indicated by the terms "up", "down", "front", "back", "left", "right", etc. are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the embodiments of the present invention.

[0064] In the description of the embodiments of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments of the present invention can be understood according to specific circumstances.

[0065] In computer systems, memory is a key component for storing data and programs. As an important type of memory, dynamic random access memory (DRAM) plays a key role in modern computer architecture. Dynamic random access memory includes a 2T0C memory cell structure. A memory cell of this dynamic random access memory consists of two transistors, one of which is responsible for gating and the other is responsible for gating and storing charge.

[0066] In the prior art, the storage units of the dynamic random access memory are arranged in an array along the horizontal direction of the wafer, that is, a two-dimensional dynamic random access memory. However, the development of computer systems has put forward higher requirements on the density of dynamic random access memory, and the density of two-dimensional dynamic random access memory is limited by the process and cannot meet the density requirements.

[0067] In order to solve the above problems, in the first aspect, please refer to FIG. 1(a) and FIG. 1(b), an embodiment of the present invention provides a dynamic random access memory, which includes: a plurality of storage cells 400 distributed in a three-dimensional array, and a dielectric structure for isolating different storage cells 400. The plurality of storage cells 400 distributed in a three-dimensional array include multiple storage layers spaced along a first direction, each storage layer includes multiple storage groups spaced along a second direction, and each storage group includes multiple storage cells 400 spaced along a third direction. The first direction, the second direction and the third direction are different from each other. Each storage cell 400 includes a first transistor 200 and a second transistor 300 distributed along the third direction. The second transistor 300 is a dual-gate structure. In the same storage cell 400, one of the first source 231 and the first drain 232 included in the first transistor 200 is electrically connected to the first gate 321 included in the second transistor 300. The dielectric structure is provided with a first through hole 340 and a second through hole 250 spaced along the third direction. The second source region 311, the second channel region 312 and the second drain region 313 included in the second transistor 300 are arranged in the first through hole 340 along the first direction. The second gate 322 included in the second transistor 300 is arranged in the first through hole 340, and the second channel region 312 included in the second transistor 300 surrounds the outer periphery of the second gate 322. The dielectric structure is provided with a first indentation 122 recessed inwardly at a portion corresponding to the second channel region 312 included in the second transistor 300, and the first gate 321 included in the second transistor 300 is arranged in the first indentation 122. One of the first source 231 and the first drain 232 that is not electrically connected to the first gate 321 is arranged in the second through hole 250. The dielectric structure is provided with a second indentation 123 recessed inwardly at a portion corresponding to the second through hole 250, and the second indentation 123 is connected to the first indentation 122. The first transistor 200 includes a first source region 211 , a first channel region 212 , and a first drain region 213 , which are distributed in the second recess 123 along the third direction.

[0068] In the case of adopting the above technical solution, please refer to Figure 1 (a) and Figure 1 (b). The dynamic random access memory provided by the embodiment of the present invention not only has multiple storage groups distributed along the second direction in the same layer, but also includes multiple storage layers distributed along the first direction. In this case, multiple storage units 400 are distributed in a three-dimensional array. Compared with a two-dimensional dynamic random access memory having only a single storage layer, each storage layer in the embodiment of the present invention can form a structure similar to that of a two-dimensional dynamic random access memory in the prior art, and the multiple storage layers stacked along the first direction in the embodiment of the present invention can double the storage density of the dynamic random access memory provided by the embodiment of the present invention, effectively solving the problem of low density of the two-dimensional dynamic random access memory. Furthermore, the first through hole 340 is connected to the first recess 122, and the second through hole 250 is connected to the second recess 123. Since the above-mentioned structures of the first transistor 200 and the above-mentioned structures of the second transistor 300 included in the storage unit 400 are all arranged in the first through hole 340, the second through hole 250, the first recess 122, and the second recess 123, when manufacturing the dynamic random access memory provided by the embodiment of the present invention, a multi-layer memory cell array can be formed at one time by operating the first through hole 340 and the second through hole 250. Under the premise of ensuring the electrical performance and stability of the memory unit 400, the integration density and storage density of the dynamic random access memory are greatly improved.

[0069] In addition, the first transistor is used as a write transistor and the second transistor is used as a read transistor. Based on this, when manufacturing the dynamic random access memory provided by the embodiment of the present invention, due to errors in the process, the structure and design of the storage unit, especially the second transistor, will deviate, resulting in the threshold voltages of the second transistors included in different storage units being different from each other, which may cause data errors when reading data. Based on this, the second transistor has a dual-gate structure, and the threshold voltage of the second transistor can be regulated and compensated by the second gate included in the second transistor to avoid errors in the read data, which is conducive to improving the accuracy of data storage in the dynamic random access memory provided by the embodiment of the present invention.

[0070] In actual application, the embodiments of the present invention do not specifically limit the specific arrangement directions and distribution conditions of different storage units, as long as the different storage units are distributed in a three-dimensional array. As for the specific directions referred to by the first direction, the second direction and the third direction, no specific limitation is made here, as long as the directions of any two of the above three directions are different.

[0071] Exemplarily, the first direction is the height direction of the dynamic random access memory provided by the embodiment of the present invention. Secondly, the second direction and the third direction can be determined according to the distribution of different storage units 400 in the same storage layer. For example: please refer to Figure 1 (a) and Figure 1 (b). When different storage units 400 in the same storage layer are distributed in a rectangular array, the second direction and the third direction can be the directions of the length and width of the rectangular array, respectively. For another example: when different storage units 400 in the same storage layer are distributed in a parallelogram array, the second direction and the third direction can be the directions of two adjacent sides of the parallelogram array, respectively. In another example, for another example: when different storage units 400 in the same storage layer are distributed in a concentric circle array, the second direction and the third direction can be the radial direction and the circumferential direction of the concentric circle array, respectively. It can be understood that when the distribution of storage units in the same storage layer is different, the second direction and the third direction can be changed with its distribution.

[0072] The structure and materials of the first transistor are further described below.

[0073] The embodiment of the present invention does not specifically limit the device type of the first transistor, and it can be determined according to actual needs.

[0074] Exemplarily, the first transistor is an indium zinc oxide thin film transistor, a tin-doped indium oxide thin film transistor, an indium oxide thin film transistor, a zinc oxide thin film transistor or a titanium oxide thin film transistor.

[0075] In the case of adopting the above technical solution, the off current of the above several metal oxide thin film transistors is low, so that the off-state power consumption of the first transistor is low, which is conducive to reducing the power consumption of the dynamic random access memory provided by the embodiment of the present invention; and the first transistor is used as a write transistor and the second transistor is used as a read transistor. Based on this, due to the low off current of the above several metal oxide thin film transistors, the speed of the discharge of the gate capacitance of the second transistor through the channel of the first transistor can be greatly slowed down, thereby greatly extending the retention time of the gate capacitance of the second transistor, and then reducing the refresh frequency of the dynamic random access memory provided by the embodiment of the present invention, thereby reducing the power consumption of the dynamic random access memory provided by the embodiment of the invention. The first transistor is the above several metal oxide thin film transistors, so that the first transistor has a relatively high carrier mobility, so that the first transistor has a faster signal transmission and switching speed, thereby improving the working efficiency and response speed of the dynamic random access memory provided by the embodiment of the present invention. At the same time, when manufacturing the dynamic random access memory provided by the embodiment of the present invention, the channel region of the above several metal oxide thin film transistors can be made by a low temperature process, and the low temperature process can reduce the demand for expensive high temperature equipment and complex process steps, and can reduce costs. In addition, the channel regions of the above-mentioned metal oxide thin film transistors can be formed in parallel through deposition and other processes, and the first channel regions included in multiple first transistors can be formed at one time, which is conducive to the simultaneous formation of the first transistors included in multiple memory cells, and is conducive to the one-time formation of a multi-layer memory cell array, which greatly improves the integration density of the dynamic random access memory while ensuring the electrical performance and stability of the memory cell. Furthermore, in the dynamic random access memory provided by the embodiment of the present invention, the first transistor uses the above-mentioned type of transistor so that the range of device types that can be selected for the first transistor is relatively large, thereby meeting the switching speed, power consumption, conductivity type, operating voltage and other parameter requirements of the memory cell for the read tube.

[0076] It is understandable that when the device type of the first transistor is any of the above, the materials of the first source region, the first channel region and the first drain region are also determined. For example, when the first transistor is a tin-doped indium oxide thin film transistor, the materials of the first source region, the first channel region and the first drain region are all tin-doped indium oxide.

[0077] For example, please refer to FIG. 1(a) and FIG. 1(b), the first transistor 200 includes: a first source 231, a first drain 232, a gate structure 220, a first source region 211, a first channel region 212, a first drain region 213 and a first gate dielectric layer 240. The first source region 211, the first channel region 212 and the first drain region 213 are distributed in the second recess 123 along the third direction, and the first drain 231 is electrically connected to the first drain region 213 and is also distributed in the second recess 123. The second recess 123 is recessed inward from the second through hole 250. The first source 231 is electrically connected to the first source region 211 and is disposed in the second through hole 250. In other words, the first source 231 is disposed at the top of the second recess 123, and along the third direction, the first source 231, the first source region 211, the first channel region 212, the first drain region 213 and the first drain 232 are distributed in sequence. The gate structure 220 is disposed in the second recess 123 and is located at least on one side of the first channel region 212 along the first direction. A first gate dielectric layer 240 is also disposed between the gate structure 220 and the first channel region 212 included in the first transistor 200. One of the first source 231 and the first drain 232 that is not electrically connected to the first gate, that is, the first source 231 in the figure, is isolated from the gate structure 220 by the first gate dielectric layer 240 included in the first transistor 200.

[0078] When the above technical solution is adopted, please refer to Figure 1(a) and Figure 1(b). The one of the first source 231 and the first drain 232 that is not electrically connected to the first gate 321 is in close contact with the gate structure 220, which is beneficial to reducing the area occupied by the one of the first source 231 and the first drain 232 that is not electrically connected to the first gate 321, thereby helping to reduce the area occupied by the first transistor 200, and facilitating the one-time formation of a multi-layer memory cell array. Under the premise of ensuring the electrical performance and stability of the memory cell, the integration density of the dynamic random access memory is greatly improved. Furthermore, the second recess 123 is connected to the second through hole 250, and the formation of the first source region 211, the first channel region 212 and the first drain region 213 in the same first transistor 200 and the formation of the first source region 211, the first channel region 212 and the first drain region 213 in different first transistors 200 connected through the first through hole can be realized in the second through hole 250 through only one deposition operation, which is conducive to forming a multi-layer memory cell array at one time, and greatly improves the integration density of the dynamic random access memory while ensuring the electrical performance and stability of the memory cell.

[0079] Regarding the gate structure 220, please refer to FIG. 1(a) and FIG. 1(b), the gate structure 220 is disposed in the second recess 123 and is located on at least one side of the first channel region 212 along the first direction. When manufacturing the gate structure 220 disposed in the second recess 123, the gate structures 220 included in all the memory cells 400 can be manufactured at one time by operating the plurality of second through holes, which is conducive to forming a multi-layer memory cell array at one time, and greatly improving the integration density of the dynamic random access memory while ensuring the electrical performance and stability of the memory cell 400.

[0080] The specific structure of the gate structure of the first transistor is not specifically limited in the embodiment of the present invention. It may be a single-gate structure, a double-gate structure or other possible gate structures, which can be determined according to actual needs.

[0081] Exemplarily, the first transistor may be a single-gate structure. The gate structure included in the first transistor is arranged on any side of the first channel region along the third direction.

[0082] For example, the first transistor may be a dual-gate structure. Referring to FIG. 1( a ) and FIG. 1( b ), the first transistor 200 includes a third gate 221 and a fourth gate 222 which are respectively disposed on both sides of the first channel region 212 along the third direction.

[0083] When the above technical solution is adopted, the conventional transistor has only one gate to control the current in the channel region, while the first transistor provided in the embodiment of the present invention has two gates. The dual-gate transistor can have twice the gate control area under the same channel region area, which can effectively improve the gate's control ability over the channel region, which makes the gate's control over the carriers in the channel region more precise and flexible, and can more effectively adjust the conduction and cutoff of the current, thereby improving the switching performance of the transistor provided in the embodiment of the present invention, and can effectively suppress the short channel effect, which is conducive to further reducing the size of the transistor provided in the embodiment of the present invention, thereby improving the storage density of the dynamic random access memory provided in the embodiment of the present invention. For example, under low-voltage operation, the first transistor of the dual-gate structure can control the current more accurately and achieve faster switching conversion, which is conducive to reducing the power consumption of the dynamic random access memory provided in the embodiment of the present invention.

[0084] It can be understood that, in combination with the above description of the gate structure 220, please refer to Figures 1(a) and 1(b), along the first direction, the third gate 221, the first channel region 212 and the fourth gate 222 are stacked and distributed in sequence, and are all arranged in the second recess 123. The first gate dielectric layer 240 is respectively arranged between the third gate 221 and the first channel region 212, and between the fourth gate 222 and the first channel region 212.

[0085] The material of the gate of the first transistor is not specifically limited in the embodiment of the present invention, and may be tantalum, titanium, tantalum nitride, titanium nitride, atomic crystal tungsten selenide, atomic crystal molybdenum selenide or other possible materials, which may be determined according to actual needs. In addition, when the first transistor is a dual-gate structure, the materials of the third gate and the fourth gate may be the same, so as to form the third gate and the fourth gate at the same time; or, the materials of the third gate and the fourth gate may be different, which may be determined according to actual needs.

[0086] Regarding the first source electrode 231 and the first drain electrode 232, as a possible implementation, please refer to FIG. 1(a) and FIG. 1(b), one of the first source electrode 231 and the first drain electrode 232 that is electrically connected to the first gate electrode 321 is integrally continuous with the first gate electrode 321. One of the first source electrode 231 and the first drain electrode 232 that is not electrically connected to the first gate electrode 321 is disposed in the second through hole 250.

[0087] In the case of adopting the above scheme, when manufacturing the dynamic random access memory provided by the embodiment of the present invention, one of the first source and the first drain that is electrically connected to the first gate and the first gate can be formed in the same process step, which is conducive to forming a multi-layer memory cell array at one time, and greatly improves the integration density of the dynamic random access memory while ensuring the electrical performance and stability of the memory cell. In addition, the above two structures are continuous as a whole, and there is no need to use an additional structure to connect them, which is conducive to reducing the area occupied by the memory cell, thereby improving the density of the dynamic random access memory provided by the embodiment of the present invention.

[0088] It should be noted that in Figure 1(a) and Figure 1(b), the first drain 232 may be electrically connected to the first gate 321. This is only an example. The positions of the first drain 232 and the first source 231 may be exchanged, and the positions of the first source region 211 and the first drain region 213 may also be exchanged. The embodiment of the present invention does not specifically limit this.

[0089] The material of the first source electrode and the first drain electrode is not specifically limited in the embodiment of the present invention, and the material may be copper, aluminum, chromium, silver, gold or other possible materials, which may be determined according to actual needs. In addition, the material of the first source electrode and the first drain electrode may be the same, so as to form the first source electrode and the first drain electrode at the same time; or, the material of the first source electrode and the first drain electrode may be different, which may be determined according to actual needs.

[0090] Regarding the above-mentioned first gate dielectric layer 240, in addition to the distribution described above, please refer to Figure 1(a) and Figure 1(b), it also extends to the first gate 321, and the first source 231 or the first drain 232 that is continuous with the first gate 321; and covers the side wall of the first recess 122, extends to the side wall of the first through hole 340, so that the first gate dielectric layer 240 also serves as a part of the gate dielectric layer between the first gate 321 and the second channel region 312; and covers the side wall of the second through hole 250.

[0091] When the above technical solution is adopted, please refer to Figure 1(a) and Figure 1(b). When forming the first gate dielectric layer 240, after forming the first recess 122 and the second recess 123 connected to the first recess 122, the material of the first gate dielectric layer 240 can be directly deposited through processes such as deposition to cover the first recess 122 and the second through hole 250 at the same time, and the first gate dielectric layer 240 of the multiple first transistors 200 included in the dynamic random access memory is formed at the same time, which is conducive to forming a multi-layer memory cell array at one time. On the premise of ensuring the electrical performance and stability of the memory cell, the integration density of the dynamic random access memory is greatly improved.

[0092] Regarding the material of the first gate dielectric layer, traditional materials such as silicon dioxide can be selected to reduce the difficulty of manufacturing the first gate dielectric layer. The material of the first gate dielectric layer can also be selected from high dielectric constant materials such as hafnium-based oxides, aluminum oxide, zirconium oxide, and tantalum oxide to reduce the thickness of the first gate dielectric layer, thereby reducing the volume of the first transistor, which is conducive to forming a multi-layer memory cell array at one time, and greatly improving the integration density of the dynamic random access memory while ensuring the electrical performance and stability of the memory cell.

[0093] The structure and materials of the second transistor are further described below.

[0094] Please refer to FIG. 1(a) and FIG. 1(b), illustratively, the second transistor 300 includes: a second source region 311, a second channel region 312, a second drain region 313, a first gate 321, a second gate 322, a second source 331, a second drain 332, a dielectric isolation layer 341 and a second gate dielectric layer 342. The second source region 311, the second channel region 312 and the second drain region 313 are arranged in the first through hole 340 along the first direction. The second gate 322 is arranged in the first through hole 340, and the second channel region 312 surrounds the outer periphery of the second gate 322. The portion of the dielectric structure corresponding to the second channel region 312 is provided with a first recess 122 recessed inwardly, and the first gate 321 is arranged in the first recess 122. The second transistor 300 includes a second source 331 and a second drain 332, which are respectively arranged in the third recess 333 and the fourth recess 334; the third recess 333 and the fourth recess 334 are respectively arranged on both sides of the first gate 321 along the first direction; the second source 331 is electrically connected to the second source region 311; and the second drain 332 is electrically connected to the second drain region 313. The bottom of the third recess 333 and / or the fourth recess 334 is in contact with the gate structure 220, and the inner wall of the third recess 333 and the inner wall of the fourth recess 334 are also covered with a dielectric isolation layer 341. The dielectric isolation layer 341 electrically isolates the second source 331 and the second drain 332 from the gate structure 220, and the dielectric isolation layer 341 and the first gate dielectric layer 240 electrically isolate the second source 331 from the first gate 321, and the second drain 332 from the first gate 321. The dielectric isolation layer 341 also covers at least the portion of the first gate 321 that contacts the first through hole 340 , so that the dielectric isolation layer 341 and the first gate dielectric layer 240 together serve as a gate dielectric layer between the first gate 321 and the second channel region 312 .

[0095] In the case of adopting the above technical solution, please refer to Figure 1 (a) and Figure 1 (b), the third recess 333 and the fourth recess 334 are formed on both sides of the first recess 122 in the third direction, and are connected to the first through hole 340. The second transistor 300 has a vertical channel structure, which reduces the area occupied by the second source region 311, the second channel region 312 and the second drain region 313 included in the second transistor 300 while ensuring the channel length of the second transistor 300, thereby reducing the area occupied by the second transistor 300, which is beneficial to improving the storage density of the dynamic random access memory. In addition, the second source 331, the second drain 332 and the first gate 321 included in the second transistor 300 are vertically stacked and distributed in the first direction, which reduces the area occupied by the second transistor 300, which is beneficial to improving the storage density of the dynamic random access memory. At the same time, the second source region 311, the second channel region 312, and the second drain region 313 are vertically stacked and distributed in the first through hole 340, and the second source region 311, the second channel region 312, and the second drain region 313 in the same second transistor 300 can be formed by only one deposition operation in the first through hole 340, as well as the second source region 311, the second channel region 312, and the second drain region 313 in different second transistors 300 connected through the first through hole 340. Furthermore, there is only a dielectric isolation layer 341 between the gate structure 240 and the second source 331 and the second drain 332, which avoids them occupying additional area, thereby reducing the area occupied by the memory cell 400, and realizing the one-time formation of a multi-layer memory cell array, and greatly improving the integration density of the dynamic random access memory while ensuring the electrical performance and stability of the memory cell 400.

[0096] Regarding the first gate 321 included in the second transistor 300, please refer to Figures 1(a) and 1(b), which serves as a storage node (SN) included in the 2T0C memory cell 400. In addition, the first gate 321 is electrically connected to the first source 231 or the first drain 232. Exemplarily, the first gate 321 is integrally continuous with the first source 231 or the first drain 232.

[0097] The material of the first gate is not specifically limited in the embodiment of the present invention, and it may be tantalum, titanium, tantalum nitride, titanium nitride, atomic crystal tungsten selenide, atomic crystal molybdenum selenide or other possible materials, which can be determined according to actual needs.

[0098] Regarding the second source region 311, the second channel region 312 and the second drain region 313, please refer to Figure 1(a) and Figure 1(b). They are arranged in the first through hole 340 along the first direction. In other words, they cover the inner wall of the first through hole 340 close to the first gate 321 and form a vertical channel for the second transistor 300.

[0099] The materials of the second source region, the second channel region, and the second drain region are not specifically limited in the embodiment of the present invention and can be determined according to actual needs.

[0100] Exemplarily, the materials of the second source region, the second channel region, and the second drain region may be indium zinc oxide, tin-doped indium oxide, indium oxide, zinc oxide, titanium oxide, or other possible materials.

[0101] When the above technical solution is adopted, the beneficial effects of using the above-mentioned types of materials for the second source region, the second channel region and the second drain region can be referred to the relevant description of the first transistor regarding the device type of the first transistor, and will not be repeated here.

[0102] Regarding the second source and the second drain included in the second transistor, the embodiment of the present invention does not specifically limit their positions, as long as they can facilitate the parallel integration of the dynamic random access memory.

[0103] Regarding the material of the above-mentioned dielectric isolation layer, traditional materials such as silicon dioxide can be selected to reduce the process difficulty of manufacturing the dielectric isolation layer. The material of the dielectric isolation layer can also be selected from high dielectric constant materials such as hafnium-based oxides, aluminum oxide, zirconium oxide, tantalum oxide, etc. to reduce the thickness of the dielectric isolation layer, thereby reducing the volume of the second transistor and improving the integration.

[0104] The material of the second source and the second drain is not specifically limited in the embodiment of the present invention, and can be copper, aluminum, chromium, silver, gold or other possible materials, which can be determined according to actual needs. In addition, the materials of the second source and the second drain can be the same, so that the second source and the second drain are formed at the same time; or, the materials of the second source and the second drain can be different, which can be determined according to actual needs.

[0105] Regarding the second gate included in the second transistor, please refer to FIG. 1( a ) and FIG. 1( b ), which is disposed in the first through hole 340 and on the second channel region 312 .

[0106] The material of the second gate is not specifically limited in the embodiment of the present invention, and it may be copper tantalum, titanium, tantalum nitride, titanium nitride, atomic crystal tungsten selenide, atomic crystal molybdenum selenide or other possible materials, which can be determined according to actual needs.

[0107] In addition, referring to FIG. 1( a ) and FIG. 1( b ), the second channel region 312 surrounds the outer periphery of the second gate 322 , and a second gate dielectric layer 342 is disposed between the second gate 322 and the second channel region 312 .

[0108] Regarding the material of the second gate dielectric layer, traditional materials such as silicon dioxide can be selected to reduce the process difficulty of manufacturing the second gate dielectric layer. The material of the second gate dielectric layer can also be selected from high dielectric constant materials such as hafnium-based oxides, aluminum oxide, zirconium oxide, and tantalum oxide to reduce the thickness of the second gate dielectric layer, thereby reducing the volume of the second transistor and improving the integration.

[0109] In actual application, the embodiment of the present invention does not specifically limit the shapes of the first through hole and the second through hole, which may be cylindrical holes, prismatic holes or other possible shapes, and the embodiment of the present invention does not specifically limit them. Exemplarily, the shapes of the first through hole and the second through hole are both prismatic holes, and the adjacent two sides of the cross section of the first through hole and the cross section of the second through hole are parallel to the second direction and the third direction respectively.

[0110] Regarding the dielectric structure for isolating different storage units, exemplarily, the dielectric structure includes a first dielectric portion, a second dielectric portion, a first dielectric filling portion, a second dielectric filling portion, and a third dielectric filling portion.

[0111] Specifically, please refer to Figure 1(a) and Figure 1(b). Along the first direction, the first dielectric portion 110 isolates two adjacent storage units 400, and is recessed inward from the first through hole 340 to form a first recess 122, and is recessed inward from the second through hole 250 to form a second recess 123.

[0112] 1( a ) and 1( b ), along the second direction, the second dielectric portion 120 electrically isolates the first source region 211 , the first channel region 212 , the first drain region 213 and the first gate 321 of two adjacent memory cells 400 .

[0113] When the above technical solution is adopted, the second dielectric part isolates the first source region, the first channel region, the first drain region and the first gate region of two adjacent storage units along the second direction, so as to achieve the isolation of the data stored in the two adjacent storage units. In addition, the second dielectric part can also serve as a support to prevent the stacking structure from bending after the first notch and the second notch are formed, which is conducive to the regular structure of the storage unit, thereby ensuring the normal operation and stable performance of the storage unit manufactured by the manufacturing method of the dynamic random access memory provided by the embodiment of the present invention, thereby improving the yield.

[0114] The material of the second dielectric part is not specifically limited in the embodiment of the present invention and can be determined according to actual needs. For example, the material of the second dielectric part may include silicon oxide, silicon nitride, or polysilicon.

[0115] 1(a) and 1(b), along the second direction, the first dielectric filling part 130 isolates two adjacent first through holes 340, and the second dielectric filling part 140 isolates two adjacent second through holes 250. The third dielectric filling part is disposed in the first through hole 340 and the second through hole 250.

[0116] The embodiments of the present invention do not specifically limit the materials of the first dielectric part, the first dielectric filling part, the second dielectric filling part, and the third dielectric filling part, as long as they can meet the insulation and strength requirements for them. For example, silicon oxide or silicon nitride can be used. In addition, the materials of the first dielectric part, the first dielectric filling part, the second dielectric filling part, and the third dielectric filling part can be the same, so that the interface between them is regular and the contact interface strength is higher; or, the materials of the first dielectric part, the first dielectric filling part, the second dielectric filling part, and the third dielectric filling part can be different to meet other design requirements.

[0117] The distribution of storage units is further described below.

[0118] Referring to the above example and to FIG. 1(a) and FIG. 1(b), one of the first source 231 and the second drain 332 that is not electrically connected to the first gate 321 extends along the first direction, covers the sidewall of the second through hole 250 located in the first dielectric portion 110, and is connected to one of the first source 231 and the second drain 332 that is not electrically connected to the first gate 321 included in the first transistor 200 adjacent to the first direction, to form a write bit line (WBL). The first gate dielectric layer 240 also extends with the write bit line. In addition, the gate structure 220 is also disposed on the first dielectric portion 110, and extends along the second direction, and is connected to the gate structure 220 included in the first transistor adjacent to the second direction to form a write word line (WWL). The second source 331 and the second drain 332 are also arranged on the first dielectric portion 110 and extend along the second direction, and are connected to the second source 331 and the second drain 332 included in the first transistor 200 adjacent to the first direction, so as to form a first signal line and a second signal line respectively, the first signal line is used as a read bit line (RBL), and the second signal line is grounded. In the first through hole 340, the second gate 322 extends along the first direction, and is connected to the second gate 322 of the second transistor 300 adjacent to the first direction, and serves as a read word line (RWL). The second source region 311, the second channel region 312, the second drain region 313, and the second gate dielectric layer 342 arranged between the second channel region 312 and the second gate 322 also extend along the first direction.

[0119] Please refer to Figure 1(a) and Figure 1(b). In the second through hole 250, multiple first transistors 200 connected to the write bit line set in the second through hole 250 constitute a first transistor 200 column. In the same second through hole 250, at least two first transistor 200 columns are set and electrically isolated by the third dielectric filling part 150.

[0120] Please refer to Figure 1(a) and Figure 1(b). In the first through hole 340, multiple second transistors 300 connected to the write bit line set in the first through hole 340 constitute a second transistor 300 column. In the same first through hole 340, at least two second transistor 300 columns are set and electrically isolated by the third dielectric filling part 150.

[0121] In a second aspect, an embodiment of the present invention further provides a method for manufacturing a dynamic random access memory. Referring to FIG. 1(a) and FIG. 1(b), the method for manufacturing the dynamic random access memory includes: forming a plurality of memory cells 400 distributed in a three-dimensional array, and forming a dielectric structure for isolating different memory cells 400; the plurality of memory cells 400 distributed in a three-dimensional array include multiple memory layers spaced apart along a first direction, each memory layer includes multiple memory groups spaced apart along a second direction, and each memory group includes multiple memory cells 400 spaced apart along a third direction; the first direction, the second direction and the third direction are different from each other; each memory cell 400 includes a first transistor 200 and a second transistor 300 distributed along the third direction; the second transistor 300 is a dual-gate structure; in the same memory cell 400, one of the first source 231 or the first drain 232 included in the first transistor 200 is electrically connected to the first gate 321 included in the second transistor 300; the dielectric structure is provided with first through holes 340 and second through holes 250 spaced apart along the third direction; the second transistor 300 includes The second source region 311, the second channel region 312 and the second drain region 313 of the second transistor 300 are arranged in the first through hole 340 along the first direction; the second gate 322 included in the second transistor 300 is arranged in the first through hole 340, and the second channel region 312 included in the second transistor 300 is surrounded by the outer periphery of the second gate 322; the dielectric structure is provided with a first indentation 122 inwardly concave at a portion corresponding to the second channel region 312 included in the second transistor 300, and the first gate 321 included in the second transistor 300 is arranged in the first through hole 340. a recess 122; one of the first source 231 or the first drain 232 that is not electrically connected to the first gate 321 is arranged in the second through hole 250; a portion of the first source 231 or the first drain 232 corresponding to the second through hole 250 of the dielectric structure is provided with a second recess 123 recessed inwardly, and the second recess 123 is connected to the first recess 122; the first transistor 200 includes a first source region 211, a first channel region 212 and a first drain region 213 distributed in the second recess 123 along a third direction.

[0122] Compared with the prior art, the beneficial effects of the method for manufacturing a dynamic random access memory provided by the embodiment of the present invention are the same as the beneficial effects of the dynamic random access memory provided by the first aspect, and are not described in detail here.

[0123] The following will describe the process of manufacturing a dynamic random access memory according to the schematic diagrams and flow charts of the operations shown in FIG. 1(a) and FIG. 1(b) to FIG. 15(a) and FIG. 15(b). Exemplarily, the method of manufacturing the dynamic random access memory includes the following steps:

[0124] As shown in FIG. 3(a) and FIG. 3(b), a stacking structure and a first dielectric filling part 130 and a second dielectric filling part 140 penetrating the stacking structure along a first direction are formed; the stacking structure includes a multi-layer stacking unit stacked along the first direction. The stacking unit includes two first dielectric layers 111 spaced apart along the first direction, and a stack located between the two first dielectric layers 111. The stack includes two metal layers 223 spaced apart along the first direction, and a second dielectric layer 121 located between the two metal layers 223. The materials of the first dielectric layer 111, the metal layer 223, and the second dielectric layer 121 are different from each other. A third through hole 131 and a fourth through hole 141 penetrating along the first direction are provided in the stacking structure, and the third through hole 131 and the fourth through hole 141 are spaced apart. The first dielectric filling part 130 is filled in the third through hole 131, and the second dielectric filling part 140 is filled in the fourth through hole 141.

[0125] As a possible implementation scheme, please refer to FIG. 3( a ) and FIG. 3( b ), along the second direction, the first medium filling portion 130 is disposed between two adjacent first through holes 340 ; along the second direction, the second medium filling portion 140 is disposed between two adjacent second through holes 250 .

[0126] Specifically, referring to FIG. 1(a) and FIG. 1(b), the first dielectric layer 111 is used to form the first dielectric portion 110, isolating the memory cell 400 along the first direction. The two metal layers 223 included in the stack are used to form the third gate 221 and the fourth gate 222 included in the first transistor 200, and as a placeholder layer, to form the third recess 333 and the fourth recess 334. The second dielectric layer 121 is used as a sacrificial layer and is partially removed later to occupy the first source region 211, the first channel region 212, the first drain region 213, the first gate 321, and the first source 231 and the first drain 232 which are continuous with the first gate 321 in advance, so as to facilitate the subsequent formation of these five structures.

[0127] It should be noted, referring to Figure 1(a) and Figure 1(b), that along the first direction, the two outermost layers of the stacking structure are the first dielectric layer 111, and the thickness of the two outermost layers of the first dielectric layer 111 of the stacking structure can be greater than the first dielectric layer 111 located inside the stacking structure, so as to protect the stacking structure and other structures formed subsequently.

[0128] In one example, see Figure 4 , and FIG. 3(a) and FIG. 3(b), Figure 5 6(a) and 6(b), the above-mentioned forming of the stacked structure and forming the first medium filling part 130 and the second medium filling part 140 penetrating the stacked structure along the first direction include the following steps:

[0129] Please refer to Figure 4 The stacked material layer is formed by epitaxy or other processes. The stacked material layer includes a plurality of stacked units stacked along a first direction.

[0130] Next, please refer to Figure 5 6(a) and 6(b), a third through hole 131 and a fourth through hole 141 penetrating the stacked material layer are formed by dry etching and other processes; along the second direction, the third through hole 131 is arranged between two adjacent first through holes 340; along the second direction, the fourth through hole 141 is arranged between two adjacent second through holes 250.

[0131] In the case of adopting the above technical solution, please refer to Figure 3 (a) and Figure 3 (b), the first dielectric filling part 130 and the second dielectric filling part 140 serve as an isolation layer between the adjacent storage units 400 along the second direction, which is conducive to avoiding leakage of the adjacent storage units 400 along the second direction. In addition, in the subsequent step of partially removing the second dielectric layer 121, the two metal layers 223 in the stacking unit will be suspended, and the first dielectric filling part 130 and the second dielectric filling part 140 can be used as a support to avoid bending of the stacking structure, which is conducive to the regular structure of the storage unit 400, thereby ensuring the normal operation and stable performance of the storage unit 400 manufactured by the manufacturing method of the dynamic random access memory provided by the embodiment of the present invention, thereby improving the yield.

[0132] In another example, the above-mentioned method of forming a stacking structure, and forming a first medium filling part and a second medium filling part that penetrate the stacking structure along a first direction may also be to first form a portion of the stacking material layer and form a third through hole and a fourth through hole, and then form another portion of the stacking material layer and form a third through hole and a fourth through hole; repeat the above process to finally form a stacking structure.

[0133] Next, referring to FIG. 6( a ) and FIG. 6( b ), the first dielectric filling portion 130 is filled in the third through hole 131 , and the second dielectric filling portion 140 is filled in the fourth through hole 141 by a deposition process.

[0134] 7(a) and 7(b), a plurality of first through holes 340 penetrating the stacked structure and spaced apart along the second direction are formed by dry etching or other processes. Along the second direction, the first dielectric filling part 130 is disposed between two adjacent first through holes 340.

[0135] Next, referring to FIG. 7( a ) and FIG. 7( b ), along the third direction, edge portions of the two metal layers 223 close to the first through hole 340 are selectively etched by dry etching or the like to form a third recess 333 and a fourth recess 334 .

[0136] Next, referring to FIG. 8( a ) and FIG. 8( b ), a dielectric isolation layer 341 is formed in the third recess 333 , the fourth recess 334 and the first through hole 340 by a deposition process and a selective etching process such as dry etching.

[0137] Next, please refer to Figure 9(a) and Figure 9(b). Through deposition and other processes, as well as selective etching processes such as dry etching, a second source 331 included in the second transistor 300 is formed in the third recess 333, and a second drain 332 included in the second transistor 300 is formed in the fourth recess 334.

[0138] In the actual manufacturing process, referring to FIG. 9( a) and FIG. 9( b), a first electrode layer may be formed in the first through hole 340, in the third recess 333, and in the fourth recess 334. Then, the portion of the first electrode layer located in the first through hole 340 is selectively etched to form a second source electrode 331 and a second drain electrode 332.

[0139] When the above technical solution is adopted, the second source and the second drain of multiple storage units included in the dynamic random access memory manufactured by the manufacturing method provided in the embodiment of the present invention can be formed at the same time, which is conducive to the one-time formation of a multi-layer storage unit array. Under the premise of ensuring the electrical performance and stability of the storage unit, the integration density of the dynamic random access memory is greatly improved.

[0140] Next, please refer to Figure 10(a) and Figure 10(b). Through deposition and other processes, as well as selective etching processes such as dry etching, a second transistor 300 including a second source region 311, a second channel region 312 and a second drain region 313 is formed in the first through hole 340 along the first direction; the second source 331 is connected to the second source region 311; and the second drain 332 is connected to the second drain region 313.

[0141] Next, referring to FIG. 10( a) and FIG. 10( b), a second gate dielectric layer 342 included in the second transistor 300 is formed in the first through hole 340 by a deposition process or the like and a selective etching process or the like of dry etching. The second gate dielectric layer 342 is formed on the second source region 311, the second channel region 312 and the second drain region 313.

[0142] Next, referring to FIG. 10( a ) and FIG. 10 ( b ), a second gate 322 included in the second transistor 300 is formed in the first through hole 340 by a deposition process or the like.

[0143] It can be understood that in order to ensure the regularity of other structures subsequently formed in the first through hole, or to achieve electrical isolation, after the structure is formed in the first through hole, the manufacturing method provided in the embodiment of the present invention also includes: selectively etching the structure formed in the first through hole to separate the structure formed in the first through hole in a third direction.

[0144] 11(a) and 11(b), a plurality of second through holes 250 penetrating the stacked structure and spaced apart along the second direction are formed by dry etching or other processes. Along the second direction, the second dielectric filling portion 140 is disposed between two adjacent second through holes 250.

[0145] Next, referring to FIG. 12(a) and FIG. 12(b), a portion of the second dielectric layer 121 located between the first through hole 340 and the second through hole 250 and adjacent to the second through hole 250 in the third direction is removed by dry etching or wet etching, so that the remaining second dielectric layer 121 forms a second dielectric portion 120. Along the second direction, the second dielectric portion 120 electrically isolates the first source region 211, the first channel region 212, the first drain region 213 and the first gate 321 included in two adjacent memory cells.

[0146] When the above technical solution is adopted, the second dielectric part isolates the first source region, the first channel region, the first drain region and the first gate region of two adjacent storage units along the second direction, so as to achieve the isolation of the data stored in the two adjacent storage units. In addition, the second dielectric part can also serve as a support to prevent the stacking structure from bending after the first notch and the second notch are formed, which is conducive to the regular structure of the storage unit, thereby ensuring the normal operation and stable performance of the storage unit manufactured by the manufacturing method of the dynamic random access memory provided by the embodiment of the present invention, thereby improving the yield.

[0147] Next, referring to FIG. 13( a ) and FIG. 13( b ), a first gate dielectric layer 240 included in the first transistor 200 is formed in the third recess 333 and in the second through hole 250 by deposition or other processes.

[0148] Next, referring to FIG. 14( a) and FIG. 14( b), a first gate electrode 321 included in the second transistor 300 and one of the first source electrode 231 and the first drain electrode 232 electrically connected to the first gate electrode 321 are formed in the first recess 122 by a deposition process or the like and a selective etching process or the like such as dry etching to form the second transistor 200. A first source region 211, a first channel region 212 and a first drain region 213 included in the first transistor 200 are formed in the second recess 123.

[0149] It can be understood that, referring to Figures 14(a) and 14(b), in the above process steps, the first gate 321 and one of the first source 231 and the first drain 232 electrically connected to the first gate 321 are first formed, and then the first source region 211, the first channel region 212 and the first drain region 213 are formed.

[0150] In the actual manufacturing process, please refer to FIG. 14(a) and FIG. 14(b), the second electrode layer can be formed in the second through hole 250, in the first recess 122, and in the second recess 123 by a deposition process. Next, the portion of the second electrode layer located in the second through hole 250 and in the second recess 123 is selectively etched to form the first gate 321, and one of the first source 231 and the first drain 232 electrically connected to the first gate 321.

[0151] When the above technical solution is adopted, the first gates of multiple memory cells included in the dynamic random access memory manufactured by the manufacturing method provided by the embodiment of the present invention, and one of the first source and the first drain electrically connected to the first gate can be formed at one time, which is conducive to forming a multi-layer memory cell array at one time. Under the premise of ensuring the electrical performance and stability of the memory cell, the integration density of the dynamic random access memory is greatly improved.

[0152] Please refer to the relevant description of the first aspect. The first transistor is an indium zinc oxide thin film transistor, a tin-doped indium oxide thin film transistor, an indium oxide thin film transistor, a zinc oxide thin film transistor or a titanium oxide thin film transistor, that is, the materials of the first source region, the first channel region and the first drain region include: indium zinc oxide, tin-doped indium oxide, indium oxide, zinc oxide or titanium oxide.

[0153] When the above technical solution is adopted, the above-mentioned metal oxide thin film transistors can be manufactured by a low-temperature process. The low-temperature process can reduce the demand for expensive high-temperature equipment and complex process steps, thereby reducing costs. Moreover, in the manufacturing method provided in the embodiment of the present invention, the first transistor is formed after the second transistor is formed. The first transistor is manufactured by a low-temperature process to avoid damaging the structure of other dynamic random access memories formed previously, which is beneficial to the integrity of the structure of other dynamic random access memories, thereby improving the yield of the dynamic random access memories.

[0154] Next, through deposition and other processes, as well as selective etching processes such as dry etching, refer to FIG. 15( a ) and FIG. 15( b ), one of the first source 231 and the first drain 232 that is not electrically connected to the first gate 321 is formed in the second through hole 250 .

[0155] It should be noted that FIG. 15( a ) and FIG. 15( b ) only show the situation where the first source electrode 231 is disposed in the second through hole 250 , and the positions of the first source electrode 231 and the first drain electrode 232 can be exchanged, which is not specifically limited in the embodiment of the present invention.

[0156] It can be understood that in order to ensure the regularity of other structures subsequently formed in the second through hole, or to achieve electrical isolation, after the structure is formed in the second through hole, the manufacturing method provided in the embodiment of the present invention also includes: selectively etching the structure formed in the second through hole to separate the structure formed in the second through hole in a third direction.

[0157] Next, by deposition and other processes, please refer to FIG. 1( a ) and FIG. 1( b ), a third dielectric filling portion 150 is formed in the second through hole 250 .

[0158] Regarding the undescribed contents such as materials, positions, etc. of the various structures manufactured by the manufacturing method of the above-mentioned dynamic random access memory and their beneficial effects, please refer to the relevant description of the first aspect and will not be repeated here.

[0159] In the case of adopting the above technical solution, please refer to FIG. 14 (a) and FIG. 14 (b), the first through hole 340 is connected to the first recess 122, the first through hole 340 is connected to the third recess 333, the first through hole 340 is connected to the fourth recess 334, and the second through hole 250 is connected to the second recess 123. After forming the first through hole 340 and the second through hole 250, the above structures included in the first transistor 200 and the second transistor 300 are formed by the processing technology in the first through hole 340 and the second through hole 250, thereby realizing the simultaneous manufacture of the memory cell 400 arranged in the same first through hole 340, and the stacking structure includes a plurality of first through holes 340, so that the plurality of memory cells 400 arranged in the plurality of first through holes 340 can be processed at the same time, so that all the memory cells 400 included in the dynamic random access memory can be manufactured at the same time, which is conducive to realizing the one-time formation of a multi-layer memory cell array, and greatly improving the integration density of the dynamic random access memory under the premise of ensuring the electrical performance and stability of the memory cell.

[0160] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0161] The embodiments of the present invention are described above. However, these embodiments are only for illustrative purposes and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A dynamic random access memory, characterized in that: include: A plurality of storage units distributed in a three-dimensional array, and a medium structure for isolating different storage units; the plurality of storage units distributed in a three-dimensional array include multiple storage layers distributed at intervals along a first direction, each storage layer includes multiple storage groups distributed at intervals along a second direction, each storage group includes multiple storage units distributed at intervals along a third direction; the first direction, the second direction and the third direction are different from each other; Each of the memory cells comprises a first transistor and a second transistor distributed along the third direction; the second transistor is a dual-gate structure; in the same memory cell, one of a first source and a first drain included in the first transistor is electrically connected to a first gate included in the second transistor; The dielectric structure is provided with a first through hole and a second through hole spaced apart along the third direction; the second source region, the second channel region and the second drain region included in the second transistor are provided in the first through hole along the first direction; the second gate included in the second transistor is provided in the first through hole, and the second channel region included in the second transistor is surrounded by the outer periphery of the second gate; the dielectric structure is provided with a first indentation concave inwardly at a portion corresponding to the second channel region included in the second transistor, and the first gate included in the second transistor is provided in the first indentation; One of the first source and the first drain that is not electrically connected to the first gate is arranged in the second through hole; a second recess that is recessed inward is arranged in a portion of the dielectric structure corresponding to the second through hole, and the second recess is connected to the first recess; a first source region, a first channel region and a first drain region included in the first transistor are distributed in the second recess along the third direction.

2. The dynamic random access memory according to claim 1, wherein: The first transistor has a dual-gate structure; a third gate and a fourth gate included in the first transistor are respectively arranged on two sides of the first channel region along the third direction.

3. The dynamic random access memory according to claim 1, wherein: The gate structure included in the first transistor is arranged in the second recess and is located on at least one side of the first channel region along the first direction; one of the first source and the first drain that is not electrically connected to the first gate is isolated from the gate structure by a first gate dielectric layer included in the first transistor.

4. The dynamic random access memory according to claim 1, wherein: The second transistor includes a second source and a second drain, which are respectively arranged in a third notch and a fourth notch; the third notch and the fourth notch are respectively arranged on both sides of the first gate along the first direction; the second source is electrically connected to the second source region; and the second drain is electrically connected to the second drain region.

5. The dynamic random access memory according to claim 1, wherein: The first transistor is an indium zinc oxide thin film transistor, a tin-doped indium oxide thin film transistor, an indium oxide thin film transistor, a zinc oxide thin film transistor or a titanium oxide thin film transistor.

6. The dynamic random access memory according to claim 1, wherein: One of the first source and the first drain, which is electrically connected to the first gate, is integrally continuous with the first gate.

7. A method for manufacturing a dynamic random access memory, characterized in that: include: A plurality of storage units distributed in a three-dimensional array and a medium structure for isolating different storage units are formed; the plurality of storage units distributed in a three-dimensional array include multiple storage layers spaced apart along a first direction, each storage layer includes multiple storage groups spaced apart along a second direction, each storage group includes multiple storage units spaced apart along a third direction; the first direction, the second direction and the third direction are different from each other; Each of the memory cells comprises a first transistor and a second transistor distributed along the third direction; the second transistor is a dual-gate structure; in the same memory cell, one of the first source or the first drain of the first transistor is electrically connected to the first gate of the second transistor; The dielectric structure is provided with a first through hole and a second through hole spaced apart along the third direction; the second source region, the second channel region and the second drain region included in the second transistor are provided in the first through hole along the first direction; the second gate included in the second transistor is provided in the first through hole, and the second channel region included in the second transistor is surrounded by the outer periphery of the second gate; the dielectric structure is provided with a first indentation concave inwardly at a portion corresponding to the second channel region included in the second transistor, and the first gate included in the second transistor is provided in the first indentation; The first source or the first drain, whichever is not electrically connected to the first gate, is arranged in the second through hole; a second recess recessed inwardly is arranged in a portion of the dielectric structure corresponding to the first source or the first drain in the second through hole, and the second recess is connected to the first recess; a first source region, a first channel region and a first drain region included in the first transistor are distributed in the second recess along the third direction.

8. The method for manufacturing a dynamic random access memory according to claim 7, characterized in that: Forming a plurality of the storage units distributed in a three-dimensional array, and forming the medium structure for isolating different storage units comprises: A stacking structure is formed, and a first dielectric filling part and a second dielectric filling part are formed that penetrate the stacking structure along the first direction; the stacking structure comprises a multi-layer stacking unit stacked along the first direction; the stacking unit comprises two first dielectric layers spaced apart along the first direction, and a stacked layer located between the two first dielectric layers; the stacked layer comprises two metal layers spaced apart along the first direction, and a second dielectric layer located between the two metal layers; the materials of the first dielectric layer, the metal layer and the second dielectric layer are different from each other; a third through hole and a fourth through hole are provided in the stacking structure that penetrate along the first direction, and the third through hole and the fourth through hole are spaced apart; the first dielectric filling part is filled in the third through hole, and the second dielectric filling part is filled in the fourth through hole; forming a plurality of first through holes penetrating the stacked structure and spaced apart along the second direction; Selectively etching edge portions of the two metal layers close to the first through hole along the third direction to form a third notch and a fourth notch; forming a dielectric isolation layer in the third notch, the fourth notch and the first through hole; forming a second source electrode included in the second transistor in the third notch, and forming a second drain electrode included in the second transistor in the fourth notch; A second source region, a second channel region and a second drain region included in the second transistor are formed in the first through hole along the first direction; the second source electrode is connected to the second source region; and the second drain electrode is connected to the second drain region; A second gate dielectric layer included in the second transistor is formed in the first through hole; the second gate dielectric layer is formed on the second source region, the second channel region and the second drain region; forming a second gate included in the second transistor in the first through hole; forming a plurality of second through holes penetrating the stacked structure and spaced apart along the second direction; Partially removing the second dielectric layer to form the first recess and the second recess, and making the remaining metal layer form a gate structure included in the first transistor; forming a first gate dielectric layer included in the first transistor in the second notch and the second through hole; forming a first gate electrode and one of the first source electrode and the first drain electrode electrically connected to the first gate electrode included in the second transistor in the first recess; and forming a first source region, a first channel region and a first drain region included in the first transistor in the second recess; One of the first source and the first drain that is not electrically connected to the first gate is formed in the second through hole.

9. The method for manufacturing a dynamic random access memory according to claim 8, characterized in that: The forming of the stacked structure, and forming a first medium filling portion and a second medium filling portion penetrating the stacked structure along the first direction include: Forming a stacked material layer; the stacked material layer includes a plurality of stacked units stacked along a first direction; forming a third through hole and a fourth through hole penetrating the stacked material layer; along the second direction, the third through hole is arranged between two adjacent first through holes; along the second direction, the fourth through hole is arranged between two adjacent second through holes; The first medium filling part is filled in the third through hole, and the second medium filling part is filled in the fourth through hole.

10. The method for manufacturing a dynamic random access memory according to claim 9, wherein: The partially removing the second dielectric layer further comprises: A portion of the second dielectric layer located between the first through hole and the second through hole and adjacent to the second through hole in the third direction is removed so that the remaining second dielectric layer forms a second dielectric portion; along the second direction, the second dielectric portion electrically isolates the first source region, the first channel region, the first drain region and the first gate included in two adjacent storage cells.

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