Low-capacitance electrostatic protection device and manufacturing method thereof

Abstract

The invention provides a low-capacitance electrostatic protection device and a manufacturing method thereof, the low-capacitance electrostatic protection device comprises an N-type heavily doped substrate, a first P-type epitaxial layer and a second P-type epitaxial layer, the resistivity of the first P-type epitaxial layer is high, the first P-type epitaxial layer and the second P-type epitaxial layer are internally provided with an N-type inversion layer, an isolation deep groove and a P-type heavily doped buried layer which are matched with each other, and the N-type inversion layer, the isolation deep groove and the P-type heavily doped buried layer are arranged in the N-type heavily doped substrate. The N-type inversion layer is divided by the P-type heavily doped buried layer, the length of the inner side part, divided by the isolation deep groove, of the P-type heavily doped buried layer is W1, W1 is larger than the thickness of the N-type inversion layer, the P-type heavily doped buried layer, the first P-type epitaxial layer and the N-type heavily doped substrate form a PIN diode, H is the distance between the P-type heavily doped buried layer and the N-type heavily doped substrate, and W2 is the distance between the P-type heavily doped buried layer and the N-type heavily doped substrate. And the breakdown voltage of the PIN diode can be changed along with the adjustment of the H. The electrostatic protection device has the beneficial effects that the electrostatic protection device with ultralow parasitic capacitance and adjustable breakdown voltage can be realized.

Description

Technical Field

[0001] The present invention relates to the technical field of electrostatic protection devices, and in particular to a low-capacitance electrostatic protection device and a manufacturing method thereof. Background Art

[0002] Electrostatic discharge (ESD) and electrical overstress (EOS) are natural phenomena in the application environment of electronic equipment. These phenomena will not only cause electronic equipment to fail and greatly reduce the reliability of the product, but in severe cases, they may even directly cause irreversible damage to the electronic equipment. One of the effective ways to solve ESD and EOS is to add transient voltage suppressors (TVS) to various interfaces of the system. TVS can provide efficient static and surge protection for back-end circuits or chips, and is a very common static protection device.

[0003] In recent years, as the system architecture of electronic products has become increasingly complex, the frequency of signal transmission within electronic systems has continued to rise, and the transmission speed has also become faster and faster. In high-speed signal transmission lines, the presence of capacitance will affect the signal, such as causing signal attenuation and distortion. At this time, it is required that the electrostatic protection device must have a low capacitance characteristic, so that the high-speed signal can avoid damage from ESD and EOS during transmission, and maintain the signal quality and transmission speed without being interfered with by the electrostatic protection device. However, in the prior art, it is often difficult to achieve the low capacitance characteristics of the electrostatic protection device.

[0004] As shown in Figure 1 (a), for on-chip and off-chip electrostatic protection, avalanche diodes are usually used in the prior art. The negative pole of the avalanche diode is usually connected to the "I / O or power port", while its positive pole is usually connected to the "ground port". When a positive ESD pulse comes, the avalanche diode is reverse-biased and avalanche-conducted, and its avalanche breakdown voltage usually needs to be higher than the maximum operating voltage of the port. When a negative ESD pulse comes, the avalanche diode is forward-biased and turned on, which is equivalent to a forward-biased PN junction. Figure 1 (b) shows the structure of a vertical avalanche diode, which is made on an N-type heavily doped substrate, grows a P-type epitaxial layer, and then isolates the deep trench and the P-type heavily doped active area. Generally speaking, the doping concentration of the P-type epitaxial layer is heavy to obtain a lower and suitable avalanche breakdown voltage. At this time, the overall parasitic capacitance of the avalanche diode is large and cannot be used for electrostatic protection of high-speed I / O ports.

[0005] As shown in Figure 2 (a) and Figure 2 (b), in order to reduce the parasitic capacitance of the avalanche tube, a high-resistivity P-type epitaxial layer can be used, thereby reducing the junction capacitance of the N-type heavily doped substrate / P-type epitaxial layer (corresponding to Figure 2 (a), representing the situation of "the doping type of the substrate and the epitaxy is different") or the junction capacitance of the N-type active area / P-type epitaxial layer (corresponding to Figure 2 (b), representing the situation of "the doping type of the substrate and the epitaxy is the same"). However, due to the existence of the oxide layer charge C (usually positive charge), an "N-type inversion layer" will be formed on the high-resistance P-type epitaxy side. These inversion layers are connected to the N-type heavily doped substrate or the N-type heavily doped active area, which ultimately increases the junction area equivalently, introduces additional N-type heavily doped substrate or active area / P-type epitaxy parasitic capacitance, and worsens the overall parasitic capacitance. At the same time, the avalanche breakdown voltage of the N-type heavily doped substrate or active area / P-type epitaxial junction will also increase with the increase of the resistivity of the epitaxial layer. The excessively high breakdown voltage cannot meet the effective electrostatic protection of some low-voltage circuit ports, such as 3.3V / 5V USB (Universal Serial Bus) and HDMI (High-Definition Multimedia Interface) ports. Therefore, this method cannot meet people's usage needs. Summary of the invention

[0006] In order to solve the problems in the prior art, the present invention provides a low-capacitance electrostatic protection device and a manufacturing method thereof. By arranging mutually coordinated N-type heavily doped substrates, a first P-type epitaxial layer, a second P-type epitaxial layer, an N-type inversion layer, an isolation deep trench and a P-type heavily doped buried layer in the low-capacitance electrostatic protection device, the high-resistance first P-type epitaxial layer and the second N-type inversion layer can reduce the capacitance of the entire electrostatic protection device, that is, a new type of longitudinal avalanche diode structure is designed, which can effectively shield the deterioration of the capacitance of the electrostatic protection device caused by the N-type inversion layer caused by the oxide charge, and can solve the contradiction between parasitic capacitance and avalanche breakdown voltage, and finally realize an electrostatic protection device with ultra-low parasitic capacitance and adjustable breakdown voltage, which is particularly suitable for electrostatic and surge protection of high-speed I / O ports, and solves the problem that it is difficult to achieve the low capacitance characteristics of electrostatic protection devices in the prior art, resulting in difficulty in meeting people's use needs.

[0007] The present invention provides a low-capacitance electrostatic protection device, comprising an N-type heavily doped substrate and a first P-type epitaxial layer and a second P-type epitaxial layer arranged from bottom to top in the N-type heavily doped substrate, wherein the resistivity of the first P-type epitaxial layer is high resistance, and the first P-type epitaxial layer and the second P-type epitaxial layer are provided with matching N-type inversion layers and isolation deep trenches, and a P-type heavily doped buried layer is further provided between the first P-type epitaxial layer and the second P-type epitaxial layer, and the N-type inversion layer is divided into a first N-type inversion layer and a second N-type inversion layer by the P-type heavily doped buried layer, and the P-type heavily doped buried layer is divided into two parts by the isolation deep trench, and the inner part of the P-type heavily doped buried layer divided by the isolation deep trench is long. The thickness is W1, W1>the thickness of the N-type inversion layer, the lower surface of the N-type heavily doped substrate can be connected to the I / O port one, the upper surface of the second P-type epitaxial layer is provided with a P+ heavily doped active area that can be connected to the I / O port two, the P-type heavily doped buried layer, the first P-type epitaxial layer, and the N-type heavily doped substrate together constitute a PIN diode, the effective thickness H of the first P-type epitaxial layer is the distance between the P-type heavily doped buried layer and the N-type heavily doped substrate, the breakdown voltage of the PIN diode can be changed with the effective thickness H of the first P-type epitaxial layer, and the first P-type epitaxial layer and the second N-type inversion layer with high resistance can reduce the capacitance of the entire electrostatic protection device.

[0008] The present invention is further improved in that the resistivity of the first P-type epitaxial layer is M, and the value range of M is 20ohm*cm≤M≤300ohm*cm.

[0009] The present invention is further improved in that an insulating oxide layer is further provided on the upper surface of the second P-type epitaxial layer, and the insulating oxide layer is provided around the P+ heavily doped active region.

[0010] The present invention is further improved in that the top of the isolation deep trench is connected to the insulating oxide layer, and the bottom of the isolation deep trench extends into the N-type heavily doped substrate.

[0011] The present invention is further improved in that the second I / O port is a ground port, and the filling material in the isolation deep trench is silicon dioxide or silicon nitride or High-K.

[0012] The present invention also provides a manufacturing method, which is applied to the above-mentioned low-capacitance electrostatic protection device, comprising: Step 1: prepare an N-type heavily doped substrate. The doping concentration of the N-type heavily doped substrate is C1, and the value range of C1 is 10 19 cm -3 ≤C1≤10 21 cm -3 ; Step 2: grow the first P-type epitaxial layer on the N-type heavily doped substrate. The doping concentration of the first P-type epitaxial layer is C2, and the value range of C2 is 10 13 cm -3 ≤C1≤10 16 cm -3 ; Step 3, forming a P-type heavily doped buried layer on the first P-type epitaxial layer by ion implantation or diffusion process, wherein the optional impurity type is boron or boron fluoride; Step 4, growing a second P-type epitaxial layer, wherein the thickness of the second P-type epitaxial layer is greater than the thickness of the first P-type epitaxial layer; Step 5, manufacturing the isolation deep trench; Step 6: Create a P+ heavily doped active area through ion implantation or diffusion process, and then open contact holes, deposit and etch metal, and open PAD windows.

[0013] The present invention is further improved. In step 3, a subsequent junction pushing process can be added to control the junction depth of the P-type heavily doped buried layer; in step 6, a subsequent junction pushing process can also be added to control the junction depth of the P+ heavily doped active area.

[0014] The present invention is further improved by only setting the second layer of P-type epitaxial layer in the N-type heavily doped substrate, and not setting the first layer of P-type epitaxial layer; the corresponding N-type inversion layer and the isolation deep trench are set in the N-type heavily doped substrate and the second layer of P-type epitaxial layer; the P-type heavily doped buried layer is set between the N-type heavily doped substrate and the second layer of P-type epitaxial layer; W1 is slightly larger than the thickness of the N-type inversion layer; the P-type heavily doped buried layer forms a PN junction with the N-type heavily doped substrate; the avalanche breakdown voltage of the PN junction can change with the adjustment of the doping concentration of the P-type heavily doped buried layer; the P-type heavily doped buried layer can shield the parasitic capacitance between the N-type inversion layer and the second layer of P-type epitaxial layer above it.

[0015] The present invention also provides a manufacturing method, which is applied to the above-mentioned low-capacitance electrostatic protection device, comprising: Step 1: prepare an N-type heavily doped substrate. The doping concentration of the N-type heavily doped substrate is C1, and the value range of C1 is 10 19 cm -3 ≤C1≤10 21 cm -3 ; Step 2: On the N-type heavily doped substrate, a P-type heavily doped buried layer is formed by ion implantation or diffusion process, and the optional impurity type is boron or boron fluoride; Step 3: grow a second P-type epitaxial layer on the N-type heavily doped substrate. The doping concentration of the second P-type epitaxial layer is C2, and the value range of C2 is 10 13 cm -3 ≤C1≤10 16 cm -3 ; Step 4, manufacturing isolation deep trenches; Step 5: Create a P+ heavily doped active area through ion implantation or diffusion process, and then perform contact hole opening, metal deposition and etching, and PAD window opening.

[0016] The present invention is further improved. In step 2, a subsequent junction pushing process can be added to control the junction depth of the P-type heavily doped buried layer; in step 5, a subsequent junction pushing process can also be added to control the junction depth of the P+ heavily doped active area.

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows: a low-capacitance electrostatic protection device and a manufacturing method thereof are provided, wherein a N-type heavily doped substrate, a first P-type epitaxial layer, a second P-type epitaxial layer, an N-type inversion layer, an isolation deep trench and a P-type heavily doped buried layer are arranged in the low-capacitance electrostatic protection device, and the high-resistance first P-type epitaxial layer and the second N-type inversion layer can reduce the capacitance of the entire electrostatic protection device, that is, a new type of longitudinal avalanche diode structure is designed, which can effectively shield the deterioration of the capacitance of the electrostatic protection device caused by the N-type inversion layer caused by the oxide charge, and can solve the contradiction between the parasitic capacitance and the avalanche breakdown voltage, and finally realize an electrostatic protection device with ultra-low parasitic capacitance and adjustable breakdown voltage, which is particularly suitable for electrostatic and surge protection of high-speed I / O ports, and solves the problem that it is difficult to realize the low capacitance characteristics of the electrostatic protection device in the prior art, resulting in difficulty in meeting people's use needs. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the solutions in the present invention or the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] FIG. 1 (a) is a schematic diagram of electrostatic protection of a typical avalanche diode; FIG1( b ) is a schematic diagram of the structure of a typical existing avalanche diode; FIG. 2 (a) is a schematic diagram of a structure of an existing low capacitance vertical avalanche diode having different doping types for the substrate and the epitaxial layer; FIG2 (b) is a schematic diagram of the structure of an existing low capacitance vertical avalanche diode in which the substrate and the epitaxial doping types are the same; Figure 3 It is a structural schematic diagram of a first embodiment of a low capacitance electrostatic protection device of the present invention; Figure 4 It is a schematic diagram of the layout of the first embodiment of the low capacitance electrostatic protection device of the present invention; Figure 5 is a flow chart of a manufacturing method of a low capacitance electrostatic protection device according to a first embodiment of the present invention; Figure 6 It is a structural schematic diagram of a second embodiment of a low capacitance electrostatic protection device of the present invention; Figure 7 FIG. 4 is a flow chart of a manufacturing method of a second embodiment of a low capacitance electrostatic protection device of the present invention. DETAILED DESCRIPTION

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs; the terms used in the specification of the application herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention; the terms "including" and "having" and any variations thereof in the specification and claims of the present invention and the above-mentioned drawings are intended to cover non-exclusive inclusions. The terms "first", "second", etc. in the specification and claims of the present invention or the above-mentioned drawings are used to distinguish different objects, not to describe a specific order.

[0021] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0022] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings.

[0023] like Figure 3-Figure 5As shown, it is an embodiment 1 of a low capacitance electrostatic protection device provided by the present invention, comprising an N-type heavily doped substrate 300 and a first P-type epitaxial layer 310 and a second P-type epitaxial layer 312 arranged from bottom to top in the N-type heavily doped substrate 300, the resistivity of the first P-type epitaxial layer 310 is high resistance, and the first P-type epitaxial layer 310 and the second P-type epitaxial layer 312 are provided with a matching N-type inversion layer and an isolation deep trench 313, and a P-type heavily doped buried layer 311 is further provided between the first P-type epitaxial layer 310 and the second P-type epitaxial layer 312, and the N-type inversion layer is divided into a first N-type inversion layer 316 and a second N-type inversion layer 317 by the P-type heavily doped buried layer 311, and the P-type heavily doped buried layer 311 is provided between the first P-type epitaxial layer 310 and the second P-type epitaxial layer 312. The doped buried layer 311 is divided into two parts by the isolation deep trench 313, and the inner part of the P-type heavily doped buried layer 311 divided by the isolation deep trench 313 is W1 in length, W1>the thickness of the N-type inversion layer, and the lower surface of the N-type heavily doped substrate 300 can be connected to the I / O port 1 130, and the upper surface of the second P-type epitaxial layer 312 is provided with a P+ heavily doped active area 314 that can be connected to the I / O port 2 120. The P-type heavily doped buried layer 311, the first P-type epitaxial layer 310, and the N-type heavily doped substrate 300 together constitute a PIN diode, and the effective thickness H of the first P-type epitaxial layer 310 is the distance between the P-type heavily doped buried layer 311 and the N-type heavily doped substrate 300. Among them, the resistivity of the first P-type epitaxial layer 310 is M, and the value range of M is 20ohm*cm≤M≤300ohm*cm. The breakdown voltage of the PIN diode can be adjusted with the effective thickness H of the first P-type epitaxial layer 310. The high-resistance first P-type epitaxial layer 310 and the second N-type inversion layer 317 can reduce the capacitance of the entire electrostatic protection device, that is, a new type of longitudinal avalanche diode structure is designed, which can effectively shield the deterioration of the capacitance of the electrostatic protection device caused by the N-type inversion layer caused by the oxide charge, and can solve the contradiction between parasitic capacitance and avalanche breakdown voltage, and finally realize an electrostatic protection device with ultra-low parasitic capacitance and adjustable breakdown voltage, which is particularly suitable for electrostatic and surge protection of high-speed I / O ports.

[0024] like Figure 3-Figure 4As shown, the upper surface of the second layer of P-type epitaxial layer 312 is also provided with an insulating oxide layer, which is arranged around the P+ heavily doped active area 314, the top of the isolation deep trench 313 is connected to the insulating oxide layer 315, the bottom of the isolation deep trench 313 extends into the N-type heavily doped substrate 300, the I / O port 2 120 is a grounding port, and the filling material in the isolation deep trench 313 is silicon dioxide or silicon nitride or High-K. In this embodiment, the resistivity of the first layer of P-type epitaxial layer 310 is high resistance to achieve low parasitic capacitance; the resistivity of the second layer of P-type epitaxial layer 312 can be selected to be high resistance, or it can be medium resistance or low resistance. The P-type heavily doped buried layer 311 surrounds the isolation deep trench 313 on the layout, and the length W1 of the inner part of the P-type heavily doped buried layer 311 divided by the isolation deep trench 313 must be greater than the thickness of the N-type inversion layer to completely block the inversion layer. The P-type heavily doped buried layer 311 exceeds the outer length W2 of the isolation deep trench 313, and there is no restriction. At this time, the N-type inversion layer is divided into a first N-type inversion layer 316 and a second N-type inversion layer 317 by the P-type heavily doped buried layer 311, wherein only the second N-type inversion layer 317 is connected to the N-type heavily doped substrate 300, and thus, only the second N-type inversion layer 317 will contribute additional capacitance. The capacitance of the first N-type inversion layer 316 can be optimized, thereby reducing the overall parasitic capacitance of the electrostatic protection device and shielding the influence of the oxide charge to the maximum extent. In addition, the breakdown voltage of the avalanche tube can be regulated by the effective thickness H of the first P-type epitaxial layer 310 (H is the "spacing between the P-type heavily doped buried layer 311 and the N-type heavily doped substrate 300"). Specifically, at this time, the P-type heavily doped buried layer 311 / the first P-type epitaxial layer 310 / the N-type heavily doped substrate 300 together constitute a PIN diode, so when H is smaller, the breakdown voltage of the PIN diode will be reduced accordingly, so that the turn-on voltage of this embodiment can be flexibly adjusted, so that it can be used for static electricity and surge protection of various low / medium / high voltage circuits. It is worth mentioning that when the base region of the PIN diode is fully depleted, the second N-type inversion layer 317 brought by the isolation deep trench 313 will no longer have a deteriorating effect on the overall parasitic capacitance.

[0025] like Figure 5 FIG. 1 is a manufacturing method according to Embodiment 1 of the present invention, comprising: Step 1: prepare an N-type heavily doped substrate. The doping concentration of the N-type heavily doped substrate is C1. The doping concentration of the N-type heavily doped substrate is usually heavy. In this embodiment, the value range of C1 is 10 19 cm -3 ≤C1≤10 21 cm -3 ; Step 2: grow a first P-type epitaxial layer on an N-type heavily doped substrate. The doping concentration of the first P-type epitaxial layer is C2. To reduce the capacitance, the doping concentration needs to be very low. In this embodiment, the value range of C2 is 10 13 cm -3 ≤C1≤10 16 cm -3 ; In addition, the effective thickness H determines the avalanche voltage of the entire electrostatic protection device, so the effective thickness H can be adjusted according to different voltage requirements; Step 3, forming a P-type heavily doped buried layer on the first P-type epitaxial layer by ion implantation or diffusion process, the optional impurity type is boron or boron fluoride, and a subsequent junction pushing process can be added to adjust the junction depth of the P-type heavily doped buried layer; Step 4, growing a second P-type epitaxial layer, wherein the thickness of the second P-type epitaxial layer is greater than that of the first P-type epitaxial layer, and the doping concentration of the second P-type epitaxial layer may be equal to the doping concentration of the first P-type epitaxial layer, or may be greater than or less than the doping concentration of the first P-type epitaxial layer; Step 5, manufacturing an isolation deep trench, wherein the filling material in the isolation deep trench is silicon dioxide or silicon nitride or High-K; Step 6: manufacture the P+ heavily doped active area by ion implantation or diffusion process. A subsequent junction push process can also be added to adjust the junction depth of the P+ heavily doped active area, followed by a typical back-end process (BEOL), including contact hole opening, metal deposition and etching, and PAD opening.

[0026] like Figure 6As shown, a second embodiment of a low-capacitance electrostatic protection device provided by the present invention is different from the first embodiment in that: only a second layer of P-type epitaxial layer is arranged in the N-type heavily doped substrate, and a first layer of P-type epitaxial layer is not arranged, a matching N-type inversion layer and an isolation deep trench are arranged in the N-type heavily doped substrate and the second layer of P-type epitaxial layer, a P-type heavily doped buried layer is arranged between the N-type heavily doped substrate and the second layer of P-type epitaxial layer, W1 is slightly larger than the thickness of the N-type inversion layer, the P-type heavily doped buried layer and the N-type heavily doped substrate form a PN junction, the avalanche breakdown voltage of the PN junction can change with the adjustment of the doping concentration of the P-type heavily doped buried layer, and the P-type heavily doped buried layer can shield the parasitic capacitance between the N-type inversion layer above it and the second layer of P-type epitaxial layer. That is to say, in this embodiment, only one epitaxial layer is used, namely the second P-type epitaxial layer, which has a simpler structure, lower cost, and easier to control yield rate. At this time, the P-type heavily doped buried layer and the N-type heavily doped substrate form a PN junction, and the avalanche breakdown voltage can be controlled by adjusting the doping concentration of the P-type heavily doped buried layer. Moreover, although the existence of the P-type heavily doped buried layer can shield the parasitic capacitance of the N-type inversion layer and the second P-type epitaxial layer above it, the junction between the P-type heavily doped buried layer and the N-type heavily doped substrate itself may also introduce considerable parasitic capacitance. Therefore, it is necessary to finely optimize the size of W1 so that it only exceeds the thickness of the N-type inversion layer, and preferably leaves a certain margin.

[0027] like Figure 7 As shown, the manufacturing method of the second embodiment of the present invention comprises: Step 1: prepare an N-type heavily doped substrate. The doping concentration of the N-type heavily doped substrate is C1, and the value range of C1 is 10 19 cm -3 ≤C1≤10 21 cm -3 ; Step 2: On the N-type heavily doped substrate, a P-type heavily doped buried layer is formed by ion implantation or diffusion process, and the optional impurity type is boron or boron fluoride; a subsequent junction pushing process can be added to control the junction depth of the P-type heavily doped buried layer; Step 3: grow a second P-type epitaxial layer on the N-type heavily doped substrate. The doping concentration of the second P-type epitaxial layer is C2, and the value range of C2 is 10 13 cm -3 ≤C1≤10 16 cm -3 ; Step 4, manufacturing isolation deep trenches; Step 5: manufacture the P+ heavily doped active area by ion implantation or diffusion process. A subsequent junction push process can also be added to adjust the junction depth of the P+ heavily doped active area, followed by a typical back-end process (BEOL), including contact hole opening, metal deposition and etching, and PAD opening.

[0028] The manufacturing process of a low-capacitance electrostatic protection device of the present invention is applicable to various common integrated circuit manufacturing processes, such as nano-scale complementary metal oxide semiconductor (CMOS) process, three-dimensional fin field effect transistor (FinField-EffectTransistor, FinFET) or gate-all-around FET (GAA) process, or silicon-on-insulator (SOI) process, etc.

[0029] As can be seen from the above, the present invention provides a low-capacitance electrostatic protection device and a manufacturing method thereof. By arranging mutually coordinated N-type heavily doped substrates, a first P-type epitaxial layer, a second P-type epitaxial layer, an N-type inversion layer, an isolation deep trench and a P-type heavily doped buried layer in the low-capacitance electrostatic protection device, the high-resistance first P-type epitaxial layer and the second N-type inversion layer can reduce the capacitance of the entire electrostatic protection device, that is, a new type of longitudinal avalanche diode structure is designed, which can effectively shield the deterioration of the capacitance of the electrostatic protection device caused by the N-type inversion layer caused by the oxide charge, and can solve the contradiction between parasitic capacitance and avalanche breakdown voltage, and finally realize an electrostatic protection device with ultra-low parasitic capacitance and adjustable breakdown voltage, which is particularly suitable for electrostatic and surge protection of high-speed I / O ports, and solves the problem that it is difficult to achieve the low capacitance characteristics of electrostatic protection devices in the prior art, resulting in difficulty in meeting people's usage needs.

[0030] The specific implementation modes described above are preferred implementation modes of the present invention, and are not intended to limit the specific implementation scope of the present invention. The scope of the present invention includes but is not limited to the specific implementation modes, and all equivalent changes made according to the present invention are within the protection scope of the present invention.

Claims

1. A low capacitance electrostatic protection device, characterized in that: The invention comprises an N-type heavily doped substrate and a first P-type epitaxial layer and a second P-type epitaxial layer arranged from bottom to top in the N-type heavily doped substrate, wherein the resistivity of the first P-type epitaxial layer is high resistance, and the first P-type epitaxial layer and the second P-type epitaxial layer are provided with matching N-type inversion layers and isolation deep trenches, and a P-type heavily doped buried layer is further provided between the first P-type epitaxial layer and the second P-type epitaxial layer, and the N-type inversion layer is divided into a first N-type inversion layer and a second N-type inversion layer by the P-type heavily doped buried layer, and the P-type heavily doped buried layer is divided into two parts by the isolation deep trench, and the inner part of the P-type heavily doped buried layer divided by the isolation deep trench is W1, and W1>the length of ... The thickness of the N-type inversion layer, the lower surface of the N-type heavily doped substrate can be connected to the I / O port one, the upper surface of the second P-type epitaxial layer is provided with a P+ heavily doped active area that can be connected to the I / O port two, the P-type heavily doped buried layer, the first P-type epitaxial layer, and the N-type heavily doped substrate together constitute a PIN diode, the effective thickness H of the first P-type epitaxial layer is the distance between the P-type heavily doped buried layer and the N-type heavily doped substrate, the breakdown voltage of the PIN diode can be adjusted with the effective thickness H of the first P-type epitaxial layer, and the high-resistance first P-type epitaxial layer and the second N-type inversion layer can reduce the capacitance of the entire electrostatic protection device.

2. The low capacitance electrostatic protection device according to claim 1, characterized in that: The resistivity of the first P-type epitaxial layer is M, and the value range of M is 20ohm*cm≤M≤300ohm*cm.

3. The low capacitance electrostatic protection device according to claim 2, characterized in that: An insulating oxide layer is also provided on the upper surface of the second P-type epitaxial layer, and the insulating oxide layer is arranged around the P+ heavily doped active region.

4. The low capacitance electrostatic protection device according to claim 3, characterized in that: The top of the isolation deep trench is connected to the insulating oxide layer, and the bottom of the isolation deep trench extends into the N-type heavily doped substrate.

5. The low capacitance electrostatic protection device according to claim 4, characterized in that: The second I / O port is a ground port, and the filling material in the isolation deep trench is silicon dioxide or silicon nitride or High-K.

6. The low capacitance electrostatic protection device according to any one of claims 1 to 5, characterized in that: Only the second layer of P-type epitaxial layer is arranged in the N-type heavily doped substrate, and the first layer of P-type epitaxial layer is not arranged. The corresponding N-type inversion layer and the isolation deep trench are arranged in the N-type heavily doped substrate and the second layer of P-type epitaxial layer. The P-type heavily doped buried layer is arranged between the N-type heavily doped substrate and the second layer of P-type epitaxial layer. W1 is slightly larger than the thickness of the N-type inversion layer. The P-type heavily doped buried layer forms a PN junction with the N-type heavily doped substrate. The avalanche breakdown voltage of the PN junction can change with the adjustment of the doping concentration of the P-type heavily doped buried layer. The P-type heavily doped buried layer can shield the parasitic capacitance between the N-type inversion layer above it and the second layer of P-type epitaxial layer.

7. A manufacturing method, applied to the low capacitance electrostatic protection device according to any one of claims 1 to 5, characterized in that: include: Step 1: prepare an N-type heavily doped substrate. The doping concentration of the N-type heavily doped substrate is C1, and the value range of C1 is 10 19 cm -3 ≤C1≤10 21 cm -3 ; Step 2: grow the first P-type epitaxial layer on the N-type heavily doped substrate. The doping concentration of the first P-type epitaxial layer is C2, and the value range of C2 is 10 13 cm -3 ≤C1≤10 16 cm -3 ; Step 3, forming a P-type heavily doped buried layer on the first P-type epitaxial layer by ion implantation or diffusion process, wherein the optional impurity type is boron or boron fluoride; Step 4, growing a second P-type epitaxial layer, wherein the thickness of the second P-type epitaxial layer is greater than the thickness of the first P-type epitaxial layer; Step 5, manufacturing the isolation deep trench; Step 6: Create a P+ heavily doped active area through ion implantation or diffusion process, and then open contact holes, deposit and etch metal, and open PAD windows.

8. The manufacturing method according to claim 7, characterized in that: In step 3, a subsequent junction pushing process may be added to control the junction depth of the P-type heavily doped buried layer; in step 6, a subsequent junction pushing process may also be added to control the junction depth of the P+ heavily doped active region.

9. A manufacturing method, applied to the low capacitance electrostatic protection device according to claim 6, characterized in that: include: Step 1: prepare an N-type heavily doped substrate. The doping concentration of the N-type heavily doped substrate is C1, and the value range of C1 is 10 19 cm -3 ≤C1≤10 21 cm -3 ; Step 2: On the N-type heavily doped substrate, a P-type heavily doped buried layer is formed by ion implantation or diffusion process, and the optional impurity type is boron or boron fluoride; Step 3: grow a second P-type epitaxial layer on the N-type heavily doped substrate. The doping concentration of the second P-type epitaxial layer is C2, and the value range of C2 is 10 13 cm -3 ≤C1≤10 16 cm -3 ; Step 4, manufacturing the isolation deep trench; Step 5: Create a P+ heavily doped active area through ion implantation or diffusion process, and then perform contact hole opening, metal deposition and etching, and PAD window opening.

10. The manufacturing method according to claim 9, characterized in that: In step 2, a subsequent junction pushing process may be added to control the junction depth of the P-type heavily doped buried layer; in step 5, a subsequent junction pushing process may also be added to control the junction depth of the P+ heavily doped active region.

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