Semiconductor device structure and manufacturing method thereof

Abstract

The invention provides a semiconductor device structure and a manufacturing method thereof, in the semiconductor device structure, the bottom of a first well region is in contact with a bottom doped region to form a PN structure, and a metal silicide layer is in contact with the first well region to form a Schottky junction. When forward voltage is accessed to the semiconductor device structure, both the Schottky junction and the PN junction are conducted, so that the overcurrent capability of the semiconductor device structure is improved. When reverse voltage is connected to the semiconductor device structure, a depletion layer between PN junctions expands upwards continuously, so that a current channel between the first isolation structure and the bottom doped region is pinched off, and the reverse breakdown voltage of the semiconductor device structure is improved. Therefore, the forward current and the reverse breakdown voltage of the semiconductor device structure are improved by forming the bottom doped region which is in contact with the first well region below the first well region.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor device manufacturing, and in particular to a semiconductor device structure and a method for manufacturing the semiconductor device structure. Background Art

[0002] A Schottky barrier diode is a semiconductor diode based on a Schottky barrier formed by the contact between metal and semiconductor. Compared with a traditional PN junction diode, its forward voltage is lower and the reverse breakdown voltage it can withstand is higher.

[0003] Since the Schottky barrier diode does not have a conductivity modulation effect, when the doping ion concentration in the semiconductor is higher, the reverse breakdown voltage of the Schottky barrier diode will be higher, but under the same forward voltage, the higher the doping ion concentration in the semiconductor, the smaller the forward current of the Schottky barrier diode will be.

[0004] Therefore, it is difficult for a Schottky barrier diode to simultaneously increase the reverse breakdown voltage and the forward current. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor device structure and a method for manufacturing the semiconductor device structure, so as to improve the forward current and reverse breakdown voltage of a Schottky barrier diode.

[0006] According to a first aspect of the present invention, there is provided a semiconductor device structure, comprising:

[0007] substrate;

[0008] a bottom doped region, the bottom doped region being located in the substrate;

[0009] a first well region, wherein the first well region is located in the substrate and on the bottom doped region, and the bottom of the first well region is in contact with the bottom doped region, and the conductivity types of doped ions in the first well region and the bottom doped region are opposite;

[0010] A metal silicide layer, wherein the metal silicide layer is located on a surface of the first well region and is in contact with the first well region;

[0011] A first isolation structure is located in the first well region, the first isolation structure is arranged around the metal silicide layer and is located at the periphery of the metal silicide layer, and the depth of the first isolation structure is less than the depth of the first well region.

[0012] Optionally, also include:

[0013] A first doping region, wherein the first doping region is located in the first well region, the first doping region is arranged around the first isolation structure and is located at the periphery of the first isolation structure, and the conductivity type of the doping ions in the first doping region is the same as the conductivity type of the doping ions in the first well region.

[0014] Optionally, also include:

[0015] a second well region, the second well region being located in the substrate and on the bottom doped region; the second well region being arranged around the first well region and being located at the periphery of the first well region, and the conductivity type of the doped ions in the second well region being the same as the conductivity type of the doped ions in the bottom doped region;

[0016] The second doping region is located in the second well region, the second doping region is arranged around the first well region and is located at the periphery of the first well region, and the conductivity type of the doping ions in the second doping region is the same as the conductivity type of the doping ions in the second well region.

[0017] Optionally, the doping ion concentration in the first well region is 10 17 cm -3 ~10 18 cm -3 The doping ion concentration in the bottom doping region is 2.5×10 17 cm -3 ~5×10 18 cm -3 The depth of the bottom doped region is 0.4 μm to 0.5 μm, and the depth of the first isolation structure is 0.375 μm to 0.395 μm.

[0018] Optionally, the concentration of doping ions in the first doping region is greater than the concentration of doping ions in the first well region, and the concentration of doping ions in the second doping region is greater than the concentration of doping ions in the bottom doping region.

[0019] Optionally, it also includes: a second isolation structure, the second isolation structure is located in the first well region and the second well region, and the second isolation structure is arranged around the second doping region and is located inside the second doping region.

[0020] Optionally, it also includes: a conductive structure, which is located on the surface of the first doping region, the second doping region and the metal silicide layer, and the bottom of the conductive structure is in contact with the first doping region, the second doping region and the metal silicide layer; the conductive structure on the surface of the second doping region is connected to the conductive structure on the surface of the metal silicide layer.

[0021] Optionally, the first isolation structure and the second isolation structure are both shallow trench isolation structures.

[0022] Optionally, the conductivity type of the doped ions in the bottom doped region is P type.

[0023] According to a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device structure, comprising:

[0024] providing a substrate;

[0025] forming a bottom doped region in the substrate;

[0026] forming a first well region in the substrate, the first well region being located in the substrate and on the bottom doped region, the bottom of the first well region being in contact with the bottom doped region, and the conductivity types of doped ions in the first well region and the bottom doped region being opposite;

[0027] forming a metal silicide layer on the surface of the first well region;

[0028] A first isolation structure is formed in the substrate, the first isolation structure is located on both sides of the metal silicide layer, and the depth of the first isolation structure is less than the depth of the first well region.

[0029] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0030] In the semiconductor device structure provided by the technical solution of the present invention, the bottom of the first well region contacts the bottom doped region to form a PN junction, and the metal silicide layer contacts the first well region to form a Schottky junction. When the semiconductor device structure is connected to a forward voltage, both the Schottky junction and the PN junction will be turned on, so that the current capacity of the semiconductor device structure is improved. When the semiconductor device structure is connected to a reverse voltage, the depletion layer formed between the first well region and the bottom doped region will continue to expand upward, so that the current channel between the first isolation structure and the bottom doped region is pinched off, thereby improving the reverse breakdown voltage of the semiconductor device structure. Therefore, by forming a bottom doped region in contact below the first well region, on the basis of the metal silicide layer contacting the first well region to form a Schottky junction, the bottom doped region and the first well region form a PN junction, thereby improving the forward current and reverse breakdown voltage of the semiconductor device structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a schematic cross-sectional view of a semiconductor device structure provided by an embodiment of the present invention;

[0032] Figure 2 It is a schematic diagram of the electric field distribution of the semiconductor device structure provided by an embodiment of the present invention when a 3.5V reverse voltage is connected.

[0033] Reference numerals:

[0034] 1- substrate;

[0035] 2- bottom doped region;

[0036] 3-first well region;

[0037] 4-metal silicide layer;

[0038] 5- first isolation structure;

[0039] 6-second well region;

[0040] 7- a second doping region;

[0041] 8- second isolation structure;

[0042] 9-a first doped region;

[0043] 10- Conductive structure. DETAILED DESCRIPTION

[0044] As described in the background art, it is difficult for a Schottky barrier diode to simultaneously increase the reverse breakdown voltage and the forward current.

[0045] In view of this, the technical solution of the present invention creatively proposes a semiconductor device structure, including: a substrate; a bottom doped region, the bottom doped region is located in the substrate; a first well region, the first well region is located in the substrate and on the bottom doped region, and the bottom of the first well region is in contact with the bottom doped region, and the conductivity type of the doped ions in the first well region and the bottom doped region is opposite; a metal silicide layer, the metal silicide layer is located on the surface of the first well region, and the metal silicide layer is in contact with the first well region; a first isolation structure, the first isolation structure is located in the first well region, the first isolation structure is arranged around the metal silicide layer and is located at the periphery of the metal silicide layer, and the depth of the first isolation structure is less than the depth of the first well region.

[0046] Therefore, on the basis that the metal silicide layer contacts the first well region to form a Schottky junction, a bottom doped region is formed under the first well region, and the bottom of the first well region contacts the bottom doped region to form a PN junction, thereby increasing the forward current and reverse breakdown voltage of the semiconductor device structure.

[0047] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the embodiments in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present invention. The terms "first", "second", "third", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0048] Figure 1 is a schematic cross-sectional view of a semiconductor device structure provided by an embodiment of the present invention; Figure 2 It is a schematic diagram of the electric field distribution of the semiconductor device structure provided by an embodiment of the present invention when a 3.5V reverse voltage is connected.

[0049] Please refer to Figure 1 The semiconductor device structure may include: a substrate 1 , a bottom doped region 2 , a first well region 3 , a metal silicide layer 4 and a first isolation structure 5 .

[0050] Wherein, the semiconductor device structure may include a diode structure.

[0051] Wherein, the substrate 1 is a silicon substrate.

[0052] In this embodiment, the bottom doped region 2 is located in the substrate 1 , and the conductivity type of the substrate 1 is the same as the conductivity type of the bottom doped region 2 .

[0053] In a specific embodiment, the conductivity type of the doped ions in the bottom doped region 2 is P type, that is, the conductivity type of the substrate 1 may also be P type.

[0054] In this embodiment, the first well region 3 is located in the substrate 1 and on the bottom doped region 2 , and the bottom of the first well region 3 is in contact with the bottom doped region 2 .

[0055] In this embodiment, the conductivity type of the doped ions in the first well region 3 is opposite to that of the bottom doped region 2. That is, continuing to cite the previous example, when the conductivity type of the doped ions in the bottom doped region 2 is P-type, the conductivity type of the doped ions in the first well region 3 is N-type, so as to form a PN junction. Therefore, when a forward voltage is connected to both ends of the PN junction, the PN junction will be turned on, and when a reverse voltage is connected to both ends of the PN junction, the depletion layer in the PN junction will expand upward.

[0056] In this embodiment, the metal silicide layer 4 is located on the surface of the first well region 3 , and the metal silicide layer 4 is in contact with the first well region 3 to form a Schottky junction.

[0057] In this embodiment, the first isolation structure 5 is located in the first well region 3. The first isolation structure 5 is arranged around the metal silicide layer 4 and is located at the periphery of the metal silicide layer 4. The depth of the first isolation structure 5 is less than the depth of the first well region 3, so that there is a first well region 3 of a certain height between the bottom doped region 2 and the first isolation structure 5 to serve as a current channel.

[0058] In one embodiment, the first isolation structure 5 is a shallow trench isolation structure, the top surface of the first isolation structure 5 is flush with the top surface of the first well region 3 , and a first well region 3 of a certain height exists between the first isolation structure 5 and the bottom doped region 2 .

[0059] In this embodiment, the semiconductor device structure may further include a first doping region 9 , a second doping region 7 and a second well region 6 .

[0060] The first doping region 9 is located in the first well region 3 , and the first doping region 9 is disposed around the first isolation structure 5 and is located at the periphery of the first isolation structure 5 .

[0061] In this embodiment, the conductivity type of the doped ions in the first doped region 9 is the same as the conductivity type of the doped ions in the first well region 3. Continuing with the previous example, the conductivity type of the doped ions in the bottom doped region 2 is P type, and the conductivity type of the doped ions in the first well region 3 is N type, then the conductivity type of the doped ions in the first doped region 9 is N type.

[0062] In this embodiment, the second well region 6 is located in the substrate 1 and on the bottom doped region 2 ; the second well region 6 is disposed around the first well region 3 and is located at the periphery of the first well region 3 .

[0063] In this embodiment, the conductivity type of the doped ions in the second well region 6 is the same as the conductivity type of the doped ions in the bottom doped region 2, that is, when the conductivity type of the doped ions in the bottom doped region 2 is P type, the conductivity type of the doped ions in the second well region 6 is also P type.

[0064] In this embodiment, the second doping region 7 is located in the second well region 6 .

[0065] In a specific embodiment, the top surface of the second doping region 7 is flush with the top surface of the second well region 6 , and a second well region 6 of a certain height exists between the bottom surface of the second doping region 7 and the bottom doping region 2 .

[0066] In this embodiment, the conductivity type of the doped ions in the second doping region 7 is the same as the conductivity type of the doped ions in the second well region 6, that is, when the conductivity type of the doped ions in the second well region 6 is P type, the conductivity type of the doped ions in the second doping region 7 is also P type.

[0067] In one embodiment, the concentration of doping ions in the first doping region 9 is greater than the concentration of doping ions in the first well region 3 , and the concentration of doping ions in the second doping region 7 is greater than the concentration of doping ions in the bottom doping region 2 .

[0068] In a specific embodiment, the doping ion concentration in the first well region 3 is 10 17 cm -3 ~10 18 cm -3 The doping ion concentration in the bottom doping region 2 is 2.5×10 17 cm -3 ~5×10 18 cm -3 .

[0069] In this embodiment, the depth of the bottom doped region 2 is 0.4 μm to 0.5 μm, and the depth of the first isolation structure 5 is 0.375 μm to 0.395 μm.

[0070] In this embodiment, the semiconductor device structure may further include: a second isolation structure 8 , the second isolation structure 8 is located in the first well region 3 and the second well region 6 , and the second isolation structure 8 is arranged around the second doping region 7 and is located inside the second doping region 7 .

[0071] In this embodiment, the second isolation structure 8 can be a shallow trench isolation structure, the top surface of the second isolation structure 8 is flush with the top surface of the first well region 3, the height of the second isolation structure 8 is lower than the height of the first well region 3, and the first well region 3 is in contact with the second well region 6 below the second isolation structure 8.

[0072] In the above embodiment, by setting the first isolation structure 5 and the second isolation structure 8 to be shallow trench isolation structures, the first isolation structure 5 is used to isolate the metal silicide layer 4 from the first doping region 9, and the second isolation structure 8 is used to isolate the first doping region 9 from the second well region 6, so as to prevent leakage. In this embodiment, the semiconductor device structure may further include: a conductive structure 10, the conductive structure 10 is located on the surface of the first doping region 9, the second doping region 7 and the metal silicide layer 4, and the bottom of the conductive structure 10 is in contact with the first doping region 9, the second doping region 7 and the metal silicide layer 4.

[0073] The conductive structure 10 on the surface of the second doping region 7 is connected to the conductive structure 10 on the surface of the metal silicide layer 4 .

[0074] Please refer to Figure 1 and Figure 2 The working principle of the semiconductor device structure is described below by taking the conductivity type of the doped ions in the bottom doped region 2 as P type as an example.

[0075] Figure 2 is a schematic diagram of electric field distribution of a semiconductor device structure provided by an embodiment of the present invention when a reverse voltage of 3.5V is connected, Figure 2 The horizontal axis in is used to represent the different depths from the substrate surface, and the vertical axis is used to represent the electric field strength. Figure 2 The curves in FIG. 1 represent the electric field magnitudes at different depths of the substrate 1 of the two semiconductor device structures when a reverse voltage of 3.5 V is applied.

[0076] Since the conductivity type of the doped ions in the bottom doped region 2 is P type, the conductivity type of the doped ions in the first well region 3 and the first doped region 9 is N type, and the conductivity type of the doped ions in the second well region 6 and the second doped region 7 is P type. Therefore, the conductive structure 10 on the surface of the first doped region 9 is used as the negative electrode of the semiconductor device structure, and the conductive structure 10 on the surface of the second doped region 7 is connected to the conductive structure 10 on the surface of the metal silicide layer 4 as the positive electrode of the semiconductor device structure.

[0077] When the semiconductor device structure is connected to a forward voltage, the Schottky junction formed by the metal silicide layer 4 and the first well region 3 will be turned on, and electrons will enter the first well region 3 from the metal silicide layer 4, and flow to the first doping region 9 through the current channel between the first isolation structure 5 and the bottom doping region 2. At the same time, the PN junction formed by the first well region 3 and the bottom doping region 2 will also be turned on, and a large number of carriers in the first well region 3 will flow to the bottom doping region 2 and flow through the second well region 6 into the second doping region 7. Therefore, when the semiconductor device structure is connected to a forward voltage, the Schottky junction and the PN junction will be turned on at the same time, so that the current capacity of the semiconductor device structure is increased.

[0078] When the semiconductor device structure is connected to a reverse voltage, the depletion layer between the first well region 3 and the bottom doped region 2 will continue to expand upward, thereby pinching off the current channel under the first isolation structure 5, thereby increasing the reverse breakdown voltage of the semiconductor device structure.

[0079] In addition, please refer to Figure 2 The electric field of the semiconductor device structure without the bottom doping region is concentrated on the surface of the substrate, that is, at the Schottky junction, and the electric field of the semiconductor device structure including the bottom doping region 2 is concentrated on the surface of the substrate 1 and the center of the substrate 1, that is, at the Schottky junction and the PN junction, and the electric field strength at the Schottky junction is lower than the electric field strength at the Schottky junction of the semiconductor device structure without the bottom doping region. Therefore, the bottom doping region 2 shifts the electric field distribution, so that the electric field is largely concentrated at the PN junction, so that the Schottky junction formed by the metal silicide layer 4 and the first well region 3 is not easily broken down, thereby improving the reverse breakdown voltage of the semiconductor device structure.

[0080] In summary, in a semiconductor device structure provided by an embodiment of the present invention, the bottom of the first well region contacts the bottom doped region to form a PN junction, and the metal silicide layer contacts the first well region to form a Schottky junction. When the semiconductor device structure is connected to a forward voltage, both the Schottky junction and the PN junction will be turned on, so that the current capacity of the semiconductor device structure is improved. When the semiconductor device structure is connected to a reverse voltage, the depletion layer formed between the first well region and the bottom doped region will continue to expand upward, so that the current channel between the first isolation structure and the bottom doped region is pinched off, thereby increasing the reverse breakdown voltage of the semiconductor device structure. Therefore, by forming a bottom doped region in contact below the first well region, the bottom doped region and the first well region form a PN junction on the basis of the metal silicide layer contacting the first well region to form a Schottky junction, thereby increasing the forward current and reverse breakdown voltage of the semiconductor device structure.

[0081] Please continue to refer to Figure 1 The present invention also provides a method for manufacturing the semiconductor device structure, including:

[0082] A substrate 1 is provided.

[0083] A bottom doped region 2 is formed in the substrate 1 .

[0084] A first well region 3 is formed in the substrate 1. The first well region 3 is located in the substrate 1 and on the bottom doped region 2. The bottom of the first well region 3 is in contact with the bottom doped region 2. The conductivity types of the doped ions in the first well region 3 and the bottom doped region 2 are opposite.

[0085] A metal silicide layer 4 is formed on the surface of the first well region 3 .

[0086] A first isolation structure 5 is formed in the substrate 1 . The first isolation structure 5 is disposed around the metal silicide layer 4 and is located at the periphery of the metal silicide layer 4 . The depth of the first isolation structure 5 is less than the depth of the first well region 3 .

[0087] In this embodiment, the method for manufacturing the semiconductor device structure further includes:

[0088] A first doping region 9 is formed in the first well region 3 . The first doping region 9 is disposed around the first isolation structure 5 and is located at the periphery of the first isolation structure 5 . The conductivity type of the doped ions in the first doping region 9 is the same as that of the doped ions in the first well region 3 .

[0089] A second well region 6 is formed. The second well region 6 is located in the substrate 1 and on the bottom doped region 2. The second well region 6 is arranged around the first well region 3 and is located at the periphery of the first well region 3. The conductivity type of the doped ions in the second well region 6 is the same as the conductivity type of the doped ions in the bottom doped region 2.

[0090] A second doping region 7 is formed in the second well region 6 . The second doping region 7 is arranged around the first well region 3 and is located at the periphery of the first well region 3 . The conductivity type of the doped ions in the second doping region 7 is the same as that of the doped ions in the second well region 6 .

[0091] A second isolation structure 8 is formed. The second isolation structure 8 is located in the first well region 3 and the second well region 6 . The second isolation structure 8 is disposed around the second doping region 7 and is located inside the second doping region 7 .

[0092] It should be noted that the order of forming the first doping region 9 and forming the second doping region 7 can be reversed.

[0093] In this embodiment, after forming the second isolation structure 8, the method for manufacturing the semiconductor device structure further includes:

[0094] Conductive structures are formed on the surfaces of the first doping region 9 , the second doping region 7 and the metal silicide layer 4 , respectively, and the bottoms of the conductive structures are in contact with the first doping region 9 , the second doping region 7 and the metal silicide layer 4 .

[0095] The conductive structure on the surface of the second doping region 7 is connected to the metal silicide layer 4 .

[0096] This embodiment is a method embodiment corresponding to the above structural embodiment. Therefore, for the detailed explanation of each feature in this embodiment, please refer to the relevant description of the same feature in the above structural embodiment, which will not be repeated here.

[0097] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor device structure, characterized in that: include: substrate; a bottom doped region, the bottom doped region being located in the substrate; a first well region, wherein the first well region is located in the substrate and on the bottom doped region, and the bottom of the first well region is in contact with the bottom doped region, and the conductivity types of doped ions in the first well region and the bottom doped region are opposite; A metal silicide layer, wherein the metal silicide layer is located on a surface of the first well region and is in contact with the first well region; A first isolation structure is located in the first well region, the first isolation structure is arranged around the metal silicide layer and is located at the periphery of the metal silicide layer, and the depth of the first isolation structure is less than the depth of the first well region.

2. The semiconductor device structure according to claim 1, characterized in that: Also includes: A first doping region, wherein the first doping region is located in the first well region, the first doping region is arranged around the first isolation structure and is located at the periphery of the first isolation structure, and the conductivity type of the doping ions in the first doping region is the same as the conductivity type of the doping ions in the first well region.

3. The semiconductor device structure according to claim 2, characterized in that: Also includes: a second well region, the second well region being located in the substrate and on the bottom doped region; The second well region is arranged around the first well region and is located at the periphery of the first well region, and the conductivity type of the doped ions in the second well region is the same as the conductivity type of the doped ions in the bottom doped region; The second doping region is located in the second well region, the second doping region is arranged around the first well region and is located at the periphery of the first well region, and the conductivity type of the doping ions in the second doping region is the same as the conductivity type of the doping ions in the second well region.

4. The semiconductor device structure according to claim 3, characterized in that: The doping ion concentration in the first well region ranges from 10 17 cm -3 ~10 18 cm -3 The doping ion concentration in the bottom doping region is in the range of 2.5×10 17 cm -3 ~5×10 18 cm -3 The depth of the bottom doped region ranges from 0.4 μm to 0.5 μm, and the depth of the first isolation structure ranges from 0.375 μm to 0.395 μm.

5. The semiconductor device structure according to claim 3, characterized in that: The concentration of doping ions in the first doping region is greater than the concentration of doping ions in the first well region, and the concentration of doping ions in the second doping region is greater than the concentration of doping ions in the bottom doping region.

6. The semiconductor device structure according to claim 3, characterized in that: Also includes: The second isolation structure is located in the first well region and the second well region, and the second isolation structure is disposed around the second doping region and is located inside the second doping region.

7. The semiconductor device structure according to claim 6, characterized in that: Also includes: A conductive structure, wherein the conductive structure is located on the surface of the first doping region, the second doping region and the metal silicide layer, and the bottom of the conductive structure is in contact with the first doping region, the second doping region and the metal silicide layer; The conductive structure on the surface of the second doping region is connected to the conductive structure on the surface of the metal silicide layer.

8. The semiconductor device structure according to claim 6, characterized in that: The first isolation structure and the second isolation structure are both shallow trench isolation structures.

9. The semiconductor device structure according to claim 1, characterized in that: The conductivity type of the doping ions in the bottom doping region is P type.

10. A method for manufacturing a semiconductor device structure, characterized in that: include: providing a substrate; forming a bottom doped region in the substrate; forming a first well region in the substrate, the first well region being located in the substrate and on the bottom doped region, the bottom of the first well region being in contact with the bottom doped region, and the conductivity types of doped ions in the first well region and the bottom doped region being opposite; forming a metal silicide layer on the surface of the first well region; A first isolation structure is formed in the substrate. The first isolation structure is located in the first well region. The first isolation structure is arranged around the metal silicide layer and is located at the periphery of the metal silicide layer. The depth of the first isolation structure is less than the depth of the first well region.

Images