Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The manufacturing method of the semiconductor device comprises the following steps. A group III-V compound semiconductor layer is formed on a first device region and a second device region of a substrate, a group III-V compound barrier layer is formed on the group III-V compound semiconductor layer, and a laminated structure is formed on the group III-V compound barrier layer. The laminated structure includes a P-type doped III-V group compound layer and a first mask layer disposed on the P-type doped III-V group compound layer. A patterning process is performed on the laminated structure, a first portion of the laminated structure over the first device region is patterned by the patterning process, and a second portion of the laminated structure over the second device region is removed by the patterning process. Before the patterning manufacturing process, the thickness of the second part of the laminated structure is greater than that of the first part of the laminated structure.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular to a semiconductor device comprising a III-V group compound semiconductor layer and a manufacturing method thereof. Background Art

[0002] III-V semiconductor compounds can be used to form many types of integrated circuit devices due to their semiconductor properties, such as high-power field-effect transistors, high-frequency transistors or high electron mobility transistors (HEMT). In HEMTs, two semiconductor materials with different band gaps are combined to form a heterojunction at the junction to provide a channel for carriers. In recent years, gallium nitride (GaN) series materials are suitable for high-power and high-frequency products due to their wide band gap and high saturation rate. Gallium nitride series HEMTs generate two-dimensional electron gas (2DEG) by the piezoelectric effect of the material itself. Its electron speed and density are relatively high, so it can be used to increase the switching speed. In addition, there are many different designs of the structure of III-V compound semiconductor transistors to meet the needs of different products and / or circuits, and it is often necessary to manufacture III-V compound semiconductor transistors with different structures on the same wafer. Therefore, how to integrate the manufacturing processes of III-V compound semiconductor transistors with different structures to improve the electrical performance of III-V compound semiconductor transistors is a research direction for people in related fields. Summary of the invention

[0003] The present invention provides a semiconductor device and a method for manufacturing the same, wherein a stacked structure including a P-type doped III-V compound layer and a mask layer is formed on a first device region and a second device region, and the thickness of the stacked structure located on the second device region is made greater than the thickness of the stacked structure located on the first device region, thereby reducing damage to the III-V compound barrier layer located on the second device region when the stacked structure is subjected to a patterning process, thereby improving the electrical performance of a transistor structure formed subsequently.

[0004] One embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising the following steps. A substrate is provided, the substrate having a first device region and a second device region. A III-V compound semiconductor layer is formed on the first device region and the second device region, a III-V compound barrier layer is formed on the III-V compound semiconductor layer, and the III-V compound barrier layer is located above the first device region and the second device region. A stacked structure is formed on the III-V compound barrier layer, a first portion of the stacked structure is located above the first device region, and a second portion of the stacked structure is located above the second device region. The stacked structure includes a P-type doped III-V compound layer and a first mask layer. The P-type doped III-V compound layer is located in the first portion and the second portion of the stacked structure. The first mask layer is disposed on the P-type doped III-V compound layer, and the first mask layer is located in the first portion and the second portion of the stacked structure. Then, a patterning process is performed on the stacked structure, wherein the first portion of the stacked structure is patterned by the patterning process, and the second portion of the stacked structure is removed by the patterning process. Before the patterning process, the thickness of the second portion of the stacked structure is greater than the thickness of the first portion of the stacked structure.

[0005] One embodiment of the present invention provides a semiconductor device, comprising a substrate, a III-V compound semiconductor layer, a III-V compound barrier layer, and a patterned P-type doped III-V compound layer. The substrate has an enhanced device region and a depletion device region. The III-V compound semiconductor layer is disposed on the enhanced device region and the depletion device region, the III-V compound barrier layer is disposed on the III-V compound semiconductor layer, and the III-V compound barrier layer is located above the enhanced device region and the depletion device region. The patterned P-type doped III-V compound layer is disposed on the III-V compound barrier layer and is located above the enhanced device region. The thickness of the III-V compound barrier layer located above the enhanced device region is substantially equal to the thickness of the III-V compound barrier layer located above the depletion device region. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figures 1 to 7 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device according to a first embodiment of the present invention, wherein

[0007] Figure 2 for Figure 1 Schematic diagram of the situation afterwards;

[0008] Figure 3 for Figure 2 Schematic diagram of the situation afterwards;

[0009] Figure 4 for Figure 3 Schematic diagram of the situation afterwards;

[0010] Figure 5 for Figure 4 Schematic diagram of the situation afterwards;

[0011] Figure 6 for Figure 5 Schematic diagram of the situation afterwards;

[0012] Figure 7 for Figure 6 Schematic diagram of the situation afterwards;

[0013] Figure 8 is a schematic diagram of a semiconductor device according to another embodiment of the present invention;

[0014] Figures 9 to 12 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device according to a second embodiment of the present invention, wherein

[0015] Fig.10 for Fig. 9 Schematic diagram of the situation afterwards;

[0016] Fig.11 for Fig.10 Schematic diagram of the situation afterwards;

[0017] Fig.12 for Fig.11 Schematic diagram of the situation afterwards;

[0018] Figures 13 to 15 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device according to a third embodiment of the present invention, wherein

[0019] Fig.14 for Fig.13 Schematic diagram of the situation afterwards;

[0020] Fig.15 for Fig.14 Schematic diagram of the situation afterwards;

[0021] Fig.16 and Fig.17 FIG. 4 is a schematic diagram of a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention, wherein Fig.17 for Fig.16 Schematic diagram of the situation afterwards.

[0022] Explanation of symbols

[0023] 10: Base

[0024] 10BS: Bottom surface

[0025] 10TS: Top surface

[0026] 12: Buffer layer

[0027] 14: III-V compound semiconductor layer

[0028] 14A: Part 1

[0029] 14B: Part 2

[0030] 16: III-V compound barrier layer

[0031] 16A: Part 1

[0032] 16B: Part 2

[0033] 20: P-type doped III-V compound layer

[0034] 20A: Part 1

[0035] 20B: Part 2

[0036] 20M: P-type doped III-V compound materials

[0037] 20P: Patterned P-type doped III-V compound layer

[0038] 22: First P-type doped III-V compound material

[0039] 22A: Part 1

[0040] 22B: Part 2

[0041] 24: Second P-type doped III-V compound material

[0042] 24A: Part 1

[0043] 24B: Part 2

[0044] 2DEG: Two-dimensional electron gas

[0045] 32: First mask layer

[0046] 32A: Part 1

[0047] 32B: Part 2

[0048] 32M: First mask material

[0049] 32P: First mask pattern

[0050] 34: Second mask layer

[0051] 34A: Part 1

[0052] 34B: Part 2

[0053] 34M: Second mask material

[0054] 34P: Second mask pattern

[0055] 36: Dielectric layer

[0056] 38: Dielectric layer

[0057] 40: Dielectric layer

[0058] 81: Patterned mask layer

[0059] 82: Patterned mask layer

[0060] 83: Patterned mask layer

[0061] 84: Patterned mask layer

[0062] 91: Thinning process

[0063] 92: Patterning production process

[0064] 93: Remove crafting process

[0065] 94: Thinning process

[0066] 95: Thinning process

[0067] 99: Annealing process

[0068] 101: Semiconductor Device

[0069] 102: Semiconductor device

[0070] DE1: Drain structure

[0071] DE2: Drain structure

[0072] DS:Distance

[0073] GE1: Gate structure

[0074] GE2: Gate structure

[0075] LS:Laminated structure

[0076] P1: Part 1

[0077] P2: Part 2

[0078] R1: First device area

[0079] R2: Second device area

[0080] SE1: Source structure

[0081] SE2: Source structure

[0082] T1: Transistor structure

[0083] T2: Transistor structure

[0084] TK1:Thickness

[0085] TK11:Thickness

[0086] TK13:Thickness

[0087] TK14:Thickness

[0088] TK15:Thickness

[0089] TK2:Thickness

[0090] TK21:Thickness

[0091] TK22:Thickness

[0092] TK23:Thickness

[0093] TK24:Thickness

[0094] TK25:Thickness

[0095] TK3:Thickness

[0096] TK4:Thickness

[0097] TS1: Top surface

[0098] TS2: Top surface

[0099] Z: vertical direction DETAILED DESCRIPTION

[0100] The following detailed description of the present invention has disclosed enough details to enable those skilled in the art to practice the present invention. The embodiments set forth below should be considered illustrative rather than restrictive. It will be apparent to those skilled in the art that various changes and modifications in form and detail may be made without departing from the spirit and scope of the present invention.

[0101] Before further describing each embodiment, specific terms used throughout the text are explained below.

[0102] The meanings of the terms "on," "over," and "over" should be interpreted in the broadest manner, so that "on" means not only "directly on" something, but also includes being on something with other intervening features or layers therebetween, and "over" or "over" means not only being "on" or "over" something, but also includes being "on" or "over" something with no other intervening features or layers therebetween (i.e., directly on something).

[0103] The ordinal numbers used in the specification and claims, such as "first", "second", etc., are used to modify the elements of the claims. Unless otherwise specified, they do not imply or represent any previous ordinal number of the requested element, nor do they represent the order of one requested element and another requested element, or the order in the manufacturing method. The use of these ordinals is only used to clearly distinguish a requested element with a certain name from another requested element with the same name.

[0104] The term "etching" is generally used herein to describe a process for patterning a material so that at least a portion of the material is left after the etching is complete. When "etching" a material, at least a portion of the material may be retained after the etching is complete. In contrast, when "removing" a material, substantially all of the material may be removed during the process. However, in some embodiments, "removing" may be considered a broad term to include etching.

[0105] The terms "forming" or "disposing" are used hereinafter to describe the act of applying a material layer to a substrate. These terms are intended to describe any feasible layer formation technique, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.

[0106] See also Figures 1 to 7 . Figures 1 to 7 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device according to a first embodiment of the present invention, wherein Figure 2 Draws Figure 1 The following diagram shows the situation: Figure 3 Draws Figure 2 The following diagram shows the situation: Figure 4 Draws Figure 3 The following diagram shows the situation: Figure 5 Draws Figure 4 The following diagram shows the situation: Figure 6 Draws Figure 5 The following diagram shows the situation: Figure 7 Draws Figure 6 This embodiment provides a method for manufacturing a semiconductor device, comprising the following steps. Figure 1 As shown, a substrate 10 is provided, and the substrate 10 has a first device region R1 and a second device region R2. Then, a III-V compound semiconductor layer 14 is formed on the first device region R1 and the second device region R2, and a III-V compound barrier layer 16 is formed on the III-V compound semiconductor layer 14, and the III-V compound barrier layer 16 is located on the first device region R1 and the second device region R2. Then, as shown in FIG. Figure 3As shown, a stacked structure LS is formed on the III-V compound barrier layer 16, a first portion P1 of the stacked structure LS is located on the first device region R1, a second portion P2 of the stacked structure LS is located on the second device region R2, and the stacked structure LS includes a P-type doped III-V compound layer 20 and a first mask layer 32. The P-type doped III-V compound layer 20 is located in the first portion P1 and the second portion P2 of the stacked structure LS, the first mask layer 32 is disposed on the P-type doped III-V compound layer 20, and the first mask layer 32 is located in the first portion P1 and the second portion P2 of the stacked structure LS. Then, as shown in FIG. Figure 3 as well as Figure 4 As shown, a patterning process 92 is performed on the stacked structure LS, the first portion P1 of the stacked structure LS is patterned by the patterning process 92, the second portion P2 of the stacked structure LS is removed by the patterning process 92, and before the patterning process 92, the thickness TK2 of the second portion P2 of the stacked structure LS is greater than the thickness TK1 of the first portion P1 of the stacked structure LS. By making the thickness TK2 of the second portion P2 of the stacked structure LS greater than the thickness TK1 of the first portion P1 of the stacked structure LS, the damage or / and thickness variation effect of the patterning process 92 on the III-V compound barrier layer 16 located on the second device region R2 can be reduced, the thickness difference or / and height difference between the III-V compound barrier layer 16 on the first device region R1 and the second device region R2 can be reduced, and the electrical performance of the semiconductor device subsequently formed on the second device region R2 can be improved.

[0107] Further explanation, the manufacturing method of this embodiment may include but is not limited to the following contents and / or steps. Figure 1As shown, in some embodiments, before forming the III-V compound semiconductor layer 14, a buffer layer 12 may be selectively formed on the substrate 10, and the III-V compound semiconductor layer 14 may be formed on the buffer layer 12. The substrate 10 may have an upper surface 10TS and a bottom surface 10BS opposite to each other in a vertical direction Z, and the buffer layer 12, the III-V compound semiconductor layer 14, and the III-V compound barrier layer 16 may be formed on one side of the upper surface 10TS. In some embodiments, the vertical direction Z may be regarded as the thickness direction of the substrate 10, and the horizontal direction substantially orthogonal to the vertical direction Z may be substantially parallel to the upper surface 10TS or / and the bottom surface 10BS of the substrate 10, but is not limited thereto. The distance between the relatively higher position or / and component in the vertical direction Z and the bottom surface 10BS of the substrate 10 in the vertical direction Z described herein may be greater than the distance between the relatively lower position or / and component in the vertical direction Z and the bottom surface 10BS of the substrate 10 in the vertical direction Z. The lower part or bottom of each component may be closer to the bottom surface 10BS of the substrate 10 in the vertical direction Z than the upper part or top of the component. Another component above a certain component may be considered to be relatively far away from the bottom surface 10BS of the substrate 10 in the vertical direction Z, and another component below a certain component may be considered to be relatively close to the bottom surface 10BS of the substrate 10 in the vertical direction Z. It is worth noting that the upper surface of a certain component described herein may include the topmost surface of the component in the vertical direction Z, and the bottom surface of a certain component may include the bottommost surface of the component in the vertical direction Z, but it is not limited thereto. In addition, the situation in which a specific component is disposed between two other objects in a certain direction described herein may include but is not limited to the situation in which the component is sandwiched between the two objects in this direction. Furthermore, unless otherwise specified, the thickness of a particular component described herein may be considered to be the thickness of the component in the vertical direction Z.

[0108] In some embodiments, the substrate 10 may include a silicon substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, a sapphire substrate or a substrate formed of other suitable materials, the buffer layer 12 may include, for example, gallium nitride, aluminum gallium nitride (alumium gallium nitride, AlGaN), aluminum indium nitride (alumium indium nitride, AlInN) or other suitable buffer materials, the III-V group compound semiconductor layer 14 may include gallium nitride, indium gallium nitride (inGaN), aluminum gallium nitride or other suitable III-V group compound semiconductor materials, and the III-V group compound barrier layer 16 may include aluminum gallium nitride, aluminum indium nitride, aluminum gallium indium nitride (alumium gallium indium nitride, AlGaInN), aluminum nitride (alumium nitride, AlN) or other suitable III-V compound barrier materials, and the P-type doped III-V compound layer 20 may include P-type doped gallium nitride, P-type doped aluminum gallium nitride, or other suitable P-type doped III-V compound materials. In addition, the P-type dopant in the P-type doped III-V compound layer 20 may include cyclopentadienyl magnesium (Cp2Mg), magnesium, beryllium (Be), zinc (Zn), a combination of the above materials, or other suitable P-type dopants. Figure 3 As shown, in some embodiments, the stacked structure LS may further include a second mask layer 34 disposed on the first mask layer 32, the second mask layer 34 is located in the first portion P1 and the second portion P2 of the stacked structure LS, and the material composition of the second mask layer 34 is different from the material composition of the first mask layer 32. For example, the first mask layer 32 may include a barrier material with conductivity such as titanium nitride, and the second mask layer 34 may include a dielectric mask material such as silicon nitride, but is not limited thereto. In addition, the first portion 14A and the second portion 14B of the III-V compound semiconductor layer 14 may be located on the first device region R1 and the second device region R2, respectively, the first portion 16A and the second portion 16B of the III-V compound barrier layer 16 may be located on the first device region R1 and the second device region R2, respectively, the first portion 20A and the second portion 20B of the P-type doped III-V compound layer 20 may be located on the first device region R1 and the second device region R2, respectively, the first portion 32A and the second portion 32B of the first mask layer 32 may be located on the first device region R1 and the second device region R2, respectively, and the first portion 34A and the second portion 34B of the second mask layer 34 may be located on the first device region R1 and the second device region R2, respectively.

[0109] In this embodiment, the method of forming the stacked structure LS may include but is not limited to the following steps. Figure 1 As shown, a P-type doped III-V compound material 20M may be formed on the first portion 16A and the second portion 16B of the III-V compound barrier layer 16, so the P-type doped III-V compound material 20M may be located on the first device region R1 and the second device region R2. Then, a first thinning process (e.g., thinning process 91) may be performed on the P-type doped III-V compound material 20M located on the first device region R1 to reduce the thickness of the P-type doped III-V compound material 20M on the first device region R1. In some embodiments, a patterned mask layer 81 may be formed to cover the P-type doped III-V compound material 20M located on the second device region R2, and the patterned mask layer 81 may be used to protect the P-type doped III-V compound material 20M on the second device region R2 during the thinning process 91, and the patterned mask layer 81 may include photoresist or other suitable mask materials. In some embodiments, the thinning process 91 may include an etching process (such as but not limited to an etch-back process) or other suitable thinning methods, and the patterned mask layer 81 may be removed after the thinning process 91. Before the thinning process 91, the thickness of the P-type doped III-V compound material 20M located on the first device region R1 may be substantially equal to the thickness of the P-type doped III-V compound material 20M located on the second device region R2 (for example, both are thickness TK21). Figure 1 to Figure 2 As shown, after the thinning process 91, the thickness TK11 of the P-type doped III-V compound material 20M located on the first device region R1 is less than the thickness TK21 of the P-type doped III-V compound material 20M located on the second device region R2. After the thinning process 91, the P-type doped III-V compound material 20M remaining on the III-V compound barrier layer 16 may become the P-type doped III-V compound layer 20 in the above-mentioned stacked structure, so the thickness TK11 of the first portion 20A of the P-type doped III-V compound layer 20 may be less than the thickness TK21 of the second portion 20B, and the first portion 20A and the second portion 20B may be respectively composed of the P-type doped III-V compound material 20M located on the first device region R1 and the second device region.

[0110] like Figures 1 to 3As shown, after the thinning process 91, a first mask layer 32 may be formed on the P-type doped III-V compound layer 20, and a second mask layer 34 may be formed on the first mask layer 32, thereby forming a first portion P1 and a second portion P2 of the stacked structure LS on the first device region R1 and the second device region R2, respectively. In some embodiments, the stacked structure LS is composed of the P-type doped III-V compound layer 20, the first mask layer 32, and the second mask layer 34, the first portion P1 of the stacked structure LS is composed of the first portion 20A of the P-type doped III-V compound layer 20, the first portion 32A of the first mask layer 32, and the first portion 34A of the second mask layer 34, and the second portion P2 of the stacked structure LS is composed of the second portion 20B of the P-type doped III-V compound layer 20, the second portion 32B of the first mask layer 32, and the second portion 34B of the second mask layer 34, but the present invention is not limited thereto. By the above method, the thickness TK11 of the first portion 20A of the P-type doped III-V compound layer 20 is made smaller than the thickness TK21 of the second portion 20B, and the thickness TK1 of the first portion P1 of the stacked structure LS is made smaller than the thickness TK2 of the second portion P2. In some embodiments, the thickness TK11 may be about 80 nanometers, and the thickness TK21 may be adjusted according to the conditions of the patterning process 92. In addition, the method for forming the first portion 20A and the second portion 20B of the P-type doped III-V compound layer 20 with different thicknesses may include but is not limited to the above steps, and other suitable methods may be used according to design requirements to form the P-type doped III-V compound layer 20 with different thicknesses and the stacked structure LS with different thicknesses on the first device region R1 and the second device region R2, respectively.

[0111] like Figure 3 and Figure 4As shown, the P-type doped III-V compound layer 20, the first mask layer 32 and the second mask layer 34 located in the first part P1 of the stacked structure LS can be patterned by the patterning process 92 to form a patterned P-type doped III-V compound layer 20P, a first mask pattern 32P and a second mask pattern 34P located on the first device region R1, and the second part P2 of the stacked structure LS can be completely removed by the patterning process 92 to expose the upper surface TS2 of the III-V compound barrier layer 16 (for example, the second part 16B) located on the second device region R2. In some embodiments, the patterning process 92 may include a photolithography process and an etching process or other suitable patterning methods. The patterning process 92 may include one or more etching steps to etch the P-type doped III-V compound layer 20, the first mask layer 32, and the second mask layer 34, respectively. By making the second portion P2 of the stacked structure LS located on the second device region R2 and to be completely removed by the patterning process 92 relatively thick, the damage (e.g., etching damage) to the III-V compound barrier layer 16 located on the second device region R2 by the patterning process 92 can be reduced. In a more ideal situation, after the patterning process 92, the thickness TK3 of the first portion 16A of the III-V compound barrier layer 16 and the thickness TK4 of the second portion 16B of the III-V compound barrier layer 16 may be substantially equal, for example, the difference between the thickness TK3 and the thickness TK4 may be less than a predetermined value, such as 1 nm, 2 nm, or 3 nm, but not limited thereto. In some embodiments, the second portion 16B of the III-V compound barrier layer 16 may still be slightly affected by the patterning process 92. Therefore, after the patterning process 92, the upper surface TS2 of the second portion 16B of the III-V compound barrier layer 16 may be slightly lower than the upper surface TS1 of the first portion 16A in the vertical direction Z. For example, the height difference between the upper surface TS2 and the upper surface TS1 in the vertical direction Z (for example, the distance DS between the upper surface TS2 and the upper surface TS1 in the vertical direction Z) may be greater than 0 and less than 3 nanometers, and the difference between the above-mentioned thickness TK3 and thickness TK4 may also be greater than 0 and less than 3 nanometers, but is not limited to this.

[0112] like Figures 3 to 5As shown, after the patterning process 92, the first mask pattern 32P may be lateral-etched to make the contact area between the first mask pattern 32P and the patterned P-type doped III-V compound layer 20P in the vertical direction Z smaller than the total area of ​​the upper surface of the patterned P-type doped III-V compound layer 20P, thereby preventing the sidewalls of the first mask pattern 32P from being flush with the sidewalls of the patterned P-type doped III-V compound layer 20P to form a leakage current path, thereby affecting the operation performance of the semiconductor device. Figures 5 and 6 As shown, after the first mask pattern 32P is lateral-etched, the second mask pattern 34P may be removed, and a dielectric layer 36 may be formed on the first device region R1 and the second device region R2. The dielectric layer 36 may include aluminum oxide or other suitable dielectric materials, and the dielectric layer 36 may cover the second portion 16B of the III-V compound barrier layer 16 on the second device region R2, and the dielectric layer 36 may cover the first portion 16A of the III-V compound barrier layer 16, the patterned P-type doped III-V compound layer 20P, and the first mask pattern 32P on the first device region R1. After the dielectric layer 36 is formed, an annealing process 99 may be performed on the patterned P-type doped III-V compound layer 20P, and the annealing process 99 may be used to activate dopants (such as but not limited to magnesium) in the patterned P-type doped III-V compound layer 20P. It is worth noting that, in some embodiments, if the P-type doped III-V compound material is annealed and activated before forming the first mask layer 32, the subsequent patterning process (eg Figure 3 The patterning process 92 shown in the figure may have a deactivating effect on the dopants in the P-type doped III-V compound material, and when the P-type doped III-V compound material above the second device region R2 is annealed and activated, it may also have a negative impact on the second portion 16B of the III-V compound barrier layer 16 thereunder (for example, but not limited to, the dopants in the P-type doped III-V compound material diffuse into the second portion 16B of the III-V compound barrier layer 16). Therefore, annealing and activating the P-type doped III-V compound material (that is, the patterned P-type doped III-V compound layer 20P) after the patterning process can avoid and / or improve the above problems.

[0113] like Figure 6 and Figure 7As shown, after the annealing process 99, a dielectric layer 38, a dielectric layer 40, a gate structure GE1, a gate structure GE2, a source structure SE1, a source structure SE2, a drain structure DE1, and a drain structure DE2 may be formed, thereby forming a semiconductor device 101 including a transistor structure T1 located on the first device region R1 and a transistor structure T2 located on the second device region R2. The dielectric layer 38 may be formed on the dielectric layer 36 and located above the first device region R1 and the second device region R2, and the dielectric layer 40 may be formed on the dielectric layer 38 and located above the first device region R1 and the second device region R2. The transistor structure T1 may include a first portion 14A of the III-V compound semiconductor layer 14, a first portion 16A of the III-V compound barrier layer 16, a patterned P-type doped III-V compound layer 20P, a first mask pattern 32P, a gate structure GE1, a source structure SE1, and a drain structure DE1, while the transistor structure T2 may include a second portion 14B of the III-V compound semiconductor layer 14, a second portion 16B of the III-V compound barrier layer 16, a gate structure GE2, a source structure SE2, and a drain structure DE2. In the transistor structure T1, the gate structure GE1 can be formed on the patterned P-type doped III-V compound layer 20P, and the gate structure GE1 can penetrate the dielectric layer 38 and the dielectric layer 36 in the vertical direction Z and be electrically connected to the patterned P-type doped III-V compound layer 20P through the first mask pattern 32P, and the source structure SE1 and the drain structure DE1 can penetrate the dielectric layer 40, the dielectric layer 38, the dielectric layer 36 and the first part 16A of the III-V compound barrier layer 16 in the vertical direction Z and be partially set in the first part 14A of the III-V compound semiconductor layer 14, but it is not limited to this. In the transistor structure T2, the gate structure GE2 can penetrate the dielectric layer 38 and the dielectric layer 36 in the vertical direction Z and be connected to the second portion 16B of the III-V compound barrier layer 16, and the source structure SE2 and the drain structure DE2 can penetrate the dielectric layer 40, the dielectric layer 38, the dielectric layer 36 and the second portion 16B of the III-V compound barrier layer 16 in the vertical direction Z and be partially set in the second portion 14B of the III-V compound semiconductor layer 14, but is not limited to this.

[0114] In some embodiments, the dielectric layer 38 and the dielectric layer 40 may include tetraethoxysilane (TEOS) or other suitable dielectric materials, and the gate structure GE1, the gate structure GE2, the source structure SE1, the source structure SE2, the drain structure DE1, and the drain structure DE2 may respectively include a barrier layer (not shown) and a metal layer (not shown) disposed on the barrier layer, but the present invention is not limited thereto. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or other suitable barrier materials, and the metal layer may include tungsten, copper, aluminum, titanium aluminum alloy, or other suitable metal materials. In the transistor structure T1 and the transistor structure T2, a two-dimensional electron gas (2DEG) may be formed in the III-V compound semiconductor layer 14 near the interface between the III-V compound semiconductor 14 and the III-V compound barrier layer 16. The two-dimensional electron gas 2DEG in the transistor structure T1 may be partially located between the source structure SE1 and the drain structure DE1 in the horizontal direction, and the two-dimensional electron gas 2DEG in the transistor structure T2 may be partially located between the source structure SE2 and the drain structure DE2 in the horizontal direction, but the present invention is not limited thereto. In some embodiments, the transistor structure T1 having the patterned P-type doped III-V compound layer 20P may be considered as an enhancement mode (E-mode) transistor, and the transistor structure T2 without the P-type doped III-V compound layer may be considered as a depletion mode (D-mode) transistor, so the first device region R1 may be an enhancement mode device region, and the second device region R2 may be a depletion mode device region, but the present invention is not limited thereto. By using the above-mentioned manufacturing method, the damage to the second portion 16B of the III-V compound barrier layer 16 in the transistor structure T2 when forming the patterned P-type doped III-V compound layer 20P can be reduced, thereby improving the electrical performance of the transistor structure T2 (for example, but not limited to reducing the leakage current of the transistor structure T2, I off ). In addition, the transistor structure formed by the manufacturing method of the present invention is not Figure 7 The transistor structure T1 and the transistor structure T2 shown in the figure are limited thereto, and the manufacturing method of the present invention can also be used to form transistors with other structures on the first device region R1 and the second device region R2.

[0115] like Figure 7As shown, the semiconductor device 101 includes a substrate 10, a III-V compound semiconductor layer 14, a III-V compound barrier layer 16, and a patterned P-type doped III-V compound layer 20P. The substrate 10 has an enhancement type device region (e.g., a first device region R1) and a depletion type device region (e.g., a second device region R2). The III-V compound semiconductor layer 14 is disposed on the first device region R1 and the second device region R2, the III-V compound barrier layer 16 is disposed on the III-V compound semiconductor layer 14, and the III-V compound barrier layer 16 is located on the first device region R1 and the second device region R2. The patterned P-type doped III-V compound layer 20P is disposed on the III-V compound barrier layer 16 and is located on the first device region R1. The thickness TK3 of the III-V compound barrier layer 16 located on the first device region R1 is substantially equal to the thickness TK4 of the III-V compound barrier layer 16 located on the second device region R2. In some embodiments, the phase difference between the thickness TK3 and the thickness TK4 may be less than a preset value, which is about 1 nanometer, 2 nanometers, or 3 nanometers, but is not limited thereto. In addition, in some embodiments, the upper surface TS2 of the III-V compound barrier layer 16 located on the second device region R2 may be slightly lower in the vertical direction Z than the upper surface TS1 of the III-V compound barrier layer 16 located on the first device region R1. For example, the distance DS between the upper surface TS2 and the upper surface TS1 in the vertical direction Z may be greater than 0 and less than 3 nanometers, and the phase difference between the thickness TK3 and the thickness TK4 may also be greater than 0 and less than 3 nanometers, but is not limited thereto.

[0116] The following will describe different embodiments of the present invention, and for simplicity, the following description will mainly describe the differences between the embodiments, and will not repeat the same parts. In addition, the same elements in the embodiments of the present invention are marked with the same reference numerals to facilitate comparison between the embodiments.

[0117] See also Figure 8 . Figure 8 FIG. 1 is a schematic diagram of a semiconductor device 102 according to another embodiment of the present invention. Figure 8As shown, in the semiconductor device 102, the thickness TK3 of the III-V compound barrier layer 16 located on the first device region R1 and the thickness TK4 of the III-V compound barrier layer 16 located on the second device region R2 may be substantially equal. In some embodiments, the difference between the thickness TK3 and the thickness TK4 may be less than 3 nanometers and approach 0, and the distance between the upper surface TS2 of the III-V compound barrier layer 16 located on the second device region R2 and the upper surface TS1 of the III-V compound barrier layer 16 located on the first device region R1 in the vertical direction Z may also be less than 3 nanometers and approach 0, but the invention is not limited thereto.

[0118] See also Figures 9 to 12 as well as Figure 4 . Figures 9 to 12 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device according to a second embodiment of the present invention, wherein Fig.10 Draws Fig. 9 The following diagram shows the situation: Fig.11 Draws Fig.10 The following diagram shows the situation: Fig.12 Draws Fig.11 In some embodiments, Figure 4 can be considered as depicting Fig.12 In this embodiment, the method for forming the stacked structure may include the following steps. Fig. 9 As shown, a first P-type doped III-V compound material 22 may be formed on the III-V compound barrier layer 16, and the first P-type doped III-V compound material 22 is located on the first device region R1 and the second device region R2. A first portion 22A of the first P-type doped III-V compound material 22 may be formed on the first portion 16A of the III-V compound barrier layer 16, and a second portion 22B of the first P-type doped III-V compound material 22 may be formed on the second portion 16B of the III-V compound barrier layer 16, and the thickness of the first portion 22A is substantially equal to the thickness of the second portion 22B. Then, as shown in FIG. Fig. 9 and Fig.10 As shown, a removal process 93 may be performed to remove the first P-type doped III-V compound material 22 (eg, the first portion 22A) located on the first device region R1 to expose the upper surface of the first portion 16A of the III-V compound barrier layer 16 .

[0119] In some embodiments, a patterned mask layer 82 may be formed to cover the first P-type doped III-V compound material 22 (e.g., the second portion 22B) located on the second device region R2. The patterned mask layer 82 may be used to protect the first P-type doped III-V compound material 22 on the second device region R2 during the removal process 93, and the patterned mask layer 82 may include photoresist or other suitable mask materials. In some embodiments, the removal process 93 may include an etching process (e.g., but not limited to a wet etching process) or other suitable removal methods, and the first P-type doped III-V compound material 22 (e.g., the first portion 22A) located on the first device region R1 may be removed by an etching process (e.g., a wet etching process). Figures 9 to 11 As shown, after the first P-type doped III-V compound material 22 located on the first device region R1 is removed, a second P-type doped III-V compound material 24 may be formed, and the second P-type doped III-V compound material 24 may be formed on the III-V compound barrier layer 16 located on the first device region R1 and on the first P-type doped III-V compound material 22 located on the second device region R2. A first portion 24A of the second P-type doped III-V compound material 24 may be formed on the first portion 16A of the III-V compound barrier layer 16 and directly contact the first portion 16A, a second portion 24B of the second P-type doped III-V compound material 24 may be formed on the second portion 22B of the first P-type doped III-V compound material 22 and directly contact the second portion 22B, and a thickness TK13 of the first portion 24A of the second P-type doped III-V compound material 24 may be substantially equal to a thickness TK23 of the second portion 24B. As shown in FIG. Fig.11 and Fig.12 As shown, after the second P-type doped III-V compound material 24 is formed, a first mask layer 32 can be formed on the second P-type doped III-V compound material 24, and a second mask layer 34 can be formed on the first mask layer 32, thereby forming a first portion P1 and a second portion P2 of the stacked structure LS on the first device region R1 and the second device region R2, respectively.

[0120] In some embodiments, the P-type doped III-V compound layer 20 (e.g., the first portion 20A described above) in the first portion P1 of the stacked structure LS may be composed of a second P-type doped III-V compound material 24 (e.g., the first portion 24A) located on the first device region R1, and the P-type doped III-V compound layer 20 (e.g., the second portion 20B described above) in the second portion P2 of the stacked structure LS may be composed of a first P-type doped III-V compound material 22 (e.g., the second portion 22B) located on the second device region R2 and a second P-type doped III-V compound material 24 (e.g., the second portion 24B) located on the second device region R2. Therefore, in this way, the thickness of the first portion 20A of the P-type doped III-V compound layer 20 (e.g., the thickness TK13) may be smaller than the thickness of the second portion 20B (e.g., the sum of the thickness TK22 and the thickness TK23), and further, the thickness TK1 of the first portion P1 of the stacked structure LS may be smaller than the thickness TK2 of the second portion P2. In some embodiments, the material composition of the second P-type doped III-V compound material 24 may be the same as the material composition of the first P-type doped III-V compound material 22, but is not limited thereto. In addition, the thickness TK23 of the second P-type doped III-V compound material 24 may be greater than the thickness TK22 of the first P-type doped III-V compound material 22, thereby preventing the overly thick first P-type doped III-V compound material 22 from affecting the patterning process 92. Fig.12 as well as Figure 4 As shown, the P-type doped III-V compound layer 20, the first mask layer 32, and the second mask layer 34 in the first portion P1 of the stacked structure LS can be patterned by the patterning process 92 to form a patterned P-type doped III-V compound layer 20P, a first mask pattern 32P, and a second mask pattern 34P located on the first device region R1, and the second portion P2 of the stacked structure LS can be completely removed by the patterning process 92 to expose the upper surface TS2 of the III-V compound barrier layer 16 located on the second device region R2. In some embodiments, the above-mentioned Figures 5 to 7 The manufacturing steps shown are used to form a semiconductor device 101, but the present invention is not limited thereto.

[0121] See also Figures 13 to 15 as well as Figure 4 . Figures 13 to 15 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device according to a third embodiment of the present invention, wherein Fig.14 Draws Fig.13 The following diagram shows the situation: Fig.15 Draws Fig.14 In some embodiments, Figure 4 can be considered as depicting Fig.15 In this embodiment, the method for forming the stacked structure may include the following steps. Fig.13 As shown, a P-type doped III-V compound layer 20 may be formed on the III-V compound barrier layer 16, and a first mask material 32M may be formed on the P-type doped III-V compound layer 20, and the first mask material 32M is located on the first device region R1 and the second device region R2. The thickness of the first mask material 32M formed on the first portion 20A of the P-type doped III-V compound layer 20 and the thickness of the first mask material 32M formed on the second portion 20B of the P-type doped III-V compound layer 20 may be substantially equal. Then, as shown in FIG. Figure 13 to Figure 14 As shown, a second thinning process (e.g., thinning process 94) may be performed on the first mask material 32M located on the first device region R1 to reduce the thickness of the first mask material 32M located on the first device region R1. In some embodiments, a patterned mask layer 83 may be formed to cover the first mask material 32M located on the second device region R2, and the patterned mask layer 83 may be used to protect the first mask material 32M on the second device region R2 in the thinning process 94, and the patterned mask layer 83 may include photoresist or other suitable mask materials. In some embodiments, the thinning process 94 may include an etching process (e.g., but not limited to an etch-back process) or other suitable thinning methods, and the patterned mask layer 83 may be removed after the thinning process 94. After the thinning process 94, the thickness TK14 of the first mask material 32M located on the first device region R1 may be less than the thickness TK24 of the first mask material 32M located on the second device region R2. In some embodiments, the thickness TK14 may be approximately 30 nanometers, and the thickness TK24 may be less than 35 nanometers, but is not limited thereto.

[0122] like Figures 13 to 15 As shown, the first mask material 32M retained on the P-type doped III-V compound layer 20 after the thinning process 94 can become the first mask layer 32 in the stacked structure LS, and after the thinning process 94, a second mask layer 34 can be formed on the first mask layer 32, thereby forming the first portion P1 and the second portion P2 of the stacked structure LS on the first device region R1 and the second device region R2, respectively. Therefore, in this embodiment, the thickness TK14 of the first portion 32A of the first mask layer 32 can be less than the thickness TK24 of the second portion 32B, thereby making the thickness TK1 of the first portion P1 of the stacked structure LS less than the thickness TK2 of the second portion P2. Afterwards, as Fig.15 as well as Figure 4As shown, the P-type doped III-V compound layer 20, the first mask layer 32, and the second mask layer 34 in the first portion P1 of the stacked structure LS can be patterned by the patterning process 92 to form a patterned P-type doped III-V compound layer 20P, a first mask pattern 32P, and a second mask pattern 34P located on the first device region R1, and the second portion P2 of the stacked structure LS can be completely removed by the patterning process 92 to expose the upper surface TS2 of the III-V compound barrier layer 16 located on the second device region R2. In some embodiments, the above-mentioned Figures 5 to 7 The manufacturing steps shown are used to form a semiconductor device 101, but the present invention is not limited thereto.

[0123] See also Fig.16 , Fig.17 as well as Figure 4 . Fig.16 and Fig.17 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention, wherein Fig.17 Draws Fig.16 In some embodiments, Figure 4 can be considered as depicting Fig.17 In this embodiment, the method for forming the stacked structure may include the following steps. Fig.16 As shown, a P-type doped III-V compound layer 20 may be formed on the III-V compound barrier layer 16, a first mask layer 32 may be formed on the P-type doped III-V compound layer 20, and a second mask material 34M may be formed on the first mask layer 32, and the second mask material 34M may be located above the first device region R1 and the second device region R2. The thickness of the second mask material 34M formed on the first portion 32A of the first mask layer 32 may be substantially equal to the thickness of the second mask material 34M formed on the second portion 32B of the first mask layer 32. Then, as shown in FIG. Figure 16 to Figure 17As shown, a third thinning process (e.g., thinning process 95) may be performed on the second mask material 34M located on the first device region R1 to reduce the thickness of the second mask material 34M located on the first device region R1. In some embodiments, a patterned mask layer 84 may be formed to cover the second mask material 34M located on the second device region R2. The patterned mask layer 84 may be used to protect the second mask material 34M on the second device region R2 during the thinning process 95, and the patterned mask layer 84 may include photoresist or other suitable mask materials. In some embodiments, the thinning process 95 may include an etching process (e.g., but not limited to an etch-back process) or other suitable thinning methods, and the patterned mask layer 84 may be removed after the thinning process 95. After the thinning process 95, the thickness TK15 of the second mask material 34M located on the first device region R1 may be less than the thickness TK25 of the second mask material 34M located on the second device region R2.

[0124] The second mask material 34M remaining on the first mask layer 32 after the thinning process 95 may become the second mask layer 34 in the stacked structure LS, so the first portion P1 and the second portion P2 of the stacked structure LS may be formed on the first device region R1 and the second device region R2 respectively through the thinning process 95. In the present embodiment, the thickness TK15 of the first portion 34A of the second mask layer 34 may be less than the thickness TK25 of the second portion 34B, thereby making the thickness TK1 of the first portion P1 of the stacked structure LS less than the thickness TK2 of the second portion P2. Fig.17 as well as Figure 4 As shown, the P-type doped III-V compound layer 20, the first mask layer 32, and the second mask layer 34 in the first portion P1 of the stacked structure LS can be patterned by the patterning process 92 to form a patterned P-type doped III-V compound layer 20P, a first mask pattern 32P, and a second mask pattern 34P located on the first device region R1, and the second portion P2 of the stacked structure LS can be completely removed by the patterning process 92 to expose the upper surface TS2 of the III-V compound barrier layer 16 located on the second device region R2. In some embodiments, the above-mentioned Figures 5 to 7 The manufacturing steps shown are used to form a semiconductor device 101, but the present invention is not limited thereto.

[0125] In summary, in the semiconductor device and its manufacturing method of the present invention, the thickness of the stacked structure located above the second device area can be made greater than the thickness of the stacked structure located above the first device area, thereby reducing the damage and / or thickness variation effect of the patterning process on the III-V compound barrier layer located above the second device area, thereby improving the electrical performance of the semiconductor device subsequently formed on the second device area.

[0126] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, comprising: Providing a substrate having a first device region and a second device region; forming a III-V compound semiconductor layer on the first device region and the second device region; forming a III-V compound barrier layer on the III-V compound semiconductor layer, wherein the III-V compound barrier layer is located above the first device region and the second device region; A stacked structure is formed on the III-V compound barrier layer, wherein a first portion of the stacked structure is located above the first device region, a second portion of the stacked structure is located above the second device region, and the stacked structure comprises: A P-type doped III-V compound layer is located in the first portion and the second portion of the stacked structure; and a first mask layer disposed on the P-type doped III-V compound layer, wherein the first mask layer is located in the first portion and the second portion of the stacked structure; and The stacked structure is subjected to a patterning process, wherein the first portion of the stacked structure is patterned by the patterning process, the second portion of the stacked structure is removed by the patterning process, and before the patterning process, the thickness of the second portion of the stacked structure is greater than the thickness of the first portion of the stacked structure. 2 . The method for manufacturing a semiconductor device as claimed in claim 1 , wherein the second portion of the stacked structure is completely removed by the patterning process to expose an upper surface of the III-V compound barrier layer located above the second device region.

3. The method for manufacturing a semiconductor device according to claim 1, wherein a method for forming the stacked structure comprises: forming a P-type doped III-V compound material on the III-V compound barrier layer, wherein the P-type doped III-V compound material is located above the first device region and the second device region; as well as A first thinning process is performed on the P-type doped III-V compound material located above the first device region, wherein after the first thinning process, the thickness of the P-type doped III-V compound material located above the first device region is less than the thickness of the P-type doped III-V compound material located above the second device region, and the P-type doped III-V compound material remaining on the III-V compound barrier layer after the first thinning process becomes the P-type doped III-V compound layer in the stacked structure.

4. The method for manufacturing a semiconductor device according to claim 3, wherein the method for forming the stacked structure further comprises: After the first thinning process, forming the first mask layer on the P-type doped III-V compound layer; as well as A second mask layer is formed on the first mask layer, wherein the second mask layer is located in the first portion and the second portion of the stacked structure, and the material composition of the second mask layer is different from the material composition of the first mask layer.

5. The method for manufacturing a semiconductor device according to claim 1, wherein a method for forming the stacked structure comprises: forming a first P-type doped III-V compound material on the III-V compound barrier layer, wherein the first P-type doped III-V compound material is located above the first device region and the second device region; removing the first P-type doped III-V compound material located above the first device region; as well as After the first P-type doped III-V compound material located above the first device area is removed, a second P-type doped III-V compound material is formed, wherein the second P-type doped III-V compound material is formed on the III-V compound barrier layer located above the first device area and on the first P-type doped III-V compound material located above the second device area.

6. A method for manufacturing a semiconductor device as described in claim 5, wherein the P-type doped III-V compound layer located in the first part of the stacked structure is composed of the second P-type doped III-V compound material located above the first device area, and the P-type doped III-V compound layer located in the second part of the stacked structure is composed of the first P-type doped III-V compound material located above the second device area and the second P-type doped III-V compound material located above the second device area. 7 . The method for manufacturing a semiconductor device as claimed in claim 5 , wherein a material composition of the second P-type doped III-V compound material is the same as a material composition of the first P-type doped III-V compound material. 8 . The method for manufacturing a semiconductor device as claimed in claim 5 , wherein a thickness of the second P-type doped III-V compound material is greater than a thickness of the first P-type doped III-V compound material. 9 . The method for manufacturing a semiconductor device as claimed in claim 5 , wherein the first P-type doped III-V compound material located on the first device region is removed by a wet etching process.

10. The method for manufacturing a semiconductor device according to claim 5, wherein the method for forming the stacked structure further comprises: forming the first mask layer on the second P-type doped III-V compound material; as well as A second mask layer is formed on the first mask layer, wherein the second mask layer is located in the first portion and the second portion of the stacked structure, and the material composition of the second mask layer is different from the material composition of the first mask layer.

11. The method for manufacturing a semiconductor device according to claim 1, wherein a method for forming the stacked structure comprises: forming the P-type doped III-V compound layer on the III-V compound barrier layer; forming a first mask material on the P-type doped III-V compound layer, wherein the first mask material is located above the first device region and the second device region; as well as A second thinning process is performed on the first mask material located above the first device area, wherein after the second thinning process, the thickness of the first mask material located above the first device area is less than the thickness of the first mask material located above the second device area, and the first mask material retained on the P-type doped III-V compound layer after the second thinning process becomes the first mask layer in the stacked structure.

12. The method for manufacturing a semiconductor device according to claim 11, wherein the method for forming the stacked structure further comprises: After the second thinning process, a second mask layer is formed on the first mask layer, wherein the second mask layer is located in the first portion and the second portion of the stacked structure, and the material composition of the second mask layer is different from that of the first mask layer.

13. The method for manufacturing a semiconductor device according to claim 1, wherein the stacked structure further comprises: The second mask layer is disposed on the first mask layer, wherein the second mask layer is located in the first part and the second part of the stacked structure. 14 . The method for manufacturing a semiconductor device as claimed in claim 13 , wherein the stacked structure is composed of the P-type doped III-V compound layer, the first mask layer and the second mask layer.

15. The method for manufacturing a semiconductor device according to claim 13, wherein a method for forming the stacked structure comprises: forming the P-type doped III-V compound layer on the III-V compound barrier layer; forming the first mask layer on the P-type doped III-V compound layer; forming a second mask material on the first mask layer, wherein the second mask material is located above the first device region and the second device region; as well as The second mask material located above the first device area is subjected to a third thinning process, wherein after the third thinning process, the thickness of the second mask material located above the first device area is less than the thickness of the second mask material located above the second device area, and the second mask material remaining on the first mask layer after the third thinning process becomes the second mask layer in the stacked structure.

16. The method for manufacturing a semiconductor device as claimed in claim 1, wherein the P-type doped III-V compound layer in the first portion of the stacked structure is patterned by the patterning process to form a patterned P-type doped III-V compound layer located on the first device region, and the method for manufacturing the semiconductor device further comprises: forming a gate structure on the patterned P-type doped III-V compound layer; as well as After the patterning process and before forming the gate structure, the patterned P-type doped III-V compound layer is subjected to an annealing process. 17 . The method for manufacturing a semiconductor device as claimed in claim 1 , wherein the first device region is an enhancement mode device region, and the second device region is a depletion mode device region.

18. The method for manufacturing a semiconductor device as claimed in claim 1, wherein after the patterning process, a distance in a vertical direction between an upper surface of the III-V compound barrier layer located above the first device region and an upper surface of the III-V compound barrier layer located above the second device region is less than 3 nanometers.

19. A semiconductor device comprising: A substrate having an enhanced device region and a depleted device region; A III-V compound semiconductor layer is disposed on the enhancement type device region and the depletion type device region; A III-V compound barrier layer disposed on the III-V compound semiconductor layer, wherein the III-V compound barrier layer is located above the enhancement mode device region and the depletion mode device region; as well as A patterned P-type doped III-V compound layer is disposed on the III-V compound barrier layer and is located above the enhancement type device region, wherein a thickness of the III-V compound barrier layer located above the enhancement type device region is substantially equal to a thickness of the III-V compound barrier layer located above the depletion type device region.

20. The semiconductor device of claim 19, wherein a distance in a vertical direction between an upper surface of the III-V compound barrier layer located above the enhancement mode device region and an upper surface of the III-V compound barrier layer located above the depletion mode device region is less than 3 nanometers.

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