Gallium nitride-based p-channel device and preparation method thereof

Abstract

The invention relates to a gallium nitride-based p-channel device and a preparation method thereof, and belongs to the technical field of semiconductor devices. The preparation method comprises the following steps: providing an epitaxial structure of which the outermost layer is a p-type GaN layer; coating the surface of the p-type GaN layer with a Mg-doped SOG solution to obtain an intermediate; performing annealing treatment on the intermediate to form a doped region and a non-doped region except the doped region on the surface of the p-type GaN layer; forming a source electrode, a drain electrode and an ohmic grid electrode at intervals on at least part of the surface corresponding to the doped region; and forming a Schottky grid electrode on a part of the surface corresponding to the non-doped region, enabling the Schottky grid electrode and the ohmic grid electrode to be in contact with each other to form a mixed grid electrode, and enabling the mixed grid electrode to be arranged between the source electrode and the drain electrode. According to the preparation method, on the premise of no etching damage and no introduction of an additional complex process, the source electrode, the drain electrode and the ohmic grid electrode are processed at the same time, preparation of low-resistance source and drain ohmic contact electrodes is achieved, meanwhile, a mixed grid electrode structure is formed, and the performance of the device can be effectively improved.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a gallium nitride-based p-channel device and a preparation method thereof. Background Art

[0002] Complementary metal oxide semiconductor (CMOS) technology based on the integration of gallium nitride (GaN)-based p-channel devices and n-channel devices can not only achieve zero static power loss and significantly reduce the impact of parasitic inductance and capacitance, but also effectively reduce circuit complexity and provide higher noise resistance and linearity for the circuit. It has become an important development trend in the commercial development of all-gallium nitride integrated circuits (all GaN ICs).

[0003] However, due to the low carrier concentration in the epitaxial structure of the GaN-based p-channel device (holes are the main carriers) and the high work function (7.5eV) of the p-type GaN layer, it is difficult to prepare the source and drain ohmic contact electrodes on the p-type GaN layer. In order to prepare good source and drain electrodes, additional etching, regrowth and other steps are often introduced, which makes the preparation process complicated and will bring secondary effects to the device performance (such as surface damage, increased leakage current and reduced device reliability). In addition, the gate structure of the GaN-based p-channel device mostly still uses the traditional Schottky gate, and its threshold voltage is easily affected by temperature changes, material inhomogeneity and long-term working conditions, resulting in significant fluctuations under high temperature or high frequency operation, thereby affecting the normal operation of the device. In addition, the Schottky gate is also prone to poor contact with the p-type GaN layer, which in turn increases the leakage current of the device and reduces the switching efficiency. Summary of the invention

[0004] To solve the above problems, the purpose of the embodiments of the present application includes providing a gallium nitride-based p-channel device and a preparation method thereof, which can simultaneously process the source, drain and ohmic gate without etching damage and without introducing additional complex processes, thereby realizing the preparation of low-resistance source and drain ohmic contact electrodes and forming a hybrid gate structure of an ohmic gate and a Schottky gate, thereby effectively improving the performance of the device.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a gallium nitride-based p-channel device, comprising the following steps:

[0006] Providing an epitaxial structure with a p-type GaN layer as the outermost layer;

[0007] Coating a Mg-doped SOG solution on the surface of the p-type GaN layer to obtain an intermediate;

[0008] Annealing the intermediate to form a doped region doped with Mg and a non-doped region other than the doped region on the surface of the p-type GaN layer;

[0009] Forming a source electrode, a drain electrode and an ohmic gate electrode spaced apart from each other on at least a portion of the surface corresponding to the doped region;

[0010] A Schottky gate is formed on a portion of the surface corresponding to the non-doped region. The Schottky gate and the ohmic gate contact each other to form a hybrid gate, and the hybrid gate is arranged between the source and the drain.

[0011] In the above technical solution, selective doping is achieved by coating the surface of the p-type GaN layer with a Mg-doped SOG solution, and while preparing the low-resistance source and drain, the ohmic gate in the hybrid gate is processed, which can avoid the damage that may be caused to the surface and crystal structure of the p-type GaN layer by processes such as dry etching and ion implantation, and effectively improve the overall performance of the device, especially in high-frequency and high-power applications, avoiding the adverse effects of etching, such as surface damage, increased leakage current, and decreased device reliability. In addition, the SOG doping process is simple and low-cost. Compared with the traditional complex etching or regrowth process, this process not only avoids cumbersome steps, but also greatly reduces the manufacturing cost. In addition, by further forming a Schottky gate to manufacture a hybrid gate, the threshold voltage instability and reliability problems caused by temperature fluctuations or process instability of a single Schottky gate, as well as the common leakage current and driving design difficulties of a single ohmic gate can be effectively avoided. It not only provides a threshold voltage with low leakage current and high stability, but also ensures a high saturation output current, improves the overall performance and reliability of the device, and enables the device to maintain better stability and longer service life in high-power and high-efficiency applications. This preparation method can not only simplify the manufacturing process and reduce costs, but also effectively improve the performance and reliability of GaN-based p-channel devices, giving them broader application prospects in GaN monolithic integration.

[0012] In some embodiments of the present application, the Mg doping concentration in the SOG solution is greater than 1e 19 cm -3 .

[0013] In some embodiments of the present application, the annealing temperature is 700° C. to 900° C., and the annealing time is 20 min to 200 min.

[0014] In some embodiments of the present application, it also includes:

[0015] Disposing a first mask and a second mask spaced apart on the surface of the p-type GaN layer so that the doped region includes a first doped region, a second doped region and a third doped region spaced apart;

[0016] Forming a source electrode, a drain electrode and an ohmic gate electrode on the surfaces corresponding to the first doping region, the second doping region and the third doping region respectively;

[0017] The first mask and the second mask are removed.

[0018] In some embodiments of the present application, the epitaxial structure includes a substrate, a buffer layer, an n-type GaN layer, an AlGaN layer, and a p-type GaN layer stacked in sequence;

[0019] The preparation method also includes:

[0020] Surface cleaning of epitaxial structures;

[0021] Part of the p-type GaN layer, the AlGaN layer and the n-type GaN layer is removed to form a mesa isolation.

[0022] In a second aspect, an embodiment of the present application provides the above-mentioned gallium nitride-based p-channel device, including a source, a drain, an ohmic gate, a Schottky gate, and an epitaxial structure with a p-type GaN layer as the outermost layer; the surface of the p-type GaN layer has a doped region doped with Mg and a non-doped region other than the doped region, the source, the drain and the ohmic gate are formed on a portion of the surface of the p-type GaN layer corresponding to the doped region intervals, the Schottky gate is formed on a portion of the surface of the p-type GaN layer corresponding to the non-doped region, the ohmic gate and the Schottky gate are in contact with each other to form a hybrid gate, and the hybrid gate is arranged between the source and the drain.

[0023] In the above technical solution, by forming a doped region on the surface of the p-type GaN layer, the ohmic contact resistance of the source, drain and ohmic gate can be reduced, thereby effectively improving the performance of the device. In addition, by setting a Schottky gate and an ohmic gate to form a hybrid gate, the threshold voltage instability and reliability problems caused by temperature fluctuations or process instability of a single Schottky gate, as well as the common problems of large leakage current and difficult driving design of a single ohmic gate can be effectively avoided. It not only provides a low leakage current and a high stability threshold voltage, but also ensures a high saturation output current, improves the overall performance and reliability of the device, and enables the device to maintain better stability and longer service life in high-power and high-efficiency applications.

[0024] In some embodiments of the present application, the doping concentration of Mg in the doping region is greater than 1e 19 cm -3 .

[0025] In some embodiments of the present application, the ohmic gate is disposed on a side close to the drain; or, the ohmic gate is disposed on a side close to the source; or, a plurality of ohmic gates and Schottky gates are alternately arranged.

[0026] In some embodiments of the present application, the number of the ohmic gates and the Schottky gates are independently 1 to 10, the heights are independently 10 nm to 500 nm, and the widths are independently 2 nm to 20 nm.

[0027] In some embodiments of the present application, the epitaxial structure includes a substrate, a buffer layer, an n-type GaN layer, an AlGaN layer, and a p-type GaN layer stacked in sequence. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0029] Figure 1 A process flow chart of a method for preparing a gallium nitride-based p-channel device provided in an embodiment of the present application.

[0030] Figure 2 A schematic cross-sectional view of an epitaxial structure provided in an embodiment of the present application.

[0031] Figure 3 For Figure 2 The cross-sectional schematic diagram of the epitaxial structure after mesa isolation is shown.

[0032] Figure 4 For Figure 3 The cross-sectional schematic diagram shown is a p-type GaN layer surface after a mask is set.

[0033] Figure 5 For Figure 4 A schematic cross-sectional view of an intermediate body obtained after a SOG coating is formed on the surface of a p-type GaN layer and a mask is shown.

[0034] Figure 6 For Figure 5 The intermediate shown is a schematic cross-sectional view after annealing to form a first doping region, a second doping region and a third doping region in the p-type GaN layer.

[0035] Figure 7 For the general Figure 6 A schematic cross-sectional view of the structure after the mask and residual SOG coating are removed is shown.

[0036] Figure 8 For Figure 7 The schematic cross-sectional view shows a first doping region surface after a source is formed on the first doping region surface, a drain is formed on the second doping region surface, and an ohmic gate is formed on the third doping region surface.

[0037] Fig. 9 A cross-sectional schematic diagram of a gallium nitride-based p-channel device provided in one embodiment of the present application.

[0038] Fig.10A schematic cross-sectional view of a gallium nitride-based p-channel device provided in accordance with another embodiment of the present application.

[0039] Fig.11 A schematic cross-sectional view of a gallium nitride-based p-channel device provided in accordance with another embodiment of the present application.

[0040] Description of main component symbols:

[0041] 10-epitaxial structure; 101-substrate; 102-buffer layer; 103-n-type GaN layer; 104-AlGaN layer; 105-p-type GaN layer; 20-mask; 201-first mask; 202-second mask; 30-SOG coating; 100-intermediate; 401-first doped region; 402-second doped region; 403-third doped region; 501-source; 502-drain; 503-hybrid gate; 5031-ohmic gate; 5032-Schottky gate; A-doped region; B-non-doped region. DETAILED DESCRIPTION

[0042] Hereinafter, the embodiments of the gallium nitride-based p-channel device and the method for preparing the same of the present application are specifically disclosed with appropriate reference to the accompanying drawings. However, there may be cases where unnecessary detailed descriptions are omitted. For example, there are cases where detailed descriptions of well-known matters and repeated descriptions of actually the same structures are omitted. This is to avoid the following description from becoming unnecessarily lengthy and to facilitate the understanding of those skilled in the art. In addition, the drawings and the following descriptions are provided for those skilled in the art to fully understand the present application and are not intended to limit the subject matter described in the claims.

[0043] If not otherwise specified, all embodiments and optional embodiments of the present application can be combined with each other to form a new technical solution.

[0044] Unless otherwise specified, all technical features and optional technical features of this application can be combined with each other to form a new technical solution.

[0045] If there is no special explanation, all steps of the present application can be performed sequentially or randomly, preferably sequentially. For example, the method includes steps (a) and (b), which means that the method may include steps (a) and (b) performed sequentially, or may include steps (b) and (a) performed sequentially. For example, the method may further include step (c), which means that step (c) may be added to the method in any order. For example, the method may include steps (a), (b) and (c), or may include steps (a), (c) and (b), or may include steps (c), (a) and (b), etc.

[0046] As mentioned above, in order to prepare good source and drain electrodes on the surface of the p-GaN layer of the GaN-based p-channel device, additional etching, regrowth and other steps are often introduced. Since the GaN material itself is relatively fragile during the etching process, especially when the gate is dry-etched, it is easy to cause surface damage. During the etching process, the surface of GaN may be affected by etching gas or physical impact, resulting in a large number of surface defects and interface states. These defects will not only reduce the quality of the GaN surface, but also cause an increase in leakage current, thereby adversely affecting the switching performance of the device. As the device is used for a longer time, these damages will further affect the reliability of the device, resulting in poor long-term stability and shortened service life. In addition, steps such as dry etching and regrowth are not only complex in process, but also costly. Dry etching involves high-energy physical and chemical reactions, which may require repeated operations many times, and there is a certain loss in each operation. The regrowth process also requires high temperature conditions and high-purity materials, further increasing the overall manufacturing cost. In addition, in order to ensure the quality of the device, complex optimization and adjustment are often required during the etching and regrowth processes to reduce damage and ensure device performance, which not only increases the production cycle, but also greatly increases the process complexity and production cost.

[0047] In addition, most of the gate structures of GaN-based p-channel devices still use traditional Schottky gates. Although the gate structure is relatively simple, the threshold voltage is easily affected by temperature changes, material inhomogeneity and long-term working conditions, resulting in significant fluctuations under high temperature or high frequency operation, thus affecting the normal operation of the device. In addition, the Schottky gate is also prone to poor contact with the p-GaN layer, which in turn increases the leakage current of the device and reduces the switching efficiency.

[0048] Based on this, the embodiment of the present application provides a method for preparing a gallium nitride-based p-channel device, which realizes selective doping by coating a Mg-doped SOG solution on the surface of the p-type GaN layer, and processes the ohmic gate in the hybrid gate while preparing a low-resistance source and drain, thereby avoiding damage to the surface and crystal structure of the p-type GaN layer caused by processes such as dry etching and ion implantation, and effectively improving the overall performance of the device, especially in high-frequency and high-power applications, avoiding the adverse effects of etching, such as surface damage, increased leakage current, and decreased device reliability. In addition, the SOG doping process is simple and low-cost. Compared with the traditional complex etching or regrowth process, this process not only avoids cumbersome steps, but also greatly reduces the manufacturing cost. In addition, by further forming a Schottky gate to manufacture a hybrid gate, the threshold voltage instability and reliability problems caused by temperature fluctuations or process instability of a single Schottky gate can be effectively avoided, as well as the large leakage current and difficult driving design problems common to a single ohmic gate. It not only provides low leakage current and high stability of the threshold voltage, but also ensures high saturation output current, improves the overall performance and reliability of the device, and enables the device to maintain better stability and longer service life in high-power, high-efficiency applications. This preparation method can not only simplify the manufacturing process and reduce costs, but also effectively improve the performance and reliability of GaN-based p-channel devices, giving it a broader application prospect in GaN monolithic integration.

[0049] The specific structure and preparation method of the gallium nitride-based p-channel device provided in the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0050] Figure 1 A process flow chart of a method for preparing a gallium nitride-based p-channel device provided in an embodiment of the present application, Figures 2 to 9 The schematic diagram of the process of preparing a GaN-based p-channel device. Figures 1 to 9 The method for preparing a gallium nitride-based p-channel device provided in the embodiment of the present application comprises the following steps:

[0051] S10, see Figure 2 , providing an epitaxial structure 10 with a p-type GaN layer 105 as the outermost layer.

[0052] It should be noted that the specific layer structure of the epitaxial structure 10 is not limited in the present application, as long as the outermost layer is a p-type GaN layer 105. The manufacturing process of the epitaxial structure 10 can refer to the prior art, and will not be introduced here. Preferably, the epitaxial structure 10 includes a double heterojunction structure with a double channel layer.

[0053] In some embodiments, the epitaxial structure 10 includes a substrate 101, a buffer layer 102, an n-type GaN layer 103, an AlGaN layer 104, and a p-type GaN layer 105 stacked in sequence. A two-dimensional electron gas (2DEG) is formed on the side of the n-type GaN layer 103 close to the AlGaN layer 104, and a two-dimensional hole gas (2DHG) is formed on the side of the p-type GaN layer 105 close to the AlGaN layer 104.

[0054] The substrate 101 is a commonly used substrate material for gallium nitride-based devices, and can be a Si substrate, a sapphire substrate, a diamond substrate, a GaN substrate, a SiC substrate, or an SOI substrate. In the embodiment of the present application, the substrate 101 is a Si substrate. The thickness of the substrate 101 can be 500 μm to 5000 μm, for example, 500 μm, 1000 μm, 2000 μm, 5000 μm, etc.

[0055] The buffer layer 102 is used to mitigate the lattice mismatch phenomenon of the GaN material growing on the substrate 101. The buffer layer 102 can be an AlN layer, an AlGaN layer with a gradient Al component, a GaN layer doped with C or Fe, etc. The thickness of the buffer layer 102 can be 1 μm to 20 μm, for example, 1 μm, 5 μm, 10 μm, 20 μm, etc.

[0056] The n-type GaN layer 103, the AlGaN layer 104 and the p-type GaN layer 105 form a double heterojunction structure with a double channel layer. The thickness of the three layers can be adjusted as needed, and the total thickness can be 50nm to 500nm. It can be understood that any structure based on the three-layer structure n-GaN / AlGaN / p-GaN that can be used to enhance 2DEG and 2DHG, such as n-GaN / AlGaN / AlN / p-GaN, n-GaN / AlN / AlGaN / p-GaN, n-GaN / AlN / AlGaN / AlN / p-GaN, etc., should be counted in the three-layer structure.

[0057] In some embodiments, the process further includes: performing surface cleaning on the epitaxial structure 10 to clean surface contamination, oxides, organic matter, etc. For example, an acidic solution (such as diluted hydrofluoric acid, nitric acid, citric acid, etc.) may be used to remove surface oxides, and an organic solvent (such as acetone, isopropyl alcohol, etc.) may be used to remove surface organic matter.

[0058] See also Figure 3, after cleaning the epitaxial structure 10, it also includes isolating the epitaxial layer of the epitaxial structure 10 for mesa. Mesa isolation refers to isolating the area for forming transistor devices on the surface of the epitaxial layer of the epitaxial structure 10 to separate different transistor devices on the epitaxial structure 10. It can be understood that the mesa isolation is used to remove the barrier layer (AlGaN layer 104) that connects each independent device so that the devices do not interfere with each other. Exemplarily, part of the p-type GaN layer 105, the AlGaN layer 104 and the n-type GaN layer 103 are removed to form a mesa isolation. Among them, the mesa isolation can use the inductively coupled plasma (ICP) dry etching isolation method, and the ion source used in the etching process can be BCl 3 and Cl 2 .

[0059] S20, see Figure 5 , a Mg-doped SOG solution is coated on the surface of the p-type GaN layer 105 to obtain an intermediate 100 .

[0060] SOG refers to spin-on-glass, and SOG solution is a liquid compound based on silicate or siloxane. The method of coating the Mg-doped SOG solution can be spin coating. Specifically, a layer of spin-on-glass SOG can be formed on the surface of the p-type GaN layer 105 by a spin coating machine to form a SOG coating 30.

[0061] In some embodiments, the Mg doping concentration in the SOG solution is greater than 1e 19 cm -3 , for example 1e 20 cm -3 , 1e 21 cm -3 wait.

[0062] S30, see Figure 5 , Figure 6 and Figure 7 The intermediate body 100 is annealed to form a doped region A doped with Mg and a non-doped region B other than the doped region on the surface of the p-type GaN layer 105 .

[0063] In some embodiments, the annealing temperature is 700° C. to 900° C., and the annealing time is 20 min to 200 min. For example, the annealing temperature is 700° C., 800° C., 900° C., etc., and the annealing time is 20 min, 50 min, 100 min, 150 min, 200 min, etc.

[0064] In some embodiments, step S20 further includes: Figure 4A mask 20 is disposed on the surface of the p-type GaN layer 105. The mask 20 includes a first mask 201 and a second mask 202 that are spaced apart. The first mask 201 and the second mask 202 divide the p-type GaN layer 105 into three independent regions. The SOG coating 30 is partially located on the surface of the p-type GaN layer 105 and partially located on the surface of the mask 20. In step S30, after annealing, Mg in the part of the SOG coating 30 located on the surface of the p-type GaN layer 105 is doped into the p-type GaN layer 105 to form a doping region A. The doping region A includes a first doping region 401, a second doping region 402, and a third doping region 403 that are spaced apart.

[0065] The material of the mask 20 can be SiN, SiO 2 The thickness of the mask 20 may be 200 nm to 500 nm, for example, 200 nm, 300 nm, 400 nm, 500 nm, etc.

[0066] It is understandable that after the annealing treatment, step S30 further includes: removing the first mask 201 and the second mask 202. Exemplarily, the first mask 201, the second mask 202 and the residual SOG solution are removed by washing with a buffered oxide etchant (BOE).

[0067] S40, see Figure 8 , a source 501 , a drain 502 and an ohmic gate 5031 are formed on at least a portion of the surface corresponding to the doped region A and are spaced apart from each other.

[0068] Specifically, a source 501 is formed on a surface corresponding to the first doping region 401 , a drain 502 is formed on a surface corresponding to the second doping region 402 , and an ohmic gate 5031 is formed on a surface corresponding to the third doping region 403 .

[0069] The source 501, the drain 502 and the ohmic gate 5031 may be formed by patterned lithography, sputtering and annealing combined with a LOR double-layer glue metal stripping process. For details, reference may be made to the prior art and will not be described in detail here.

[0070] In some embodiments, the source 501, the drain 502 and the ohmic gate 5031 may be made of a variety of high work function metals such as Ni, Au, Mg, Pt, Pd, Ti, Al, NiO, CuO, high hole concentration oxides, and stacked combinations of other metals. The thickness may be independently 10 nm to 500 nm, such as 10 nm, 50 nm, 100 nm, 200 nm, 500 nm, etc.

[0071] S50, see Fig. 9A Schottky gate 5032 is formed on a portion of the surface corresponding to the non-doped region B. The Schottky gate 5032 and the ohmic gate 5031 contact each other to form a hybrid gate 503 , and the hybrid gate 503 is disposed between the source 501 and the drain 502 .

[0072] The Schottky gate 5032 covers at least a portion of the ohmic gate 5031 .

[0073] In some embodiments, the Schottky gate 5032 may be formed by patterning photolithography or sputtering. The Schottky gate 5032 may be made of metals such as Ni, Au, Pt, Pd, Ti, Al, or a stacked combination of these metals.

[0074] It is understandable that after step S50, a passivation layer may be deposited, and low pressure chemical vapor deposition (LPCVD) SiN, atomic layer deposition (ALD) Al 2 O 3 and AlN, plasma enhanced chemical vapor deposition (PECVD) SiN, SiO 2 Etc.; then, interconnect metal through hole etching and interconnect metal evaporation can be performed.

[0075] See also Fig. 9 The present application also provides a gallium nitride-based p-channel device prepared by the above-mentioned preparation method, comprising a source 501, a drain 502, an ohmic gate 5031, a Schottky gate 5032, and an epitaxial structure 10 with a p-type GaN layer 105 as the outermost layer. The surface of the p-type GaN layer 105 has a doped region A doped with Mg and a non-doped region B except the doped region A. The source 501, the drain 502, and the ohmic gate 5031 are formed on a portion of the surface of the p-type GaN layer 105 at intervals corresponding to the doped region A. The Schottky gate 5032 is formed on a portion of the surface of the p-type GaN layer 105 corresponding to the non-doped region B. The ohmic gate 5031 and the Schottky gate 5032 are in contact with each other to form a hybrid gate 503, and the hybrid gate 503 is arranged between the source 501 and the drain 503.

[0076] The epitaxial structure 10 includes a substrate 101, a buffer layer 102, an n-type GaN layer 103, an AlGaN layer 104, and a p-type GaN layer 105 which are stacked in sequence. A 2DEG is formed on the side of the n-type GaN layer 103 close to the AlGaN layer 104, and a 2DHG is formed on the side of the p-type GaN layer 105 close to the AlGaN layer 104.

[0077] In some embodiments, the doping region A includes a first doping region 401, a second doping region 402, and a third doping region 403 that are spaced apart from each other, and the doping concentration of Mg in the doping region A is greater than 1e 19 cm-3 The source electrode 501 corresponds to the surface corresponding to the first doping region 401 , the drain electrode 502 corresponds to the surface corresponding to the second doping region 402 , and the ohmic gate electrode 5031 corresponds to the surface corresponding to the third doping region 403 .

[0078] In some embodiments, the Schottky gate 5032 covers at least a portion of the ohmic gate 5031 .

[0079] In some embodiments, see Fig. 9 , the ohmic gate 5031 is arranged on a side close to the drain 502 .

[0080] In some embodiments, see Fig.10 , the ohmic gate 5031 is arranged on a side close to the source 501 .

[0081] In some embodiments, see Fig.11 , multiple ohmic gates 5031 and Schottky gates 5032 are alternately arranged. The number of the ohmic gates 5031 and the Schottky gates 5032 can be the same or different, and the number of the ohmic gates 5031 and the Schottky gates 5032 can be 1 to 10 independently, the height can be 10 nm to 500 nm independently, and the width can be 2 nm to 20 nm independently.

[0082] The position of the ohmic gate 5031 affects the hole injection channel. When the ohmic gate 5031 is disposed on the side close to the drain 502 (see Fig. 9 ), the gate leakage current of the device can be reduced; when the ohmic gate 5031 is arranged on the side close to the source 501 (see Fig.10 ), the output current of the device can be increased; and when the ohmic gate 5031 and the Schottky gate 5032 are alternately arranged (see Fig.10 ), which can disperse the gate electric field and improve the gate voltage resistance level.

[0083] The embodiments described above are part of the embodiments of the present application, rather than all of the embodiments. The detailed description of the embodiments of the present application is not intended to limit the scope of the present application for protection, but merely represents the selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

Claims

1. A method for preparing a gallium nitride-based p-channel device, characterized in that: The following steps are involved: Providing an epitaxial structure with a p-type GaN layer as the outermost layer; Coating a Mg-doped SOG solution on the surface of the p-type GaN layer to obtain an intermediate; Annealing the intermediate to form a doped region doped with Mg and a non-doped region other than the doped region on the surface of the p-type GaN layer; Forming a source electrode, a drain electrode and an ohmic gate electrode spaced apart from each other on at least a portion of the surface corresponding to the doped region; A Schottky gate is formed on a portion of the surface corresponding to the non-doped region, the Schottky gate and the ohmic gate are in contact with each other to form a hybrid gate, and the hybrid gate is arranged between the source and the drain.

2. The preparation method according to claim 1, characterized in that: The Mg doping concentration in the SOG solution is greater than 1e 19 cm -3 .

3. The preparation method according to claim 1 or 2, characterized in that: The annealing treatment temperature is 700° C. to 900° C., and the annealing time is 20 min to 200 min.

4. The preparation method according to claim 1, characterized in that: Also includes: Disposing a first mask and a second mask spaced apart on the surface of the p-type GaN layer so that the doping region includes a first doping region, a second doping region and a third doping region spaced apart; forming the source electrode, the drain electrode and the ohmic gate electrode on surfaces corresponding to the first doping region, the second doping region and the third doping region respectively; The first mask and the second mask are removed.

5. The preparation method according to claim 1, characterized in that: The epitaxial structure comprises a substrate, a buffer layer, an n-type GaN layer, an AlGaN layer and the p-type GaN layer stacked in sequence; The preparation method also includes: Cleaning the surface of the epitaxial structure; Parts of the p-type GaN layer, the AlGaN layer and the n-type GaN layer are removed to form mesa isolation.

6. A gallium nitride-based p-channel device, characterized in that: The invention relates to an epitaxial structure comprising a source electrode, a drain electrode, an ohmic gate electrode, a Schottky gate electrode and a p-type GaN layer as the outermost layer, wherein the surface of the p-type GaN layer has a doped region doped with Mg and a non-doped region other than the doped region, the source electrode, the drain electrode and the ohmic gate electrode are formed on a portion of the surface of the p-type GaN layer at intervals corresponding to the doped region, the Schottky gate electrode is formed on a portion of the surface of the p-type GaN layer corresponding to the non-doped region, the ohmic gate electrode and the Schottky gate electrode are in contact with each other to form a hybrid gate electrode, and the hybrid gate electrode is arranged between the source electrode and the drain electrode.

7. The gallium nitride-based p-channel device according to claim 6, characterized in that: The doping concentration of Mg in the doping region is greater than 1e 19 cm -3 .

8. The gallium nitride-based p-channel device according to claim 6, characterized in that: The ohmic gate is arranged on a side close to the drain; Or, the ohmic gate is arranged on a side close to the source; Alternatively, a plurality of the ohmic gates and the Schottky gates are alternately arranged.

9. The gallium nitride-based p-channel device according to claim 6 or 8, characterized in that: The number of the ohmic gate and the Schottky gate is independently 1 to 10, the height is independently 10 nm to 500 nm, and the width is independently 2 nm to 20 nm.

10. The gallium nitride-based p-channel device according to claim 6, characterized in that: The epitaxial structure includes a substrate, a buffer layer, an n-type GaN layer, an AlGaN layer and the p-type GaN layer which are stacked in sequence.

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