Transistor and preparation method thereof
By inserting a two-dimensional material layer between the barrier layer and the P-GaN layer, the current leakage problem caused by hole diffusion of the P-GaN layer is solved, and the reliability and stability of the transistor are improved.
Patent Information
- Application Number
- CN202411933880.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-26
- Publication Date
- 2025-05-13
AI Technical Summary
In the prior art, holes in the P-GaN layer have a risk of diffusing toward the channel layer side, resulting in current leakage and reducing the reliability of the transistor.
A two-dimensional material layer is inserted between the barrier layer and the P-GaN layer, and the two-dimensional material acts as the spreading area. The transformation of the interface reduces the stacking dislocation density and reduces the diffusion of holes and Mg ions.
It effectively reduces the diffusion of holes and Mg ions in the P-GaN layer to the channel layer side, reduces leakage, and improves the reliability and stability of the transistor.
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Figure CN119997544A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a transistor and a method for preparing the same. Background Art
[0002] GaN-on-Si is widely used in semiconductors, such as transistors.
[0003] The related art provides a transistor structure, including a channel layer, a barrier layer, a P-GaN layer, a first electrode, a second electrode and a control electrode. The channel layer, the barrier layer and the P-GaN layer are stacked in sequence, the first electrode and the second electrode are connected to the barrier layer, and the control electrode is located on the P-GaN layer.
[0004] In the related art, there is a risk that holes in the P-GaN layer diffuse toward the channel layer side, resulting in current leakage and reducing the reliability of the transistor. Summary of the invention
[0005] The disclosed embodiment provides a transistor and a method for manufacturing the same, which can significantly improve the current leakage phenomenon and enhance the reliability. The technical solution is as follows:
[0006] In one aspect, a transistor is provided, the transistor comprising: a channel layer, a barrier layer, a two-dimensional material layer, a P-GaN layer, a first electrode, a second electrode and a control electrode;
[0007] The channel layer, the barrier layer and the two-dimensional material layer are stacked in sequence, the P-GaN layer is located on the two-dimensional material layer, the first electrode and the second electrode are connected to the barrier layer through the two-dimensional material layer, and the control electrode is located on the P-GaN layer.
[0008] Optionally, the material band gap of the two-dimensional material layer is greater than 3 eV.
[0009] Optionally, the two-dimensional material layer is a MoS2 layer or a BN layer.
[0010] Optionally, the thickness of the two-dimensional material layer is 10 to 30 nm.
[0011] In another aspect, a method for manufacturing a transistor includes:
[0012] manufacturing a channel layer;
[0013] forming a barrier layer on the channel layer;
[0014] fabricating a two-dimensional material layer on the barrier layer;
[0015] Fabricating a P-GaN layer on the two-dimensional material layer;
[0016] Manufacturing a first electrode and a second electrode, wherein the first electrode and the second electrode are connected to the barrier layer through the two-dimensional material layer;
[0017] A control electrode is manufactured, wherein the control electrode is located on the P-GaN layer.
[0018] Optionally, the material band gap of the two-dimensional material layer is greater than 3 eV.
[0019] Optionally, the manufacturing of a two-dimensional material layer on the barrier layer comprises:
[0020] performing surface treatment on the barrier layer;
[0021] After surface treatment, a two-dimensional material layer is fabricated on the barrier layer.
[0022] Optionally, when the two-dimensional material layer is a MoS2 layer, the barrier layer is subjected to surface treatment, comprising:
[0023] The barrier layer is surface treated by S ions in a vacuum environment for 3 to 7 minutes.
[0024] Optionally, when the two-dimensional material layer is a BN layer, surface treatment is performed on the barrier layer, comprising:
[0025] The barrier layer is surface treated by N ions in a vacuum environment for 3 to 7 minutes.
[0026] Optionally, the thickness of the two-dimensional material layer is 10 to 30 nm.
[0027] The technical solution provided by the embodiments of the present disclosure has the following beneficial effects:
[0028] In the disclosed embodiment, a two-dimensional material layer is inserted between the barrier layer and the P-GaN layer. The two-dimensional material serves as a spreading area. The transformation of the interface reduces the stacking dislocation density, greatly reduces the diffusion of holes in the P-GaN layer to the channel layer side, and reduces leakage. In addition, the two-dimensional material can also reduce the diffusion of Mg doped in the P-GaN layer to the channel layer side, improve the reliability of the gate, reduce the risk of gate drift, and enable the transistor to maintain stability and reliability under long-term high-power working conditions. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0030] Figure 1is a schematic structural diagram of a transistor provided by an embodiment of the present disclosure;
[0031] Figure 2 is a flow chart of a transistor manufacturing method provided by an embodiment of the present disclosure;
[0032] Figure 3 is a flow chart of another transistor manufacturing method provided by an embodiment of the present disclosure;
[0033] Figure 4 It is a schematic diagram between the two-dimensional material layer and the P-GaN layer provided in an embodiment of the present disclosure.
[0034] The reference numerals are as follows:
[0035] 100: substrate; 101: first buffer layer; 102: second buffer layer; 103: channel layer; 104: barrier layer; 105: two-dimensional material layer; 106: P-GaN layer; 107: first electrode; 108: second electrode; 109: control electrode; 110: passivation layer;
[0036] 201: Mg ion. DETAILED DESCRIPTION
[0037] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.
[0038] Figure 1 is a schematic diagram of the structure of a transistor provided by an embodiment of the present disclosure. Figure 1 The transistor includes: a channel layer 103 , a barrier layer 104 , a two-dimensional material layer 105 , a P-GaN layer 106 , a first electrode 107 , a second electrode 108 and a control electrode 109 .
[0039] Among them, the channel layer 103, the barrier layer 104 and the two-dimensional material layer 105 are stacked in sequence, the P-GaN layer 106 is located on the two-dimensional material layer 105, the first electrode 107 and the second electrode 108 pass through the two-dimensional material layer 105 to connect with the barrier layer 104, and the control electrode 109 is located on the P-GaN layer 106.
[0040] In the disclosed embodiment, a two-dimensional material layer is inserted between the barrier layer and the P-GaN layer. The two-dimensional material serves as a spreading area. The transformation of the interface reduces the stacking dislocation density, greatly reduces the diffusion of holes in the P-GaN layer to the channel layer side, and reduces leakage. In addition, the two-dimensional material can also reduce the diffusion of Mg doped in the P-GaN layer to the channel layer side, improve the reliability of the gate, reduce the risk of gate drift, and enable the transistor to maintain stability and reliability under long-term high-power working conditions.
[0041] In the embodiment of the present disclosure, the material band gap of the two-dimensional material layer 105 is greater than 3 eV.
[0042] In this implementation, selecting a two-dimensional material layer with a band gap greater than 3eV can effectively prevent holes in the P-GaN layer from diffusing to the channel layer side, and can also effectively prevent Mg ions in the P-GaN layer from diffusing to the channel layer side, thereby improving the stability of the device.
[0043] In the embodiment of the present disclosure, the two-dimensional material layer 105 may be a MoS2 layer or a BN layer.
[0044] In this implementation, MoS2 and BN are selected as the two-dimensional material layers because, on the one hand, both materials can form a two-dimensional structure, and on the other hand, the material band gap meets the requirement of being greater than 3eV.
[0045] In the embodiment of the present disclosure, the thickness of the two-dimensional material layer 105 may be 10 to 30 nm.
[0046] In this implementation, a two-dimensional material layer of the above thickness is selected to be inserted between the barrier layer and the P-GaN layer, which can satisfy the aforementioned anti-diffusion function and will not cause the overall size of the transistor to be too large due to the layer being too thick.
[0047] Exemplarily, the thickness of the two-dimensional material layer 105 is 20 nm.
[0048] In the embodiment of the present disclosure, the transistor may also include a substrate 100, a first buffer layer 101, a second buffer layer 102 and a passivation layer 110, the first buffer layer 101, the second buffer layer 102, the channel layer 103, the barrier layer 104 and the two-dimensional material layer 105 are stacked in sequence on the substrate 100, and the passivation layer 110 covers the P-GaN layer 106.
[0049] Among them, the substrate can provide a platform for the growth of transistors, and the passivation layer can protect the transistors and improve the stability of the transistors.
[0050] In the embodiment of the present disclosure, the substrate 100 may be a single crystal substrate or a composite substrate, and may have a size of 2 to 8 inches.
[0051] Exemplarily, the substrate 100 is a single crystal substrate with a size of 5 inches.
[0052] Of course, in other embodiments, the transistor may not have a substrate, and the present disclosure is not limited to this.
[0053] In the embodiment of the present disclosure, the first buffer layer 101 may be an AlN buffer layer, and the thickness of the first buffer layer 101 may be 100-300 nm.
[0054] Exemplarily, the thickness of the first buffer layer 101 is 200 nm.
[0055] In the embodiment of the present disclosure, the second buffer layer 102 may be an AlGaN buffer layer, and the thickness of the second buffer layer 102 may be 1000-3000 nm.
[0056] Exemplarily, the thickness of the second buffer layer 102 is 2000 nm.
[0057] In the embodiment of the present disclosure, the molar amount of Al in the second buffer layer 102 gradually decreases along the direction from the first buffer layer 101 to the channel layer 103 .
[0058] Exemplarily, along the direction from the first buffer layer 101 to the channel layer 103 , the molar amount of Al in the second buffer layer 102 decreases from 1.0 to 0.2.
[0059] In the embodiment of the present disclosure, the channel layer 103 may be a GaN channel layer, and the thickness of the channel layer 103 may be 100-500 nm.
[0060] Exemplarily, the thickness of the channel layer 103 is 300 nm.
[0061] In the embodiment of the present disclosure, the barrier layer 104 may be an AlGaN barrier layer, and the thickness of the barrier layer 104 may be 20-30 nm.
[0062] Exemplarily, the thickness of the barrier layer 104 is 25 nm.
[0063] In the embodiment of the present disclosure, the molar amount of Al in the barrier layer 104 is 0.2-0.3.
[0064] Exemplarily, the molar amount of Al in the barrier layer 104 is 0.25.
[0065] In the embodiment of the present disclosure, the thickness of the P-GaN layer 106 may be 50-90 nm.
[0066] Exemplarily, the thickness of the P-GaN layer 106 is 70 nm.
[0067] In the embodiment of the present disclosure, one of the first electrode 107 and the second electrode 108 is a source electrode, and the other is a drain electrode; the control electrode 109 is a gate electrode.
[0068] In the embodiment of the present disclosure, the passivation layer 110 may be a silicon oxide, silicon nitride, gallium nitride or aluminum nitride layer.
[0069] By way of example, the passivation layer 110 may be a silicon oxide layer.
[0070] Figure 2 is a flow chart of a transistor manufacturing method provided by an embodiment of the present disclosure. Figure 2 The method steps include:
[0071] S11 . Manufacturing a channel layer.
[0072] In the embodiment of the present disclosure, the growth temperature of the channel layer may be 900-1100°C.
[0073] Exemplarily, the growth temperature of the channel layer is 1000°C.
[0074] In the embodiment of the present disclosure, the channel layer may be a GaN channel layer, and the thickness of the channel layer may be 100 to 500 nm.
[0075] Exemplarily, the thickness of the channel layer is 300 nm.
[0076] S12. Fabricating a barrier layer on the channel layer.
[0077] In the embodiment of the present disclosure, the barrier layer may be an AlGaN barrier layer, and the thickness of the barrier layer may be 20-30 nm.
[0078] Exemplarily, the thickness of the barrier layer is 25 nm.
[0079] In the embodiment of the present disclosure, the molar amount of Al in the barrier layer is 0.2-0.3.
[0080] Exemplarily, the molar amount of Al in the barrier layer is 0.25.
[0081] S13. Fabricate a two-dimensional material layer on the barrier layer.
[0082] In the embodiment of the present disclosure, the material band gap of the two-dimensional material layer is greater than 3 eV.
[0083] In this implementation, selecting a two-dimensional material layer with a band gap greater than 3eV can effectively prevent holes in the P-GaN layer from diffusing to the channel layer side, and can also effectively prevent Mg ions in the P-GaN layer from diffusing to the channel layer side, thereby improving the stability of the device.
[0084] In the embodiment of the present disclosure, the two-dimensional material layer may be a MoS2 layer or a BN layer.
[0085] In this implementation, MoS2 and BN are selected as the two-dimensional material layers because, on the one hand, both materials can form a two-dimensional structure, and on the other hand, the material band gap meets the requirement of being greater than 3eV.
[0086] In the embodiment of the present disclosure, the thickness of the two-dimensional material layer may be 10 to 30 nm.
[0087] In this implementation, a two-dimensional material layer of the above thickness is selected to be inserted between the barrier layer and the P-GaN layer, which can satisfy the aforementioned anti-diffusion function and will not cause the overall size of the transistor to be too large due to the layer being too thick.
[0088] Exemplarily, the thickness of the two-dimensional material layer is 20 nm.
[0089] In the embodiment of the present disclosure, through holes are provided on the two-dimensional material layer.
[0090] S14. Fabricate a P-GaN layer on the two-dimensional material layer.
[0091] In one example, step S14 includes:
[0092] The first step is to make P-GaN thin film.
[0093] In the embodiment of the present disclosure, the thickness of the P-GaN film may be 50 to 90 nm.
[0094] Exemplarily, the thickness of the P-GaN film is 70 nm.
[0095] In the second step, the P-GaN film is patterned to obtain a P-GaN layer.
[0096] In the embodiment of the present disclosure, patterning the P-GaN film may include: forming a patterned mask layer on the surface of the P-GaN film; and etching the P-GaN film under the protection of the mask layer to form a P-GaN layer.
[0097] S15, manufacturing a first electrode and a second electrode, wherein the first electrode and the second electrode pass through the two-dimensional material layer and are connected to the barrier layer.
[0098] In the embodiment of the present disclosure, the first electrode and the second electrode are respectively connected to the barrier layer through through holes on the two-dimensional material layer. The through holes are located on both sides of the P-GaN layer.
[0099] In the embodiment of the present disclosure, the first electrode and the second electrode may include a first Ti sublayer, an Al sublayer, a second Ti sublayer, and a TiN sublayer (anti-oxidation sublayer) stacked in sequence.
[0100] In the embodiment of the present disclosure, one of the first electrode and the second electrode is a source electrode, and the other is a drain electrode.
[0101] S16, making a control electrode, wherein the control electrode is located on the P-GaN layer.
[0102] In the embodiment of the present disclosure, the control electrode is a gate.
[0103] In the disclosed embodiment, a two-dimensional material layer is inserted between the barrier layer and the P-GaN layer. The two-dimensional material serves as a spreading area. The transformation of the interface reduces the stacking dislocation density, greatly reduces the diffusion of holes in the P-GaN layer to the channel layer side, and reduces leakage. In addition, the two-dimensional material can also reduce the diffusion of Mg doped in the P-GaN layer to the channel layer side, improve the reliability of the gate, reduce the risk of gate drift, and enable the transistor to maintain stability and reliability under long-term high-power working conditions.
[0104] Figure 3 is a flow chart of another transistor manufacturing method provided by an embodiment of the present disclosure. Figure 3 The method steps include:
[0105] S21. Provide a substrate and process the substrate.
[0106] In the embodiment of the present disclosure, the substrate may be a single crystal substrate or a composite substrate, and the size may be 2 to 8 inches.
[0107] Exemplarily, the substrate is a single crystal substrate with a size of 5 inches.
[0108] In the disclosed embodiment, under pure H2 atmosphere, the temperature is controlled at 1000-1100°C and the cleaning time is 5-10 minutes.
[0109] Exemplarily, under pure H2 atmosphere conditions, the temperature is controlled at 1050°C and the cleaning time is 8 minutes.
[0110] S22, forming a first buffer layer on the substrate.
[0111] In the embodiment of the present disclosure, step S22 may include:
[0112] The first buffer layer is formed by physical vapor deposition (PVD), metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), atomic layer deposition (ALD) or pulsed laser deposition (PLD).
[0113] Exemplarily, the first buffer layer is manufactured by MOCVD.
[0114] In the embodiment of the present disclosure, the growth temperature of the first buffer layer may be 700-900°C.
[0115] Exemplarily, the growth temperature of the first buffer layer may be 800°C.
[0116] In the embodiment of the present disclosure, the first buffer layer may be an AlN buffer layer, and the thickness of the first buffer layer may be 100-300 nm.
[0117] Exemplarily, the thickness of the first buffer layer is 200 nm.
[0118] S23, manufacturing a second buffer layer on the first buffer layer.
[0119] In the embodiment of the present disclosure, the growth temperature of the second buffer layer may be 1150-1300°C.
[0120] Exemplarily, the growth temperature of the second buffer layer is 1250°C.
[0121] In the embodiment of the present disclosure, the second buffer layer may be an AlGaN buffer layer, and the thickness of the second buffer layer may be 1000-3000 nm.
[0122] Exemplarily, the thickness of the second buffer layer is 2000 nm.
[0123] In the embodiment of the present disclosure, the molar amount of Al in the second buffer layer gradually decreases along the direction from the first buffer layer to the channel layer.
[0124] Illustratively, along the direction from the first buffer layer to the channel layer, the molar amount of Al in the second buffer layer decreases from 1.0 to 0.2.
[0125] S24, forming a channel layer on the second buffer layer.
[0126] In the embodiment of the present disclosure, the growth temperature of the channel layer may be 900-1100°C.
[0127] Exemplarily, the growth temperature of the channel layer is 1000°C.
[0128] In the embodiment of the present disclosure, the channel layer may be a GaN channel layer, and the thickness of the channel layer may be 100 to 500 nm.
[0129] Exemplarily, the thickness of the channel layer is 300 nm.
[0130] S25. Fabricate a barrier layer on the channel layer.
[0131] In the embodiment of the present disclosure, the barrier layer may be an AlGaN barrier layer, and the thickness of the barrier layer may be 20-30 nm.
[0132] Exemplarily, the thickness of the barrier layer is 25 nm.
[0133] In the embodiment of the present disclosure, the molar amount of Al in the barrier layer is 0.2-0.3.
[0134] Exemplarily, the molar amount of Al in the barrier layer is 0.25.
[0135] S26. Processing the surface of the barrier layer.
[0136] In the embodiment of the present disclosure, when the two-dimensional material layer is a MoS2 layer, the barrier layer is surface treated, including:
[0137] The barrier layer is surface treated with S ions.
[0138] In the embodiment of the present disclosure, when the two-dimensional material layer is a MoS2 layer, the barrier layer is surface treated with S ions for 3 to 7 minutes in a vacuum environment, and plasma is used to adjust the surface dangling bonds to prepare for the subsequent growth of the MoS2 two-dimensional material.
[0139] Exemplarily, when the two-dimensional material layer is a MoS2 layer, the barrier layer is surface treated with S ions in a vacuum environment for 5 minutes.
[0140] In the embodiment of the present disclosure, when the two-dimensional material layer is a BN layer, the barrier layer is subjected to surface treatment, including:
[0141] The barrier layer is surface treated by N ions.
[0142] In the embodiment of the present disclosure, when the two-dimensional material layer is a BN layer, the barrier layer is surface treated with N ions in a vacuum environment for 3 to 7 minutes, and plasma is used to adjust the surface dangling bonds to prepare for the subsequent growth of MoS2 two-dimensional material.
[0143] Exemplarily, when the two-dimensional material layer is a BN layer, the barrier layer is surface treated by N ions in a vacuum environment for 5 minutes.
[0144] S27. Fabricating a two-dimensional material layer on the surface of the barrier layer after the treatment.
[0145] In the disclosed embodiment, the growth temperature of the two-dimensional material is 900-1000°C.
[0146] Exemplarily, the growth temperature of the two-dimensional material is 950°C.
[0147] In the embodiment of the present disclosure, the material band gap of the two-dimensional material layer is greater than 3 eV.
[0148] In this implementation, selecting a two-dimensional material layer with a band gap greater than 3eV can effectively prevent holes in the P-GaN layer from diffusing to the channel layer side, and can also effectively prevent Mg ions in the P-GaN layer from diffusing to the channel layer side, thereby improving the stability of the device.
[0149] In the embodiment of the present disclosure, the two-dimensional material layer may be a MoS2 layer or a BN layer.
[0150] In this implementation, MoS2 and BN are selected as the two-dimensional material layers because, on the one hand, both materials can form a two-dimensional structure, and on the other hand, the material band gap meets the requirement of being greater than 3eV.
[0151] In the embodiment of the present disclosure, the thickness of the two-dimensional material layer may be 10 to 30 nm.
[0152] In this implementation, a two-dimensional material layer of the above thickness is selected to be inserted between the barrier layer and the P-GaN layer, which can satisfy the aforementioned anti-diffusion function and will not cause the overall size of the transistor to be too large due to the layer being too thick.
[0153] Exemplarily, the thickness of the two-dimensional material layer is 20 nm.
[0154] Figure 4 Schematic diagram of the two-dimensional material layer and the P-GaN layer provided by the embodiment of the present disclosure. Figure 4 The transistor provided in the embodiment of the present disclosure uses the two-dimensional material 105 as the spreading area. The transformation of the interface reduces the stacking dislocation density and the leakage current. At the same time, it blocks the downward injection of holes in space and prevents the diffusion of Mg ions 201. The reliability is guaranteed and the power conversion efficiency is also improved.
[0155] S28. Fabricate a P-GaN layer on the two-dimensional material layer.
[0156] In one example, step S28 includes:
[0157] The first step is to make P-GaN thin film.
[0158] In the embodiment of the present disclosure, the thickness of the P-GaN film may be 50 to 90 nm.
[0159] Exemplarily, the thickness of the P-GaN film is 70 nm.
[0160] In the second step, the P-GaN film is patterned to obtain a P-GaN layer.
[0161] In the embodiment of the present disclosure, patterning the P-GaN film may include: forming a patterned mask layer on the surface of the P-GaN film; and etching both ends of the P-GaN film under the protection of the mask layer to form a P-GaN layer.
[0162] S29. Fabricate a passivation layer on the P-GaN layer.
[0163] In the embodiment of the present disclosure, the passivation layer may be a silicon oxide, silicon nitride, gallium nitride or aluminum nitride passivation layer.
[0164] Exemplarily, the passivation layer may be a silicon oxide passivation layer.
[0165] S30, etching the passivation layer and the two-dimensional material layer to form a through hole.
[0166] In the embodiment of the present disclosure, a patterned mask layer is formed on the surface of the passivation layer; under the protection of the mask layer, a first through hole and a second through hole are made, the first through hole penetrates the passivation layer and the two-dimensional material layer, and the second through hole penetrates the passivation layer.
[0167] S31, manufacturing a first electrode and a second electrode.
[0168] In the embodiment of the present disclosure, the first electrode and the second electrode are connected to the barrier layer through the first through hole.
[0169] In the embodiment of the present disclosure, one of the first electrode and the second electrode is a source electrode, and the other of the first electrode and the second electrode is a drain electrode.
[0170] S32. Make a control electrode.
[0171] The control electrode is connected to the P-GaN layer through the second through hole.
[0172] In the embodiment of the present disclosure, the control electrode is a gate.
[0173] After fabrication, the transistors are tested for resistance, capacitance, current, and voltage.
[0174] The transistor structure provided by the embodiments of the present disclosure has a better breakdown voltage than the related art, a reduced gate leakage current is beneficial to device performance, and a better dynamic resistance performance.
[0175] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.
Claims
1. A transistor, characterized in that: The transistor comprises: a channel layer (103), a barrier layer (104), a two-dimensional material layer (105), a P-GaN layer (106), a first electrode (107), a second electrode (108) and a control electrode (109); The channel layer (103), the barrier layer (104) and the two-dimensional material layer (105) are stacked in sequence, the P-GaN layer (106) is located on the two-dimensional material layer (105), the first electrode (107) and the second electrode (108) pass through the two-dimensional material layer (105) to be connected to the barrier layer (104), and the control electrode (109) is located on the P-GaN layer (106).
2. The transistor according to claim 1, characterized in that The material band gap of the two-dimensional material layer (105) is greater than 3 eV.
3. The transistor according to claim 2, characterized in that The two-dimensional material layer (105) is a MoS2 layer or a BN layer.
4. The transistor according to any one of claims 1 to 3, characterized in that: The thickness of the two-dimensional material layer (105) is 10 to 30 nm.
5. A method for preparing a transistor, characterized in that: The transistor preparation method comprises: manufacturing a channel layer; forming a barrier layer on the channel layer; fabricating a two-dimensional material layer on the barrier layer; Fabricating a P-GaN layer on the two-dimensional material layer; Manufacturing a first electrode and a second electrode, wherein the first electrode and the second electrode are connected to the barrier layer through the two-dimensional material layer; A control electrode is manufactured, wherein the control electrode is located on the P-GaN layer.
6. The transistor manufacturing method according to claim 5, characterized in that: The material band gap of the two-dimensional material layer is greater than 3 eV.
7. The transistor manufacturing method according to claim 5, characterized in that: The step of fabricating a two-dimensional material layer on the barrier layer comprises: performing surface treatment on the barrier layer; After surface treatment, a two-dimensional material layer is fabricated on the barrier layer.
8. The transistor manufacturing method according to claim 6, characterized in that: When the two-dimensional material layer is a MoS2 layer, the barrier layer is subjected to surface treatment, comprising: The barrier layer is surface treated by S ions in a vacuum environment for 3 to 7 minutes.
9. The transistor manufacturing method according to claim 6, characterized in that: When the two-dimensional material layer is a BN layer, surface treatment is performed on the barrier layer, including: The barrier layer is surface treated by N ions in a vacuum environment for 3 to 7 minutes.
10. The transistor manufacturing method according to any one of claims 5 to 9, characterized in that: The thickness of the two-dimensional material layer is 10 to 30 nm.