A tensile-strained high-hole-mobility field effect transistor and a method of fabricating the same

Abstract

The application discloses a tensile strain high hole mobility field effect transistor, comprising a base substrate, a substrate, a buffer layer, a barrier layer, an insertion layer, a space isolation layer, a hole supply layer, a source electrode, a drain electrode and a gate electrode; the substrate is made of polycrystalline AlN material, and a plurality of blind holes are formed in the substrate; when the buffer layer is grown on the substrate, the material of the buffer layer is grown on the surface of the substrate and the sidewalls of the plurality of blind holes and is combined to introduce tensile strain; the barrier layer is located on the buffer layer, the insertion layer is located on the barrier layer, the space isolation layer is located on the insertion layer, the hole supply layer is located on the space isolation layer, and the source electrode, the drain electrode and the gate electrode are located on the hole supply layer. The application further discloses a preparation method of the tensile strain high hole mobility field effect transistor. According to the application, the p-channel heterojunction epitaxy is performed on the polycrystalline AlN substrate with the blind holes, the introduction and distribution of stress can be accurately controlled, and the hole mobility is improved.

Description

Technical Field

[0001] This invention relates to the field of field-effect transistor technology, and in particular to a tensile strain high hole mobility field-effect transistor and its fabrication method. Background Technology

[0002] Compared to silicon, a material used in traditional electronic power devices, group III nitride semiconductors possess superior properties such as a large bandgap, high breakdown electric field strength, high saturated electron mobility, high thermal conductivity, low dielectric constant, and strong radiation resistance. Furthermore, the polarization-induced carrier density in gallium nitride is independent of temperature. Therefore, gallium nitride (GaN) is considered a promising candidate material for power integrated circuits used in harsh environments.

[0003] In the past two years, GaN-based complementary logic circuits have been researched and proven, and monolithic GaN CL gates with truly "CMOS-like" behavior have been obtained. GaN-based complementary logic integrated circuits are currently in their early stages, and further optimization of device performance is needed. Carrier concentration and mobility need to be improved, especially the low channel mobility and high on-resistance of current GaN-based p-channel field-effect transistors. On the one hand, Mg impurities in GaN have high ionization energy and low hole concentration; on the other hand, the large effective hole mass greatly limits hole mobility. First-principles calculations show that introducing biaxial tensile strain into GaN can raise the spin-orbit coupling splitting band to above the light hole band and heavy hole band. This effect changes the order of the valence band top and the characteristics of the wave function, which can significantly reduce the effective hole mass and thus achieve the desired hole mobility in GaN. Currently, common methods for introducing the required stress distribution in GaN during metal-organic chemical vapor deposition (MOCVD) growth are to use a substrate with a large lattice constant and change the barrier layer material. However, due to lattice mismatch, the crystal growth quality will degrade. Therefore, existing GaN-based p-channel field-effect transistors have low hole mobility and lack effective means to improve hole mobility. Tensile stress introduction is unstable and it is difficult to control the stress intensity. Stress introduction is difficult and can easily cause thin film cracking. Stress introduction will introduce a large number of defects and dislocations, making it difficult to obtain high-quality materials. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a tensile-strained high-hole-mobility field-effect transistor and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] The first aspect of the present invention provides a tensile strain high hole mobility field-effect transistor, comprising: a substrate, a buffer layer, a barrier layer, an insertion layer, a spatial isolation layer, a hole supply layer, a source electrode, a drain electrode, and a gate electrode;

[0006] The substrate includes: a base substrate and a substrate located on the base substrate;

[0007] The substrate is made of polycrystalline AlN material, and multiple blind vias are formed on the substrate; the multiple blind vias are evenly arranged.

[0008] The buffer layer is located on the substrate. When the buffer layer is grown on the substrate, the material of the buffer layer grows and merges on the substrate surface and multiple blind hole sidewalls to introduce tensile strain.

[0009] The barrier layer is located on the buffer layer, the insertion layer is located on the barrier layer, the spatial isolation layer is located on the insertion layer, the hole supply layer is located on the spatial isolation layer, and the source electrode, the drain electrode, and the gate electrode are located on the hole supply layer.

[0010] In one embodiment of the present invention, the plurality of blind holes form an array, with adjacent columns or rows of blind holes being staggered.

[0011] In one embodiment of the present invention, the buffer layer is made of GaN material, the barrier layer is made of AlGaN material with an Al composition of 20%-40%, the insertion layer is made of AlN material, the space isolation layer is made of GaN material, and the hole supply layer is made of p-type doped GaN material.

[0012] In one embodiment of the present invention, the blind hole is prepared by inductively coupled plasma etching.

[0013] In one embodiment of the present invention, the thickness of the substrate is 2μm-4μm, the diameter of the blind via is 1μm-3μm, and the depth is 100nm-800nm; the center-to-center distance between two adjacent blind vias is 6μm-10μm.

[0014] The thickness of the buffer layer is 2μm-4μm;

[0015] The thickness of the barrier layer is 15nm-60nm;

[0016] The thickness of the insertion layer is 1nm-3nm;

[0017] The thickness of the spatial isolation layer is 5nm-10nm;

[0018] The hole supply layer is doped with Mg at a concentration of 1×10⁻⁶. 19 cm -3 -6×10 19 cm -3 The thickness is 20nm-80nm.

[0019] A second aspect of this invention provides a method for fabricating a tensile strain high hole mobility field-effect transistor, comprising the following steps:

[0020] Step 1: Growing a substrate on a base substrate; wherein the substrate is made of polycrystalline AlN material;

[0021] Step 2: Prepare multiple blind vias on the substrate, wherein the multiple blind vias are evenly arranged;

[0022] Step 3: Grow a buffer layer on the substrate; wherein the material of the buffer layer is grown and merged on the substrate surface and multiple blind hole sidewalls to introduce tensile strain;

[0023] Step 4: Grow a barrier layer on the buffer layer, grow an insertion layer on the barrier layer, grow a space isolation layer on the insertion layer, grow a hole supply layer on the space isolation layer, and fabricate a source electrode, a drain electrode, and a gate electrode on the hole supply layer.

[0024] In one embodiment of the present invention, the plurality of blind holes form an array, with adjacent columns or rows of blind holes being staggered.

[0025] In one embodiment of the present invention, step one specifically includes the following steps:

[0026] The substrate is grown on the substrate using controlled sputtering or physical vapor transport.

[0027] In one embodiment of the present invention, step two specifically includes the following steps:

[0028] Multiple blind holes were etched on the substrate using inductively coupled plasma etching.

[0029] In one embodiment of the present invention, the buffer layer is made of GaN material and has a thickness of 2μm-4μm;

[0030] The barrier layer is made of AlGaN material with an Al composition of 20%-40% and a thickness of 15nm-60nm;

[0031] The insertion layer is made of AlN material and has a thickness of 1nm-3nm.

[0032] The spatial isolation layer is made of GaN material and has a thickness of 5nm-10nm.

[0033] The hole supply layer is made of p-type doped GaN material, with Mg as the dopant and a doping concentration of 1×10⁻⁶. 19 cm -3 -6×10 19 cm -3 The thickness is 20nm-80nm.

[0034] The beneficial effects of this invention are:

[0035] This invention enables the non-coherent growth of p-channel heterojunctions using a polycrystalline AlN substrate. Simultaneously, vias are created on the polycrystalline AlN substrate, allowing epitaxial material to grow in both longitudinal and lateral directions on the substrate surface and within the vias, resulting in lateral merging. This introduces tensile strain, which alters the order of the valence band tops and the characteristics of the wavefunction, reducing the effective mass of holes and achieving the fabrication of tensile-strained p-channel heterojunctions, thereby improving hole mobility. The strain state can be precisely controlled by varying the size and spacing of the vias. Furthermore, polycrystalline AlN fabrication methods are diverse, the growth process is simple, highly controllable, and the fabrication process is straightforward. The size of the vias allows for precise stress adjustment, improving the stability of growth processes such as MOCVD, ensuring material quality, and precisely controlling mobility. This helps reduce the impact of process variations on film quality, improving production consistency and reliability.

[0036] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings.

[0037] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0038] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0039] Figure 1 A schematic diagram of a tensile strain high hole mobility field-effect transistor provided in an embodiment of the present invention;

[0040] Figure 2 This is a schematic diagram of the fabrication process of a tensile strain high hole mobility field-effect transistor provided in an embodiment of the present invention. Detailed Implementation

[0041] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0042] like Figure 1 As shown, a first aspect of the present invention provides a tensile strain high hole mobility field-effect transistor, comprising: a substrate, a buffer layer 5, a barrier layer 6, an insertion layer 7, a spatial isolation layer 8, a hole supply layer 9, a source electrode 10, a drain electrode 11, and a gate electrode 13.

[0043] The substrate includes: a base substrate 1 and a substrate 2 located on the base substrate 1.

[0044] The substrate 2 is made of polycrystalline AlN material, and multiple blind holes 3 are formed on the substrate 2. The multiple blind holes 3 are evenly arranged, and the blind holes 3 are the same size and the spacing between two adjacent blind holes 3 is equal. Among them, the buffer layer 5 is located on the substrate 2. When the buffer layer 5 is grown on the substrate 2, the material of the buffer layer 5 grows on the surface of the substrate 2 and the sidewalls of the multiple blind holes 3 and merges to introduce tensile strain.

[0045] Barrier layer 6 is located on buffer layer 5, insertion layer 7 is located on barrier layer 6, spatial isolation layer 8 is located on insertion layer 7, hole supply layer 9 is located on spatial isolation layer 8, and source electrode 10, drain electrode 11 and gate electrode 13 are located on hole supply layer 9.

[0046] In this embodiment, a p-channel heterojunction can be non-coherently grown using a polycrystalline AlN substrate 2. Simultaneously, vias are created on the polycrystalline AlN substrate 2. During the growth of epitaxial material on the polycrystalline AlN substrate 2, nucleation occurs at different sites. Then, the material grows in both lateral and longitudinal directions on the surface of the polycrystalline AlN substrate 2 and within the blind vias 3. After lateral growth extends a certain distance, the nucleated materials at different sites meet and merge (materials on the surface of substrate 2 merge laterally, and materials within the blind vias 3 merge laterally). After longitudinal growth extends a certain distance, the materials on the surface of substrate 2 and within the blind vias 3 merge laterally, introducing tensile strain during merging. This stress reduces the effective mass of holes, enabling the fabrication of a tensile-strained p-channel heterojunction and significantly improving hole mobility. The strain state can be precisely controlled by varying the size of the blind vias 3 and the spacing between them. Furthermore, polycrystalline AlN fabrication methods are diverse, the growth process is simple, highly controllable, and the fabrication process is straightforward. The size of the blind via 3 can be precisely adjusted to adjust the stress, improve the stability of growth processes such as MOCVD, ensure material quality, and precisely control the migration rate. This helps to reduce the impact of process changes on film quality and improve production consistency and reliability.

[0047] Meanwhile, the tensile strain method using polycrystalline AlN substrate 2 is applicable to the growth of various group III nitride semiconductor materials and heterostructures, and has broad application prospects.

[0048] Furthermore, after the epitaxial material merges at the blind hole 3, a cavity will be generated at the bottom of the blind hole 3.

[0049] Preferably, multiple blind holes 3 are arranged in an array, with adjacent columns or rows of blind holes 3 staggered from each other. Therefore, regular hexagons can be formed in any three consecutive columns of blind holes 3, which is similar to the crystal structure of nitrides and facilitates the growth of nitrides.

[0050] The substrate 2 is made of polycrystalline AlN material with a thickness of 2μm-4μm, and can be fabricated using methods such as, but not limited to, magnetron sputtering and physical vapor transport (PVT). The blind vias 3 are fabricated using inductively coupled plasma etching (ICP), with a diameter of 1μm-3μm and a depth of 100nm-800nm. The center-to-center distance between two adjacent blind vias 3 is 6μm-10μm.

[0051] Buffer layer 5 is made of GaN material with a thickness of 2μm-4μm. Barrier layer 6 is made of AlGaN material with an Al composition of 20%-40% and a thickness of 15nm-60nm. Insertion layer 7 is made of AlN material with a thickness of 1nm-3nm. Spare layer 8 is made of GaN material with a thickness of 5nm-10nm. Hole supply layer 9 is made of p-type doped GaN material with Mg as the dopant and a doping concentration of 1×10⁻⁶. 19 cm -3 -6×10 19 cm -3 The thickness is 20nm-80nm.

[0052] A second aspect of this invention provides a method for fabricating a tensile strain high hole mobility field-effect transistor, used to fabricate the field-effect transistor provided in the first aspect of this invention, comprising the following steps:

[0053] Step 1: Grow substrate 2 on substrate 1; wherein substrate 2 is made of polycrystalline AlN material.

[0054] Step 2: Prepare multiple blind holes 3 on substrate 2, with the multiple blind holes 3 evenly arranged.

[0055] Step 3: Grow a buffer layer 5 on the substrate 2. The material of the buffer layer 5 is grown on the surface of the substrate 2 and the sidewalls of multiple blind holes 3 and merged to introduce tensile strain.

[0056] Step 4: Grow a barrier layer 6 on the buffer layer 5, grow an insertion layer 7 on the barrier layer 6, grow a spatial isolation layer 8 on the insertion layer 7, grow a hole supply layer 9 on the spatial isolation layer 8, and fabricate a source electrode 10, a drain electrode 11, and a gate electrode 13 on the hole supply layer 9.

[0057] The specific preparation method of this embodiment is further described below, including the following steps:

[0058] Step S11: On the substrate 1, a substrate 2 with a thickness of 2μm-4μm is grown; the substrate 2 is made of polycrystalline AlN material.

[0059] In step S12, blind vias 3 with a diameter of 1μm-3μm and a depth of 100nm-800nm ​​are fabricated on substrate 2 using inductively coupled plasma etching, with a spacing of 6μm-10μm. Multiple blind vias 3 are uniformly arranged and form an array, with adjacent columns or rows of blind vias 3 staggered from each other.

[0060] Step S13: On substrate 2, a buffer layer 5 of GaN material with a thickness of 2μm-4μm is grown using MOCVD process. The material of the buffer layer 5 is grown on the surface of substrate 2 and on the sidewalls of multiple blind holes 3 and merged to introduce tensile strain.

[0061] Step S14: On the buffer layer 5, a barrier layer 6 of AlGaN material with an Al composition of 20%-40% and a wavelength of 15nm-60nm is grown using MOCVD process.

[0062] Step S15: On the barrier layer 6, an insertion layer 7 of 1nm-3nm AlN material is grown using MOCVD process.

[0063] Step S16: On the insertion layer 7, a 5nm-10nm GaN material space isolation layer 8 is grown using MOCVD process.

[0064] Step S17: On the spatial isolation layer 8, a hole supply layer 9 of p-type doped GaN material with a diameter of 20nm-80nm is grown using MOCVD process.

[0065] In step S18, a Ni / Au metal stack (50nm / 100nm) is deposited on the hole supply layer 9 using an electron beam evaporation process, and then annealed at 550°C in an O2 environment to form the ohmic contact between the source electrode 10 and the drain electrode 11 in the p-FET.

[0066] Step S19: The hole supply layer 9 is etched using low-damage GaN etching technology with an etching depth of 10nm-70nm, and then annealed at 450℃ in an N2 atmosphere to form the gate groove 12.

[0067] In step S20, a W / Au (20nm / 100nm) metal stack is deposited on the gate groove 12 using a magnetron sputtering process to form the gate electrode 13 of the p-FET. After the fabrication is completed, the field-effect transistor provided in Embodiment 1 of the present invention is obtained.

[0068] Preferably, the substrate 2 is 3 μm thick, the blind via 3 has a diameter of 2 μm, the via depth is 100 nm, the spacing is 8 μm, the buffer layer 5 has a thickness of 4 μm, the barrier layer 6 has a thickness of 30 nm and an Al composition of 25%, the insertion layer 7 has a thickness of 2 nm, the space isolation layer 8 has a thickness of 10 nm, and the hole supply layer 9 has a thickness of 30 nm and a doping concentration of 3 × 10⁻⁶. 19 cm-3 Taking the fabrication method of tensile strained GaN-based p-FETs as an example, the fabrication method of this embodiment will be specifically described:

[0069] Step S21: Select substrate 1 material, such as Figure 2 As shown in (a).

[0070] Sapphire was chosen as the substrate 1.

[0071] Step S22: Preparation of substrate 2, such as Figure 2 As shown in (b).

[0072] A 3 μm thick polycrystalline AlN layer was grown using the PVT method.

[0073] Step S23: Open holes in substrate 2, such as... Figure 2 As shown in (c).

[0074] ICP was used to create holes in the substrate 2. A Cl2 / BCl3 mixed gas was used as the etching gas, with a Cl2 flow rate of 70 sccm and a BCl3 flow rate of 5 sccm. The etching rate was 55 nm / min, the etching time was 1.5 min, and the etching depth was 100 nm. Blind holes 3 with a diameter of 2 μm were formed on the AlN surface. The center distance between two adjacent blind holes 3 was 8 μm. Regular hexagons could be found in any three consecutive rows of blind holes 3, which is similar to the crystal structure of nitrides and is conducive to the growth of nitrides.

[0075] Step S24: Epitaxial buffer layer 5, as shown Figure 2 As shown in (d).

[0076] The product prepared in step S23 is placed in an MOCVD reaction chamber. The temperature of the reaction chamber is raised to 960°C and the pressure of the reaction chamber is maintained at 30 Torr. At the same time, a nitrogen source with a flow rate of 2500 sccm and a gallium source with a flow rate of 180 sccm are introduced. A GaN buffer layer 5 with a thickness of 4 μm is grown on the AlN substrate 2 using the MOCVD process.

[0077] Step S25: Epitaxial barrier layer 6, as shown Figure 2 As shown in (e).

[0078] The reaction chamber temperature was raised to 1010℃, and the reaction chamber pressure was maintained at 20 Torr. Simultaneously, a nitrogen source with a flow rate of 2500 sccm, a gallium source with a flow rate of 60 sccm, and an aluminum source with a flow rate of 300 sccm were introduced to grow a 30 nm thick Al layer on the buffer layer 5. 0.25 Ga 0.75 N-barrier layer 6.

[0079] Step S26: Epitaxial insertion layer 7, as shown Figure 2 As shown in (f).

[0080] The reaction chamber temperature was kept at 1010℃ and the reaction chamber pressure was kept at 20 Torr. At the same time, a nitrogen source with a flow rate of 3200 sccm and an aluminum source with a flow rate of 400 sccm were introduced to grow an AlN insertion layer 7 with a thickness of 2 nm on the barrier layer 6.

[0081] Step S27: Extended space isolation layer 8, such as Figure 2 As shown in (g).

[0082] The reaction chamber temperature was reduced to 960°C, the reaction chamber pressure was maintained at 20 Torr, and a nitrogen source with a flow rate of 2500 sccm and a gallium source with a flow rate of 180 sccm were simultaneously introduced to grow a GaN space isolation layer 8 with a thickness of 10 nm on the insertion layer 7.

[0083] Step S28: Epitaxial hole supply layer 9, such as Figure 2 As shown in (h).

[0084] The reaction chamber temperature was kept at 960°C and the reaction chamber pressure was kept at 20 Torr. Nitrogen source with a flow rate of 2500 sccm, gallium source with a flow rate of 180 sccm and magnesium source with a flow rate of 100 sccm were simultaneously introduced to grow a p-type GaN hole supply layer 9 with a thickness of 30 nm on the space isolation layer 8.

[0085] Step S29: Fabricate the source electrode 10 and drain electrode 11, as follows Figure 2 As shown in (i).

[0086] A Ni / Au metal stack with a thickness of 50 nm / 100 nm was deposited on the hole supply layer 9 using electron beam evaporation. After annealing in an O2 environment at 550 °C for 5 minutes, a source electrode 10 and a drain electrode 11 were fabricated on the hole supply layer 9.

[0087] Step S30: Etch gate groove 12, as shown Figure 2 As shown in (j).

[0088] The hole supply layer 9 was etched using a low-damage Cl2 / BCl3 slow etching process at an etching rate of 2.4 nm / min and an etching depth of 20 nm. The sample was then treated with NH3:H2O (1:6) at 55 °C for 5 minutes to remove surface contaminants and residual photoresist. The sample was then annealed in an N2 environment at 450 °C for 5 minutes to reduce surface damage caused by etching, resulting in the gate groove 12.

[0089] Step S31: Fabricate the gate electrode 13, as follows Figure 2 As shown in (k).

[0090] A W / Au metal stack with a thickness of 20nm / 100nm is deposited on the gate groove 12 using a magnetron sputtering process to form the gate electrode 13.

[0091] Through the above implementation method, the strain-strained GaN-based high hole mobility p-channel field-effect transistor of the present invention can effectively control the strain and significantly improve the hole mobility.

[0092] This invention significantly improves migration rate: by utilizing stress to change the effective mass of the hole, the migration rate is greatly improved.

[0093] The stress introduction of this invention is simple: there are various methods for preparing polycrystalline AlN, the growth process is simple and highly controllable, and there is no need to introduce complex processes.

[0094] This invention improves process stability: adjusting the size of blind vias allows for precise stress regulation, enhancing the stability of growth processes such as MOCVD, ensuring material quality, and enabling precise control of migration rates. This helps reduce the impact of process variations on film quality, improving production consistency and reliability.

[0095] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0096] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0097] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0098] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0099] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0100] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A tensile strained high vertical hole mobility field effect transistor, characterized by, The application relates to a substrate, a buffer layer, a barrier layer, an intercalation layer, a spatial isolation layer, a hole supply layer, a source electrode, a drain electrode and a gate electrode. The substrate comprises a base substrate and a base plate on the base substrate. The base plate is made of polycrystalline AlN material, and a plurality of blind holes are arranged on the base plate. The buffer layer is arranged on the base plate, and when the buffer layer is grown on the base plate, the material of the buffer layer grows on the surface of the base plate and the sidewalls of the plurality of blind holes and is combined to introduce tensile strain. The barrier layer is arranged on the buffer layer, the intercalation layer is arranged on the barrier layer, the spatial isolation layer is arranged on the intercalation layer, the hole supply layer is arranged on the spatial isolation layer, and the source electrode, the drain electrode and the gate electrode are arranged on the hole supply layer. The plurality of blind holes form an array, and adjacent two columns or two rows of blind holes are staggered.

2. A tensile strained high vertical hole mobility field effect transistor as in claim 1, wherein: The buffer layer is made of GaN material, the barrier layer is made of AlGaN material with an Al component of 20%-40%, the intercalation layer is made of AlN material, the spatial isolation layer is made of GaN material, and the hole supply layer is made of p-type doped GaN material.

3. A tensile strained high vertical hole mobility field effect transistor as in claim 1, wherein: The blind holes are prepared by inductive coupling plasma etching.

4. A tensile strained high vertical hole mobility field effect transistor as in Claim 2, wherein the gate dielectric layer is a high-k gate dielectric layer. The thickness of the base plate is 2-4 mu m, the diameter of the blind hole is 1-3 mu m, the depth is 100-800 nm, and the center distance between adjacent two blind holes is 6-10 mu m.

5. A tensile strained high vertical hole mobility field effect transistor as in Claim 2, wherein the gate dielectric layer is a high-k gate dielectric layer. The thickness of the buffer layer is 2-4 mu m. The thickness of the barrier layer is 15-60 nm. The thickness of the intercalation layer is 1-3 nm. The thickness of the spatial isolation layer is 5-10 nm. The application further discloses a preparation method of the substrate. The dopant of the hole supply layer is Mg, the doping concentration is 1 x 10 19 cm -3 -6 x 10 19 cm -3 , and the thickness is 20 nm-80 nm.

6. A method for fabricating a tensile strain high hole mobility field-effect transistor, characterized in that, Step one: growing a base plate on a base substrate, wherein the base plate is made of polycrystalline AlN material. Step two: preparing a plurality of blind holes on the base plate, and the plurality of blind holes are uniformly arranged. Step three: growing a buffer layer on the base plate, wherein the material of the buffer layer grows on the surface of the base plate and the sidewalls of the plurality of blind holes and is combined to introduce tensile strain. Step four: growing a barrier layer on the buffer layer, growing an intercalation layer on the barrier layer, growing a spatial isolation layer on the intercalation layer, growing a hole supply layer on the spatial isolation layer, and preparing a source electrode, a drain electrode and a gate electrode on the hole supply layer. The plurality of blind holes form an array, and adjacent two columns or two rows of blind holes are staggered.

7. The method for fabricating a tensile strain high hole mobility field-effect transistor as described in claim 6, characterized in that, The specific steps of the step one comprise the following steps.

8. The method for fabricating a tensile strain high hole mobility field-effect transistor as described in claim 6, characterized in that, The base plate is grown on the base substrate by using a controlled sputtering method or a physical vapor transmission method. The specific steps of the step two comprise the following steps.

9. The method for fabricating a tensile strain high hole mobility field-effect transistor as described in claim 6, characterized in that, The plurality of blind holes are etched on the base plate by using inductive coupling plasma etching. The buffer layer is made of GaN material and has a thickness of 2-4 mu m.

10. The method for fabricating a tensile strain high hole mobility field-effect transistor as described in claim 6, characterized in that, The barrier layer is made of AlGaN material with an Al component of 20%-40% and has a thickness of 15-60 nm. The intercalation layer is made of AlN material and has a thickness of 1-3 nm. The spatial isolation layer is made of GaN material and has a thickness of 5-10 nm. ​ The hole supply layer adopts p-type doped GaN material, the dopant is Mg, the doping concentration is 1x10 19 cm -3 -6x10 19 cm -3 , and the thickness is 20nm-80nm.

Images