Gallium nitride transistor and preparation method thereof

Abstract

The invention discloses a gallium nitride transistor and a preparation method thereof, and relates to the technical field of semiconductor devices. The gallium nitride transistor comprises a substrate; the plurality of superlattice structures are positioned on one side of the substrate and are arranged in sequence; a spacing cavity is formed between every two adjacent superlattice structures; the superlattice structure comprises a channel layer and a barrier layer which are stacked; the first groove and the second groove penetrate through the channel layer and the barrier layer of each second superlattice structure and the barrier layer of the first superlattice structure, and are positioned on two opposite sides of each superlattice structure; the source electrode and the drain electrode are respectively positioned in the first groove and the second groove and are in contact with each superlattice structure; the dielectric structures are located between the source electrode and the drain electrode, located in the interval cavities and cover the surfaces of the superlattice structures; and the grid electrode is positioned between the source electrode and the drain electrode and surrounds the dielectric structure. According to the technical scheme, the control effect of the grid electrode on the conducting channel layer is improved by arranging the grid electrode of the dielectric structure surrounding and covering the surface of each superlattice structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of semiconductor devices, and in particular to a gallium nitride transistor and a method for preparing the same. Background Art

[0002] Due to the wide bandgap and high saturated electron drift velocity of gallium nitride (GaN), high electron mobility transistors (HEMT) based on GaN show broad prospects in the next generation of high-power, high-frequency switching applications.

[0003] In the prior art, a superlattice epitaxial structure is usually used to increase the current density of GaN transistors, which effectively improves carrier transport and enhances the performance of GaN transistors. However, due to the thick conductive channel layer in the superlattice epitaxial structure, the gate has poor control effect on the flow of carriers in the conductive channel layer, thereby limiting the performance and stability of GaN transistors. Therefore, it is urgent to solve the technical problem of poor control effect of the gate on the conductive channel layer in the superlattice epitaxial structure of GaN transistors. Summary of the invention

[0004] The present invention provides a gallium nitride transistor and a method for preparing the same, so as to improve the control effect of a gate on a conductive channel layer, thereby improving the performance and stability of the gallium nitride transistor.

[0005] A first aspect of the present invention provides a gallium nitride transistor, the gallium nitride transistor comprising:

[0006] substrate;

[0007] A plurality of superlattice structures are arranged in sequence on one side of the substrate; a cavity is provided between any two adjacent superlattice structures; the superlattice structure comprises a channel layer and a barrier layer arranged in a stacked manner; the superlattice structure closest to the substrate among the superlattice structures is a first superlattice structure, and the other superlattice structures located on the side of the first superlattice structure away from the substrate are all second superlattice structures;

[0008] A first trench and a second trench penetrating the channel layer and the barrier layer of each of the second superlattice structures, and the barrier layer of the first superlattice structure; the first trench and the second trench are located on opposite sides of each of the superlattice structures;

[0009] a source electrode located in the first trench and in contact with each of the superlattice structures, and a drain electrode located in the second trench and in contact with each of the superlattice structures;

[0010] A dielectric structure located between the source and the drain, located in each of the spacing cavities, and covering a surface of each of the superlattice structures;

[0011] A gate is located between the source and the drain and surrounds the dielectric structure.

[0012] Optionally, the dielectric structure at least includes a gate dielectric layer located between the source and the drain and covering each of the superlattice surfaces, and covering each of the superlattice surfaces in the spacing cavity, and surfaces of the source and the drain.

[0013] Optionally, the dielectric structure further includes a conductive dielectric layer located on a side of the gate dielectric layer away from the superlattice structure and covering the gate dielectric layer.

[0014] Optionally, the gate dielectric layer includes at least one of a silicon oxide layer and an aluminum oxide layer, and the conductive dielectric layer includes a titanium nitride layer.

[0015] Optionally, along the arrangement direction of each of the superlattice structures, a value range of a thickness L1 of the spacing cavity between two adjacent superlattice structures is: 20 nm≤L1≤70 nm.

[0016] Optionally, the thickness L2 of the channel layer is in the range of: 15 nm ≤ L2 ≤ 100 nm;

[0017] The thickness L3 of the barrier layer has a value range of 15 nm ≤ L3 ≤ 50 nm.

[0018] Optionally, along the arrangement direction of the first groove and the second groove, a width W1 of the first groove has a value range of W1≥5 μm, and a width W2 of the second groove has a value range of W2≥5 μm.

[0019] A second aspect of the present invention provides a method for preparing a gallium nitride transistor, the method for preparing a gallium nitride transistor comprising:

[0020] providing a substrate;

[0021] A plurality of superlattice structures and a barrier layer located between two adjacent superlattice structures are sequentially formed on one side of the substrate; wherein the superlattice structure comprises a channel layer and a barrier layer which are stacked; the superlattice structure closest to the substrate among the superlattice structures is a first superlattice structure, and the other superlattice structures located on the side of the first superlattice structure away from the substrate are all second superlattice structures;

[0022] Forming a first trench and a second trench penetrating the channel layer and the barrier layer of each of the second superlattice structures and the barrier layer of the first superlattice structure; wherein the first trench and the second trench are located on opposite sides of each of the superlattice structures;

[0023] forming a source electrode in contact with each of the superlattice structures in the first trench, and forming a drain electrode in contact with each of the superlattice structures in the second trench;

[0024] removing the barrier layer between the superlattice structures;

[0025] forming a dielectric structure between the source and the drain; wherein the dielectric structure is located in each of the spacer cavities and covers the surface of each of the superlattice structures;

[0026] A gate is formed between the source and the drain and surrounds the dielectric structure.

[0027] Optionally, forming a dielectric structure between the source and the drain includes:

[0028] Forming a gate dielectric layer located between the source and the drain and covering each of the superlattice surfaces, and covering each of the superlattice surfaces in the spacing cavity, and the source and drain surfaces;

[0029] A conductive dielectric layer is formed which is located on a side away from the superlattice structure and covers the gate dielectric layer.

[0030] Optionally, removing the barrier layer between the superlattice structures comprises:

[0031] A hydrofluoric acid solution is used for selective etching to remove the barrier layers between the superlattice structures.

[0032] The technical solution of the present invention improves the current carrying capacity of the gallium nitride transistor by arranging a plurality of superlattice structures arranged in sequence on one side of the substrate of the gallium nitride transistor, each superlattice structure includes a stacked channel layer and a barrier layer to form a plurality of conductive channels; after patterning the plurality of superlattice structures, a first trench and a second trench are formed on opposite sides of the plurality of superlattice structures, and a source is formed in the first trench and a drain is formed in the second trench, and both the source and the drain are directly in contact with the channel layer in the first superlattice structure, which helps to reduce the contact resistance, ensure the structural stability of the gallium nitride transistor, and ensure the effective transmission of carriers in the conductive channel of the gallium nitride transistor. In addition, by arranging a dielectric structure covering the surface of each superlattice structure between the source and the drain and in each spacing cavity, the depletion effect of the gallium nitride transistor can be enhanced while ensuring good contact between two adjacent superlattice structures, effectively reducing the leakage current between the two adjacent superlattice structures, reducing energy loss, and improving the electrical performance of the gallium nitride transistor. At the same time, by arranging a gate between the source and the drain and surrounding the dielectric structure, the dielectric structure can form electrical isolation between each superlattice structure and the gate, avoiding current leakage and interference, and the gate can more comprehensively cover and control each superlattice structure in the multiple superlattice structures. The gate can more effectively control the transmission efficiency and performance of carriers in the conductive channel of the gallium nitride transistor, thereby improving the control effect of the gate on the conductive channel layer of the gallium nitride transistor and improving the performance and stability of the gallium nitride transistor.

[0033] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0035] Figure 1 is a schematic diagram of a device structure of a gallium nitride transistor provided by an embodiment of the present invention;

[0036] Figure 2 is a schematic diagram of the device structure of another gallium nitride transistor provided by an embodiment of the present invention;

[0037] Figure 3 It is a schematic flow chart of a method for preparing a gallium nitride transistor provided by an embodiment of the present invention;

[0038] Figure 4 It is a structural schematic diagram of a process for preparing a gallium nitride transistor provided by an embodiment of the present invention;

[0039] Figure 5 It is a schematic flow chart of a method for preparing a dielectric structure provided by an embodiment of the present invention;

[0040] Figure 6 It is a structural schematic diagram of a process for preparing a dielectric structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0041] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0042] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0043] Figure 1 is a schematic diagram of a device structure of a gallium nitride transistor provided by an embodiment of the present invention, such as Figure 1As shown, the gallium nitride transistor includes: a substrate 1; a plurality of superlattice structures located on one side of the substrate 1 and arranged in sequence; a spacer cavity is provided between any two adjacent superlattice structures; the superlattice structure includes a channel layer 01 and a barrier layer 02 arranged in a stacked manner; the superlattice structure closest to the substrate 1 among the superlattice structures is a first superlattice structure 201, and the other superlattice structures located on the side of the first superlattice structure 201 away from the substrate 1 are all second superlattice structures; the channel layer 01 and the barrier layer 02 that penetrate through each second superlattice structure, as well as the first superlattice structure 201; The present invention relates to a first groove 21 and a second groove 22 of the barrier layer 02 of the structure 201; the first groove 21 and the second groove 22 are located at opposite sides of each superlattice structure; a source 501 is located in the first groove 21 and in contact with each superlattice structure, and a drain 503 is located in the second groove 22 and in contact with each superlattice structure; a dielectric structure 4 is located between the source 501 and the drain 503, located in each spacing cavity, and covers the surface of each superlattice structure; a gate 502 is located between the source 501 and the drain 503 and is arranged around the dielectric structure.

[0044] Among them, substrate 1 can be specifically understood as a material that supports the device structure of the entire gallium nitride transistor. Exemplarily, substrate 1 can be a combination of one or more of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, silicon, or any other material that can grow group III nitrides.

[0045] A plurality of superlattice structures are arranged in sequence on one side of the substrate 1. The superlattice structure closest to the substrate 1 among the superlattice structures is the first superlattice structure 201, and the other superlattice structures on the side of the first superlattice structure 201 away from the substrate 1 are all second superlattice structures. The number of superlattice structures can be designed according to actual needs, and the embodiment of the present invention does not make specific restrictions on this. For the convenience of description, without special restrictions, continue to refer to Figure 1The embodiments of the present invention all take the first superlattice structure 201, the first second superlattice structure 202, the second second superlattice structure 203 and the third second superlattice structure 204 as an example to exemplarily illustrate the technical solutions of the embodiments of the present invention. Among them, the first superlattice structure 201, the first second superlattice structure 202, the second second superlattice structure 203 and the third second superlattice structure 204 all include a stacked channel layer 01 and a barrier layer 02. For example, the channel layer 01 can be a GaN layer, and the barrier layer 02 can be an AlGaN layer, that is, a periodically stacked GaN layer and AlGaN layer combination are included on one side of the substrate 1. It can be understood that in each superlattice structure, the AlGaN layer has a larger bandgap width, while the GaN layer has a smaller bandgap width and high carrier mobility. When the AlGaN layer and the GaN layer are stacked, the GaN layer provides a channel with high carrier mobility. At the same time, the larger bandgap width of the AlGaN layer helps to form a stable energy level structure between the AlGaN layer and the GaN layer, which can prevent the scattering of carriers in the conductive channel of the gallium nitride transistor, thereby improving the carrier transmission efficiency and current density of the gallium nitride transistor. It can also be understood that arranging a plurality of superlattice structures arranged in sequence on one side of the substrate 1 is equivalent to forming a plurality of conductive channels on one side of the substrate 1, thereby increasing the number of channels for carrier transmission. Through the parallel action of multiple conductive channels, the movement path of carriers in the device becomes more diversified and balanced, reducing the congestion phenomenon when carriers migrate in a single channel, thereby improving the current carrying capacity of the gallium nitride transistor, and significantly improving the current transmission efficiency and performance of the gallium nitride transistor. In addition, the first superlattice structure 201 is located at the bottom layer of multiple superlattice structures and is in contact with the substrate 1. The first superlattice structure 201 is the first superlattice structure formed. The GaN layer in the first superlattice structure 201 can be used as a buffer layer to reduce the stress caused by the lattice mismatch between the substrate 1 and the multiple superlattice structures, which helps to optimize the growth and performance of subsequent hierarchical structures, thereby improving the stability of the overall structure of the gallium nitride transistor and the electrical performance of the gallium nitride transistor.

[0046] It can also be understood that a spacing cavity is provided between any two adjacent superlattice structures. Figure 1, a first spacing cavity 301 is provided between the first superlattice structure 201 and the first second superlattice structure 202, a second spacing cavity 302 is provided between the first second superlattice structure 202 and the second second superlattice structure 203, and a third spacing cavity 303 is provided between the second second superlattice structure 203 and the third second superlattice structure 204. By forming a spacing cavity between any two adjacent superlattice structures, a basis is provided for subsequently forming a dielectric structure covering the surface of each superlattice structure in each spacing cavity, so that the charge interference between the two adjacent superlattice structures can be effectively reduced, which is helpful to improve the stability and reliability of the gallium nitride transistor. In addition, the leakage phenomenon of carriers between the two adjacent superlattice structures can be reduced, thereby reducing energy loss and improving the efficiency and stability of the gallium nitride transistor.

[0047] Continue to refer Figure 1 After patterning the multiple superlattice structures, first trenches 21 and second trenches 22 can be formed on opposite sides of the multiple superlattice structures along the first direction X, wherein the first trenches 21 and the second trenches 22 can be specifically understood as depressions formed on opposite sides of the multiple superlattice structures along the first direction X, which are used to define the source region and the drain region in the gallium nitride transistor, providing a basis for subsequently forming a source 501 in the first trench 21 and a drain 503 in the second trench 22. In addition, the first trench 21 and the second trench 22 penetrate the channel layer 01 and the barrier layer 02 of each second superlattice structure, as well as the barrier layer 02 of the first superlattice structure 201, that is, the bottoms of the first trench 21 and the second trench 22 are both the channel layer 01 in the first superlattice structure 201, so that the source 501 subsequently formed in the first trench 21 and the drain 503 formed in the second trench 22 can directly contact the GaN layer in the first superlattice structure 201, thereby forming an ohmic contact with a low Schottky barrier, which helps to reduce contact resistance, facilitates the transmission of carriers between the source 501 and the drain 503, and improves the electrical performance and power consumption characteristics of the gallium nitride transistor. It can also be understood that the width of the first trench 21 along the first direction X and the width of the second trench 22 along the first direction X can be the same, so as to ensure that the width of the source 501 formed in the first trench 21 along the first direction X and the width of the drain 503 formed in the second trench 22 along the first direction X are the same, so that carriers can flow evenly between the source 501 and the drain 503, thereby optimizing the performance and stability of the gallium nitride transistor.

[0048] In addition, a source electrode 501 is disposed in the first trench 21, and a drain electrode 503 is disposed in the second trench 22. The source electrode 501 and the drain electrode 503 are both in contact with the GaN layer at the bottom of the first trench 21 and the second trench 22, which helps to reduce the contact resistance. At the same time, the source electrode 501 and the drain electrode 503 are also in contact with each superlattice structure. For example, continue to refer to Figure 1 , the width of the source 501 along the first direction X is equal to the width of the first groove 21 along the first direction X, the width of the drain 503 along the first direction X is equal to the width of the second groove 22 along the first direction X, and the height of the source 501 and the drain 503 along the second direction Y is consistent with the height of the multiple superlattice structures along the second direction Y, ensuring the structural stability of the gallium nitride transistor and ensuring the effective transmission of carriers in the conductive channel of the gallium nitride transistor.

[0049] A dielectric structure 4 covering the surface of each superlattice structure is disposed between the source 501 and the drain 503 and in each spacer cavity, wherein, Figure 1 The dielectric structure 4 is located in the first spacing cavity 301 between the first superlattice structure 201 and the first second superlattice structure 202, the second spacing cavity 302 between the first second superlattice structure 202 and the second second superlattice structure 203, and the third spacing cavity 303 between the second second superlattice structure 203 and the third second superlattice structure 204. At the same time, the dielectric structure 4 covers the surfaces of the first second superlattice structure 202, the second second superlattice structure 203 and the third second superlattice structure 204, so that the first superlattice structure 201, the first second superlattice structure 202, the second second superlattice structure 203 and the third second superlattice structure 204 can be stably contacted through the dielectric structure 4. It can be understood that by providing a dielectric structure 4 covering the surface of each superlattice structure between the source 501 and the drain 503 and in each spaced cavity, the depletion effect of the gallium nitride transistor can be enhanced under the premise of ensuring good contact between any two adjacent superlattice structures, effectively reducing the leakage current between the two adjacent superlattice structures and reducing energy loss. At the same time, when the gate surrounding the dielectric structure 4 is subsequently generated, the dielectric structure 4 can form electrical isolation between each superlattice structure and the gate, thereby avoiding current leakage and interference. The gate can more effectively control the transmission efficiency and performance of carriers in the conductive channel of the gallium nitride transistor, thereby improving the efficiency and reliability of the gallium nitride transistor. It can also be understood that the first superlattice structure 201 is a basic structure among multiple superlattice structures, and no dielectric structure is provided corresponding to the first superlattice structure 201 to ensure the structural stability and reliability of the gallium nitride transistor.

[0050] In addition, a gate 502 is provided between the source 501 and the drain 503 and around the dielectric structure. When a voltage is applied to the gate 502 and the threshold voltage of the gallium nitride transistor is reached, a current channel can be formed in the channel layer between the source 501 and the drain 503, so that carriers can flow between the source 501 and the drain 503, thereby generating current and turning on the gallium nitride transistor. When the voltage applied by the gate 502 does not meet the threshold voltage condition of the gallium nitride transistor, a current channel cannot be formed between the source 501 and the drain 503, so that the gallium nitride transistor is in a cut-off state. Since the gate 502 is disposed around the dielectric structure, and the dielectric structure is located in each spaced cavity and covers the surface of each superlattice structure, the gate 502 can more comprehensively cover and control each superlattice structure in the multiple superlattice structures, thereby increasing the control area of ​​the gate 502 on the conductive channel, thereby improving the control effect of the gate 502 on the conductive channel layer of the gallium nitride transistor, enhancing the depletion effect of the gallium nitride transistor, effectively reducing the leakage current between two adjacent superlattice structures, and improving the switching speed and performance of the gallium nitride transistor. It can be understood that, under the premise of ensuring that the width of the gate 502 along the first direction X is less than the width of the multiple superlattice structures along the first direction X, and the gate 502 can surround the dielectric structure, the width of the gate 502 along the first direction X and the height along the second direction Y can be specifically designed according to actual needs, and the embodiment of the present invention does not make specific limitations on this.

[0051] In this embodiment, multiple superlattice structures arranged in sequence are arranged on one side of the substrate of the gallium nitride transistor, and each superlattice structure includes a stacked channel layer and a barrier layer to form multiple conductive channels, thereby improving the current carrying capacity of the gallium nitride transistor; after patterning the multiple superlattice structures, a first trench and a second trench are formed on opposite sides of the multiple superlattice structures, and a source is formed in the first trench and a drain is formed in the second trench, and the source and the drain are directly in contact with the channel layer in the first superlattice structure, which helps to reduce the contact resistance, ensure the structural stability of the gallium nitride transistor, and ensure the effective transmission of carriers in the conductive channel of the gallium nitride transistor. In addition, by arranging a dielectric structure covering the surface of each superlattice structure between the source and the drain and in each spacer cavity, the depletion effect of the gallium nitride transistor can be enhanced under the premise of ensuring good contact between the two adjacent superlattice structures, effectively reducing the leakage current between the two adjacent superlattice structures, reducing energy loss, and improving the electrical performance of the gallium nitride transistor. At the same time, by arranging a gate between the source and the drain and surrounding the dielectric structure, the dielectric structure can form electrical isolation between each superlattice structure and the gate, avoiding current leakage and interference. The gate can more comprehensively cover and control each superlattice structure in the multiple superlattice structures. The gate can more effectively control the transmission efficiency and performance of carriers in the conductive channel of the gallium nitride transistor, thereby improving the control effect of the gate on the conductive channel layer of the gallium nitride transistor and improving the performance and stability of the gallium nitride transistor.

[0052] Optional, Figure 2 is a schematic diagram of the device structure of another gallium nitride transistor provided by an embodiment of the present invention, such as Figure 2 As shown, the dielectric structure 4 at least includes a gate dielectric layer 6 located between the source 501 and the drain 503 and covering each superlattice surface, and covering each superlattice surface in the spacing cavity, and the source 501 and the drain 503 surfaces.

[0053] Specifically, the gate dielectric layer 6 is filled in the first spacing cavity 301 between the first superlattice structure 201 and the first second superlattice structure 202, the second spacing cavity 302 between the first second superlattice structure 202 and the second second superlattice structure 203, and the third spacing cavity 303 between the second second superlattice structure 203 and the third second superlattice structure 204, and the gate dielectric layer 6 covers the surface of the first second superlattice structure 202, the surface of the second second superlattice structure 203, and the surface of the third second superlattice structure 204, so that the gate dielectric layer 6 can cover the surroundings of each superlattice structure. Among them, the gate dielectric layer 6 can be specifically understood as an insulating layer for isolating the gate 502 from each superlattice structure. In an optional embodiment, the gate dielectric layer 6 includes at least one of a silicon oxide layer and an aluminum oxide layer. The silicon oxide layer and the aluminum oxide layer both have good insulation properties, which are helpful to optimize the performance and reliability of the gallium nitride transistor. It can be understood that by providing a gate dielectric layer covering each superlattice surface and each superlattice surface in the spacer cavity, electrical isolation can be formed between each superlattice structure and the gate 502 through the gate dielectric layer 6, thereby avoiding current leakage and interference. At the same time, the width of the gate dielectric layer 6 along the first direction X is equal to the width of the multiple superlattice structures along the first direction X, so that the gate dielectric layer 6 can contact the surface of the source 501 and the drain 503 formed in the first groove 21 and the second groove 22 on the opposite sides of the multiple superlattice structures along the first direction X, so that the gate dielectric layer 6 can also serve as an insulating layer to isolate the source 501 and the drain 502 from each superlattice structure, and the gate dielectric layer 6 can protect the gallium nitride transistor when the gate voltage increases abnormally, thereby improving the performance and stability of the gallium nitride transistor. It can also be understood that the first superlattice structure 201 is the basic structure among multiple superlattice structures. If a gate dielectric layer 6 is set corresponding to the first superlattice structure 201, it may cause instability of several layers of superlattice structures, increase the risk of instability of the gallium nitride transistor, and may even cause it to fall or structural damage. Therefore, the gate dielectric layer 6 is not set corresponding to the first superlattice structure 201 to ensure the structural stability and reliability of the gallium nitride transistor.

[0054] Optional, continue to refer to Figure 2 The dielectric structure 4 further includes a conductive dielectric layer 7 which is located on a side of the gate dielectric layer 6 away from the superlattice structure and covers the gate dielectric layer 6 .

[0055] Specifically, the conductive dielectric layer 7 is located on the side of the gate dielectric layer 6 away from the superlattice structure and covers the gate dielectric layer 6, that is, the conductive dielectric layer 7 fills the first spacing cavity 301 between the first superlattice structure 201 and the first-second superlattice structure 202, the second spacing cavity 302 between the first-second superlattice structure 202 and the second-second superlattice structure 203, and the third spacing cavity 303 between the second-second superlattice structure 203 and the third-second superlattice structure 204, and covers the periphery of the gate dielectric layer 6, so that the first superlattice structure 201, the first-second superlattice structure 202, the second-second superlattice structure 203 and the third-second superlattice structure can be stably contacted through the conductive dielectric layer 7. Among them, the conductive dielectric layer 7 can be specifically understood as a hierarchical structure with certain conductive properties. In an optional embodiment, the conductive dielectric layer 7 includes a titanium nitride layer, which has a low resistivity and good conductive properties, so as to effectively improve the interface characteristics between each superlattice structure and the gate, improve the transmission efficiency of carriers in the conductive channel of the gallium nitride transistor, and help optimize the performance and reliability of the gallium nitride transistor. It can be understood that by arranging the conductive dielectric layer 7 covering the gate dielectric layer 6 on the side of the gate dielectric layer 6 away from the superlattice structure, it is achieved that the depletion effect of the gallium nitride transistor can be enhanced under the premise of ensuring good contact between two adjacent superlattice structures, effectively reducing the leakage current between the two adjacent superlattice structures and reducing energy loss. At the same time, when the gate 502 surrounding the conductive dielectric layer 7 is subsequently generated, the gate 502 can more effectively control the transmission efficiency and performance of carriers in the conductive channel of the gallium nitride transistor, thereby improving the efficiency and reliability of the gallium nitride transistor. In addition, since the gate dielectric layer 6 is disposed between the conductive dielectric layer 7 and the source 501 and the drain 503, the width of the conductive dielectric layer along the first direction X is smaller than the width of the multiple superlattice structures between the source 501 and the drain 503 along the first direction X, ensuring that the conductive dielectric layer will not directly contact the source 501 and the drain 503 located in the first trench 21 and the second trench 22 formed on the opposite sides of the multiple superlattice structures along the first direction X, thereby effectively preventing the short circuit between the source 501 and the drain 503, and improving the stability and reliability of the gallium nitride transistor. It can also be understood that the first superlattice structure 201 is the basic structure of the multiple superlattice structures. In order to avoid instability of several layers of superlattice structures, the gate dielectric layer 6 is not disposed corresponding to the first superlattice structure 201. Similarly, the conductive dielectric layer 7 is not disposed corresponding to the first superlattice structure 201 to ensure the structural stability and reliability of the gallium nitride transistor.

[0056] Optional, continue to refer to Figure 2 As shown, along the arrangement direction of each superlattice structure, the value range of the thickness L1 of the spacer cavity between two adjacent superlattice structures is: 20nm≤L1≤70nm.

[0057] Specifically, along the arrangement direction of each superlattice structure, that is, along the second direction Y, the thickness L1 of the spacing cavity between two adjacent superlattice structures is between 20nm and 70nm. This thickness value range provides a certain thickness variation range for the dielectric structure filling the spacing cavity between two adjacent superlattice structures and covering the surface of each superlattice structure. On the premise of ensuring that two adjacent dielectric structures are in contact with each other, the thickness of each dielectric structure can be designed according to actual needs, so that the electrical properties and characteristics of the gallium nitride transistor can be adjusted to meet different application requirements, thereby optimizing the performance and stability of the gallium nitride transistor.

[0058] Optional, continue to refer to Figure 2 As shown, the value range of the thickness L2 of the channel layer 01 is: 15nm≤L2≤100nm; the value range of the thickness L3 of the barrier layer 02 is: 15nm≤L3≤50nm.

[0059] Specifically, in each of the multiple superlattice structures, the thickness L2 of the channel layer GaN layer is between 15nm and 100nm, and the thickness L3 of the barrier layer AlGaN layer is between 15nm and 50nm. The thickness range of the GaN layer and the AlGaN layer can ensure that the thickness of each layer of the superlattice structure is moderate on the one hand, and on the other hand, it can ensure the stability of the gallium nitride transistor. It can be understood that a thicker GaN layer helps to reduce surface states and defects, thereby improving the mobility of carriers. Therefore, setting the thickness L2 of the GaN layer between 15nm and 100nm helps the GaN layer to form a channel with high carrier mobility. Setting the thickness L3 of the AlGaN layer between 15nm and 50nm can ensure that a stable energy level structure is formed between the AlGaN layer and the GaN layer, preventing carriers from scattering in the conductive channel of the gallium nitride transistor, thereby improving the carrier transmission efficiency and current density of the gallium nitride transistor. By setting the thickness of each GaN layer and each AlGaN layer in the multi-layer superlattice structure within an appropriate range, the performance and stability of the gallium nitride transistor are optimized.

[0060] Optional, continue to refer to Figure 2 As shown, along the arrangement direction of the first groove 21 and the second groove 22 , the width W1 of the first groove 21 has a value range of W1 ≥ 5 μm, and the width W2 of the second groove 22 has a value range of W2 ≥ 5 μm.

[0061] Specifically, the width W1 of the first groove 21 formed after patterning multiple superlattice structures along the arrangement direction of the first groove 21 and the second groove 22 is greater than or equal to 5μm, that is, the width W1 of the first groove 21 along the first direction X is greater than or equal to 5μm, and the width W2 of the second groove 22 formed after patterning multiple superlattice structures along the arrangement direction of the first groove 21 and the second groove 22 is greater than or equal to 5μm, that is, the width W2 of the second groove 22 along the first direction X is greater than or equal to 5μm. It can be understood that the source 501 is arranged in the first trench 21, and the drain 503 is arranged in the second trench 22. Therefore, the widths of the first trench 21 and the second trench 22 along the first direction X are both greater than or equal to 5 μm, ensuring that the first trench 21 and the second trench 22 can provide sufficient space to accommodate the source 501 and the drain 503, so that the widths of the formed source 501 and the drain 503 along the first direction X are appropriate, thereby ensuring the stability of the structure of the gallium nitride transistor, ensuring the effective transmission of carriers in the conductive channel of the gallium nitride transistor, and improving the performance and stability of the gallium nitride transistor.

[0062] Based on the same inventive concept, an embodiment of the present invention further provides a method for preparing a gallium nitride transistor. Figure 3 is a schematic flow chart of a method for preparing a gallium nitride transistor provided by an embodiment of the present invention, Figure 4 is a structural schematic diagram of a preparation process of a gallium nitride transistor provided by an embodiment of the present invention, combined with Figure 3 and Figure 4 As shown, the method for preparing the gallium nitride transistor includes:

[0063] S101. Provide a substrate.

[0064] Among them, substrate 1 can be specifically understood as a material that supports the device structure of the entire gallium nitride transistor. Exemplarily, substrate 1 can be a combination of one or more of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, silicon, or any other material that can grow group III nitrides.

[0065] S102 , sequentially forming a plurality of superlattice structures and a barrier layer located between two adjacent superlattice structures on one side of the substrate.

[0066] The superlattice structure includes a stacked channel layer and a barrier layer; the superlattice structure closest to the substrate is the first superlattice structure, and the other superlattice structures located on the side of the first superlattice structure away from the substrate are the second superlattice structures.

[0067] Specifically, multiple superlattice structures and a barrier layer 03 located between two adjacent superlattice structures are formed on one side of the substrate 1 by epitaxial growth technology, wherein each superlattice structure includes a stacked channel layer 01 and a barrier layer 02. For example, the channel layer 01 may be a GaN layer, the barrier layer 02 may be an AlGaN layer, and the barrier layer 03 may be a SiN layer or a SiO 2 Layer. In an optional embodiment, a GaN layer, an AlGaN layer and a SiN layer can be sequentially deposited on one side of the substrate 1 by epitaxial growth technology, so that a plurality of superlattice structures stacked and arranged and a barrier layer 03 located between two adjacent superlattice structures can be formed on one side of the substrate 1, which is equivalent to forming a plurality of conductive channels on one side of the substrate 1, thereby increasing the number of channels for carrier transmission and significantly improving the current transmission efficiency and performance of the gallium nitride transistor. It can also be understood that the formation of a barrier layer between two adjacent superlattice structures by epitaxial growth technology provides a basis for the subsequent formation of a spacing cavity between two adjacent superlattice structures, and the subsequent formation of a dielectric structure covering the surface of each superlattice structure in each spacing cavity, so as to reduce the leakage of carriers between two adjacent superlattice structures, thereby reducing energy loss and improving the efficiency and stability of gallium nitride transistors.

[0068] It can also be understood that by setting the barrier layer 03 to be a SiN layer or a SiO 2 The SiN layer or SiO2 layer provides a basis for the subsequent use of wet etching technology to remove the barrier layer between the superlattice structures. When the wet etching technology is used to selectively etch multiple superlattice structures, the SiN layer or SiO2 layer 2 The layer has a higher corrosion rate than the GaN layer and the AlGaN layer, so that the SiN layer or SiO 2 The layer can be rapidly etched while protecting the GaN layer and the AlGaN layer from wet etching, thereby helping to maintain the integrity of the GaN layer and the AlGaN layer when a spacer cavity is formed between two adjacent superlattice structures, thereby improving the performance and stability of the gallium nitride transistor.

[0069] S103 , forming a first trench and a second trench penetrating the channel layer and the barrier layer of each second superlattice structure and the barrier layer of the first superlattice structure.

[0070] The first trench 21 and the second trench 22 are located on two opposite sides of each superlattice structure.

[0071] Exemplarily, multiple superlattice structures can be patterned by photolithography, etching or laser processing to form the first trench 21 and the second trench 22 in the multiple superlattice structures. Specifically, the first trench 21 and the second trench 22 are depressions formed on both sides of the multiple superlattice structures along the first direction X, which are used to define the source region and the drain region in the gallium nitride transistor. In addition, the bottom of the first trench 21 and the second trench 22 are both the GaN layer in the first superlattice structure 201, so that the source 501 formed in the first trench 21 and the drain 503 formed in the second trench 22 can directly contact the GaN layer in the first superlattice structure 201, so that an ohmic contact with a low Schottky barrier can be formed, which helps to reduce the contact resistance and improve the electrical performance and power consumption characteristics of the gallium nitride transistor.

[0072] In an optional embodiment, the plasma etching technique is used to 2 / BCl 3 Plasma patterning of multiple superlattice structures by Cl - The ion energy cuts off the Ga-N bonds in multiple superlattice structures and removes them through a dry gas, such as nitrogen, thereby achieving precise patterning of multiple superlattice structures and reducing the preparation cost to form a first trench 21 and a second trench 22 in multiple superlattice structures, providing a basis for the subsequent formation of a source 501 in the first trench 21 and a drain 503 in the second trench 22.

[0073] S104 , forming a source electrode in contact with each superlattice structure in the first trench, and forming a drain electrode in contact with each superlattice structure in the second trench.

[0074] Exemplarily, the method of forming the source and the drain may include first forming a metal layer on the entire surface of the device, and then removing part of the metal layer through processes such as photolithography and etching, leaving the metal parts of the source and the drain; or forming the source and the drain through electron beam evaporation process, chemical vapor deposition, etc.

[0075] Specifically, the source 501 and the drain 503 are both in contact with the GaN layer at the bottom of the first trench 21 and the second trench 22. At the same time, the source 501 and the drain 503 are also in contact with multiple superlattice structures, ensuring the structural stability of the gallium nitride transistor when the barrier layer between the multiple superlattice structures is subsequently removed, and ensuring the effective transmission of carriers in the conductive channel of the gallium nitride transistor.

[0076] In an optional embodiment, a first metal structure is formed in the first trench 21 and a second metal structure is formed in the second trench 22 by an electron beam evaporation process. The metal structure formed by the electron beam evaporation process can provide good metal contact, which helps to reduce contact resistance and improve the performance and efficiency of the gallium nitride transistor. The first metal structure and the second metal structure are rapidly annealed to form a source 501 and a drain 503 in the first trench 21 and the second trench 22, respectively. The rapid annealing process can improve the bonding between the metal structure and the GaN layer at the bottom of the first trench 21 and the second trench 22, enhance the stability of the metal and the semiconductor, reduce the interface resistance, and improve the reliability of the gallium nitride transistor. The first metal structure and the second metal structure include at least one of Ni, Al, Ti and Au.

[0077] S105 , removing the barrier layers between the superlattice structures.

[0078] Exemplarily, methods for removing the barrier layer 03 between each superlattice structure may include utilizing the difference in reactivity between each superlattice structure and the barrier layer in a specific chemical solution to selectively remove the target layer; or utilizing the difference in physical properties between each superlattice structure and the barrier layer to perform selective etching; or achieving selective etching of the barrier layer by adjusting the laser energy and wavelength of laser etching.

[0079] In an optional embodiment, removing the barrier layer 03 between each superlattice structure includes: selectively etching with a hydrofluoric acid solution to remove the barrier layer 03 between each superlattice structure.

[0080] Specifically, a wet etching technique is used to selectively etch the plurality of superlattice structures. For example, the etching solution used in the wet etching technique may include HF solution, NH 4 OH solution and HF solution and NH 4 OH solution, when the etching solution is used to selectively etch multiple superlattice structures, the SiN layer or SiO 2 The layer has a higher corrosion rate than the GaN layer and the AlGaN layer, so that the SiN layer or SiO 2 The layer can be rapidly corroded, and at the same time, the GaN layer and the AlGaN layer can be protected from wet etching, thereby helping to maintain the integrity of the GaN layer and the AlGaN layer when removing the barrier layer between each superlattice structure, so as to ensure the formation of a spacing cavity between two adjacent superlattice structures, and provide a basis for the subsequent formation of a dielectric structure covering the surface of each superlattice structure in each spacing cavity, so as to reduce the leakage of carriers between two adjacent superlattice structures, thereby reducing energy loss and improving the efficiency and stability of gallium nitride transistors.

[0081] S106 , forming a dielectric structure between the source and the drain.

[0082] The dielectric structure 4 is located in each spacing cavity and covers the surface of each superlattice structure.

[0083] Specifically, the dielectric structure 4 is formed at the periphery of each second superlattice structure in the plurality of superlattice structures by atomic layer deposition technology, wherein the atomic layer deposition technology can be specifically understood as alternately depositing different atomic layers layer by layer at the periphery of each second superlattice structure to accurately form the dielectric structure 4 at the periphery of each second superlattice structure. It can be understood that the method of forming the dielectric structure can include first forming the dielectric structure on the entire device surface, and then removing the dielectric structure portion on the source and drain surfaces by processes such as photolithography and etching, leaving the dielectric structure portion located in each spacing cavity and covering the surface of each superlattice structure. It can also be understood that the dielectric structure 4 fills the spaced cavities formed after removing the barrier layer 03 between two adjacent superlattice structures, and the dielectric structure 4 covers the surface of each superlattice structure, so as to achieve the premise of ensuring good contact between any two adjacent superlattice structures, and can enhance the depletion effect of the gallium nitride transistor, effectively reduce the leakage current between the two adjacent superlattice structures, and reduce energy loss. At the same time, when the gate 502 surrounding the dielectric structure 4 is subsequently generated, the dielectric structure 4 can form electrical isolation between each superlattice structure and the gate 502, thereby avoiding current leakage and interference, and the gate 502 can more effectively control the transmission efficiency and performance of the carriers in the conductive channel of the gallium nitride transistor, thereby improving the efficiency and reliability of the gallium nitride transistor. It can also be understood that the first superlattice structure 201 is the basic structure of multiple superlattice structures, and the dielectric structure 4 is not set corresponding to the first superlattice structure 201 to ensure the structural stability and reliability of the gallium nitride transistor.

[0084] In an optional embodiment, if Figure 5 and Figure 6 As shown, a dielectric structure 4 is formed between the source and the drain, including:

[0085] S1061, forming a gate dielectric layer located between the source and the drain and covering the surfaces of each superlattice, and covering the surfaces of each superlattice in the spacing cavity, and the surfaces of the source and the drain.

[0086] Specifically, a gate dielectric layer 6 is formed around each second superlattice structure in the plurality of superlattice structures by atomic layer deposition technology, wherein the atomic layer deposition technology can be specifically understood as alternately depositing different atomic layers layer by layer around each second superlattice structure to accurately form a gate dielectric layer 6 around each second superlattice structure. The gate dielectric layer 6 fills the spacer cavity formed after removing the barrier layer 03 between two adjacent superlattice structures, and covers the surface of each superlattice structure, so as to form electrical isolation between the superlattice structure and the gate 502 formed subsequently through the gate dielectric layer 6, thereby avoiding current leakage and interference. In an optional embodiment, the gate dielectric layer 6 includes at least one of a silicon oxide layer and an aluminum oxide layer. At the same time, the width of the gate dielectric layer along the first direction X is equal to the width of the multiple superlattice structures along the first direction X, so that the gate dielectric layer 6 can contact the surface of the source 501 and the drain 503 formed in the first trench 21 and the second trench 22 on the opposite sides of the multiple superlattice structures along the first direction X, so that the gate dielectric layer 6 can also serve as an insulating layer to isolate the source 501 and the drain 502 from the multiple superlattice structures, and the gate dielectric layer can protect the gallium nitride transistor when the gate voltage increases abnormally, thereby improving the performance and stability of the gallium nitride transistor. It can also be understood that the first superlattice structure 201 is the basic structure of the multiple superlattice structures, and the gate dielectric layer is not set corresponding to the first superlattice structure 201 to ensure the structural stability and reliability of the gallium nitride transistor.

[0087] S1062, forming a conductive dielectric layer located on a side away from the superlattice structure and covering the gate dielectric layer.

[0088] Specifically, a conductive dielectric layer 7 covering the gate dielectric layer 6 is formed on the side away from the superlattice structure by atomic layer deposition technology, wherein the atomic layer deposition technology can be specifically understood as alternately depositing different atomic layers layer by layer on the gate dielectric layer 6 at the periphery of each second superlattice structure to accurately form a conductive dielectric layer 7 on the gate dielectric layer 6 at the periphery of each second superlattice structure. It can be understood that by providing a conductive dielectric layer 7 covering the gate dielectric layer 6 on the side of the gate dielectric layer 6 away from the superlattice structure, the depletion effect of the gallium nitride transistor can be enhanced while ensuring good contact between two adjacent superlattice structures, and the leakage current between the two adjacent superlattice structures can be effectively reduced. At the same time, when a gate 502 surrounding the conductive dielectric layer 7 is subsequently generated, the gate 502 can more effectively control the transmission efficiency and performance of carriers in the conductive channel of the gallium nitride transistor, thereby improving the efficiency and reliability of the gallium nitride transistor. In an optional embodiment, the conductive dielectric layer includes a TiN layer. In addition, since the gate dielectric layer 6 is disposed between the conductive dielectric layer 7 and the source 501 and the drain 503, the width of the conductive dielectric layer 7 along the first direction X is smaller than the width of the multiple superlattice structures along the first direction X, ensuring that the conductive dielectric layer 7 does not directly contact the source 501 and the drain 503 in the first trench 21 and the second trench 22 formed on opposite sides of the multiple superlattice structures along the first direction X, thereby effectively preventing the short circuit between the source and the drain. It can also be understood that the first superlattice structure 201 is a basic structure among the multiple superlattice structures, and the conductive dielectric layer is not disposed corresponding to the first superlattice structure 201 to ensure the structural stability and reliability of the gallium nitride transistor.

[0089] S107 , forming a gate located between the source and the drain and surrounding the dielectric structure.

[0090] Exemplarily, the method of forming the gate may include first forming a metal layer on the entire device surface, and then removing part of the metal layer through processes such as photolithography and etching, leaving the metal part of the gate; or forming the gate through electron beam evaporation process, chemical vapor deposition, etc.

[0091] Specifically, the gate 502 is arranged around the dielectric structure 4, wherein the dielectric structure 4 is located in each spacing cavity and covers the surface of each superlattice structure. Therefore, the gate 502 can more comprehensively cover and control each layer of the superlattice structure in the multiple superlattice structures, thereby increasing the control area of ​​the gate 502 on the channel, thereby improving the control effect of the gate 502 on the conductive channel layer of the gallium nitride transistor, enhancing the depletion effect of the gallium nitride transistor, effectively reducing the leakage current between two adjacent superlattice structures, and improving the switching speed and performance of the gallium nitride transistor.

[0092] In an optional embodiment, a third metal structure surrounding the dielectric structure is formed by an electron beam evaporation process to form a gate 502 surrounding the dielectric structure 4. The electron beam evaporation process can achieve high-precision metal deposition, ensure accurate positioning and formation of the gate 502, and improve the stability and electrical performance of the gallium nitride transistor. The third metal structure includes at least one of Ni, Al, Ti and Au.

[0093] The above-mentioned method for preparing the gallium nitride transistor can prepare the gallium nitride transistor provided by any embodiment of the present invention, and has the corresponding functions and beneficial effects of the gallium nitride transistor. For technical details not fully described in this embodiment, please refer to the gallium nitride transistor provided by any embodiment of the present invention.

[0094] Since the method for preparing the gallium nitride transistor described above can prepare the gallium nitride transistor in the embodiment of the present invention, based on the gallium nitride transistor described in the embodiment of the present invention, the skilled person in the art can understand the specific implementation of the method for preparing the gallium nitride transistor in the present embodiment and its various variations, so how the method for preparing the gallium nitride transistor can achieve the preparation of the gallium nitride transistor in the embodiment of the present invention is not described in detail here. As long as the skilled person in the art implements the method for preparing the gallium nitride transistor in the embodiment of the present invention, it falls within the scope of protection of this application.

[0095] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution disclosed in the present invention can be achieved, and this document does not limit this.

[0096] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A gallium nitride transistor, characterized in that: include: substrate; A plurality of superlattice structures are located on one side of the substrate and arranged in sequence; a spacer cavity is provided between any two adjacent superlattice structures; The superlattice structure comprises a channel layer and a barrier layer which are stacked; the superlattice structure closest to the substrate among the superlattice structures is a first superlattice structure, and the other superlattice structures located on the side of the first superlattice structure away from the substrate are all second superlattice structures; A first trench and a second trench penetrating the channel layer and the barrier layer of each of the second superlattice structures, and the barrier layer of the first superlattice structure; the first trench and the second trench are located on opposite sides of each of the superlattice structures; a source electrode located in the first trench and in contact with each of the superlattice structures, and a drain electrode located in the second trench and in contact with each of the superlattice structures; A dielectric structure located between the source and the drain, located in each of the spacing cavities, and covering a surface of each of the superlattice structures; A gate is located between the source and the drain and surrounds the dielectric structure.

2. The gallium nitride transistor according to claim 1, characterized in that: The dielectric structure at least includes a gate dielectric layer located between the source and the drain and covering each of the superlattice surfaces, and covering each of the superlattice surfaces in the spacing cavity, as well as the source and drain surfaces.

3. The gallium nitride transistor according to claim 2, characterized in that: The dielectric structure further includes a conductive dielectric layer located on a side of the gate dielectric layer away from the superlattice structure and covering the gate dielectric layer.

4. The gallium nitride transistor according to claim 2, characterized in that: The gate dielectric layer includes at least one of a silicon oxide layer and an aluminum oxide layer, and the conductive dielectric layer includes a titanium nitride layer.

5. The gallium nitride transistor according to claim 1, characterized in that: Along the arrangement direction of each of the superlattice structures, the thickness L1 of the spacing cavity between two adjacent superlattice structures is in the range of 20 nm ≤ L1 ≤ 70 nm.

6. The gallium nitride transistor according to claim 1, characterized in that the thickness L2 of the channel layer is in the range of: 15nm≤L2≤100nm; The thickness L3 of the barrier layer has a value range of 15 nm ≤ L3 ≤ 50 nm.

7. The gallium nitride transistor according to claim 1, characterized in that: Along the arrangement direction of the first groove and the second groove, the width W1 of the first groove has a value range of W1≥5 μm, and the width W2 of the second groove has a value range of W2≥5 μm.

8. A method for preparing a gallium nitride transistor, characterized in that: include: providing a substrate; A plurality of superlattice structures and a barrier layer located between two adjacent superlattice structures are sequentially formed on one side of the substrate; wherein the superlattice structure comprises a channel layer and a barrier layer which are stacked; the superlattice structure closest to the substrate among the superlattice structures is a first superlattice structure, and the other superlattice structures located on the side of the first superlattice structure away from the substrate are all second superlattice structures; Forming a first trench and a second trench penetrating the channel layer and the barrier layer of each of the second superlattice structures and the barrier layer of the first superlattice structure; wherein the first trench and the second trench are located on opposite sides of each of the superlattice structures; forming a source electrode in contact with each of the superlattice structures in the first trench, and forming a drain electrode in contact with each of the superlattice structures in the second trench; removing the barrier layer between the superlattice structures; forming a dielectric structure between the source and the drain; wherein the dielectric structure is located in each of the spacer cavities and covers the surface of each of the superlattice structures; A gate is formed between the source and the drain and surrounds the dielectric structure.

9. The method for preparing a gallium nitride transistor according to claim 8, characterized in that: Forming a dielectric structure between the source and the drain, comprising: Forming a gate dielectric layer located between the source and the drain and covering each of the superlattice surfaces, and covering each of the superlattice surfaces in the spacing cavity, and the source and drain surfaces; A conductive dielectric layer is formed which is located on a side away from the superlattice structure and covers the gate dielectric layer.

10. The method for preparing a gallium nitride transistor according to claim 8, characterized in that: Removing the barrier layer between the superlattice structures, comprising: A hydrofluoric acid solution is used for selective etching to remove the barrier layers between the superlattice structures.

Images