Embedded germanium-silicon device and manufacturing method thereof

Abstract

The invention provides an embedded germanium-silicon device and a manufacturing method thereof, and belongs to the field of semiconductors. The embedded germanium-silicon device comprises the following steps: providing a substrate, wherein the substrate is provided with a groove; cleaning the inner wall of the groove; after processing, a germanium-silicon strain layer structure and a silicon cap layer structure are sequentially formed at the bottom of the groove, the germanium-silicon strain layer structure is deposited at the bottom of the groove, and the silicon cap layer structure wraps the germanium-silicon strain layer structure. According to the invention, the silicon cap layer structure is alternately formed by respectively taking dichlorosilane and silane as silicon sources, so that the germanium-silicon strain layer structure can be completely coated, an isolation effect is achieved, and the germanium-silicon strain layer structure is prevented from being exposed. Therefore, unstable germanium-silicon alloy can be prevented from being generated in the subsequent metallization process, the contact resistance of the source / drain region is reduced, and the silicon cap layer structure is uniformly distributed. In addition, the side wall of the silicon cap layer structure can be enhanced, so that the stability of the germanium-silicon strain layer structure can be enhanced, and the performance of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an embedded germanium silicon device and a manufacturing method thereof. Background Art

[0002] With the rapid development of integrated circuit technology, device size continues to shrink, and the market has higher and higher requirements for device response speed. In order to meet such demands, embedded silicon germanium (SiGe) epitaxial technology has been introduced into the integrated circuit process to increase the mobility of holes and improve the performance of PMOS.

[0003] Sigma (∑) type e-SiGe epitaxial layer, due to silane (SiH4) as the silicon (Si) source, there is a problem that the grown Si cap layer and the bottom SiGe strain layer are not commensurate. The exposed SiGe strain layer and metal nickel (Ni) will form NiSi with poor thermal stability. 1-x Ge y Alloy, it will agglomerate at 550-600℃, making the contact resistance high and unevenly distributed.

[0004] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or suggestion in any form that the information constitutes prior art already known to those skilled in the art. Summary of the invention

[0005] The purpose of the present invention is to provide an embedded silicon germanium device and a method for manufacturing the same, so as to solve the problem that the source / drain contact resistance of the device becomes high and the Si cap layer is unevenly distributed due to the non-conformity between the Si cap layer and the bottom SiGe strain layer.

[0006] In order to solve the above technical problems, the present invention provides an embedded germanium silicon device, comprising:

[0007] A substrate, a gate structure is disposed on the substrate, and grooves are disposed on both sides of the substrate adjacent to the gate structure;

[0008] A germanium silicon epitaxial structure is arranged in the groove to form a source region and a drain region. The germanium silicon epitaxial structure includes a germanium silicon strained layer structure and a silicon cap layer structure. The germanium silicon strained layer structure is deposited at the bottom of the groove. The silicon cap layer structure covers the germanium silicon strained layer structure. The silicon cap layer structure is an alternating stack formed by heavily doped different silicon sources.

[0009] Preferably, the germanium silicon strained layer structure comprises: a low-doped low-germanium first buffer layer, a low-doped high-germanium seed layer and a low-doped low-germanium second buffer layer stacked in sequence, wherein the doping concentration range of the first buffer layer is between 5E17cm -3 ~1E18cm-3 The content of germanium is between 10% and 25%, and the concentration of seed layer doping ranges from 1E19cm -3 ~8E19cm -3 The content of germanium is between 30% and 50%, and the concentration of the second buffer layer is between 5E17cm -3 ~1E18cm -3 The germanium content is between 10% and 25%.

[0010] Preferably, the concentration of germanium in the first buffer layer and the seed crystal layer gradually increases from the substrate upward, while the concentration of germanium in the second buffer layer gradually decreases from the substrate upward, and both are distributed in a stepped manner.

[0011] Preferably, the silicon cap layer structure is heavily doped with boron, and the concentration of boron doping is between 5E20cm -3 ~6E21cm -3 between.

[0012] Preferably, the silicon source includes dichlorosilane and silane, and the silicon cap layer structure includes: an alternating stack of a cap layer formed with dichlorosilane as the silicon source and a cap layer formed with silane as the silicon source.

[0013] Based on the same inventive concept, the present invention also provides a method for manufacturing the above-mentioned embedded silicon-germanium device, comprising:

[0014] Providing a substrate having a groove;

[0015] Forming a germanium-silicon strained layer structure at the bottom of the trench, and doping in the germanium-silicon strained layer structure;

[0016] Different silicon sources are used to form alternating stacked layers on the surface of the germanium silicon strained layer structure, and the stacked layers are heavily doped to form a silicon cap layer structure.

[0017] Preferably, a germanium-silicon strained layer structure is formed at the bottom of the trench, and doping in the germanium-silicon strained layer structure includes:

[0018] A selective epitaxial growth process is performed using a precursor gas containing a doping gas, and a first buffer layer, a seed crystal layer and a second buffer layer are sequentially deposited in the groove.

[0019] Preferably, the silicon source includes dichlorosilane and silane, and different silicon sources are used on the surface of the germanium silicon strained layer structure to form an alternating stack, and the stack is heavily doped to form a silicon cap layer structure, which includes:

[0020] Dichlorosilane and silane are used alternately as silicon sources to form an alternating stack in the germanium-silicon strained layer structure, and doping gas is introduced into the silicon source to heavily dope the stack to form a silicon cap layer structure.

[0021] Preferably, the silicon cap layer structure includes boron doping, and the concentration of boron doping is between 5E20cm -3 ~6E21cm -3 between.

[0022] Preferably, the substrate is an N-type silicon substrate, and the first buffer layer, the seed layer and the second buffer layer are boron-doped.

[0023] Compared with the prior art, the method for manufacturing the embedded germanium silicon device of the present invention has the following advantages:

[0024] The present invention uses dichlorosilane and silane as silicon sources to alternately form a silicon cap layer structure, which can completely cover the germanium silicon strain layer structure and play an isolation role to prevent the germanium silicon strain layer structure from being exposed. x Ge y The alloy can avoid agglomeration, reduce the contact resistance of the source / drain region, and evenly distribute the silicon cap layer structure. In addition, the sidewall of the silicon cap layer structure can be strengthened, thereby enhancing the stability of the germanium silicon strained layer structure and improving the performance of the device.

[0025] The embedded germanium silicon device provided by the present invention and the method for manufacturing the embedded germanium silicon device provided by the present invention belong to the same inventive concept, therefore, the embedded germanium silicon device provided by the present invention has at least all the advantages of the method for manufacturing the embedded germanium silicon device provided by the present invention, which can reduce the contact resistance of the source / drain region and make the silicon cap layer structure uniformly distributed. At the same time, it can also enhance the stability of the germanium silicon strain layer structure and improve the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is an electronic scanning image of a silicon capping layer in one embodiment;

[0027] Figure 2 is an electron scanning image of a silicon capping layer in another embodiment;

[0028] Figure 3 is a flow chart of a method for manufacturing an embedded silicon-germanium device in one embodiment of the present invention;

[0029] Figure 4 is a schematic diagram of a structure in which a sigma-type trench is formed on a substrate in one embodiment of the present invention;

[0030] Figure 5 is a schematic diagram of a germanium silicon strained layer structure in one embodiment of the present invention;

[0031] Figure 6 is a schematic diagram of a silicon cap layer structure in one embodiment of the present invention;

[0032] In the figure,

[0033] 100-substrate; 200-silicon germanium strained layer structure;

[0034] 210 - first buffer layer; 220 - seed layer;

[0035] 230-second buffer layer; 300-silicon cap layer structure;

[0036] 310-first cap layer; 320-second cap layer;

[0037] 330-third cap layer; 340-fourth cap layer;

[0038] 400-gate structure; 410-gate;

[0039] 420-side wall; 500-groove. DETAILED DESCRIPTION

[0040] In order to make the purpose, advantages and features of the present invention clearer, the embedded germanium silicon device and its manufacturing method proposed by the present invention are further described in detail in combination with the drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It should be understood that the drawings in the specification do not necessarily show the specific structure of the present invention in proportion, and the illustrative features used to illustrate certain principles of the present invention in the drawings in the specification will also adopt a slightly simplified drawing method. The specific design features of the present invention disclosed herein include, for example, specific dimensions, directions, positions and shapes, which will be determined in part by the specific application and use environment. And, in the embodiments described below, sometimes the same figure mark is used in common between different drawings to represent the same part or a part with the same function, and its repeated description is omitted. In this specification, similar numbers and letters are used to represent similar items, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0041] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0042] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0043] Ginseng Figure 1 and Figure 2 As shown in the figure, the SiGe epitaxial layer structure of the PMOS device is generally composed of a buffer layer L1 with a low Ge%, a seed layer L2 with a high Ge%, a buffer layer L3 with a low Ge%, and a Si cap layer L4. Among them, the buffer layer L1, the seed layer L2, and the buffer layer L3 form a SiGe strain layer. The Si cap layer L4 can not only stabilize the SiGe strain layer below it, but also reduce the contact resistance of the device. However, if the Si cap layer L4 is not co-shaped with the SiGe strain layer below, NiSi will be formed in the later stage. 1-x Ge x The film has poor thermal stability and begins to agglomerate at 550-600°C, making it impossible to form highly uniform, low-resistance silicide, which ultimately affects device performance.

[0044] In the existing process, the Si source for growing the Si cap layer L4 is consistent with the SiGe strain layer, which is mostly SiH4 or SiH2Cl2. However, when SiH4 is used as the Si source, the grown Si cap layer L4 is not conformal to the bottom SiGe strain layer. Figure 1 The morphology shown. Figure 1 It can be seen that the sidewall of the Si cap layer L4 is relatively weak, which reduces the stability of the SiGe strain layer. Figure 2 Although the Si cap layer L4 is highly consistent with the SiGe strain layer, the Si source grows the Si cap layer at a relatively slow rate because the bond energy of the Si-Cl bond is greater than that of the Si-H bond, which will greatly extend the process time and increase the thermal budget. The Si cap layer grown by SiH4 is not conformal to the SiGe strain layer because the Si single crystal <111> The atomic density in the crystal direction is greater than <100> crystal orientation, causing the Si single crystal to <100> The growth rate in the direction is greater than <111> Growth rate in the direction.

[0045] The core idea of ​​the present invention is to provide an embedded SiGe device and a method for manufacturing the same, which can enhance the stability of the SiGe strain layer, reduce the device contact resistance, improve the performance of the device, and also reduce the heating budget.

[0046] In order to realize the above idea, the present invention provides a method for manufacturing an embedded silicon-germanium device. Figures 3 to 6 A specific implementation of an embedded germanium silicon device disclosed herein includes the following steps S1 to S4.

[0047] Step S1 : providing a substrate 100 , wherein the substrate 100 has a groove 500 .

[0048] Specifically, refer to Figure 3 and Figure 4 As shown, a substrate 100 is provided. The substrate 100 may be a silicon substrate, for example, a silicon substrate having a surface crystal orientation of <110> The substrate 100 is provided with a gate structure 400. The gate structure 400 includes a gate 410 and a sidewall 420. Grooves 500 are provided on both sides of the substrate 100 adjacent to the gate structure 400.

[0049] The groove 500 may be a sigma-shaped groove, a U-shaped groove or a groove of a similar shape. In the present embodiment, a sigma-shaped groove is used, and the steps of forming the sigma-shaped groove include: performing dry etching with the sidewall 420 and the hard mask layer (not shown) as a pattern mask to form an opening in the substrate 100; then, selectively etching the opening with the sidewall 420 and the hard mask layer as a pattern mask using wet etching so that the sidewall of the opening is recessed into the substrate 100 below the sidewall 420, thereby forming a sigma-shaped groove. Specifically, the selective etching process may be anisotropic wet etching, and the anisotropic wet etching has a faster etching rate in the direction perpendicular to the surface of the substrate 100 and parallel to the surface of the substrate 100, and a lower etching rate in the direction of etching. <111> The etching rate is slower when the crystal plane is selected, so that the opening is expanded into a sigma-type trench. For example, an alkaline etchant may be selected to perform the selective etching process, such as tetramethylammonium hydroxide (TMAH).

[0050] Step S2: The inner wall of the groove 500 is cleaned and baked in sequence.

[0051] Specifically, refer to Figure 3 and Figure 4 As shown, after the trench 500 is formed, NF3 and NH3 are used as gas sources to generate NH4F and NH4.HF plasma to pre-clean the trench 500. Subsequently, hydrogen (H2) low-temperature baking is used to remove C and O remaining on the surface of the trench 500. The temperature of the hydrogen (H2) low-temperature baking is 600-800°C.

[0052] Step S3 : after the baking process, a Germanium-SiS strained layer structure 200 is formed at the bottom of the trench 500 , and doping is performed in the Germanium-SiS strained layer structure 200 .

[0053] Specifically, refer to Figures 3 to 5 As shown, after the baking process, a SiGe strained layer structure 200 is first formed at the bottom of the trench 500 .

[0054] Forming the SiGe strained layer structure 200 in the trench 500 includes:

[0055] Using dichlorosilane (SiH2Cl2) as a silicon source, a first buffer layer 210, a seed layer 220 and a second buffer layer 230 are sequentially formed in the trench 500. The first buffer layer 210, the seed layer 220 and the second buffer layer 230 include boron doping. A selective epitaxial growth process can be performed using a precursor gas containing a doping gas, such as a chemical vapor deposition process (CVD), to perform in-situ doping while selectively epitaxially growing the first buffer layer 210, the seed layer 220 and the second buffer layer 230. For example, the doping gas can be selected as borane (BH3). In this embodiment, the average doping concentration of all doped germanium silicon layers in the buffer layer is between 1E19cm -3 ~1E20cm -3 The doping concentration of the first buffer layer 210 is in the range of 5E17cm -3 ~1E18cm -3 The content of germanium is between 10% and 25%. The thickness of the first buffer layer 210 is The doping concentration of the seed layer 220 is in the range of 1E19cm -3 ~8E19cm -3 The content of germanium is between 30% and 50%. The thickness of the seed layer 220 is The doping concentration of the second buffer layer 230 is in the range of 5E17cm -3 ~1E18cm -3 The content of germanium is between 10% and 25%. The thickness of the second buffer layer 230 is

[0056] The concentration of germanium in the first buffer layer 210 and the seed layer 220 gradually increases from the substrate 100 upward, while the concentration of germanium in the second buffer layer 230 gradually decreases from the substrate 100 upward, and both are distributed in a stepped manner. This can increase the lateral stress of the source-drain region embedded silicon-germanium epitaxial structure on the channel, which is beneficial to improving the quality of the silicon-germanium epitaxial structure.

[0057] Step S4: using different silicon sources to form alternating stacked layers on the surface of the SiGe strained layer structure 200 , and heavily doping the stacked layers to form a silicon cap layer structure 300 .

[0058] Specifically, refer to Figures 3 to 6 As shown, the silicon cap layer structure 300 is P-type doped, for example, the silicon cap layer structure 300 includes boron doping. A selective epitaxial growth process is performed using a silicon source containing a doping gas, such as a chemical vapor deposition process (CVD), and in-situ doping is performed while selectively epitaxially growing the silicon cap layer structure 300. The doping gas can be borane (BH3). Whether dichlorosilane is used as the silicon source to grow the cap layer or silane is used as the silicon source to grow the cap layer, the concentration of boron doping is between 5E20cm -3 ~6E21cm -3 The specific number of layers of the silicon cap layer structure 300 may be two layers, three layers, or more than three layers. The following explanation will be given by taking the formation of four cap layers as an example.

[0059] Forming the silicon cap layer structure 300 in the trench 500 includes:

[0060] The silicon cap layer structure 300 is deposited on the surface of the second buffer layer 230 by alternately using dichlorosilane and silane (SiH 4 ) as silicon sources.

[0061] The silicon cap layer structure 300 includes a first cap layer 310, a second cap layer 320, a third cap layer 330 and a fourth cap layer 340. The silicon cap layer structure 300 is deposited on the surface of the second buffer layer 230 alternately using dichlorosilane (SiH2Cl2) and silane (SiH4) as silicon sources. The silicon cap layer structure 300 includes:

[0062] First, dichlorosilane is used as a silicon source to deposit a first cap layer 310 on the surface of the second buffer layer 230, wherein the thickness of the first cap layer 310 is In order to perform boron doping on the first cap layer 310, borane (BH3) and dichlorosilane are introduced into a deposition apparatus together.

[0063] Next, using silane as a silicon source, a second cap layer 320 is deposited on the surface of the first cap layer 310, wherein the thickness of the second cap layer 320 is Silane and borane are introduced into the deposition equipment together, and while the second cap layer 320 is being grown, the second cap layer 320 is also doped with boron.

[0064] Then, using dichlorosilane as a silicon source, a third cap layer 330 is deposited on the surface of the second cap layer 320, wherein the thickness of the third cap layer 330 is In order to perform boron doping on the third capping layer 330 , borane (BH 3 ) and dichlorosilane are introduced into a deposition device together, and the third capping layer 330 is doped while the third capping layer 330 is grown.

[0065] Finally, using silane as a silicon source, a fourth cap layer 340 is deposited on the surface of the third cap layer 330. The thickness of the fourth cap layer 340 is Silane and borane are introduced into the deposition equipment together, and while the fourth cap layer 340 is being grown, the fourth cap layer 340 is also doped with boron.

[0066] It should be noted that the thickness of each of the first cap layer 310 , the second cap layer 320 , the third cap layer 330 and the fourth cap layer 340 can be adjusted according to actual needs.

[0067] In subsequent processes, the silicon cap layer structure 300 may form metal silicide to reduce the resistance of the resulting source / drain regions.

[0068] By using dichlorosilane and silane (SiH4) as silicon sources to alternately form the silicon cap layer structure 300, the germanium silicon strained layer structure 200 can be covered to play an isolation role and prevent the germanium silicon strained layer structure 200 from being exposed. This can prevent the metal germanium and Ni in the germanium silicon strained layer structure 200 from forming a NiSi with poor thermal stability. x Ge y The alloy can avoid agglomeration, reduce the contact resistance of the source / drain region, and be evenly distributed. At the same time, the sidewall of the silicon cap layer structure 300 can be strengthened, thereby enhancing the stability of the germanium silicon strained layer structure 200 and improving the performance of the device. In addition, the heating budget can also be reduced.

[0069] To realize the above idea, the invention also discloses an embedded SiGe device, including a substrate 100, a gate structure 400 is arranged on the substrate 100, and grooves 500 are arranged on both sides of the substrate 100 adjacent to the gate structure 400. A SiGe epitaxial structure is arranged in the groove 500 to form a source region and a drain region, and the SiGe epitaxial structure includes a SiGe strained layer structure 200 and a silicon cap layer structure 300, wherein the SiGe strained layer structure 200 is deposited on the inner wall of the groove 500, and the silicon cap layer structure 300 covers the SiGe strained layer structure 200, and the silicon cap layer structure 300 is an alternating stack formed by heavily doped different silicon sources.

[0070] The germanium silicon strained layer structure 200 comprises: a low-doped low-germanium first buffer layer 210, a low-doped high-germanium seed layer 220 and a low-doped low-germanium second buffer layer 230 stacked in sequence, wherein the doping concentration range of the first buffer layer 210 is between 5E17cm -3 ~1E18cm -3 The content of germanium is between 10% and 25%, and the doping concentration of the seed layer 220 is between 1E19cm -3 ~8E19cm -3 The content of germanium is between 30% and 50%, and the doping concentration of the second buffer layer 230 is between 5E17cm -3 ~1E18cm -3The germanium content in the first buffer layer 210 and the seed layer 220 gradually increases from the substrate 100 upward, while the germanium concentration in the second buffer layer 230 gradually decreases from the substrate 100 upward, and both are distributed in a stepped manner.

[0071] The substrate 100 is an N-type silicon substrate, and the first buffer layer 210 , the seed layer 220 and the second buffer layer 230 are doped with boron.

[0072] The silicon source includes dichlorosilane and silane, and the silicon cap layer structure 300 includes: an alternating stack of cap layers formed using dichlorosilane as the silicon source and cap layers formed using silane as the silicon source.

[0073] The embedded silicon germanium device provided in this embodiment and the method for manufacturing the embedded silicon germanium device provided in this embodiment belong to the same inventive concept, therefore, the embedded silicon germanium device provided in this embodiment has at least all the advantages of the method for manufacturing the embedded silicon germanium device provided in the present invention, which can reduce the contact resistance of the source / drain region and make the silicon cap layer structure 300 evenly distributed. At the same time, the stability of the silicon germanium strained layer structure 200 can also be enhanced to improve the performance of the device.

[0074] In summary, the above embodiments provide detailed descriptions of different configurations of embedded silicon-germanium devices and methods for manufacturing the same. Of course, the above description is only a description of a preferred embodiment of the present invention, and is not any limitation to the scope of the present invention. The present invention includes but is not limited to the configurations listed in the above embodiments. Those skilled in the art can draw inferences based on the contents of the above embodiments. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. An embedded silicon-germanium device, characterized in that: include: A substrate, a gate structure is disposed on the substrate, and grooves are disposed on both sides of the substrate adjacent to the gate structure; A germanium silicon epitaxial structure is arranged in the groove to form a source region and a drain region. The germanium silicon epitaxial structure includes a germanium silicon strained layer structure and a silicon cap layer structure. The germanium silicon strained layer structure is deposited at the bottom of the groove. The silicon cap layer structure covers the germanium silicon strained layer structure. The silicon cap layer structure is an alternating stack formed by heavily doped different silicon sources.

2. The embedded silicon germanium device according to claim 1, characterized in that: The germanium silicon strained layer structure comprises: a low-doped low-germanium first buffer layer, a low-doped high-germanium seed crystal layer and a low-doped low-germanium second buffer layer stacked in sequence, wherein the doping concentration range of the first buffer layer is between 5E17cm -3 ~1E18cm -3 The content of germanium is between 10% and 25%, and the concentration of seed layer doping ranges from 1E19cm -3 ~8E19cm -3 The content of germanium is between 30% and 50%, and the concentration of the second buffer layer is between 5E17cm -3 ~1E18cm -3 The germanium content is between 10% and 25%.

3. The embedded silicon germanium device according to claim 2, characterized in that: The concentration of germanium in the first buffer layer and the seed crystal layer gradually increases from the substrate upward, while the concentration of germanium in the second buffer layer gradually decreases from the substrate upward, and both are distributed in a step-like manner.

4. The embedded silicon germanium device according to claim 2, characterized in that: The silicon cap layer structure is heavily doped including boron doping, and the concentration of boron doping is between 5E20cm -3 ~6E21cm -3 between.

5. The embedded silicon germanium device according to claim 4, characterized in that: The silicon source includes dichlorosilane and silane, and the silicon cap layer structure includes: an alternating stack of cap layers formed by using dichlorosilane as the silicon source and cap layers formed by using silane as the silicon source.

6. A method for manufacturing an embedded silicon-germanium device according to any one of claims 1 to 5, characterized in that: include: Providing a substrate having a groove; Forming a germanium-silicon strained layer structure at the bottom of the trench, and doping in the germanium-silicon strained layer structure; Different silicon sources are used to form alternating stacked layers on the surface of the germanium silicon strained layer structure, and the stacked layers are heavily doped to form a silicon cap layer structure.

7. The method for manufacturing an embedded silicon-germanium device according to claim 6, characterized in that: Forming a germanium-silicon strained layer structure at the bottom of the trench, and doping the germanium-silicon strained layer structure comprises: A selective epitaxial growth process is performed using a precursor gas containing a doping gas, and a first buffer layer, a seed crystal layer and a second buffer layer are sequentially deposited in the groove.

8. The method for manufacturing an embedded silicon-germanium device according to claim 6, characterized in that: The silicon source includes dichlorosilane and silane, and different silicon sources are used on the surface of the germanium silicon strained layer structure to form an alternating stack, and the stack is heavily doped to form a silicon cap layer structure, which includes: Dichlorosilane and silane are used alternately as silicon sources to form an alternating stack in the germanium-silicon strained layer structure, and doping gas is introduced into the silicon source to heavily dope the stack to form a silicon cap layer structure.

9. The method for manufacturing an embedded silicon-germanium device according to claim 8, characterized in that: The silicon cap layer structure includes boron doping, and the concentration of boron doping is between 5E20cm -3 ~6E21cm -3 between.

10. The method for manufacturing an embedded silicon-germanium device according to claim 7, characterized in that: The substrate is an N-type silicon substrate, and the first buffer layer, the seed crystal layer and the second buffer layer are doped with boron.

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