Semiconductor device and manufacturing method thereof, power module, power conversion circuit, and vehicle

Abstract

The embodiment of the invention discloses a semiconductor device, a manufacturing method, a power module, a power conversion circuit and a vehicle. The semiconductor device comprises a semiconductor body, and the semiconductor body comprises a first surface, a second surface, a well region and a first region; the first surface is provided with a gate trench and a source trench; the first insulating layer is located on the bottom surface and the side wall of the gate trench; the trench gate is located on the side, away from the semiconductor body, of the first insulating layer in the gate trench; the source trench structure comprises a filling layer located in the source trench; the barrier layer is located on the side, away from the semiconductor body, of the filling layer and located in the source trench; the ohmic contact metal layer is located on the first surface and provided with an opening; the source electrode is located on one side, away from the first surface, of the ohmic contact metal layer and contacts the barrier layer through the opening; the drain is located on the second surface. According to the technical scheme of the embodiment of the invention, the surface of the source trench can be flat, no abnormal morphology such as holes or grooves exists, and the reliability of the semiconductor device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] Wide bandgap semiconductor materials such as silicon carbide (SiC) are widely used in the automotive, aerospace and power electronics fields due to their excellent high-temperature performance, chemical stability and electronic properties.

[0003] The trench-type silicon carbide metal oxide semiconductor field effect transistor (MOSFET) in the prior art has the advantages of high current density and small cell pitch. However, the high electric field at the bottom and corner of the trench leads to a high electric field on the gate oxide layer, which is easy to break down. In order to protect the gate oxide layer, a double-trench SiC MOSFET device is set up, and silicon dioxide is used to cover the gate trench, leaking part of the SiC and source trench. An insulating layer and doped polysilicon are provided in the source trench. In order to make the source metal form a good ohmic contact with SiC, it is generally necessary to prepare a layer of metal on the surface of SiC, and then perform high-temperature treatment to form an alloy between the metal and SiC.

[0004] However, since doped polysilicon has a greater reactivity, the doped polysilicon in the source trench reacts violently with the metal during high-temperature processing, consuming the doped polysilicon in the source trench, thereby causing the surface of the source trench to be uneven, forming abnormal morphologies such as holes or grooves, and reducing the reliability of the semiconductor device. Summary of the invention

[0005] The present invention provides a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle, so as to solve the problem that the reliability of the semiconductor device is reduced due to abnormal morphology on the surface of a source trench.

[0006] According to one aspect of the present invention, a semiconductor device is provided, the semiconductor device comprising: a semiconductor body, comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprising a well region and a first region, the first region being set to a first conductivity type and being located on the first surface, and the well region being set to a second conductivity type and being located on a side of the first region away from the first surface; a gate trench being arranged on the first surface, the gate trench extending from the first surface into the semiconductor body; a source trench being arranged on the first surface, the source trench extending from the first surface into the semiconductor body; the semiconductor body further comprising a first insulating layer, the first insulating layer being located on the bottom surface and sidewalls of the gate trench;

[0007] A trench gate is located in the gate trench on a side of the first insulating layer away from the semiconductor body; the first insulating layer is used to insulate the semiconductor body and the trench gate;

[0008] A source trench structure, comprising a filling layer, wherein the filling layer is located in the source trench;

[0009] A barrier layer, located on a side of the filling layer away from the semiconductor body and in the source trench;

[0010] An ohmic contact metal layer is located on the first surface, and the ohmic contact metal layer is provided with an opening;

[0011] A source electrode is located at a side of the ohmic contact metal layer away from the first surface and contacts the barrier layer through the opening;

[0012] The drain is located on the second surface.

[0013] Optionally, the semiconductor body further includes a second region; the second region is set to the second conductivity type and is located at the bottom and sidewalls of the source trench.

[0014] Optionally, the source trench structure further includes a second insulating layer, and the second insulating layer is located on the bottom surface and side walls of the source trench.

[0015] Optionally, the thickness of the barrier layer is greater than or equal to 50 nm and less than or equal to 200 nm.

[0016] Optionally, the filling layer includes polysilicon, and the barrier layer includes silicon dioxide.

[0017] According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, the method comprising:

[0018] A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprises a well region and a first region, the first region is set to a first conductivity type and is located on the first surface, and the well region is set to a second conductivity type and is located on a side of the first region away from the first surface; a gate trench is provided on the first surface, and the gate trench extends from the first surface into the semiconductor body; a source trench is also provided on the first surface, and the source trench extends from the first surface into the semiconductor body; the semiconductor body further comprises a first insulating layer, and the first insulating layer is located on the bottom surface and sidewalls of the gate trench;

[0019] A trench gate is formed on a side of the first insulating layer away from the semiconductor body in the gate trench; the first insulating layer is used to insulate the semiconductor body and the trench gate;

[0020] forming a source trench structure including a filling layer in the source trench;

[0021] forming a barrier layer on a side of the filling layer away from the semiconductor body in the source trench;

[0022] An ohmic contact metal layer is formed on the first surface; the ohmic contact metal layer is provided with an opening;

[0023] A source electrode is formed on a side of the ohmic contact metal layer away from the first surface; the source electrode contacts the barrier layer through the opening;

[0024] A drain electrode is formed on the second surface.

[0025] Optionally, providing a semiconductor body includes:

[0026] Providing a semiconductor body, the semiconductor body comprising a first surface and a second surface arranged opposite to each other;

[0027] A transition well region and a transition area are formed on the first surface; the transition area is set to be of the first conductivity type and is located on the first surface; the transition well region is set to be of the second conductivity type and is located on a side of the transition area away from the first surface;

[0028] forming a gate trench on the first surface, the gate trench extending from the first surface into the semiconductor body;

[0029] forming a source trench on the first surface, the source trench extending from the first surface into the semiconductor body;

[0030] A second region is formed at the bottom and sidewall of the source trench; the second region is set to a second conductivity type; a transition region retained after forming the gate trench, the source trench, and the second region is used as a first region; a transition well region retained after forming the gate trench, the source trench, and the second region is used as a well region;

[0031] A first insulating layer is formed on the bottom surface and sidewalls of the gate trench.

[0032] Optionally, the filling layer includes polysilicon, the barrier layer includes silicon dioxide, and the barrier layer is formed on a side of the filling layer away from the semiconductor body in the source trench, including:

[0033] A side of a portion of the filling layer in the source trench away from the semiconductor body is converted into a blocking layer through a thermal oxidation process.

[0034] Optionally, forming an ohmic contact metal layer on the first surface includes:

[0035] A contact hole is formed by etching on the first surface, and a metal is deposited in the contact hole to form an ohmic contact metal layer; and an unreacted ohmic contact metal layer on a side of the barrier layer away from the filling layer is removed by a wet process to form an opening.

[0036] According to another aspect of the present invention, a power module is provided. The power module includes a substrate and at least one semiconductor device as described above. The substrate is used for carrying the semiconductor device.

[0037] According to another aspect of the present invention, there is provided a power conversion circuit, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0038] The power conversion circuit comprises a circuit board and at least one of the semiconductor devices mentioned above, and the semiconductor device is electrically connected to the circuit board.

[0039] According to another aspect of the present invention, a vehicle is provided, which includes a load and the above-mentioned power conversion circuit, the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0040] The technical solution of the embodiment of the present invention provides a double-trench silicon carbide MOSFET device, and an interlayer insulating layer is set to cover the trench gate to achieve insulation isolation between the trench gate and the source. A barrier layer is set, which can be formed by converting the side of the filling layer away from the semiconductor body through a thermal oxidation process. Since the thermal oxidation rate of the filling layer is higher than that of silicon carbide, a thicker barrier layer will be generated on the surface of the filling layer when the thermal oxidation temperature is lower than 1000°C. The ohmic contact metal layer is located on the first surface, and is formed by depositing an ohmic contact metal on the first surface, and then subjected to high-temperature treatment to react the ohmic contact metal with silicon carbide to form an alloy. Since the barrier layer has a low reaction activity, the formed barrier layer does not react with the ohmic contact metal layer. The barrier layer is used to block the diffusion of the ohmic contact metal, and the ohmic contact metal is prevented from reacting with the filling layer, so that the surface of the source trench is flat, without abnormal morphology such as holes or grooves, thereby improving the reliability of the semiconductor device.

[0041] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0043] Figure 1 is a schematic structural diagram of a semiconductor device provided according to an embodiment of the present invention;

[0044] Figure 2 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0045] Figure 3-Figure 7 is a cross-sectional view corresponding to each step of a method for manufacturing a semiconductor device provided according to an embodiment of the present invention;

[0046] Figure 8 According to an embodiment of the present invention, Figure 2 A schematic diagram of the process included in S110;

[0047] Figure 9-13 According to an embodiment of the present invention, Figure 2 The cross-sectional view corresponding to each step included in S110. DETAILED DESCRIPTION

[0048] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0049] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0050] In order to improve the reliability of semiconductor devices, the embodiments of the present invention provide the following technical solutions:

[0051] Figure 1 is a schematic diagram of the structure of a semiconductor device provided according to an embodiment of the present invention, such as Figure 1As shown, the semiconductor device includes: a semiconductor body 100, including a first surface 101 and a second surface 102 arranged opposite to each other; the semiconductor body 100 also includes a well region 103 and a first region 104, the first region 104 is set to a first conductivity type and is located on the first surface 101, and the well region 103 is set to a second conductivity type and is located on a side of the first region 104 away from the first surface 101; the first surface 101 is provided with a gate trench 105, and the gate trench 105 extends from the first surface 101 to the semiconductor body 100; the first surface 101 is also provided with a source trench 106, and the source trench 106 extends from the first surface 101 to the semiconductor body 100; the semiconductor body 100 also includes a first insulating layer 107, and the first insulating layer 107 is located at the gate The bottom surface and side wall of the gate trench 105; the trench gate 200, which is located in the gate trench 105 on the side of the first insulating layer 107 away from the semiconductor body 100; the first insulating layer 107 is used to insulate the semiconductor body 100 and the trench gate 200; the source trench structure 300, including a filling layer 301, the filling layer 301 is located in the source trench 106; the barrier layer 302, which is located on the side of the filling layer 301 away from the semiconductor body 100 and is located in the source trench 106; the ohmic contact metal layer 30, which is located on the first surface 101, and the ohmic contact metal layer 30 is provided with an opening 40; the source 400, which is located on the side of the ohmic contact metal layer 30 away from the first surface 101, and contacts with the barrier layer 302 through the opening 40; the drain 500, which is located on the second surface 102.

[0052] like Figure 1 As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. Among them, the epitaxial layer 20 is a semiconductor layer formed by a single epitaxial process on the basis of the substrate 10, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD) and atomic layer epitaxy (ALE) and other processes.

[0053] In the embodiment of the present invention, the semiconductor device includes but is not limited to an N-type MOSFET or a P-type MOSFET. The semiconductor body 100 may include a third-generation wide bandgap semiconductor material such as a silicon carbide semiconductor body, and the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device. The silicon carbide MOSFET semiconductor device has the advantages of high withstand voltage, low on-resistance and high frequency, which can further improve the performance of the semiconductor device.

[0054] For an N-type MOSFET, the first conductivity type is N-type and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type and the second conductivity type is N-type. Exemplarily, for an N-type MOSFET, the first region 104 is an N+ doping region, and the N-type doping ions in the N+ doping region may be phosphorus (P) ions or nitrogen (N) ions; the well region 103 is a P-well region, and the P-type doping ions in the P-well region may be aluminum (Al) ions or boron (B) ions. The first region 104 may be formed on the first surface 101 of the semiconductor body 100 by processes such as ion implantation, ion diffusion, or vapor deposition.

[0055] The first surface 101 of the semiconductor body 100 is provided with a gate trench 105 and a source trench 106, and the semiconductor device of the embodiment of the present invention is a double-trench silicon carbide MOSFET device. The gate trench 105 and the source trench 106 can be formed by photolithography and etching processes. If the trench depths of the gate trench 105 and the source trench 106 are the same, they can be formed by a one-step photolithography and etching process; if the trench depths of the gate trench 105 and the source trench 106 are different, two steps of photolithography and etching are required. Exemplarily, the gate trench 105 is etched first, and then the source trench 106 is etched; or, the source trench 106 is etched first, and then the gate trench 105 is etched. It should be noted that when the trench depths of the gate trench 105 and the source trench 106 are different, the order of etching the gate trench 105 and the source trench 106 is not specifically limited.

[0056] The semiconductor body 100 also includes a first insulating layer 107. The first insulating layer 107 can be formed by a thermal oxidation process. The thermal oxidation process is a process that achieves a specific processing effect through heating and oxidation reaction. Exemplarily, in an embodiment of the present invention, a dense silicon dioxide film is generated on the surface of the silicon wafer by chemically reacting silicon and a gas containing an oxidizing substance, such as water vapor and oxygen, at a high temperature, thereby forming the first insulating layer 107. The first insulating layer 107 can be a gate oxide layer. The first insulating layer 107 is located on the bottom surface and sidewalls of the gate trench 105, and the first insulating layer 107 on the bottom surface of the gate trench 105 is thicker, and the first insulating layer 107 on the sidewalls of the gate trench 105 is thinner. In a semiconductor device, when the device is in a reverse bias or other working state, the electric field strength at the bottom of the gate trench 105 is relatively high. Arranging a thicker first insulating layer 107 at the bottom of the gate trench 105 can increase the attenuation length of the electric field in the first insulating layer 107, thereby effectively reducing the electric field strength at the bottom of the gate trench 105, reducing the electric field concentration phenomenon, reducing the risk of the first insulating layer 107 being broken down, and improving the withstand voltage and reliability of the semiconductor device. The first insulating layer 107 on the side wall of the gate trench 105 is relatively thin, which can reduce the influence of parasitic capacitance and improve the high-frequency performance of the semiconductor device. Polysilicon is deposited on the side of the first insulating layer 107 in the gate trench 105 away from the semiconductor body 100 to form a trench gate 200. The first insulating layer 107 is used to insulate the semiconductor body 100 and the trench gate 200.

[0057] The source trench structure 300 includes a filling layer 301. The filling layer 301 can be formed by depositing doped polysilicon in the source trench 106. The semiconductor device also includes an interlayer insulating layer 304, and the material of the interlayer insulating layer 304 can be silicon dioxide. The interlayer insulating layer 304 covers the trench gate 200, and leaks a portion of the first region 104 and the filling layer 301 in the source trench 106. The interlayer insulating layer 304 is used to insulate and isolate the trench gate 200 and the source 400.

[0058] The barrier layer 302 can be formed by thermal oxidation from the side of the filling layer 301 away from the semiconductor body 100. In an optional embodiment of the present invention, the thickness of the barrier layer 302 is greater than or equal to 50nm and less than or equal to 200nm. The key to forming the barrier layer 302 of this thickness is to control the temperature of thermal oxidation between 500℃-1000℃. In an optional embodiment of the present invention, reference Figure 1The filling layer 301 includes polysilicon, and the barrier layer 302 includes silicon dioxide. Since the thermal oxidation rate of polysilicon is higher than that of silicon carbide, a thicker silicon dioxide will be generated on the surface of polysilicon when the thermal oxidation temperature is lower than 1000°C, and only a small amount of silicon dioxide will be generated on the surface of silicon carbide. Then, a small amount of silicon dioxide on the surface of silicon carbide is removed by using a hydrofluoric acid solution, so that the barrier layer 302 can be formed on the side of the filling layer 301 away from the semiconductor body 100.

[0059] The ohmic contact metal layer 30 is located on the first surface 101 and is formed by depositing an ohmic contact metal on the first surface 101, for example, depositing a metal such as titanium (Ti), nickel (Ni), aluminum (Al) or tungsten (W) on the first surface 101. Then, a high temperature treatment (temperature between 400°C and 900°C) is performed to react the ohmic contact metal with silicon carbide to form an alloy. Since silicon dioxide has a low reactivity, the formed barrier layer 302 does not react with the ohmic contact metal layer 30. The barrier layer 302 is used to block the diffusion of the ohmic contact metal and prevent the ohmic contact metal from reacting with the filling layer 301, so that the surface of the source trench 106 is flat, without abnormal morphology such as holes or grooves, thereby improving the reliability of the semiconductor device. Exemplarily, the unreacted ohmic contact metal layer 30 is removed by a wet process, and an opening 40 is formed in the ohmic contact metal layer 30. A high temperature annealing process is then used to produce a more stable alloy phase in the formed alloy layer.

[0060] The source electrode 400 may be formed by depositing metal on the first surface 101. The drain electrode 500 may be formed by depositing metal on the second surface 102. The deposited metal includes, but is not limited to, aluminum or titanium.

[0061] The technical solution of the embodiment of the present invention provides a double-trench silicon carbide MOSFET device, and an interlayer insulating layer 304 is provided to cover the trench gate 200 to achieve insulation isolation between the trench gate 200 and the source 400. A barrier layer 302 is provided, which can be formed by a thermal oxidation process by converting the side of the filling layer 301 away from the semiconductor body 100. Since the thermal oxidation rate of the filling layer 301 is higher than that of silicon carbide, a thicker barrier layer 302 will be generated on the surface of the filling layer 301 when the thermal oxidation temperature is lower than 1000°C. The ohmic contact metal layer 30 is located on the first surface 101, and is formed by depositing an ohmic contact metal on the first surface 101, and then performing a high-temperature treatment to react the ohmic contact metal with silicon carbide to form an alloy. Since the barrier layer 302 has a low reaction activity, the formed barrier layer 302 does not react with the ohmic contact metal layer 30. The barrier layer 302 is used to block the diffusion of the ohmic contact metal and prevent the ohmic contact metal from reacting with the filling layer 301, so that the surface of the source trench 106 is flat without abnormal morphology such as holes or grooves, thereby improving the reliability of the semiconductor device.

[0062] In an optional embodiment of the present invention, reference Figure 1The semiconductor body 100 further includes a second region 108 ; the second region 108 is configured as a second conductivity type and is located at the bottom and sidewalls of the source trench 106 .

[0063] In the embodiment of the present invention, for an N-type MOSFET, P+ ion implantation is performed at the bottom and sidewalls of the source trench 106 to form a second region 108. The second region 108 is a P+ doped region, and its doping concentration is greater than the doping concentration of the well region 103. The first region 104 and the second region 108 can form a good ohmic contact with the source 400.

[0064] In an optional embodiment of the present invention, reference Figure 1 The source trench structure 300 further includes a second insulating layer 303 , and the second insulating layer 303 is located on the bottom surface and sidewalls of the source trench 106 .

[0065] In the embodiment of the present invention, the second insulating layer 303 can be formed by a thermal oxidation process. The second insulating layer 303 can be an oxide layer. The second insulating layer 303 is located on the bottom surface and sidewalls of the source trench 106, and the second insulating layer 303 on the bottom surface of the source trench 106 is thicker, and the second insulating layer 303 on the sidewalls of the source trench 106 is thinner. Doped polysilicon is deposited on the side of the second insulating layer 303 in the source trench 106 away from the semiconductor body 100 to form a filling layer 301. The filling layer 301 and the second insulating layer 303 together constitute the source trench structure 300.

[0066] refer to Figure 1 , the semiconductor device also includes a passivation layer 600 and a polyimide layer 700. The passivation layer 600 is arranged on the side of the source 400 away from the semiconductor body 100. The material of the passivation layer 600 can be silicon nitride. The passivation layer 600 is used to prevent the semiconductor device from being corroded, oxidized or affected by other external factors, thereby improving the corrosion resistance and stability of the semiconductor device. The polyimide layer 700 covers the passivation layer 600. The polyimide layer 700 can be a film or coating made of a polyimide material. The polyimide layer 700 has high temperature resistance, radiation resistance, electrical insulation performance and good mechanical properties. The provision of the polyimide layer 700 can improve the performance of the semiconductor device.

[0067] Figure 2 FIG. 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 2 As shown, the method for manufacturing the semiconductor device includes:

[0068] S110. Provide a semiconductor body, the semiconductor body comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprising a well region and a first region, the first region being set to a first conductivity type and being located on the first surface, the well region being set to a second conductivity type and being located on a side of the first region away from the first surface; a gate trench being arranged on the first surface, the gate trench extending from the first surface into the semiconductor body; a source trench being arranged on the first surface, the source trench extending from the first surface into the semiconductor body; the semiconductor body further comprising a first insulating layer, the first insulating layer being located on the bottom surface and sidewalls of the gate trench.

[0069] refer to Figure 3 The semiconductor body 100 includes a first surface 101 and a second surface 102 that are arranged opposite to each other; the semiconductor body 100 also includes a well region 103 and a first region 104, the first region 104 is set to the first conductivity type and is located on the first surface 101, and the well region 103 is set to the second conductivity type and is located on the side of the first region 104 away from the first surface 101; the first surface 101 is provided with a gate trench 105, and the gate trench 105 extends from the first surface 101 to the semiconductor body 100; the first surface 101 is also provided with a source trench 106, and the source trench 106 extends from the first surface 101 to the semiconductor body 100; the semiconductor body 100 also includes a first insulating layer 107, and the first insulating layer 107 is located on the bottom surface and sidewall of the gate trench 105.

[0070] Among them, a gate trench 105 and a source trench 106 are formed on the first surface 101 by photolithography and etching processes. For an N-type MOSFET, the first conductivity type is N-type and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type and the second conductivity type is N-type. Exemplarily, for an N-type MOSFET, the first region 104 is an N+ doping region, and the N-type doping ions in the N+ doping region may be phosphorus (P) ions or nitrogen (N) ions; the well region 103 is a P-well region, and the P-type doping ions in the P-well region may be aluminum (Al) ions or boron (B) ions. The first region 104 may be formed on the first surface 101 of the semiconductor body 100 by processes such as ion implantation, ion diffusion or vapor deposition. The semiconductor body 100 also includes a first insulating layer 107. The first insulating layer 107 may be formed by a thermal oxidation process. The first insulating layer 107 may be a gate oxide layer. The first insulating layer 107 is located on the bottom surface and sidewalls of the gate trench 105 , and the first insulating layer 107 on the bottom surface of the gate trench 105 is thicker, and the first insulating layer 107 on the sidewalls of the gate trench 105 is thinner.

[0071] like Figure 3As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. Among them, the epitaxial layer 20 is a semiconductor layer formed by a single epitaxial process on the basis of the substrate 10, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD) and atomic layer epitaxy (ALE) and other processes.

[0072] Optional, reference Figure 3 The semiconductor body 100 further includes a second region 108 ; the second region 108 is configured as a second conductivity type and is located at the bottom and sidewalls of the source trench 106 .

[0073] S120, forming a trench gate on a side of the first insulating layer away from the semiconductor body in the gate trench; the first insulating layer is used to insulate the semiconductor body and the trench gate.

[0074] refer to Figure 4 Polysilicon is deposited on the side of the first insulating layer 107 in the gate trench 105 away from the semiconductor body 100 to form a trench gate 200. The first insulating layer 107 is used to insulate the semiconductor body 100 from the trench gate 200.

[0075] S130 , forming a source trench structure including a filling layer in the source trench.

[0076] refer to Figure 5 , a source trench structure 300 including a filling layer 301 is formed in the source trench 106 ; the filling layer 201 can be formed by depositing doped polysilicon in the source trench 106 .

[0077] Optionally, a second insulating layer 303 is formed on the bottom surface and sidewall of the source trench 106 by thermal oxidation, and doped polysilicon is deposited on the side of the second insulating layer 303 away from the semiconductor body 100 in the source trench 106 to form a filling layer 301. The filling layer 301 and the second insulating layer 303 together constitute the source trench structure 300.

[0078] S140, forming a blocking layer on a side of the filling layer in the source trench away from the semiconductor body.

[0079] In an optional embodiment of the present invention, reference Figure 6 The filling layer 301 includes polysilicon, the barrier layer 302 includes silicon dioxide, and the barrier layer 302 is formed on the side of the filling layer 301 in the source trench 106 away from the semiconductor body 100, including: converting a part of the filling layer 301 in the source trench 106 away from the semiconductor body 100 into the barrier layer 302 through a thermal oxidation process.

[0080] Specifically, refer to Figure 6 , an interlayer insulating layer 304 is formed on the first surface 101, and the material of the interlayer insulating layer 304 can be silicon dioxide. The interlayer insulating layer 304 covers the trench gate 200 and is used to insulate and isolate the trench gate 200 and the source 400. A barrier layer 302 is formed on the side of the filling layer 301 away from the semiconductor body 100 in the source trench 106. The barrier layer 302 can be formed by converting the side of the filling layer 301 away from the semiconductor body 100 through a thermal oxidation process. In an optional embodiment of the present invention, the thickness of the formed barrier layer 302 is greater than or equal to 50nm and less than or equal to 200nm. The key to forming a barrier layer 302 of this thickness is to control the temperature of thermal oxidation between 500℃-1000℃. In an optional embodiment of the present invention, since the thermal oxidation rate of polysilicon is higher than that of silicon carbide, a thicker silicon dioxide will be generated on the surface of polysilicon when the thermal oxidation temperature is lower than 1000°C, and only a small amount of silicon dioxide will be generated on the surface of silicon carbide. The small amount of silicon dioxide on the surface of silicon carbide is then removed using a hydrofluoric acid solution, thereby forming a barrier layer 302 on the side of the filling layer 301 away from the semiconductor body 100.

[0081] S150, forming an ohmic contact metal layer on the first surface; the ohmic contact metal layer is provided with an opening.

[0082] refer to Figure 7 , an ohmic contact metal layer 30 is formed on the first surface 101; the ohmic contact metal layer 30 is provided with an opening 40. Specifically, the ohmic contact metal layer 30 is formed by depositing an ohmic contact metal on the first surface 101, for example, a metal such as titanium (Ti), nickel (Ni), aluminum (Al) or tungsten (W) is deposited on the first surface 101 to form the ohmic contact metal layer 30. Then a high temperature treatment (temperature between 400°C-900°C) is performed to react the ohmic contact metal with silicon carbide to form an alloy. Since silicon dioxide has a low reactivity, the formed barrier layer 302 does not react with the ohmic contact metal layer 30. The barrier layer 302 is used to block the diffusion of the ohmic contact metal, and to prevent the ohmic contact metal from reacting with the filling layer 301, so that the surface of the source trench 106 is flat, without abnormal morphology such as holes or grooves, and the reliability of the semiconductor device is improved. Exemplarily, the unreacted ohmic contact metal layer 30 is removed by a wet process, and an opening 40 is formed in the ohmic contact metal layer 30. A high temperature annealing process is then used to make the formed alloy layer produce a more stable alloy phase.

[0083] S160, forming a source electrode on a side of the ohmic contact metal layer away from the first surface; the source electrode contacts the barrier layer through the opening.

[0084] refer to Figure 1, a source electrode 400 is formed by depositing metal on a side of the ohmic contact metal layer 30 away from the first surface 101 ; the source electrode 400 contacts the barrier layer 302 through the opening 40 .

[0085] S170, forming a drain on the second surface.

[0086] refer to Figure 1 , metal is deposited on one side of the second surface 102 of the semiconductor body 100 to form a drain 500 .

[0087] The technical solution of the embodiment of the present invention is to set a method for manufacturing a semiconductor device to form a double-trench silicon carbide MOSFET device. An interlayer insulating layer 304 is set to cover the trench gate 200 to achieve insulation isolation between the trench gate 200 and the source 400. The barrier layer 302 can be formed by a thermal oxidation process from the side of the filling layer 301 away from the semiconductor body 100. Since the thermal oxidation rate of the filling layer 301 is higher than that of silicon carbide, a thicker barrier layer 302 will be generated on the surface of the filling layer 301 when the thermal oxidation temperature is lower than 1000°C. An ohmic contact metal layer 30 is formed by depositing an ohmic contact metal on the first surface 101, and then performing a high-temperature treatment to react the ohmic contact metal with silicon carbide to form an alloy. Since the barrier layer 302 has a low reaction activity, the formed barrier layer 302 does not react with the ohmic contact metal layer 30. The barrier layer 302 is used to block the diffusion of the ohmic contact metal and prevent the ohmic contact metal from reacting with the filling layer 301, so that the surface of the source trench 106 is flat without abnormal morphology such as holes or grooves, thereby improving the reliability of the formed semiconductor device.

[0088] In an optional embodiment of the present invention, Figure 8 According to an embodiment of the present invention, Figure 2 The flow chart of S110 is shown in FIG. Figure 8 As shown, S110 provides a semiconductor body including:

[0089] S1101 . Provide a semiconductor body, wherein the semiconductor body includes a first surface and a second surface that are oppositely disposed.

[0090] refer to Fig. 9 , the semiconductor body 100 includes a first surface 101 and a second surface 102 arranged opposite to each other. The semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. Among them, the epitaxial layer 20 is a semiconductor layer formed by a single epitaxial process on the basis of the substrate 10, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD) and atomic layer epitaxy (ALE) and other processes.

[0091] S1102, forming a transition well region and a transition area on the first surface; the transition area is set to the first conductivity type and is located on the first surface; the transition well region is set to the second conductivity type and is located on a side of the transition area away from the first surface.

[0092] refer to Fig.10 , a transition well region 50 and a transition region 60 are formed on the first surface 101; the transition region 60 is set to the first conductivity type and is located on the first surface 101; the transition well region 50 is set to the second conductivity type and is located on the side of the transition region 60 away from the first surface 101. The transition region 60 can be formed on the first surface 101 of the semiconductor body 100 by ion implantation, ion diffusion or vapor deposition. The transition well region 50 can be formed on the side of the transition region 60 away from the first surface 101 by ion implantation, ion diffusion or vapor deposition. Exemplarily, for an N-type MOSFET, the transition well region 50 is a P-well region, and the transition region 60 is an N+ doped region.

[0093] S1103 , forming a gate trench on the first surface, wherein the gate trench extends from the first surface into the semiconductor body.

[0094] refer to Fig.11 Through photolithography and etching processes, a gate trench 105 is formed on the first surface 101 , and the gate trench 105 extends from the first surface 101 into the semiconductor body 100 .

[0095] S1104 , forming a source trench on the first surface, wherein the source trench extends from the first surface into the semiconductor body.

[0096] refer to Fig.11 Through photolithography and etching processes, a source trench 106 is formed on the first surface 101 , and the source trench 106 extends from the first surface 101 into the semiconductor body 100 .

[0097] S1105. Form a second region at the bottom and sidewall of the source trench; set the second region to a second conductivity type; form the gate trench, the source trench, and the transition region retained after the second region is formed as the first region; and form the gate trench, the source trench, and the transition well region retained after the second region is formed as the well region.

[0098] refer to Fig.12 A second region 108 is formed at the bottom and sidewalls of the source trench 106 by P+ ion implantation; the second region 108 is set to a second conductivity type; the transition region 60 retained after the gate trench 105, the source trench 106 and the second region 108 are formed is used as the first region 104; the transition well region 50 retained after the gate trench 105, the source trench 106 and the second region 108 are formed is used as the well region 103.

[0099] S1106 , forming a first insulating layer on the bottom surface and sidewalls of the gate trench.

[0100] refer to Fig.13 A first insulating layer 107 is formed on the bottom surface and sidewall of the gate trench 105 by a thermal oxidation process. The first insulating layer 107 may be a gate oxide layer. The first insulating layer 107 on the bottom surface of the gate trench 105 is relatively thick, and the first insulating layer 107 on the sidewall of the gate trench 105 is relatively thin.

[0101] In an optional embodiment of the present invention, S150, forming an ohmic contact metal layer on the first surface, includes: etching to form a contact hole on the first surface, depositing metal in the contact hole to form an ohmic contact metal layer; removing the unreacted ohmic contact metal layer on the side of the barrier layer away from the filling layer by a wet process to form an opening.

[0102] Specifically, refer to Fig.13 When forming the first insulating layer 107, there will also be deposited silicon dioxide on the surface of the silicon carbide. After forming the source trench structure 300, the first surface 101 is etched back to form a Figure 5 The structure shown; reference Figure 6 After the first surface 101 is completely etched back, an interlayer insulating layer 304 is deposited, and then a contact hole CT is formed on the first surface 101 by photolithography and etching processes, and a side of the filling layer 301 away from the semiconductor body 100 is converted into a blocking layer 302 by a thermal oxidation process; Figure 7 , an ohmic contact metal layer 30 is formed in the contact hole CT by depositing an ohmic contact metal.

[0103] Since silicon dioxide has a low reactivity, the formed barrier layer 302 does not react with the ohmic contact metal layer 30. The barrier layer 302 is used to block the diffusion of the ohmic contact metal and prevent the ohmic contact metal from reacting with the filling layer 301, so that the surface of the source trench 106 is flat and has no abnormal morphology such as holes or grooves, thereby improving the reliability of the semiconductor device. The unreacted ohmic contact metal layer 30 is removed by a wet process, and an opening 40 is formed in the ohmic contact metal layer 30.

[0104] An embodiment of the present invention provides a power module, comprising a substrate and at least one semiconductor device according to any embodiment of the present invention, wherein the substrate is used to carry the semiconductor device. Therefore, the beneficial effects of the power module including any semiconductor device according to any embodiment of the present invention are not described in detail here.

[0105] An embodiment of the present invention provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device described in any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0106] Therefore, the power conversion circuit includes the beneficial effects of any semiconductor device described in any embodiment of the present invention, which will not be repeated here.

[0107] An embodiment of the present invention also provides a vehicle, which includes a load and the above-mentioned power conversion circuit, the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0108] Therefore, the beneficial effects of the power conversion circuit described in any embodiment of the present invention included in the vehicle will not be repeated here.

[0109] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0110] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body, comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprising a well region and a first region, the first region being set to a first conductivity type and being located on the first surface, the well region being set to a second conductivity type and being located on a side of the first region away from the first surface; a gate trench being arranged on the first surface, the gate trench extending from the first surface into the semiconductor body; a source trench being arranged on the first surface, the source trench extending from the first surface into the semiconductor body; the semiconductor body further comprising a first insulating layer, the first insulating layer being located on the bottom surface and sidewalls of the gate trench; A trench gate is located in the gate trench on a side of the first insulating layer away from the semiconductor body; The first insulating layer is used to insulate the semiconductor body and the trench gate; A source trench structure, comprising a filling layer, wherein the filling layer is located in the source trench; A barrier layer, located on a side of the filling layer away from the semiconductor body and in the source trench; An ohmic contact metal layer, located on the first surface, and the ohmic contact metal layer is provided with an opening; A source electrode, located at a side of the ohmic contact metal layer away from the first surface, and in contact with the barrier layer through the opening; The drain is located on the second surface.

2. The semiconductor device according to claim 1, wherein: The semiconductor body further includes a second region; the second region is set to a second conductivity type and is located at the bottom and sidewalls of the source trench.

3. The semiconductor device according to claim 1, wherein: The source trench structure further includes a second insulating layer, and the second insulating layer is located on the bottom surface and sidewalls of the source trench.

4. The semiconductor device according to claim 1, wherein: The thickness of the barrier layer is greater than or equal to 50 nm and less than or equal to 200 nm.

5. The semiconductor device according to claim 1, wherein: The filling layer includes polysilicon, and the barrier layer includes silicon dioxide.

6. A method for manufacturing a semiconductor device, characterized in that: include: A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprising a well region and a first region, the first region being set to a first conductivity type and being located on the first surface, the well region being set to a second conductivity type and being located on a side of the first region away from the first surface; a gate trench is provided on the first surface, the gate trench extends from the first surface into the semiconductor body; a source trench is also provided on the first surface, the source trench extends from the first surface into the semiconductor body; the semiconductor body further comprises a first insulating layer, the first insulating layer being located on the bottom surface and sidewalls of the gate trench; Forming a trench gate on a side of the first insulating layer away from the semiconductor body in the gate trench; The first insulating layer is used to insulate the semiconductor body and the trench gate; forming a source trench structure including a filling layer in the source trench; forming a blocking layer in the source trench on a side of the filling layer away from the semiconductor body; An ohmic contact metal layer is formed on the first surface; the ohmic contact metal layer is provided with an opening; forming a source electrode on a side of the ohmic contact metal layer away from the first surface; The source electrode contacts the barrier layer through the opening; A drain electrode is formed on the second surface.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The semiconductor body provided includes: Providing a semiconductor body, the semiconductor body comprising a first surface and a second surface arranged opposite to each other; A transition well region and a transition area are formed on the first surface; the transition area is set to a first conductivity type and is located on the first surface; the transition well region is set to a second conductivity type and is located on a side of the transition area away from the first surface; forming a gate trench on the first surface, wherein the gate trench extends from the first surface into the semiconductor body; forming a source trench on the first surface, wherein the source trench extends from the first surface into the semiconductor body; A second region is formed at the bottom and sidewall of the source trench; the second region is set to a second conductivity type; the transition region retained after forming the gate trench, the source trench and the second region is used as a first region; the transition well region retained after forming the gate trench, the source trench and the second region is used as a well region; A first insulating layer is formed on the bottom surface and sidewalls of the gate trench.

8. The method for manufacturing a semiconductor device according to claim 6, wherein: The filling layer includes polysilicon, the barrier layer includes silicon dioxide, and a barrier layer is formed on a side of the filling layer away from the semiconductor body in the source trench, including: A portion of the filling layer in the source trench that is away from the semiconductor body is converted into a blocking layer through a thermal oxidation process.

9. The method for manufacturing a semiconductor device according to claim 6, wherein: Forming an ohmic contact metal layer on the first surface includes: A contact hole is formed by etching on the first surface, and a metal is deposited in the contact hole to form an ohmic contact metal layer; and unreacted ohmic contact metal layer on a side of the barrier layer away from the filling layer is removed by a wet process to form an opening.

10. A power module, characterized in that: It comprises a substrate and the semiconductor device according to any one of claims 1 to 5, wherein the substrate is used to carry the semiconductor device.

11. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one semiconductor device according to any one of claims 1 to 5, wherein the semiconductor device is electrically connected to the circuit board.

12. A vehicle, characterized in that: It includes a load and a power conversion circuit as claimed in claim 11, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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