Semiconductor device and preparation method thereof, power module, power conversion circuit and vehicle

Abstract

The invention discloses a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. The semiconductor device comprises a semiconductor body; the semiconductor body further comprises a well region, a first region, a first insulating layer and a second insulating layer, the first region is arranged on the first surface, the well region is arranged on the side, away from the first surface, of the first region, and the first insulating layer is arranged on the side, away from the first surface, of the well region; the first surface is provided with a gate trench; the grid electrode is positioned in the grid electrode groove; the interlayer dielectric layer is located on one side, far away from the semiconductor body, of the gate, and the vertical projection of the interlayer dielectric layer on the first surface covers the vertical projection of the gate on the first surface; the source electrode is positioned on the first surface; and a drain electrode located on the second surface. The voltage endurance capability of the semiconductor device can be effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] Trench-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET) semiconductor devices have advantages such as high current density and small cell size. However, the high electric field at the bottom and corner of the gate trench leads to a high electric field on the gate oxide layer, which in turn makes the gate oxide layer very easy to break down.

[0003] In order to better protect the gate oxide layer, one solution is that the trench MOSFET semiconductor device adopts a double trench structure, that is, constructs a double source trench on both sides of the gate trench to shield the electric field at the bottom of the gate trench, but the double trench structure requires additional source trenches to be made, and the process is complicated. Another solution is that the trench MOSFET semiconductor device adopts an asymmetric gate trench structure, and the electric field at the bottom of the gate trench is weakened by embedding a P++ doped region or an N++ doped region at the bottom of the gate trench, but the asymmetric structure sacrifices half of the conductive trench, thereby reducing the on-state current. Summary of the invention

[0004] The present invention provides a semiconductor device and a preparation method, a power module, a power conversion circuit and a vehicle, so as to solve the problem that the high electric field at the bottom and corner of the gate trench leads to a very high electric field on the gate oxide layer, thereby causing the gate oxide layer to be extremely easy to break down, when the trench MOSFET semiconductor device does not adopt a double trench structure and an asymmetric structure.

[0005] In a first aspect, the present invention provides a semiconductor device, the semiconductor device comprising:

[0006] A semiconductor body of a first conductivity type is provided; the semiconductor body comprises a first surface and a second surface arranged opposite to each other, the semiconductor body further comprises a well region of a second conductivity type, a first region of a first conductivity type, a first insulating layer and a second insulating layer, the first region being provided on the first surface, the well region being provided on a side of the first region away from the first surface, and the first insulating layer being provided on a side of the well region away from the first surface; a gate trench is provided on the first surface, the gate trench extends from the first surface into the semiconductor body, and the bottom of the gate trench contacts the first insulating layer; a vertical projection of the gate trench on the first surface is within a vertical projection of the first insulating layer on the first surface; and the second insulating layer is provided on a sidewall of the gate trench;

[0007] A gate located in the gate trench and on a side of the second insulating layer away from the semiconductor body;

[0008] An interlayer dielectric layer located on a side of the gate away from the semiconductor body, wherein a vertical projection of the interlayer dielectric layer on the first surface covers a vertical projection of the gate on the first surface;

[0009] a source electrode located on the first surface;

[0010] A drain is located on the second surface.

[0011] Optionally, the semiconductor body further comprises a third insulating layer;

[0012] The third insulating layer is disposed on a side of the first insulating layer away from the first surface, the third insulating layer is connected to the first insulating layer, and a vertical projection of the third insulating layer on the first surface is within a vertical projection of the first insulating layer on the first surface.

[0013] Optionally, the thickness of the first insulating layer is smaller than the thickness of the third insulating layer.

[0014] Optionally, the first insulating layer includes a silicon dioxide insulating layer, and the third insulating layer includes a silicon dioxide insulating layer.

[0015] Optionally, the source is located on the first surface of the semiconductor body, the source is connected to the first region, and a vertical projection of the source on the first surface covers a vertical projection of the interlayer dielectric layer on the first surface.

[0016] Optionally, a source trench is provided on the first surface, and the source trench extends from the first surface into the semiconductor body; the semiconductor body further comprises a fourth insulating layer, and the fourth insulating layer is located on the bottom surface and sidewalls of the source trench;

[0017] The source is located on the first surface of the semiconductor body, the source is connected to the first region, and a vertical projection of the source on the first surface covers a vertical projection of the interlayer dielectric layer on the first surface.

[0018] In a second aspect, the present invention provides a method for preparing a semiconductor device, the method comprising:

[0019] A semiconductor body of a first conductivity type is provided; the semiconductor body comprises a first surface and a second surface arranged opposite to each other, the semiconductor body further comprises a well region arranged as a second conductivity type, a first region arranged as a first conductivity type, a first insulating layer and a second insulating layer, the first region being arranged on the first surface, the well region being arranged on a side of the first region away from the first surface, and the first insulating layer being arranged on a side of the well region away from the first surface; a gate trench is arranged on the first surface, the gate trench extends from the first surface into the semiconductor body, and the bottom of the gate trench contacts the first insulating layer; a vertical projection of the gate trench on the first surface is within a vertical projection of the first insulating layer on the first surface; and the second insulating layer is arranged on a sidewall of the gate trench;

[0020] forming a gate in the gate trench and on a side of the second insulating layer away from the semiconductor body;

[0021] An interlayer dielectric layer is formed on a side of the gate away from the semiconductor body; a vertical projection of the interlayer dielectric layer on the first surface covers a vertical projection of the gate on the first surface;

[0022] forming a source electrode on the first surface;

[0023] A drain electrode is formed on the second surface.

[0024] Optionally, providing a semiconductor body of a first conductivity type further includes:

[0025] A third insulating layer is formed on a side of the first insulating layer away from the first surface. The third insulating layer is connected to the first insulating layer, and a vertical projection of the third insulating layer on the first surface is within a vertical projection of the first insulating layer on the first surface.

[0026] Optionally, a semiconductor body of a first conductivity type is provided, comprising:

[0027] providing a substrate;

[0028] forming an epitaxial layer on one side of the substrate;

[0029] forming a first mask layer on a side of the epitaxial layer away from the substrate, wherein the first mask layer is provided with a first mask trench;

[0030] forming a first insulating layer in the epitaxial layer; a vertical projection of the first mask trench on the substrate coincides with a vertical projection of the first insulating layer on the substrate;

[0031] removing the first mask layer;

[0032] forming a second mask layer on a side of the epitaxial layer away from the substrate, wherein the second mask layer is provided with a second mask trench;

[0033] forming a third insulating layer on a side of the first insulating layer close to the substrate; a vertical projection of the second mask trench on the substrate coincides with a vertical projection of the third insulating layer on the substrate;

[0034] removing the second mask layer;

[0035] continuing to epitaxially grow the epitaxial layer on a side of the epitaxial layer away from the substrate;

[0036] forming a well region and a first region on a side of the epitaxial layer away from the substrate;

[0037] forming a gate trench on the first surface, wherein the gate trench extends from the first surface into the semiconductor body, and a bottom of the gate trench contacts the first insulating layer;

[0038] A second insulating layer is formed on the sidewalls of the gate trench.

[0039] Optionally, forming a first insulating layer in the epitaxial layer, removing the first mask layer, forming a second mask layer on a side of the epitaxial layer away from the substrate, forming a third insulating layer on a side of the first insulating layer close to the substrate, and removing the second mask layer includes:

[0040] implanting oxygen ions into the epitaxial layer to form a first oxygen ion region, wherein a vertical projection of the first oxygen ion region on the substrate coincides with a vertical projection of the first mask trench on the substrate;

[0041] removing the first mask layer;

[0042] forming a second mask layer on a side of the epitaxial layer away from the substrate, wherein the second mask layer is provided with a second mask trench;

[0043] implanting oxygen ions into a side of the first oxygen ion region close to the substrate to form a second oxygen ion region, wherein a vertical projection of the second oxygen ion region on the substrate coincides with a vertical projection of the second mask trench on the substrate;

[0044] removing the second mask layer;

[0045] The epitaxial layer is thermally oxidized to thermally oxidize the first oxygen ion region into a first insulating layer and the second oxygen ion region into a third insulating layer.

[0046] Optionally, forming a second insulating layer on the sidewall of the gate trench includes:

[0047] forming a second insulating layer on the first surface and the sidewalls of the gate trench;

[0048] An interlayer dielectric layer is formed on a side of the gate away from the semiconductor body, comprising:

[0049] An interlayer dielectric layer is formed on a side of the gate away from the semiconductor body and a side of the second insulating layer on the first surface away from the first surface;

[0050] A portion of the interlayer dielectric layer on the first surface and a portion of the second insulating layer on the first surface are removed, and a vertical projection of the interlayer dielectric layer on the first surface covers a vertical projection of the gate on the first surface.

[0051] Optionally, the semiconductor body further includes a fourth insulating layer; providing a semiconductor body of the first conductivity type and forming a source electrode on the first surface, comprising:

[0052] Forming a source trench on the first surface; the source trench extends from the first surface into the semiconductor body;

[0053] forming a fourth insulating layer at the bottom and sidewalls of the source trench;

[0054] A source electrode is formed on the first surface, the source electrode is connected to the first region, and a vertical projection of the source electrode on the first surface covers a vertical projection of the interlayer dielectric layer on the first surface.

[0055] In a third aspect, the present invention provides a power module, which includes a substrate and at least one semiconductor device provided in the first aspect, wherein the substrate is used to carry the semiconductor device.

[0056] In a fourth aspect, the present invention provides a power conversion circuit, wherein the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction;

[0057] The power conversion circuit includes a circuit board and at least one semiconductor device as provided in the first aspect above, and the semiconductor device is electrically connected to the circuit board.

[0058] In a fifth aspect, the present invention provides a vehicle, comprising a load and a power conversion circuit as provided in the fourth aspect above, the power conversion circuit being used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0059] The technical solution of the embodiment of the present invention is to set a first insulating layer in the epitaxial layer below the bottom of the gate trench or in the semiconductor layer formed by other processes. The first insulating layer can effectively improve the withstand voltage of the semiconductor device, and solve the problem that the high electric field at the bottom of the gate trench and the groove corner of the trench MOSFET semiconductor device leads to a high electric field on the second insulating layer, which in turn leads to the second insulating layer being extremely easy to break down. The semiconductor device provided by the technical solution of the embodiment of the present invention may include a single trench MOSFET semiconductor device, that is, the source structure is a planar source structure, and there is no need to set a source trench. By setting the first insulating layer, the withstand voltage of the semiconductor device can be effectively improved, and the preparation process of the semiconductor device is effectively simplified. And there is no need to adopt an asymmetric gate trench structure, which effectively avoids the problem that the asymmetric structure sacrifices half of the conductive trench, thereby reducing the on-state current. The technical solution of the embodiment of the present invention effectively solves the problem that the strong electric field at the bottom of the gate trench and the groove corner leads to a high electric field on the gate oxide layer, which in turn leads to the gate oxide layer being extremely easy to break down, and effectively improves the reliability of the semiconductor device.

[0060] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0062] Figure 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0063] Figure 2 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0064] Figure 3 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0065] Figure 4 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0066] Figure 5-Figure 10 It is a structural diagram corresponding to each step in a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0067] Fig.11is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0068] Figure 12-Figure 21 It is a structural diagram corresponding to some steps in another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0069] Fig. 22 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0070] Figure 23-Figure 27 It is a structural diagram corresponding to some steps in another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0071] Fig.28 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0072] Figure 29-Figure 31 It is a structural diagram corresponding to some steps in another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0073] Fig.32 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0074] Figure 33-Figure 35 It is a structural diagram corresponding to some steps in another method for preparing a semiconductor device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0075] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0076] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0077] In order to solve the problem that the high electric field at the bottom and the corner of the gate trench of the trench MOSFET semiconductor device causes a high electric field on the gate oxide layer, which in turn causes the gate oxide layer to be easily broken down, and improve the reliability of the trench MOSFET semiconductor device, the embodiment of the present invention provides the following technical solutions:

[0078] Figure 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention, Figure 2 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention, Figure 3 is a schematic diagram of the structure of another semiconductor device provided by an embodiment of the present invention, such as Figure 1-Figure 3 As shown, the semiconductor device includes: a semiconductor body 1 set to a first conductivity type; the semiconductor body 1 includes a first surface 101 and a second surface 102 arranged oppositely, the semiconductor body 1 also includes a well region 14 set to a second conductivity type, a first region 13 set to a first conductivity type, a first insulating layer 16 and a second insulating layer 18, the first region 13 is arranged on the first surface 101, the well region 14 is arranged on a side of the first region 13 away from the first surface 101, and the first insulating layer 16 is arranged on a side of the well region 14 away from the first surface 101. The first surface 101 is provided with a gate trench, the gate trench extends from the first surface 101 to the semiconductor body 1, and the bottom of the gate trench contacts the first insulating layer 16. The vertical projection of the gate trench on the first surface 101 is within the vertical projection of the first insulating layer 16 on the first surface 101; the second insulating layer 18 is arranged on the sidewall of the gate trench. The gate 2 is located in the gate trench and on the side of the second insulating layer 18 away from the semiconductor body 1. An interlayer dielectric layer 3 is located on the side of the gate 2 away from the semiconductor body 1, and the vertical projection of the interlayer dielectric layer 3 on the first surface 101 covers the vertical projection of the gate 2 on the first surface 101. A source 4 is located on the first surface 101. A drain 5 is located on the second surface 102.

[0079] A semiconductor device according to an embodiment of the present invention comprises Figure 1 The single trench MOSFET semiconductor device shown and Figure 2 and Figure 3 A double trench MOSFET semiconductor device is shown.

[0080] Alternatively, if Figure 1-Figure 3 As shown, the semiconductor body 1 may further include a second region 15 . The doping concentration of the second region 15 is greater than the doping concentration of the well region 14 , and a good ohmic contact may be formed with the source 4 .

[0081] It should be noted that the MOSFET semiconductor device may include an N-channel MOSFET semiconductor device or a P-channel MOSFET semiconductor device. Exemplarily, for an N-channel MOSFET semiconductor device, the first conductivity type is N-type, and the second conductivity type is P-type. The semiconductor body 1 is an N-type semiconductor body, the well region 14 is a P-type well region, the first region 13 is an N++ doped region, and the second region 15 is a P++ doped region. For a P-channel MOSFET semiconductor device, the first conductivity type is P-type, and the second conductivity type is N-type. The semiconductor body 1 is a P-type semiconductor body, the well region 14 is an N-type well region, the first region 13 is a P++ doped region, and the second region 15 is an N++ doped region.

[0082] For example, Figure 1-Figure 3 As shown, the semiconductor body 1 may also include a substrate 11 and an epitaxial layer 12. For an N-channel MOSFET semiconductor device, the substrate 11 includes an N+ substrate, and the epitaxial layer 12 includes an N-epitaxial layer. For a P-channel MOSFET semiconductor device, the substrate 11 includes a P+ substrate, and the epitaxial layer 12 includes a P-epitaxial layer. In some embodiments of the present invention, the semiconductor body 1 may also include only the epitaxial layer 12. In other embodiments of the present invention, the semiconductor body 1 may also include a substrate 11 and a semiconductor layer formed by other processes. Among them, the epitaxial layer 12 is a semiconductor layer formed by a single epitaxial process on the basis of the substrate 11, and the epitaxial process includes processes such as chemical vapor epitaxy (CVE), molecular beam epitaxy (MBE), and atomic layer epitaxy (ALE).

[0083] like Figure 1-Figure 3 As shown, a first insulating layer 16 may be provided in the epitaxial layer 12. When the semiconductor body 1 includes a substrate 11 and a semiconductor layer formed by other processes, the first insulating layer 16 may also be provided in the semiconductor layer formed by other processes. The first insulating layer 16 is provided below the bottom of the gate trench. The gate trench extends from the first surface 101 to the epitaxial layer 12 of the semiconductor body 1, and the bottom of the gate trench contacts the first insulating layer 16. The width of the first insulating layer 16 near the gate trench is relatively wide. The first insulating layer 16 can effectively improve the withstand voltage capability of the semiconductor device, and solve the problem that the high electric field at the bottom and the groove corner of the gate trench of the trench MOSFET semiconductor device leads to a high electric field on the second insulating layer 18, which in turn leads to the second insulating layer 18 being easily broken down. The vertical projection of the first insulating layer 16 on the first surface 101 covers the vertical projection of the gate groove on the first surface 101. This arrangement can further ensure that the first insulating layer 16 can effectively improve the voltage resistance of the semiconductor device, solve the problem that the high electric field at the bottom and groove corner of the gate trench of the trench MOSFET semiconductor device leads to a very high electric field on the second insulating layer 18, which in turn causes the second insulating layer 18 to be extremely easy to break down, and effectively improve the reliability of the semiconductor device.

[0084] The semiconductor body 1 may further include a second insulating layer 18, the second insulating layer 18 is located on the sidewall of the gate trench, and the gate 2 is located on the side of the second insulating layer 18 away from the semiconductor body 1. The gate 2 may contact the first insulating layer 16 through the bottom of the gate trench. The second insulating layer 18 is a gate oxide layer. The second insulating layer 18 may be located on the sidewall of the gate trench, or may be located on the sidewall of the gate trench and extend to the first surface 101, and the vertical projection of the second insulating layer 18 on the first surface 101 may coincide with the vertical projection of the interlayer dielectric layer 3 on the first surface 101. The gate 2 is located in the gate trench and on the side of the second insulating layer 18 away from the semiconductor body 1, and the gate 2 may contact the first insulating layer 16 through the bottom of the gate trench.

[0085] The technical solution of the embodiment of the present invention is to set a first insulating layer 16 in the epitaxial layer 12 below the bottom of the gate trench or in the semiconductor layer formed by other processes. The first insulating layer 16 can effectively improve the withstand voltage of the semiconductor device, and solve the problem that the high electric field at the bottom and groove corner of the gate trench of the trench MOSFET semiconductor device leads to a high electric field on the second insulating layer 18, which in turn leads to the second insulating layer 18 being extremely easy to break down. The semiconductor device provided by the technical solution of the embodiment of the present invention may include a single trench MOSFET semiconductor device, that is, the source structure is a planar source structure, and there is no need to set a source trench. By setting the first insulating layer 16, the withstand voltage of the semiconductor device can be effectively improved, and the preparation process of the semiconductor device is effectively simplified. And there is no need to adopt an asymmetric gate trench structure, which effectively avoids the problem that the asymmetric structure sacrifices half of the conductive trench, thereby reducing the on-state current. The technical solution of the embodiment of the present invention effectively solves the problem that the strong electric field at the bottom and groove corner of the gate trench leads to a high electric field on the gate oxide layer, which in turn leads to the gate oxide layer being extremely easy to break down, and effectively improves the reliability of the semiconductor device.

[0086] Optionally, based on the above embodiments, continue to refer to Figure 1-Figure 3 For the single trench MOSFET semiconductor device and the double trench MOSFET semiconductor device, the semiconductor body 1 further includes a third insulating layer 17. The third insulating layer 17 is disposed on a side of the first insulating layer 16 away from the first surface 101, the third insulating layer 17 is connected to the first insulating layer 16, and a vertical projection of the third insulating layer 17 on the first surface 101 is within a vertical projection of the first insulating layer 16 on the first surface 101.

[0087] Specifically, a third insulating layer 17 may be further provided in the epitaxial layer 12. When the semiconductor body 1 includes a substrate 11 and a semiconductor layer formed by other processes, the third insulating layer 17 may also be provided in the semiconductor layer formed by other processes. The third insulating layer 17 is provided on the side of the first insulating layer 16 away from the first surface 101, and the combined shape of the first insulating layer 16 and the third insulating layer 17 may be an inverted convex shape. The width of the third insulating layer 17 away from the gate trench is narrower than the width of the first insulating layer 16. The third insulating layer 17 may also effectively improve the withstand voltage capability of the semiconductor device, further solving the problem that the high electric field at the bottom and groove corner of the gate trench of the trench MOSFET semiconductor device causes a high electric field on the second insulating layer 18, thereby causing the second insulating layer 18 to be easily broken down. The narrow width of the third insulating layer 17 may also effectively ensure the current channel.

[0088] Optionally, based on the above embodiments, continue to refer to Figure 1-Figure 3 For the single trench MOSFET semiconductor device and the double trench MOSFET semiconductor device, the thickness of the first insulating layer 16 is less than the thickness of the third insulating layer 17 .

[0089] Specifically, the thickness range of the first insulating layer 16 can be set to 0-0.3um, and the thickness range of the third insulating layer 17 can be set to 0-0.7um. The thickness of the first insulating layer 16 and the third insulating layer 17 can be arbitrarily set according to specific needs, so as to effectively improve the voltage resistance of the semiconductor device and ensure the reliable operation of the semiconductor device. In some embodiments of the present invention, the semiconductor body 1 may only include the first insulating layer 16. In other embodiments of the present invention, the semiconductor body 1 may also only include the third insulating layer 17. When the semiconductor body 1 only includes the third insulating layer 17, the third insulating layer 17 may be set below the bottom of the gate trench, so that the bottom of the gate trench can contact the third insulating layer 17.

[0090] Optionally, based on the above embodiments, continue to refer to Figure 1-Figure 3 For the single trench MOSFET semiconductor device and the double trench MOSFET semiconductor device, the first insulating layer 16 includes a silicon dioxide insulating layer, and the third insulating layer 17 includes a silicon dioxide insulating layer.

[0091] Specifically, the materials of the first insulating layer 16 and the third insulating layer 17 can both be silicon dioxide, and the combined shape of the two silicon dioxide insulating layers can be an inverted convex shape. The width of the silicon dioxide insulating layer close to the gate groove is relatively wide, which can effectively improve the withstand voltage of the semiconductor device and solve the problem that the high electric field at the bottom and groove corner of the gate groove of the trench MOSFET semiconductor device causes the electric field on the second insulating layer 18 to be very high, thereby causing the second insulating layer 18 to be extremely easy to break down. The width of the silicon dioxide insulating layer far away from the gate groove is relatively narrower than the width of the silicon dioxide insulating layer close to the gate groove. The silicon dioxide insulating layer far away from the gate groove can also effectively improve the withstand voltage of the semiconductor device, further solving the problem that the high electric field at the bottom and groove corner of the gate groove of the trench MOSFET semiconductor device causes the electric field on the second insulating layer 18 to be very high, thereby causing the second insulating layer 18 to be extremely easy to break down. The width of the third insulating layer 17 is relatively narrow, and it can also effectively ensure the current channel.

[0092] Optionally, based on the above embodiments, continue to refer to Figure 1 For a single trench MOSFET semiconductor device, the source 4 is located on the first surface 101 of the semiconductor body 1 , the source 4 is connected to the first region 13 , and the vertical projection of the source 4 on the first surface 101 covers the vertical projection of the interlayer dielectric layer 3 on the first surface 101 .

[0093] Specifically, the semiconductor body 1 of the single trench MOSFET semiconductor device does not need to be provided with a source trench, and the source 4 is located on the first surface 101 of the semiconductor body 1. The source 4 can be a metal electrode, and the source 4 is electrically connected to the first region 13. The manufacturing process of the single trench MOSFET semiconductor device is simple, which can effectively simplify the manufacturing process of the MOSFET semiconductor device, thereby effectively reducing the time cost.

[0094] Optionally, based on the above embodiments, continue to refer to Figure 2-Figure 3 For a double trench MOSFET semiconductor device, a source trench 10 is provided on the first surface 101, and the source trench 10 extends from the first surface 101 into the semiconductor body 1. The semiconductor body 1 further includes a fourth insulating layer 19, and the fourth insulating layer 19 is located on the bottom surface and sidewalls of the source trench 10. The source 4 is located on the first surface 101 of the semiconductor body 1, the source 4 is connected to the first region 13, and the vertical projection of the source 4 on the first surface 101 covers the vertical projection of the interlayer dielectric layer 3 on the first surface 101.

[0095] Specifically, for a double trench MOSFET semiconductor device, a source trench 10 needs to be provided on the first surface 101 of the semiconductor body 1, and the source trench 10 can be located inside the second region 15. A fourth insulating layer 19 is provided on the bottom and sidewalls of the source trench 10. Figure 2As shown, the source trench 10 may not be filled with a source trench structure. Figure 3 As shown, the source trench can be filled with a source trench structure 6, and the material of the source trench structure 6 can be metal or polysilicon, etc. The setting of the source trench can further effectively alleviate the problem that the electric field at the bottom and corner of the gate trench is strong, resulting in a high electric field on the second insulating layer 18, which in turn causes the second insulating layer 18 to be easily broken down, and further improve the reliability of the semiconductor device.

[0096] Figure 4 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention, Figure 5-Figure 10 is a structural diagram corresponding to each step in a method for preparing a semiconductor device provided by an embodiment of the present invention, such as Figure 4 As shown, the preparation method comprises:

[0097] S100: Provide a semiconductor body of the first conductive type; the semiconductor body includes a first surface and a second surface arranged opposite to each other, the semiconductor body also includes a well region set to the second conductive type, a first region set to the first conductive type, a first insulating layer and a second insulating layer, the first region is arranged on the first surface, the well region is arranged on a side of the first region away from the first surface, and the first insulating layer is arranged on a side of the well region away from the first surface; a gate trench is arranged on the first surface, the gate trench extends from the first surface to the semiconductor body, and the bottom of the gate trench contacts the first insulating layer; the vertical projection of the gate trench on the first surface is within the vertical projection of the first insulating layer on the first surface; the second insulating layer is arranged on the sidewall of the gate trench.

[0098] Specifically, Figure 5 As shown, a semiconductor body 1 is first provided. The semiconductor body 1 may further include a substrate 11 and an epitaxial layer 12. In some embodiments of the present invention, the semiconductor body 1 may also include only the epitaxial layer 12. In other embodiments of the present invention, the semiconductor body 1 may further include a substrate 11 and a semiconductor layer formed by other processes. Among them, the epitaxial layer 12 is a semiconductor layer formed by a single epitaxial process on the basis of the substrate 11. The epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBE), and atomic layer epitaxy (ALE) and other processes.

[0099] The semiconductor body 1 may further include a well region 14, a first region 13, and a second region 15. The well region 14, the first region 13, and the second region 15 are formed on the side of the epitaxial layer 12 away from the substrate 11 by doping and other processes, and then the doped impurities are activated by an annealing process. A gate trench 20 is formed on the first surface 101 by processes such as photolithography and etching, and the gate trench 20 can penetrate the well region 14 and the first region 13 and extend into the epitaxial layer 12.

[0100] The MOSFET semiconductor device may include an N-channel MOSFET semiconductor device or a P-channel MOSFET semiconductor device. Exemplarily, for an N-channel MOSFET semiconductor device, the first conductivity type is N-type, and the second conductivity type is P-type. The semiconductor body 1 is an N-type semiconductor body, the well region 14 is a P-type well region, the first region 13 is an N++ doped region, the second region 15 is a P++ doped region, the substrate 11 includes an N+ substrate, and the epitaxial layer 12 includes an N-epitaxial layer. For a P-channel MOSFET semiconductor device, the first conductivity type is P-type, and the second conductivity type is N-type. The semiconductor body 1 is a P-type semiconductor body, the well region 14 is an N-type well region, the first region 13 is a P++ doped region, the second region 15 is an N++ doped region, the substrate 11 includes a P+ substrate, and the epitaxial layer 12 includes a P-epitaxial layer.

[0101] A first insulating layer 16 may be provided in the epitaxial layer 12. When the semiconductor body 1 includes a substrate 11 and a semiconductor layer formed by other processes, the first insulating layer 16 may also be provided in the semiconductor layer formed by other processes. The first insulating layer 16 is provided below the bottom of the gate trench 20. The gate trench 20 extends from the first surface 101 to the epitaxial layer 12 of the semiconductor body 1. The bottom of the gate trench 20 contacts the first insulating layer 16. The width of the first insulating layer 16 near the gate trench 20 is relatively wide. The first insulating layer 16 can effectively improve the withstand voltage capability of the semiconductor device, and solve the problem that the high electric field at the bottom and groove corner of the gate trench 20 of the trench MOSFET semiconductor device leads to a high electric field on the second insulating layer 18, which in turn leads to the second insulating layer 18 being easily broken down. The vertical projection of the first insulating layer 16 on the first surface 101 covers the vertical projection of the gate groove 20 on the first surface 101. This arrangement can further ensure that the first insulating layer 16 can effectively improve the voltage resistance of the semiconductor device, solve the problem that the high electric field at the bottom and groove corner of the gate groove 20 of the trench MOSFET semiconductor device leads to a very high electric field on the second insulating layer 18, which in turn causes the second insulating layer 18 to be extremely easy to break down, and effectively improve the reliability of the semiconductor device.

[0102] The semiconductor body 1 may further include a second insulating layer 18 , which is located on the sidewalls of the gate trench 20 and is a gate oxide layer. The second insulating layer 18 may be located on the sidewalls of the gate trench 20 or may be located on the sidewalls of the gate trench 20 and extend to the first surface 101 .

[0103] A third insulating layer 17 may also be provided in the epitaxial layer 12. When the semiconductor body 1 includes a substrate 11 and a semiconductor layer formed by other processes, the third insulating layer 17 may also be provided in the semiconductor layer formed by other processes. The third insulating layer 17 is provided on the side of the first insulating layer 16 away from the first surface 101, and the combined shape of the first insulating layer 16 and the third insulating layer 17 may be an inverted convex shape. The width of the third insulating layer 17 away from the gate trench 20 is narrower than the width of the first insulating layer 16. The third insulating layer 17 may also effectively improve the withstand voltage capability of the semiconductor device, further solving the problem that the high electric field at the bottom and groove corner of the gate trench 20 of the trench MOSFET semiconductor device causes a high electric field on the second insulating layer 18, thereby causing the second insulating layer 18 to be easily broken down. The narrow width of the third insulating layer 17 may also effectively ensure the current channel.

[0104] S110 : forming a gate in the gate trench and on a side of the second insulating layer away from the semiconductor body.

[0105] Specifically, Figure 6 As shown, a gate 2 is formed in the gate trench and on a side of the second insulating layer 18 away from the semiconductor body 1. Exemplarily, the second insulating layer 18 may include a silicon dioxide insulating layer, and the gate 2 may include a polysilicon gate.

[0106] S120: forming an interlayer dielectric layer on a side of the gate away from the semiconductor body; a vertical projection of the interlayer dielectric layer on the first surface covers a vertical projection of the gate on the first surface.

[0107] Specifically, Figure 7 As shown, an interlayer dielectric layer 3 is formed on the side of the gate 2 away from the semiconductor body 1, and the vertical projection of the interlayer dielectric layer 3 on the first surface 101 can coincide with the vertical projection of the second insulating layer 18 on the first surface 101, and the vertical projection of the interlayer dielectric layer 3 on the first surface 101 must cover the vertical projection of the gate 2 on the first surface 101, thereby effectively insulating the source and the gate 2.

[0108] S130: forming a source electrode on the first surface.

[0109] Specifically, Figure 8 As shown, for a single trench MOSFET semiconductor device, the semiconductor body 1 does not need to be provided with a source trench, and illustratively, metal is deposited on the first surface 101 to form a source 4. The source 4 is electrically connected to the first region 13, and the vertical projection of the source 4 on the first surface 101 covers the vertical projection of the interlayer dielectric layer 3 on the first surface 101.

[0110] like Fig. 9 and Fig.10As shown, for a double trench MOSFET semiconductor device, a source trench 10 needs to be provided on the first surface 101 of the semiconductor body 1, and the source trench 10 can be located inside the second region 15. A fourth insulating layer 19 is provided on the bottom and sidewalls of the source trench 10. Fig. 9 As shown, the source trench 10 may not be filled with a source trench structure. Fig.10 As shown, the source trench can be filled with a source trench structure 6, and the material of the source trench structure 6 can be metal or polysilicon, etc. The setting of the source trench can further effectively alleviate the problem that the electric field at the bottom and corner of the gate trench is strong, resulting in a high electric field on the second insulating layer 18, which in turn causes the second insulating layer 18 to be easily broken down, and further improve the reliability of the semiconductor device.

[0111] S140: forming a drain electrode on the second surface.

[0112] Specifically, Figure 1-Figure 3 As shown, for the single trench MOSFET semiconductor device and the double trench MOSFET semiconductor device, a drain 5 is formed on the second surface 102 . Exemplarily, the drain 5 is formed by depositing metal on the second surface 102 .

[0113] The technical solution of the embodiment of the present invention is to set a first insulating layer 16 in the epitaxial layer 12 below the bottom of the gate trench or in the semiconductor layer formed by other processes. The first insulating layer 16 can effectively improve the withstand voltage of the semiconductor device, and solve the problem that the high electric field at the bottom and groove corner of the gate trench of the trench MOSFET semiconductor device leads to a high electric field on the second insulating layer 18, which in turn leads to the second insulating layer 18 being extremely easy to break down. The semiconductor device provided by the technical solution of the embodiment of the present invention may include a single trench MOSFET semiconductor device, that is, the source structure is a planar source structure, and there is no need to set a source trench. By setting the first insulating layer 16, the withstand voltage of the semiconductor device can be effectively improved, and the preparation process of the semiconductor device is effectively simplified. And there is no need to adopt an asymmetric gate trench structure, which effectively avoids the problem that the asymmetric structure sacrifices half of the conductive trench, thereby reducing the on-state current. The technical solution of the embodiment of the present invention effectively solves the problem that the strong electric field at the bottom and groove corner of the gate trench leads to a high electric field on the gate oxide layer, which in turn leads to the gate oxide layer being extremely easy to break down, and effectively improves the reliability of the semiconductor device.

[0114] Optionally, based on the above embodiments, Fig.11 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention, Figure 12-Figure 21 is a structural diagram corresponding to some steps in another method for preparing a semiconductor device provided by an embodiment of the present invention, such as Fig.11 As shown, the preparation method comprises:

[0115] S200: providing a substrate.

[0116] Specifically, Fig.12 As shown, a substrate 11 is first provided, and the semiconductor material of the substrate 11 may be silicon carbide or gallium nitride. The MOSFET semiconductor device may include an N-channel MOSFET semiconductor device or a P-channel MOSFET semiconductor device. For an N-channel MOSFET semiconductor device, the substrate 11 is an N+ silicon carbide substrate or an N+ gallium nitride substrate, and for a P-channel MOSFET semiconductor device, the substrate 11 is a P+ silicon carbide substrate or a P+ gallium nitride substrate.

[0117] S210: forming an epitaxial layer on one side of the substrate.

[0118] Specifically, Fig.13 As shown, an epitaxial layer 12 is epitaxially grown on one side of the substrate 11. The epitaxial layer 12 may be a semiconductor layer formed by a single epitaxial process on the basis of the substrate 11, and the epitaxial process includes processes such as chemical vapor epitaxy (CVE), molecular beam epitaxy (MBE), and atomic layer epitaxy (ALE). For an N-channel MOSFET semiconductor device, the epitaxial layer 12 includes an N-epitaxial layer; for a P-channel MOSFET semiconductor device, the epitaxial layer 12 includes a P-epitaxial layer.

[0119] S220: forming a first mask layer on a side of the epitaxial layer away from the substrate, wherein the first mask layer is provided with a first mask trench.

[0120] Specifically, Fig.14 As shown, a first mask layer 7 is formed on a side of the epitaxial layer 12 away from the substrate 11, and the first mask layer 7 is provided with a first mask trench 71. Exemplarily, the first mask layer 7 may include a mask.

[0121] S230: forming a first insulating layer in the epitaxial layer; a vertical projection of the first mask trench on the substrate coincides with a vertical projection of the first insulating layer on the substrate.

[0122] Specifically, Fig.15 As shown, a first insulating layer 16 is formed in the epitaxial layer 12 at a position corresponding to the first mask trench 71. Exemplarily, the semiconductor material of the substrate 11 and the epitaxial layer 12 is silicon carbide, and the material of the first insulating layer 16 is silicon dioxide. A high-energy ion implanter can be used to implant oxygen ions to a certain depth into the epitaxial layer 12 from the first mask trench 71, and the implantation energy can be controlled according to specific needs to implant the oxygen ions to a suitable depth. Then, a high-temperature thermal oxidation treatment is performed to react the implanted oxygen ions with silicon carbide to generate silicon dioxide, thereby forming the first insulating layer 16.

[0123] S240: removing the first mask layer.

[0124] Specifically, Fig.16 As shown, after the first insulating layer 16 is formed, the first mask layer is removed.

[0125] S250: forming a second mask layer on a side of the epitaxial layer away from the substrate, wherein the second mask layer is provided with a second mask trench.

[0126] Specifically, Fig.17 As shown, a second mask layer 8 is formed on the side of the epitaxial layer 12 away from the substrate 11, and the second mask layer 8 is provided with a second mask trench 81. Exemplarily, the second mask layer 8 may include a mask. The width of the second mask trench 81 may be smaller than the width of the first mask trench.

[0127] S260: forming a third insulating layer on a side of the first insulating layer close to the substrate; a vertical projection of the second mask trench on the substrate coincides with a vertical projection of the third insulating layer on the substrate.

[0128] Specifically, Fig.18 As shown, a third insulating layer 17 is formed in the epitaxial layer 12 on the side of the first insulating layer 16 close to the substrate 11 at the corresponding position of the second mask trench 81. Exemplarily, the semiconductor material of the substrate 11 and the epitaxial layer 12 is silicon carbide, and the material of the third insulating layer 17 is silicon dioxide. A high-energy ion implanter can be used to implant oxygen ions to a certain depth into the epitaxial layer 12 from the second mask trench 81, and the implantation energy can be controlled according to specific needs to implant the oxygen ions to a suitable depth. Then, a high-temperature thermal oxidation treatment is performed to react the implanted oxygen ions with silicon carbide to generate silicon dioxide, thereby forming the third insulating layer 17.

[0129] S270: removing the second mask layer.

[0130] Specifically, Fig.19 As shown, after the third insulating layer 17 is formed, the second mask layer is removed.

[0131] S280: Continue epitaxially growing the epitaxial layer on a side of the epitaxial layer away from the substrate.

[0132] Specifically, Fig. 20 As shown, the epitaxial growth of the epitaxial layer 12 continues on the side of the epitaxial layer 12 away from the substrate 11 .

[0133] S290: forming a well region and a first region on a side of the epitaxial layer away from the substrate.

[0134] Specifically, Fig.21As shown, a well region 14, a first region 13, and a second region 15 are formed on the side of the epitaxial layer 12 away from the substrate 11 by doping and other processes, and then the doped impurities are activated by an annealing process. For an N-channel MOSFET semiconductor device, the well region 14 is a P-type well region, the first region 13 is an N++ doped region, and the second region 15 is a P++ doped region; for a P-channel MOSFET semiconductor device, the well region 14 is an N-type well region, the first region 13 is a P++ doped region, and the second region 15 is an N++ doped region.

[0135] S291: forming a gate trench on the first surface, wherein the gate trench extends from the first surface into the semiconductor body, and a bottom of the gate trench contacts the first insulating layer.

[0136] Specifically, Figure 5 As shown, a gate trench 20 is formed on the first surface 101 by photolithography and etching processes. The gate trench 20 can penetrate the well region 14 and the first region 13 and extend into the epitaxial layer 12. The bottom of the gate trench 20 contacts the first insulating layer 16.

[0137] S292: forming a second insulating layer on the sidewalls of the gate trench.

[0138] Specifically, Figure 5 As shown, a second insulating layer 18 is formed on the sidewalls of the gate trench 20 and a portion of the first surface 101 .

[0139] S293: forming a gate in the gate trench and on a side of the second insulating layer away from the semiconductor body.

[0140] S294: forming an interlayer dielectric layer on a side of the gate away from the semiconductor body; a vertical projection of the interlayer dielectric layer on the first surface covers a vertical projection of the gate on the first surface.

[0141] S295: forming a source electrode on the first surface.

[0142] S296: forming a drain on the second surface.

[0143] Optionally, based on the above embodiments, Fig. 22 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention. Figure 23-Figure 27 is a structural diagram corresponding to some steps in another method for preparing a semiconductor device provided by an embodiment of the present invention, such as Fig. 22 As shown, the preparation method comprises:

[0144] S300: providing a substrate.

[0145] S310: forming an epitaxial layer on one side of the substrate.

[0146] S320: forming a first mask layer on a side of the epitaxial layer away from the substrate, wherein the first mask layer is provided with a first mask trench.

[0147] S330: implanting oxygen ions into the epitaxial layer to form a first oxygen ion region, wherein a vertical projection of the first oxygen ion region on the substrate coincides with a vertical projection of the first mask trench on the substrate.

[0148] Specifically, Fig.23 As shown, oxygen ions can be implanted to a certain depth into the epitaxial layer 12 from the first mask trench 71 using a high energy ion implanter to form a first oxygen ion region 161. The implantation energy can be controlled according to specific requirements to implant the oxygen ions to a suitable depth.

[0149] S340: removing the first mask layer.

[0150] Specifically, Fig.24 As shown, after the first oxygen ion region 161 is formed, the first mask layer is removed.

[0151] S350: forming a second mask layer on a side of the epitaxial layer away from the substrate, wherein the second mask layer is provided with a second mask trench.

[0152] Specifically, Fig.25 As shown, a second mask layer 8 is formed on the side of the epitaxial layer 12 away from the substrate 11, and the second mask layer 8 is provided with a second mask trench 81. Exemplarily, the second mask layer 8 may include a mask. The width of the second mask trench 81 may be smaller than the width of the first mask trench.

[0153] S360: implanting oxygen ions into a side of the first oxygen ion region close to the substrate to form a second oxygen ion region, wherein a vertical projection of the second oxygen ion region on the substrate coincides with a vertical projection of the second mask trench on the substrate.

[0154] Specifically, Fig.26 As shown, a high-energy ion implanter is used to implant oxygen ions to a certain depth into the epitaxial layer 12 on the side of the substrate 11 of the first oxygen ion region 161 corresponding to the second mask trench 81, thereby forming a second oxygen ion region 171. The implantation energy can be controlled according to specific needs so that the oxygen ions are implanted to a suitable depth. Exemplarily, the combined pattern of the first oxygen ion region 161 and the second oxygen ion region 171 can be an inverted convex shape, that is, the width of the first oxygen ion region 161 can be greater than the width of the second oxygen ion region 171. When forming the first oxygen ion region 161 and the second oxygen ion region 171, it is necessary to form a first mask layer and a second mask layer 8 respectively, and perform two ion implantations. When forming the first oxygen ion region 161, the ion implantation width is large and the depth is small, and when forming the second oxygen ion region 171, the ion implantation width is small and the depth is large.

[0155] S370: removing the second mask layer.

[0156] Specifically, Fig. 27 As shown, after the second oxygen ion region 171 is formed, the second mask layer is removed.

[0157] S380: performing a thermal oxidation process on the epitaxial layer to thermally oxidize the first oxygen ion region into a first insulating layer and thermally oxidize the second oxygen ion region into a third insulating layer.

[0158] Specifically, Fig.19 As shown, after ion implantation is performed in the epitaxial layer 12 to form the first oxygen ion region and the second oxygen ion region, a high-temperature thermal oxidation treatment is performed on the epitaxial layer 12 to thermally oxidize the first oxygen ion region into the first insulating layer 16 and the second oxygen ion region into the third insulating layer 17. Exemplarily, the semiconductor material of the substrate 11 and the epitaxial layer 12 is silicon carbide, and the material of the first insulating layer 16 and the third insulating layer 17 is silicon dioxide. During the high-temperature thermal oxidation treatment, the oxygen ions in the first oxygen ion region and the second oxygen ion region react with silicon carbide to generate silicon dioxide, thereby forming the first insulating layer 16 and the third insulating layer 17.

[0159] S390: Continue epitaxially growing the epitaxial layer on a side of the epitaxial layer away from the substrate.

[0160] S391: forming a well region and a first region on a side of the epitaxial layer away from the substrate.

[0161] S392: forming a gate trench on the first surface, wherein the gate trench extends from the first surface into the semiconductor body, and a bottom of the gate trench contacts the first insulating layer.

[0162] S393: forming a second insulating layer on the sidewalls of the gate trench.

[0163] S394: forming a gate in the gate trench and on a side of the second insulating layer away from the semiconductor body.

[0164] S395: forming an interlayer dielectric layer on a side of the gate away from the semiconductor body; a vertical projection of the interlayer dielectric layer on the first surface covers a vertical projection of the gate on the first surface.

[0165] S396: forming a source on the first surface.

[0166] S397: forming a drain on the second surface.

[0167] The method for preparing a semiconductor device provided in an embodiment of the present invention injects oxygen ions to a certain depth through a high-energy ion implanter, and then performs high-temperature annealing to allow the oxygen ions to react with silicon carbide to generate a buried silicon dioxide layer, thereby forming a first insulating layer 16 and a third insulating layer 17. At this time, the side of the epitaxial layer 12 away from the substrate 11 still maintains the silicon carbide lattice, so the epitaxial layer 12 can continue to grow epitaxially.

[0168] Optionally, based on the above embodiments, Fig.28 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention. Figure 29-Figure 31 is a structural diagram corresponding to some steps in another method for preparing a semiconductor device provided by an embodiment of the present invention, such as Fig.28 As shown, the preparation method comprises:

[0169] S400: providing a substrate.

[0170] S410: forming an epitaxial layer on one side of the substrate.

[0171] S420: forming a first mask layer on a side of the epitaxial layer away from the substrate, wherein the first mask layer is provided with a first mask trench.

[0172] S430: forming a first insulating layer in the epitaxial layer; a vertical projection of the first mask trench on the substrate coincides with a vertical projection of the first insulating layer on the substrate.

[0173] S440: removing the first mask layer.

[0174] S450: forming a second mask layer on a side of the epitaxial layer away from the substrate, wherein the second mask layer is provided with a second mask trench.

[0175] S460: forming a third insulating layer on a side of the first insulating layer close to the substrate; a vertical projection of the second mask trench on the substrate coincides with a vertical projection of the third insulating layer on the substrate.

[0176] S470: removing the second mask layer.

[0177] S480: Continue epitaxially growing the epitaxial layer on a side of the epitaxial layer away from the substrate.

[0178] S490: forming a well region and a first region on a side of the epitaxial layer away from the substrate.

[0179] S491: forming a gate trench on the first surface, wherein the gate trench extends from the first surface into the semiconductor body, and the bottom of the gate trench contacts the first insulating layer.

[0180] S492: Form a second insulating layer on the first surface and the sidewalls of the gate trench.

[0181] Specifically, Fig.29 As shown, a second insulating layer 18 is formed on the sidewalls of the gate trench 20 and the first surface 101 by thermal oxidation. Exemplarily, the second insulating layer 18 may include a silicon dioxide insulating layer.

[0182] S493: forming a gate in the gate trench and on a side of the second insulating layer away from the semiconductor body.

[0183] Specifically, Fig.30 As shown, a gate 2 is formed in the gate trench and on the side of the second insulating layer 18 away from the semiconductor body 1. Exemplarily, the gate 2 may include a polysilicon gate, and doped polysilicon may be first deposited on the entire surface of the gate trench and on the side of the second insulating layer 18 of the first surface 101 away from the first surface 101, and then the entire surface is etched back to form the gate 2 in the gate trench. Since the bottom of the gate trench is directly in contact with the first insulating layer 16, when the second insulating layer 18 is formed by thermal oxidation, the second insulating layer 18 will not be formed at the bottom of the gate trench.

[0184] S494: forming an interlayer dielectric layer on a side of the gate away from the semiconductor body and a side of the second insulating layer on the first surface away from the first surface.

[0185] Specifically, Fig.31 As shown, an interlayer dielectric layer 3 is formed on a side of the gate 2 away from the semiconductor body 1 and a side of the second insulating layer 18 of the first surface 101 away from the first surface 101 .

[0186] S495: removing a portion of the interlayer dielectric layer on the first surface and a portion of the second insulating layer on the first surface, wherein a vertical projection of the interlayer dielectric layer on the first surface covers a vertical projection of the gate on the first surface.

[0187] Specifically, Figure 7 As shown, part of the interlayer dielectric layer 3 on the first surface 101 and part of the second insulating layer 18 on the first surface 101 are removed, the width of the interlayer dielectric layer 3 is greater than the width of the gate trench, and the first region 13 needs to be exposed.

[0188] S496: forming a source electrode on the first surface.

[0189] S497: Form a drain on the second surface.

[0190] Optionally, based on the above embodiments, Fig.32 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention. Figure 33-Figure 35 is a structural diagram corresponding to some steps in another method for preparing a semiconductor device provided by an embodiment of the present invention, such as Fig.32 As shown, the preparation method comprises:

[0191] S500: Provide a semiconductor body of the first conductive type; the semiconductor body includes a first surface and a second surface arranged opposite to each other, the semiconductor body also includes a well region set to the second conductive type, a first region set to the first conductive type, a first insulating layer and a second insulating layer, the first region is arranged on the first surface, the well region is arranged on a side of the first region away from the first surface, and the first insulating layer is arranged on a side of the well region away from the first surface; a gate trench is arranged on the first surface, the gate trench extends from the first surface to the semiconductor body, and the bottom of the gate trench contacts the first insulating layer; the vertical projection of the gate trench on the first surface is within the vertical projection of the first insulating layer on the first surface; the second insulating layer is arranged on the sidewall of the gate trench.

[0192] S510 : forming a gate in the gate trench and on a side of the second insulating layer away from the semiconductor body.

[0193] S520: forming an interlayer dielectric layer on a side of the gate away from the semiconductor body; a vertical projection of the interlayer dielectric layer on the first surface covers a vertical projection of the gate on the first surface.

[0194] S530: forming a source trench on the first surface; the source trench extends from the first surface into the semiconductor body.

[0195] Specifically, Fig.33 As shown, for a double trench MOSFET semiconductor device, the source structure is a trench source structure, and a source trench 10 is formed on the first surface 101 by an etching process, and the source trench 10 is located inside the second region 15 .

[0196] S540: forming a fourth insulating layer on the bottom and sidewalls of the source trench.

[0197] Specifically, Fig.34 As shown, a fourth insulating layer 19 is formed at the bottom and sidewalls of the source trench 10 . Exemplarily, a silicon dioxide insulating layer is formed at the bottom and sidewalls of the source trench 10 by a thermal oxidation process to form the fourth insulating layer 19 .

[0198] S550: forming a source electrode on the first surface, the source electrode being connected to the first region, and a vertical projection of the source electrode on the first surface covering a vertical projection of the interlayer dielectric layer on the first surface.

[0199] Specifically, Fig.35 As shown, metal is deposited on the first surface 101 to form a source 4. The source 4 is electrically connected to the first region 13, and the vertical projection of the source 4 on the first surface 101 covers the vertical projection of the interlayer dielectric layer 3 on the first surface 101.

[0200] S560: forming a drain on the second surface.

[0201] An embodiment of the present invention provides a power module, wherein the power module includes a substrate and at least one semiconductor device provided by any of the above embodiments of the present invention, and the substrate is used to carry at least one semiconductor device provided by any of the above embodiments of the present invention.

[0202] The power module provided in any of the above embodiments of the present invention includes the semiconductor device provided in any of the above embodiments of the present invention, and has the beneficial effects of the semiconductor device provided in any of the above embodiments of the present invention.

[0203] An embodiment of the present invention provides a power conversion circuit, wherein the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction.

[0204] The power conversion circuit includes a circuit board and at least one semiconductor device provided by any one of the above embodiments of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0205] The power conversion circuit provided in any of the above embodiments of the present invention includes the semiconductor device provided in any of the above embodiments of the present invention, and has the beneficial effects of the semiconductor device provided in any of the above embodiments of the present invention.

[0206] An embodiment of the present invention provides a vehicle, wherein the vehicle includes a load and a power conversion circuit provided by any one of the above embodiments of the present invention, and the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0207] The vehicle provided in any of the above embodiments of the present invention includes the power conversion circuit provided in any of the above embodiments of the present invention, and the power conversion circuit provided in any of the above embodiments of the present invention includes the semiconductor device provided in any of the above embodiments of the present invention, so the vehicle provided in any of the above embodiments of the present invention has the beneficial effects of the semiconductor device provided in any of the above embodiments of the present invention.

[0208] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0209] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body of a first conductivity type; the semiconductor body comprises a first surface and a second surface arranged opposite to each other, the semiconductor body further comprises a well region of a second conductivity type, a first region of a first conductivity type, a first insulating layer and a second insulating layer, the first region being arranged on the first surface, the well region being arranged on a side of the first region away from the first surface, and the first insulating layer being arranged on a side of the well region away from the first surface; a gate trench being arranged on the first surface, the gate trench extending from the first surface into the semiconductor body, the bottom of the gate trench being in contact with the first insulating layer; a vertical projection of the gate trench on the first surface being within a vertical projection of the first insulating layer on the first surface; and the second insulating layer being arranged on a sidewall of the gate trench; A gate located in the gate trench and located on a side of the second insulating layer away from the semiconductor body; an interlayer dielectric layer located on a side of the gate away from the semiconductor body, wherein a vertical projection of the interlayer dielectric layer on the first surface covers a vertical projection of the gate on the first surface; a source electrode located on the first surface; A drain is located on the second surface.

2. The semiconductor device according to claim 1, wherein: The semiconductor body further includes a third insulating layer; The third insulating layer is disposed on a side of the first insulating layer away from the first surface, the third insulating layer is connected to the first insulating layer, and a vertical projection of the third insulating layer on the first surface is within a vertical projection of the first insulating layer on the first surface.

3. The semiconductor device according to claim 2, characterized in that The thickness of the first insulating layer is smaller than the thickness of the third insulating layer.

4. The semiconductor device according to claim 2 or 3, characterized in that: The first insulating layer includes a silicon dioxide insulating layer, and the third insulating layer includes a silicon dioxide insulating layer.

5. The semiconductor device according to claim 1, wherein: The source is located on the first surface of the semiconductor body, the source is connected to the first region, and a vertical projection of the source on the first surface covers a vertical projection of the interlayer dielectric layer on the first surface.

6. The semiconductor device according to claim 1, wherein: The first surface is provided with a source trench, and the source trench extends from the first surface into the semiconductor body; the semiconductor body further comprises a fourth insulating layer, and the fourth insulating layer is located on the bottom surface and sidewalls of the source trench; The source is located on the first surface of the semiconductor body, the source is connected to the first region, and a vertical projection of the source on the first surface covers a vertical projection of the interlayer dielectric layer on the first surface.

7. A method for preparing a semiconductor device, characterized in that: include: A semiconductor body of a first conductivity type is provided; the semiconductor body comprises a first surface and a second surface arranged opposite to each other, the semiconductor body further comprises a well region set to the second conductivity type, a first region set to the first conductivity type, a first insulating layer and a second insulating layer, the first region is arranged on the first surface, the well region is arranged on a side of the first region away from the first surface, and the first insulating layer is arranged on a side of the well region away from the first surface; a gate trench is arranged on the first surface, the gate trench extends from the first surface into the semiconductor body, and the bottom of the gate trench contacts the first insulating layer; a vertical projection of the gate trench on the first surface is within a vertical projection of the first insulating layer on the first surface; the second insulating layer is arranged on the sidewall of the gate trench; forming a gate in the gate trench and on a side of the second insulating layer away from the semiconductor body; forming an interlayer dielectric layer on a side of the gate away from the semiconductor body; The vertical projection of the interlayer dielectric layer on the first surface covers the vertical projection of the gate on the first surface; forming a source electrode on the first surface; A drain electrode is formed on the second surface.

8. The method for preparing a semiconductor device according to claim 7, characterized in that: A semiconductor body of a first conductivity type is provided, further comprising: A third insulating layer is formed on a side of the first insulating layer away from the first surface, the third insulating layer is connected to the first insulating layer, and a vertical projection of the third insulating layer on the first surface is within a vertical projection of the first insulating layer on the first surface.

9. The method for preparing a semiconductor device according to claim 8, characterized in that: A semiconductor body of a first conductivity type is provided, comprising: providing a substrate; forming an epitaxial layer on one side of the substrate; forming a first mask layer on a side of the epitaxial layer away from the substrate, wherein the first mask layer is provided with a first mask trench; forming the first insulating layer in the epitaxial layer; a vertical projection of the first mask trench on the substrate coincides with a vertical projection of the first insulating layer on the substrate; removing the first mask layer; forming a second mask layer on a side of the epitaxial layer away from the substrate, wherein the second mask layer is provided with a second mask trench; forming the third insulating layer on a side of the first insulating layer close to the substrate; a vertical projection of the second mask trench on the substrate coincides with a vertical projection of the third insulating layer on the substrate; removing the second mask layer; Continue epitaxially growing the epitaxial layer on a side of the epitaxial layer away from the substrate; forming a well region and a first region on a side of the epitaxial layer away from the substrate; forming a gate trench on the first surface, wherein the gate trench extends from the first surface into the semiconductor body, and a bottom of the gate trench contacts the first insulating layer; The second insulating layer is formed on the sidewalls of the gate trench.

10. The method for preparing a semiconductor device according to claim 9, characterized in that: Forming the first insulating layer in the epitaxial layer, removing the first mask layer, forming a second mask layer on a side of the epitaxial layer away from the substrate, forming the third insulating layer on a side of the first insulating layer close to the substrate, and removing the second mask layer, comprising: implanting oxygen ions into the epitaxial layer to form a first oxygen ion region, wherein a vertical projection of the first oxygen ion region on the substrate coincides with a vertical projection of the first mask trench on the substrate; removing the first mask layer; forming a second mask layer on a side of the epitaxial layer away from the substrate, wherein the second mask layer is provided with a second mask trench; implanting oxygen ions into a side of the first oxygen ion region close to the substrate to form a second oxygen ion region, wherein a vertical projection of the second oxygen ion region on the substrate coincides with a vertical projection of the second mask trench on the substrate; removing the second mask layer; The epitaxial layer is thermally oxidized to thermally oxidize the first oxygen ion region into the first insulating layer and the second oxygen ion region into the third insulating layer.

11. The method for preparing a semiconductor device according to claim 9, characterized in that: Forming the second insulating layer on the sidewall of the gate trench comprises: forming a second insulating layer on the first surface and the sidewalls of the gate trench; An interlayer dielectric layer is formed on a side of the gate away from the semiconductor body, comprising: forming the interlayer dielectric layer on a side of the gate away from the semiconductor body and a side of the second insulating layer of the first surface away from the first surface; A portion of the interlayer dielectric layer on the first surface and a portion of the second insulating layer on the first surface are removed, and a vertical projection of the interlayer dielectric layer on the first surface covers a vertical projection of the gate on the first surface.

12. The method for preparing a semiconductor device according to claim 7, characterized in that: The semiconductor body further includes a fourth insulating layer; providing a semiconductor body of a first conductivity type and forming a source electrode on the first surface, comprising: Forming a source trench on the first surface; the source trench extending from the first surface into the semiconductor body; forming the fourth insulating layer at the bottom and sidewalls of the source trench; A source electrode is formed on the first surface, the source electrode is connected to the first region, and a vertical projection of the source electrode on the first surface covers a vertical projection of the interlayer dielectric layer on the first surface.

13. A power module, characterized in that: It comprises a substrate and at least one semiconductor device according to any one of claims 1 to 6, wherein the substrate is used for carrying the semiconductor device.

14. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one semiconductor device according to any one of claims 1 to 6, wherein the semiconductor device is electrically connected to the circuit board.

15. A vehicle, characterized in that: It includes a load and a power conversion circuit as described in claim 14, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

Images