Semiconductor device and preparation method thereof, power module, power conversion circuit and vehicle

Abstract

The invention discloses a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. The semiconductor device comprises a semiconductor body, the semiconductor body comprises a first surface and a second surface which are oppositely arranged, the semiconductor body further comprises a well region, a first region and a second region, the first region and the second region are arranged to be of a first conduction type and are located on the first surface, the well region is of a second conduction type and is located on one side, far away from the first surface, of the first region; the gate structure extends to a preset position in the semiconductor body from the first surface; wherein the first region and the second region are located on two opposite sides of the gate structure; the source electrode is positioned on one side, far away from the second surface, of the first region; and the drain electrode is positioned on one side, far away from the second surface, of the second region. According to the semiconductor device provided by the invention, the thickness of the semiconductor device is reduced under the condition that the bearing pressure is not changed.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a preparation method thereof, a power module, a power conversion circuit, and a vehicle. Background Art

[0002] Semiconductor devices, such as transistors, have important applications in the field of modern electronic technology, and the corresponding requirements for semiconductor devices are becoming increasingly higher.

[0003] However, the semiconductor devices in the related art have the problem of being relatively thick under certain pressure, which limits the further application of the semiconductor devices. Summary of the invention

[0004] The present invention provides a semiconductor device and a preparation method thereof, a power module, a power conversion circuit, and a vehicle, so as to reduce the thickness of the semiconductor device under the condition that the pressure of the semiconductor device remains unchanged.

[0005] According to one aspect of the present invention, there is provided a semiconductor device, the semiconductor device comprising:

[0006] A semiconductor body, comprising a first surface and a second surface arranged opposite to each other, the semiconductor body further comprising a well region, a first region and a second region, the first region and the second region being set to a first conductivity type and located on the first surface, the well region being set to a second conductivity type and located on a side of the first region away from the first surface;

[0007] A gate structure extending from the first surface to a predetermined position in the semiconductor body; wherein the first region and the second region are located on opposite sides of the gate structure;

[0008] a source electrode, located at a side of the first region away from the second surface;

[0009] The drain is located on a side of the second region away from the second surface.

[0010] Optionally, the semiconductor body includes an epitaxial layer, and the epitaxial layer includes a third surface and a fourth surface relative to each other; wherein the third surface is the first surface of the semiconductor body; and the distance from the preset position to the fourth surface is 5% to 15% of the thickness of the epitaxial layer.

[0011] Optionally, the gate structure includes a trench gate and an insulating layer;

[0012] The trench gate is located in the gate structure at a position close to the first region.

[0013] Optionally, the gate structure includes a trench gate and an insulating layer;

[0014] The trench gate is located in the gate structure at a position close to the first surface.

[0015] Optionally, the first surface of the semiconductor body further includes a third region, and the third region runs through the first region and the well region;

[0016] Wherein, the third region is set to be of the second conductivity type.

[0017] Optionally, the semiconductor body includes an epitaxial layer, the epitaxial layer includes a third surface and a fourth surface opposite to each other; wherein the third surface is the first surface of the semiconductor body; the semiconductor body also includes a substrate, the substrate is arranged on the fourth surface of the epitaxial layer; the surface of the substrate away from the fourth surface is the second surface of the semiconductor body; the substrate includes an intrinsic semiconductor layer; or, the substrate is arranged as a first conductivity type, and the ion doping concentration of the substrate is less than the ion doping concentration of the first region;

[0018] Alternatively, the semiconductor body includes an epitaxial layer, and the epitaxial layer includes a third surface and a fourth surface opposite to each other; wherein the third surface is the first surface of the semiconductor body, and the fourth surface is the second surface of the semiconductor body.

[0019] Optionally, the semiconductor device further includes:

[0020] an interlayer dielectric layer, located on a side of the gate structure away from the second surface;

[0021] a passivation layer, located on a side of the interlayer dielectric layer away from the second surface;

[0022] The protection layer is located on a side of the passivation layer away from the second surface.

[0023] According to another aspect of the present invention, there is provided a method for preparing a semiconductor device, comprising:

[0024] A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface arranged opposite to each other, the semiconductor body further comprising a well region, a first region and a second region, the first region and the second region being set to a first conductivity type and being located on the first surface, the well region being set to a second conductivity type and being located on a side of the first region away from the first surface;

[0025] A gate structure is formed on the first surface of the semiconductor body, wherein the gate structure extends from the first surface to a predetermined position in the semiconductor body; and the first region and the second region are located on opposite sides of the gate structure;

[0026] A source and a drain are formed on the first surface of the semiconductor body.

[0027] Optionally, providing a semiconductor body comprises:

[0028] The well region and the first doped region are formed on the first surface of the semiconductor body, wherein the well region is located on a side of the first doped region away from the first surface, and the first doped region is set to a first conductivity type.

[0029] Optionally, forming a gate structure on the first surface of the semiconductor body includes:

[0030] forming a trench on the first surface of the semiconductor body;

[0031] The gate structure is formed in the trench.

[0032] Optionally, forming the gate structure in the trench includes:

[0033] forming an insulating layer in the trench;

[0034] forming a gate groove on a surface of the insulating layer close to the first surface;

[0035] A trench gate is formed in the gate trench.

[0036] According to another aspect of the present invention, a power module is provided, comprising a substrate and at least one semiconductor device as described above, wherein the substrate is used to carry the semiconductor device.

[0037] According to another aspect of the present invention, there is provided a power conversion circuit, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0038] The power conversion circuit includes a circuit board and at least one semiconductor device as described above, wherein the semiconductor device is electrically connected to the circuit board.

[0039] According to another aspect of the present invention, a vehicle is provided, comprising a load and a power conversion circuit as described above, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0040] The technical solution of the embodiment of the present invention adopts a semiconductor device including a semiconductor body, including a first surface and a second surface arranged oppositely, the semiconductor body also includes a well region, a first region and a second region, the first region and the second region are set to the first conductivity type and are located on the first surface, and the well region is set to the second conductivity type and is located on the side of the first region away from the first surface; a gate structure extends from the first surface to a preset position in the semiconductor body; wherein the first region and the second region are located on two opposite sides of the gate structure; the source is located on the side of the first region away from the second surface; the drain is located on the side of the second region away from the second surface. The drain and the source are both arranged on one side of the first surface and are located on two opposite sides of the gate structure. The current between the drain and the source needs to bypass the gate structure in the semiconductor body, and the path required to flow is longer, so that a higher pressure bearing effect can be achieved when the thickness of the semiconductor body is small. Or a higher pressure bearing effect can be achieved when the thickness of the semiconductor body is constant. In addition, the thickness of the semiconductor body is small, and the time required to grow the semiconductor body can also be reduced, thereby improving production capacity.

[0041] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0043] Figure 1 A schematic diagram of the structure of a semiconductor device provided by an embodiment of the present invention;

[0044] Figure 2 A schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0045] Figure 3 A schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0046] Figure 4 A flowchart of a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0047] Figure 5-Figure 12 It is a schematic diagram of the product structure corresponding to the main preparation steps of the semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0048] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0049] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0050] Figure 1 A schematic diagram of a semiconductor device according to an embodiment of the present invention is provided. Figure 1 , the semiconductor device includes: a semiconductor body 2, a gate structure 25, a source 50 and a drain 40. The semiconductor body 2 includes a first surface and a second surface arranged opposite to each other, and the semiconductor body 2 also includes a well region 24, a first region 22 and a second region 23; the first region 22 and the second region 23 are set to the first conductivity type and are located on the first surface, and the well region 24 is set to the second conductivity type and is located on the side of the first region 22 away from the first surface. The gate structure 25 extends from the first surface to a preset position in the semiconductor body 2; wherein the first region 22 and the second region 23 are located on opposite sides of the gate structure 25. The source 50 is located on the side of the first region 22 away from the second surface. The drain 40 is located on the side of the second region 23 away from the second surface.

[0051] Specifically, the semiconductor device is a transistor structure, which includes a gate structure 25, a drain 40 and a source 50. When an appropriate voltage is applied between the gate structure 25 and the source 50, the well region 24 is opened, so that current can flow from the drain 40 to the source 50. Among them, the drain 40 and the source 50 are structures in the semiconductor device that allow current to flow. The drain 40 and the source 50 can be made of heavily doped N-type silicon material or metal.

[0052] The semiconductor body 2 may include an epitaxial layer 20 formed by growth, and the first region 22, the second region 23 and the well region 24 may be formed by ion implantation on the epitaxial layer 20. A trench structure is made in the epitaxial layer 20, and a gate structure 25 is formed in the trench. The portion of the epitaxial layer 20 other than the first region 22, the second region 23 and the trench structure may be understood as a drift layer 21, and the drift layer 21 is used to provide a conductive path. And the drift layer 21 may be a semiconductor material of the first conductivity type, for example, a silicon carbide layer of the first conductivity type.

[0053] The first region 22 can also be understood as a source region, and the second region 23 can also be understood as a drain region. In the related art, the drain is located on the second surface of the semiconductor body 2, and the current direction is from the second surface of the semiconductor body 2 to the first surface, that is, the effective length of the pressure-bearing effect is the length of a thickness of the semiconductor body 2. If the pressure-bearing capacity of the semiconductor device needs to be increased, the thickness of the semiconductor body 2 needs to be increased. In this embodiment, the source 50 and the drain 40 are both located on the first surface and on both sides of the gate structure 25, so the current of the current drain 40 will first flow in the semiconductor body 2 toward the second surface, then bypass the gate structure 25 at the bottom of the gate structure 25, and finally flow toward the first surface to the source 50. In other words, the effective length of the pressure-bearing effect on the current between the drain 40 and the source 50 is twice the thickness of a part of the semiconductor body 2, that is, twice the thickness of the gate structure 25, so that a higher pressure-bearing effect can be achieved when the thickness of the semiconductor body 2 is reduced. Alternatively, in the case of the same thickness of the semiconductor body 2, the solution of this embodiment has a higher pressure-bearing effect.

[0054] The technical solution of this embodiment adopts a semiconductor device including a semiconductor body, including a first surface and a second surface arranged oppositely, the semiconductor body also includes a well region, a first region and a second region, the first region and the second region are set to the first conductivity type and are located on the first surface, and the well region is set to the second conductivity type and is located on the side of the first region away from the first surface; a gate structure extends from the first surface to a preset position in the semiconductor body; wherein the first region and the second region are located on opposite sides of the gate structure; the source is located on the side of the first region away from the second surface; the drain is located on the side of the second region away from the second surface. The drain and the source are both arranged on one side of the first surface and are located on opposite sides of the gate structure. The current between the drain and the source needs to bypass the gate structure in the semiconductor body, and the path required to flow is longer, so a higher pressure bearing effect can be achieved when the thickness of the semiconductor body is small. Or a higher pressure bearing effect can be achieved when the thickness of the semiconductor body is constant. In addition, the small thickness of the semiconductor body can also reduce the time required to grow the semiconductor body, thereby improving production capacity.

[0055] Optionally, the drift layer 21 of the semiconductor body 2 is set to a first conductivity type. The first conductivity type is different from the second conductivity type. The first conductivity type may be, for example, an N-type conductivity type, and the second conductivity type may be a P-type conductivity type. Of course, the first conductivity type may be a P-type conductivity type, and the second conductivity type may be an N-type conductivity type. Herein, the first conductivity type is exemplarily taken as an N-type conductivity type and the second conductivity type is a P-type conductivity type. Exemplarily, the doping ions of the N-type conductivity type may be P (phosphorus) ions or N (nitrogen) ions. The doping ions of the P-type conductivity type may be Al (aluminum) ions or B (boron) ions.

[0056] Further, the ion doping concentration of the drift layer 21 is less than the ion doping concentration of the first region 22. For example, the drift layer 21 may be lightly N-type doped. Thus, the drift layer 21 may have a higher resistivity, so that the current has a higher impedance when flowing through the drift layer 21, that is, the pressure-bearing capacity of the semiconductor device may be further improved. And the first region 22 may be heavily doped, and the heavily doped first region 22 has a higher conductivity. The first region 22 may also be understood as a contact source region, and the subsequent contact resistance between the first region 22 and the source 50 is small.

[0057] Furthermore, the ion doping concentrations of the first region 22 and the second region 23 are the same. When preparing the semiconductor device, the first region 22 and the second region 23 can be doped at the same time, that is, the first region 22 and the second region 23 can be prepared at the same time through a single doping process, thereby simplifying the steps of the semiconductor device preparation process and further reducing the cost of the semiconductor device.

[0058] Alternatively, if Figure 1 As shown, the semiconductor body 2 includes an epitaxial layer 20, and the epitaxial layer 20 includes a third surface and a fourth surface relative to each other; wherein the third surface is the first surface of the semiconductor body 2; and the distance from the preset position to the fourth surface is 5% to 15% of the thickness of the epitaxial layer 20.

[0059] Specifically, in the semiconductor device, the current of the drain 40 needs to go around the bottom surface of the gate structure 25 in the epitaxial layer 20, and then flow from the bottom surface of the gate structure 25 toward the source 50. That is, the effective length of the corresponding current between the drain 40 and the source 50 is twice the thickness of the gate structure 25. The specific position of the preset position determines the thickness of the gate structure 25, and further determines the effective length that the current between the drain 40 and the source 50 needs to flow. Therefore, in this embodiment, the distance from the preset position to the fourth surface is set to 5% to 15% of the thickness of the semiconductor body, which can effectively utilize the thickness of the epitaxial layer 20, so that the effective length of the corresponding current between the source 50 and the drain 40 is longer. For example, in this embodiment, the thickness of the gate structure is close to the thickness of the epitaxial layer, so the effective length of the corresponding current between the source and the drain is close to twice the thickness of the epitaxial layer. When the pressure of the semiconductor device in the related art is the same, the thickness of the epitaxial layer in this embodiment only needs to be about half of the thickness of the semiconductor device in the related art. At the same time, in the semiconductor device of this embodiment, there is at least 5% of the thickness of the epitaxial layer between the gate structure 25 and the fourth surface, which can avoid the problem that the distance between the preset position and the fourth surface is too small and the current is small. Exemplarily, the distance from the preset position to the fourth surface is 5%, 6%, 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14% or 15% of the thickness of the epitaxial layer 20.

[0060] Optionally, continue to refer to Figure 1 The gate structure 25 includes a trench gate 252 and an insulating layer 251 . The trench gate 252 is located in the gate structure 25 close to the first region 22 .

[0061] Specifically, the trench gate 252 is, for example, metal or polysilicon. When an appropriate voltage is applied between the trench gate 252 and the source 50, the current path is turned on; and when no voltage or an inappropriate voltage is applied between the trench gate 252 and the source 50, the current path is turned off. The insulating layer 251 is, for example, a silicon dioxide insulating layer, which can play an insulating role. When an electric field exists between the well region 24 and the trench gate 252, the current flows from the trench gate 252 to the well region 24. In other words, the formation of a current channel between the drain 40 and the source 50 can be ensured by providing the insulating layer 251. The trench gate 252 can extend from the first surface to the inside of the semiconductor body, and the side of the trench gate 252 away from the first surface exceeds the side of the well region 24 away from the first surface. The insulating layer 251 extends directly from the first surface to a preset position. As a result, the insulating layer 251 can also adjust the electric field distribution at the bottom of the semiconductor body 2 (i.e., the part away from the first surface).

[0062] In this embodiment, the trench gate 252 is disposed close to the first region 22. In other words, the thickness of the insulating layer between the trench gate 252 and the second region 23 is greater than the thickness of the insulating layer between the trench gate 252 and the first region 22, which can prevent the semiconductor device from being broken down when a high voltage is applied to the drain 40. Therefore, the semiconductor device of this embodiment has a higher withstand voltage and better stability.

[0063] Optionally, continue to refer to Figure 1 , the trench gate 252 is located in the gate structure 25 near the first surface. The trench gate 252 may be located on the first surface to facilitate electrical connection between the gate structure 25 and external devices.

[0064] Optionally, continue to refer to Figure 1 The first surface of the semiconductor body 2 further includes a third region 26 , and the third region 26 runs through the first region 22 and the well region 24 ; wherein the third region 26 is set to the second conductivity type.

[0065] Specifically, the third region 26 is formed by, for example, performing ion implantation again after the semiconductor body 2 is ion implanted to form the first region 22 and the well region 24. The conductivity type of the third region 26 is also different from the conductivity type of the epitaxial layer 20, and the third region 26 may be of the second conductivity type, such as a P-type conductivity type. And further, the third region 26 may be heavily doped. The third region 26 is used to form a freewheeling diode between the source 50 and the drain 40. In the present embodiment, since the insulating layer 251 in the gate structure 25 is close to the second surface, the insulating layer 251 can play a role in regulating the bottom electric field, and there is no need to use the third region 26 to adjust the electric field at the bottom of the trench and the groove angle. In other words, in the present embodiment, the third region 26 can be used only to form a freewheeling diode, and thus can have a smaller size, thereby further reducing the size of the semiconductor device.

[0066] Optionally, continue to refer to Figure 1 The semiconductor body includes an epitaxial layer 20 and a substrate 10, the substrate 10 is arranged on the fourth surface of the epitaxial layer 20, and the surface of the substrate 10 away from the fourth surface is the second surface of the semiconductor body 2; the substrate 10 includes an intrinsic semiconductor layer; or, the substrate 10 is set to a first conductivity type, and the ion doping concentration of the substrate 10 is less than the ion doping concentration of the first region 22.

[0067] Specifically, the substrate 10 plays a role in supporting the entire semiconductor device. For example, the substrate 10 can be formed on the second surface of the epitaxial layer 20 after the second surface is thinned. Of course, in some other embodiments, the epitaxial layer 20 can also be directly formed by epitaxy on the substrate 10, and then each region is prepared by ion implantation or the like on the epitaxial layer 20. The substrate 10 can be a silicon carbide layer. In this embodiment, since the source 50 and the drain 40 are both arranged on the first surface of the epitaxial layer 20, the side of the substrate 10 away from the second surface does not need to be provided with a drain, so the substrate 10 does not need to play a conductive role. Therefore, the substrate 10 does not need to be heavily doped, that is, the substrate 10 can be undoped or lightly doped, thereby further reducing the time required for the preparation of the semiconductor device. In addition, in the related art, the side of the substrate 10 away from the second surface needs to prepare a drain, and the step of preparing the drain will undoubtedly increase the preparation time of the semiconductor device. However, the side of the substrate 10 away from the second surface does not need to prepare an electrode, which is conducive to reducing the preparation time of the semiconductor device, improving the production capacity, and further reducing the preparation cost of the semiconductor device.

[0068] Optionally, Figure 2 A schematic diagram of a semiconductor device according to an embodiment of the present invention is provided. Figure 2 In the present embodiment, the semiconductor body 2 includes an epitaxial layer 20 , and the epitaxial layer 20 includes a third surface and a fourth surface opposite to each other; wherein the third surface is the first surface of the semiconductor body 2 , and the fourth surface is the second surface of the semiconductor body 2 .

[0069] Specifically, in this embodiment, compared with Figure 1 In the embodiment shown, the semiconductor body 2 does not include the substrate 10. The epitaxial layer 20 may be first formed on the substrate 10 by epitaxy, and then after the corresponding structure is prepared on the epitaxial layer 20, the substrate 10 is finally removed to form Figure 2 The semiconductor device shown.

[0070] Optionally, Figure 3 A schematic diagram of a semiconductor device according to an embodiment of the present invention is provided. Figure 3 The semiconductor device further includes an interlayer dielectric layer 30, a passivation layer 60 and a protective layer 70. The interlayer dielectric layer 30 is located on a side of the gate structure 25 away from the second surface. The passivation layer 60 is located on a side of the interlayer dielectric layer 30 away from the second surface. The protective layer 70 is located on a side of the passivation layer 60 away from the second surface.

[0071] Specifically, the interlayer dielectric layer 30 is a structure that insulates the source 50 and the gate structure 25 . The interlayer dielectric layer 30 can prevent current conduction between the source 50 and the gate structure 25 , and the interlayer dielectric layer 30 can ensure the normal operation of the semiconductor device.

[0072] The passivation layer 60 can protect the semiconductor device and reduce the impact of the external environment on the semiconductor device. For example, the passivation layer 60 can reduce the probability of the semiconductor device reacting with substances such as water and oxygen in the external environment, thereby reducing the corrosion of the surface of the semiconductor device and extending the service life of the semiconductor device. In addition, the passivation layer 60 can also shield the external current to prevent the external current from interfering with the semiconductor device, thereby enhancing the stability of the operation of the semiconductor device. Exemplarily, the passivation layer 60 can be prepared from materials such as silicon dioxide or silicon nitride.

[0073] The protective layer 70 plays a further protective role, reducing the impact of external physical collision or chemical corrosion on the semiconductor device, thereby further extending the service life of the semiconductor device. The protective layer 70 can be made of materials such as polyimide (PI).

[0074] The present invention also provides a method for preparing a semiconductor device, such as Figure 4 shown. Figure 4 A flowchart of a method for preparing a semiconductor device provided in an embodiment of the present invention, the method for preparing a semiconductor device includes:

[0075] Step S110, providing a semiconductor body, the semiconductor body including a first surface and a second surface arranged opposite to each other, the semiconductor body also including a well region, a first region and a second region, the first region and the second region are set to a first conductivity type and are located on the first surface, the well region is set to a second conductivity type and is located on a side of the first region away from the first surface.

[0076] Step S120 , forming a gate structure on the first surface of the semiconductor body, wherein the gate structure extends from the first surface to a preset position in the semiconductor body; and the first region and the second region are located on opposite sides of the gate structure.

[0077] Step S130 , forming a source and a drain on the first surface of the semiconductor body.

[0078] In the method for preparing a semiconductor device of this embodiment, the prepared semiconductor device has a drain and a source both disposed on one side of the first surface and located on opposite sides of the gate structure. The current between the drain and the source needs to bypass the gate structure in the semiconductor body, and the required path is longer, so a higher pressure bearing effect can be achieved when the thickness of the semiconductor body is small. Alternatively, a higher pressure bearing effect can be achieved when the thickness of the semiconductor body is constant. In addition, a smaller thickness of the semiconductor body can also reduce the time required to grow the semiconductor body, thereby increasing production capacity.

[0079] Further, Figure 5-Figure 12 Schematic diagram of the product structure corresponding to the main preparation steps of the semiconductor device according to the embodiment of the present invention. Figure 5-Figure 12 Providing a semiconductor body includes: forming a well region and a first doped region on a first surface of the semiconductor body, wherein the well region is located on a side of the first doped region away from the first surface, and the first doped region is set to a first conductivity type.

[0080] Specifically, a substrate 10 and an epitaxial layer 20 may be provided first. Figure 6 , firstly, ion implantation is performed on the epitaxial layer 20 to form a well region 24 and a first doping region 231. The first doping region 231 is used to subsequently form the first region and the second region. Exemplarily, ion implantation may be performed first to form the well region 24, and then ion implantation may be performed to form the first doping region 231. And after forming the well region 24 and the first doping region 231, ion implantation may be further performed to form the third region 26. Exemplarily, the ion implantation may be performed at 500-600°C by high temperature ion implantation equipment, which may reduce damage to the silicon carbide material.

[0081] Optionally, forming a gate structure on the first surface of the semiconductor body includes: forming a trench on the first surface of the semiconductor body; and forming the gate structure in the trench. Figure 7 As shown, firstly, trench etching is performed on the first surface to form a trench Gap. The trench Gap is used to form a gate structure, that is, the shape and size of the trench Gap are the same as the shape and size of the gate structure to be formed subsequently. Etching can be performed using processes such as photolithography, such as preparing a mask layer, patterning the mask layer based on a photolithography process, etching to form a trench, and the like.

[0082] Optionally, forming a gate structure in the trench includes: forming an insulating layer in the trench; forming a gate trench on a surface of the insulating layer close to the first surface; and forming a trench gate in the gate trench. Figure 8 As shown, an insulating layer 251 is deposited in the groove Gap, and the groove Gap is filled with the insulating layer 251 by etching back the entire surface.

[0083] Then, if Fig. 9 As shown, a gate groove Gap1 is formed by a photolithography process. The gate groove Gap1 is used to accommodate a trench gate later.

[0084] Then, if Fig.10 As shown, a gate oxide layer is formed by thermal oxidation or the like.

[0085] Then, if Fig.11 As shown, a gate structure 25 is formed in the gate groove Gap1. For example, polysilicon can be formed in the gate groove Gap1 by depositing doped polysilicon, etc. The groove can be filled with polysilicon by full-surface etching.

[0086] Then, if Fig.12 As shown, an interlayer dielectric layer 30 is formed on the first surface, and the interlayer dielectric layer 30 covers the gate structure 25 and exposes at least a portion of the first region 22 , at least a portion of the second region 23 , and at least a portion of the third region 26 .

[0087] Then, if Figure 3 As shown, a source electrode 50 and a drain electrode 40 are formed, and the source electrode 50 and the drain electrode 40 can be formed at the same time. After the source electrode 50 and the drain electrode 40 are formed, a passivation layer and a protection layer are formed in sequence.

[0088] An embodiment of the present invention further provides a power module, which includes a substrate and at least one semiconductor device according to any embodiment of the present invention; wherein the substrate is used to carry the semiconductor device.

[0089] In the power module provided by the embodiment of the present invention, the drain and source of the semiconductor device are both arranged on one side of the first surface and on opposite sides of the gate structure. The current between the drain and the source needs to bypass the gate structure in the semiconductor body, and the path required to flow is longer, so a higher pressure-bearing effect can be achieved when the thickness of the semiconductor body is small. Alternatively, a higher pressure-bearing effect can be achieved when the thickness of the semiconductor body is constant. In addition, the smaller the thickness of the semiconductor body, the less time required to grow the semiconductor body, thereby increasing production capacity.

[0090] The embodiment of the present invention further provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction;

[0091] The power conversion circuit includes a circuit board and at least one semiconductor device according to any of the above embodiments, wherein the semiconductor device is electrically connected to the circuit board.

[0092] In the power conversion circuit provided by the embodiment of the present invention, the drain and source of the semiconductor device are both arranged on one side of the first surface and on opposite sides of the gate structure. The current between the drain and the source needs to bypass the gate structure in the semiconductor body, and the path required to flow is longer, so a higher pressure-bearing effect can be achieved when the thickness of the semiconductor body is small. Alternatively, a higher pressure-bearing effect can be achieved when the thickness of the semiconductor body is constant. In addition, the smaller the thickness of the semiconductor body, the less time required to grow the semiconductor body, thereby increasing production capacity.

[0093] An embodiment of the present invention also provides a vehicle, including a load and a power conversion circuit as described above, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0094] In the vehicle provided by the embodiment of the present invention, the drain and source of the semiconductor device are both arranged on one side of the first surface and on opposite sides of the gate structure. The current between the drain and the source needs to bypass the gate structure in the semiconductor body, and the path required to flow is longer, so a higher pressure-bearing effect can be achieved when the thickness of the semiconductor body is small. Alternatively, a higher pressure-bearing effect can be achieved when the thickness of the semiconductor body is constant. In addition, the small thickness of the semiconductor body can also reduce the time required to grow the semiconductor body, thereby increasing production capacity.

[0095] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0096] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: A semiconductor body, comprising a first surface and a second surface arranged opposite to each other, the semiconductor body further comprising a well region, a first region and a second region, the first region and the second region being set to a first conductivity type and located on the first surface, the well region being set to a second conductivity type and located on a side of the first region away from the first surface; A gate structure extending from the first surface to a predetermined position in the semiconductor body; wherein the first region and the second region are located on opposite sides of the gate structure; a source electrode, located at a side of the first region away from the second surface; The drain is located on a side of the second region away from the second surface.

2. The semiconductor device according to claim 1, wherein: The semiconductor body includes an epitaxial layer, and the epitaxial layer includes a third surface and a fourth surface relative to each other; wherein the third surface is the first surface of the semiconductor body; and the distance from the preset position to the fourth surface is 5% to 15% of the thickness of the epitaxial layer.

3. The semiconductor device according to claim 1, wherein: The gate structure includes a trench gate and an insulating layer; The trench gate is located in the gate structure at a position close to the first region.

4. The semiconductor device according to claim 1, wherein: The gate structure includes a trench gate and an insulating layer; The trench gate is located in the gate structure at a position close to the first surface.

5. The semiconductor device according to claim 1, wherein: The first surface of the semiconductor body further includes a third region, and the third region runs through the first region and the well region; Wherein, the third region is set to be of the second conductivity type.

6. The semiconductor device according to claim 1, wherein: The semiconductor body includes an epitaxial layer, and the epitaxial layer includes a third surface and a fourth surface opposite to each other; wherein the third surface is the first surface of the semiconductor body; the semiconductor body also includes a substrate, and the substrate is arranged on the fourth surface of the epitaxial layer; the surface of the substrate away from the fourth surface is the second surface of the semiconductor body; the substrate includes an intrinsic semiconductor layer; or, the substrate is arranged to be a first conductivity type, and the ion doping concentration of the substrate is less than the ion doping concentration of the first region; Alternatively, the semiconductor body includes an epitaxial layer, and the epitaxial layer includes a third surface and a fourth surface opposite to each other; wherein the third surface is the first surface of the semiconductor body, and the fourth surface is the second surface of the semiconductor body.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that: The semiconductor device further comprises: an interlayer dielectric layer, located on a side of the gate structure away from the second surface; a passivation layer, located on a side of the interlayer dielectric layer away from the second surface; The protection layer is located on a side of the passivation layer away from the second surface.

8. A method for preparing a semiconductor device, characterized in that: include: A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface arranged opposite to each other, the semiconductor body further comprising a well region, a first region and a second region, the first region and the second region being set to a first conductivity type and being located on the first surface, the well region being set to a second conductivity type and being located on a side of the first region away from the first surface; A gate structure is formed on the first surface of the semiconductor body, wherein the gate structure extends from the first surface to a predetermined position in the semiconductor body; and the first region and the second region are located on opposite sides of the gate structure; A source and a drain are formed on the first surface of the semiconductor body.

9. The method for preparing a semiconductor device according to claim 8, characterized in that: Providing a semiconductor body comprises: The well region and the first doped region are formed on the first surface of the semiconductor body, wherein the well region is located on a side of the first doped region away from the first surface, and the first doped region is set to a first conductivity type.

10. The method for preparing a semiconductor device according to claim 9, characterized in that: The forming of a gate structure on the first surface of the semiconductor body comprises: forming a trench on the first surface of the semiconductor body; The gate structure is formed in the trench.

11. The method for preparing a semiconductor device according to claim 10, characterized in that: The forming the gate structure in the trench comprises: forming an insulating layer in the trench; forming a gate groove on a surface of the insulating layer close to the first surface; A trench gate is formed in the gate trench.

12. A power module, characterized in that: It comprises a substrate and at least one semiconductor device according to any one of claims 1 to 7, wherein the substrate is used for carrying the semiconductor device.

13. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one semiconductor device according to any one of claims 1 to 7, wherein the semiconductor device is electrically connected to the circuit board.

14. A vehicle, characterized in that: It includes a load and a power conversion circuit as described in claim 13, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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