Shield gate field effect transistor for eliminating voltage clamping and preparation method thereof

Abstract

The invention discloses a shield gate field effect transistor for eliminating voltage clamping and a preparation method thereof, the shield gate field effect transistor comprises a shield gate, a control gate and source electrode metal, the shield gate and the control gate are located in a groove, the shield gate comprises a gate body part and an extension part, the gate body part is located below the control gate, the extension part extends upwards from the gate body part, and the source electrode metal is located in the groove. The extension part is led out from two sides of the control gate to the top of the groove, or the extension part is led out from one side of the control gate to the top of the groove; the top of the extension portion is in direct contact with the source metal by configuring a contact hole structure. Compared with an up-and-down structure of a shield grid and a control grid in a traditional SGT, a whole contact hole can be formed in the top of the extending part of the extended shield grid to be in direct contact with source electrode metal, shield grid resistance is eliminated, shield grid current and voltage are avoided, the voltage clamping problem introduced by shielding is eliminated, and the stability of the SGT is improved. Meanwhile, the charge balance effect and electric field distribution of the whole chip are improved, and current concentration is reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors, relates to medium and low voltage power devices, and is a shielded gate field effect transistor for eliminating voltage clamping and a preparation method thereof. Background Art

[0002] In the field of medium and low voltage power devices, trench MOSFETs are widely used in medium and low voltage high performance DC / DC converters, low voltage system motor control, motor drive and other fields due to their advantages of low on-resistance and fast switching speed. With the continuous development of technology, higher system response speed and circuit conversion efficiency, as well as lower power consumption and electromagnetic interference are required in terminal applications. All of these point to the need for shorter circuit opening and closing time. Selecting components with fast switching characteristics can significantly improve the switching speed.

[0003] In the medium and low voltage field, shielded gate trench power MOSFET (Shield / Split Gate Trench MOSFET, SGTMOSFET) is one of the most competitive power MOSFET devices at present. It is necessary to improve the switching speed of SGT devices and improve the performance of SGT devices under switching speed. Among them, the voltage clamping problem is a problem that is easily encountered in fast switching speed. Solving the voltage clamping problem is also an important issue in the development of SGT.

[0004] There are two common structures of shielded gate MOSFET. One is the left-right structure, in which the shield gate extends to the top of the trench, and the control gate is set on the left and right sides of the shield gate in the top area of ​​the trench, that is, the control gate is split into two and placed on the left and right sides of the shield gate. The disadvantage of this structure is that the control gate and the shield gate have a large overlapping area, which introduces a large input capacitance and easily causes the gate to be turned on by mistake.

[0005] The second is the up-down structure, that is, the shielding grid is placed entirely below the control grid. The disadvantage of this structure is that the shielding grid is not easy to lead out, resulting in uneven potential of the shielding grid, which affects the switching speed of the device. Figure 1-4As shown, the shielding gate 101 is used as a field plate, buried inside the trench, and covered with a gate oxide layer IPO and a control gate 102 of a certain thickness. From the perspective of looking down at the field effect transistor, the shielding gate can only be configured with contact holes from the upper and lower ends to lead out from the interlayer dielectric ILD and connect to the source metal 103. As a result, the shielding gate generates a parasitic resistance Rsp and a parasitic capacitance Csp. The farther the distance between the contact holes leading out of the upper and lower longitudinal shielding gates, the greater the parasitic resistance Rsp generated. In the application of SGT switches, when the drain voltage Vd changes, it will cause a displacement current Idif=Csp*dv / dt of the parasitic capacitance Csp. This current will increase through the shielding gate parasitic resistance Rsp and flow to the contact hole, thereby generating a voltage drop Vsp on Rsp, that is, the voltage difference between the drain end and the SG node, Vsp=Rsp*Idif=Rsp*Csp*dv / dt. During the device shutdown process, the time for Vsp to decrease to 0 will be longer due to the increase of Rsp, which will buffer the Vds reduction process, affect the device shutdown speed, and cause voltage clamping in fast switching applications, resulting in additional shoot-through losses. In severe cases, when the avalanche current of other cells that have been turned off flows to the cells that are not turned off, the current is concentrated in the turned-off cells, causing device failure. Summary of the invention

[0006] The technical problem to be solved by the present invention is that the switching speed of the shielded gate trench power MOSFET needs to be improved, wherein the voltage clamping problem affects the improvement of the switching speed, and the structure of the existing shielded gate trench power MOSFET cannot overcome the generation of voltage clamping.

[0007] The technical solution of the present invention is: a shielded gate field effect transistor that eliminates voltage clamping, including a shielding gate, a control gate and a source metal, the shielding gate and the control gate are located in a groove, the shielding gate includes a gate body part and an extension part, the gate body part is located below the control gate, the extension part extends upward from the gate body part, and is led out from the left and right sides of the control gate to the top of the groove, the shielding gate forms a "concave" shape, the control gate is sandwiched in the middle of the extension part, and the top of the extension part is in contact with the source metal by configuring a contact hole contact structure.

[0008] Furthermore, as another implementation, the extension portion extends upward from the gate body portion, leading out from the left or right side of the control gate to the top of the trench, and the top of the extension portion contacts the source metal by configuring a contact hole contact structure.

[0009] Furthermore, the extension portion of the shielding grid is arranged side by side with the control grid, and the contact hole contact structure is arranged along the top surface of the extension portion, presenting a side-by-side long strip shape.

[0010] The method for preparing the shielded gate field effect transistor for eliminating voltage clamping comprises the following steps: 1) Prepare the original wafer; 2) Trench etching to grow an oxide layer in the trench; 3) etching the oxide layer to form a first trench, and filling the first trench with polysilicon to form a shield gate; 4) etching the shield gate to form a second groove, retaining the shield gate on the left and right sides or one side during etching to form an extended portion, and the unetched portion forms a gate body; 5) depositing an oxide layer on the second trench etched in step 4), then etching the oxide layer to form a filling space for the control gate and a gate oxide layer, filling the gate polysilicon to obtain a control gate, and then undergoing a subsequent electrode process of a shielded gate field effect transistor to obtain the shielded gate field effect transistor that eliminates voltage clamping.

[0011] Furthermore, the shielding gate extension part and the control gate form a side-by-side structure in the trench, and the top width of the extension part is kept as large as possible to facilitate the preparation process of the contact hole while satisfying the space required by the control gate.

[0012] Compared with the upper and lower structures of the shield gate and the control gate in the traditional SGT, the present invention can open a whole contact line on the top of the extended shield gate extension part to directly contact the source metal, such as Figure 6 As shown, since there is no distance between the contact holes on the shielding gate, the shielding gate resistance Rsp is eliminated, thereby avoiding the shielding gate current voltage and the voltage clamping problem introduced by the shielding, while improving the charge balance effect and electric field distribution of the entire chip and reducing current concentration.

[0013] In the present invention, the structure in which the shielding gate extension part is led out on one side of the control gate reduces the input capacitance by half, which can further improve the switching speed. At the same time, compared with the solution of leading out the extension part on both sides, the solution of leading out only on one side of the control gate can reduce the groove space occupied by the extension part, which is beneficial to reducing the groove width, or when the groove size is fixed, compared with the solution of leading out on both sides, the single-side lead-out can be beneficial to increase the width of the led-out shielding gate. In this regard, on the one hand, the lower the device voltage, the narrower the gate pitch and the trench trench width, and the solution of leading out on one side is more suitable for low-voltage SGT devices. On the other hand, compared with the solution of leading out on both sides, the increase in the top width of the shielding gate extension part is beneficial to the subsequent contact hole and metal filling process, which can alleviate the process difficulty. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 FIG. 4 is a schematic diagram of the three-dimensional structure of a conventional SGT MOSFET in the prior art.

[0015] Figure 2 FIG. 1 is a top view of a conventional SGT MOSFET structure in the prior art.

[0016] Figure 3 For the corresponding Figure 2 Schematic diagram of the cross-section of the SGT MOSFET cell structure at the middle AA section.

[0017] Figure 4 For the corresponding Figure 2 Schematic diagram of the cross-section of the SGT MOSFET cell structure at the middle BB section.

[0018] Figure 5 It is a schematic structural diagram of the shielded gate field effect transistor embodiment 1 of the present invention.

[0019] Figure 6 It is a schematic diagram of the three-dimensional structure of the shielded gate field effect transistor embodiment 1 of the present invention.

[0020] Figure 7 It is a schematic structural diagram of the shielded gate field effect transistor embodiment 2 of the present invention.

[0021] Figure 8 It is a schematic structural diagram of the shielded gate field effect transistor embodiment 3 of the present invention.

[0022] Fig. 9 This is a schematic diagram of the preparation process of the shielded gate field effect transistor embodiment 1 of the present invention.

[0023] Fig.10 It is a schematic diagram of the preparation process of the shielded gate field effect transistor embodiment 2 of the present invention.

[0024] Fig.11 It is a simulation schematic diagram of the first embodiment of the shielded gate field effect transistor of the present invention.

[0025] Fig.12 The simulated electrical property result of the drain-source breakdown voltage BVDSS of the shielded gate field effect transistor embodiment 1 of the present invention shows a curve of the drain current Id-drain-source voltage Vds.

[0026] Fig.13 It is a simulation schematic diagram of the second embodiment of the shielded gate field effect transistor of the present invention.

[0027] Fig.14 The simulated electrical property result of the drain-source breakdown voltage BVDSS of the shielded gate field effect transistor embodiment 2 of the present invention shows a curve of the drain current Id-drain-source voltage Vds.

[0028] The reference numerals in the figure are: 101 - shielding gate, 102 - control gate, 103 - source metal, 104 - contact hole contact, 105 - interlayer dielectric ILD, 106 - N+ source region, 107 - P-type body region Pbody, 108 - N-type epitaxial layer Nepi, 109 - N-type substrate Nsub. DETAILED DESCRIPTION

[0029] The present invention proposes a shielded gate field effect transistor that eliminates voltage clamping. The shielded gate of the traditional upper and lower structure is extended to the surface, so that the shielded gate and the source metal are more easily in contact, thereby avoiding the potential unevenness caused by the long contact distance between the shielded gate and the source metal of the traditional SGT upper and lower structure, which in turn causes the clamping problem of the application and affects the use effect, thereby solving the clamping problem in fast switching applications.

[0030] The implementation of the present invention will be described below in conjunction with the accompanying drawings.

[0031] like Figure 5 As shown, the SGT of the first embodiment of the present invention includes a shielding gate 101, a control gate 102 and a source metal 103. The shielding gate 101 and the control gate 102 are located in the trench. The shielding gate 101 includes a gate body part and an extension part. The gate body part is located below the control gate 102. The extension part extends upward from the gate body part and is led out from the left and right sides of the control gate 102 to the top of the trench. The shielding gate 101 forms a "concave" shape, and the control gate 102 is sandwiched in the middle of the extension part. The top of the extension part is directly in contact with the source metal 103 through a contact hole contact104 structure. Figure 6 It can be seen that in the structure of the first embodiment of the present invention, the extension part of the shielding grid is arranged side by side with the control grid, so that the shielding grid extends to the surface of the groove, the contact hole contact structure is arranged along the top surface of the extension part, and a whole contact is opened on the extension part of the shielding grid. Figure 1 The existing technology can only configure contacts on the shield grid from both ends, eliminating the shield grid resistance Rsp, thereby avoiding the shield grid current voltage and eliminating the voltage clamping problem introduced by the shield. Fig.11 and Fig.12 The simulation results show that the shielded gate structure of the first embodiment can achieve a lateral charge coupling effect and achieve the same blocking effect as the traditional SGT. The first embodiment of the present invention describes the main structural features of the field effect transistor. The finished product of the shielded gate field effect transistor of the present invention mainly includes a shielding gate, a control gate and a source metal, and also includes a gate oxide, a field oxide, a P+ region, an N+ region, a dielectric layer, a passivation layer and other structures of a conventional shielded gate field effect transistor.

[0032] like Fig. 9 The preparation process of Example 1 is shown in FIG. The preparation process of Example 1 includes the following steps: 1) Prepare the original wafer; 2) Trench etching, growing an oxide layer in the trench; 3) etching the oxide layer to form a first trench, and filling the first trench with polysilicon to form a shield gate; 4) Etching the shield gate to a certain depth to form a second groove, retaining a certain width of the shield gate on both sides of the left and right sides during etching to form an extension part, and the unetched part forms the gate body part, and the shield gate forms a "concave" shape. The certain width is retained according to the process conditions, and the width and depth of the second groove are set according to the size parameters of the control gate; 5) Depositing an oxide layer on the second trench obtained by etching in step 4), and then etching the oxide layer to form a filling space and gate oxide layer for the control gate, and after filling the gate polysilicon, obtaining the control gate, and then undergoing the subsequent electrode process of the shielded gate field effect transistor, obtaining the shielded gate field effect transistor that eliminates voltage clamping. For example, after preparing the shielding gate and the control gate, P+ implantation and annealing → N+ implantation and annealing → interlayer oxide layer deposition → making contact holes (etching oxide layer and Si) → filling metal → depositing a passivation layer, and finally obtaining a complete SGT.

[0033] Among them, when preparing the extension part, due to the limited width of the trench, space for the control gate must be left, and the width of the lead-out shielding gate must be divided into two sides, which is relatively narrow, and has high requirements for filling, etching and packaging processes, such as Fig.11 As shown in the expanded diagram, under the two-side lead-out solution, the width of the top side of the extended part is 0.14um~0.16um, which has high process requirements.

[0034] The structure of the first embodiment can eliminate the problem of clamping voltage, but due to the large overlap area between the control gate and the shield gate extensions on both sides, a large input capacitance is introduced, and it is easy to cause the gate to be turned on by mistake. The present invention further proposes a single-side lead-out solution, and proposes the second and third embodiments, such as Figure 7 and Figure 8 As shown, the extension portion of the shielding gate 101 extends upward from the gate body portion and is led out from the left or right side of the control gate 102. The top of the extension portion is directly in contact with the source metal 103 through a contact hole contact104 structure.

[0035] The preparation process of Examples 2 and 3 is as follows Fig.10 As shown, the following steps are included: 1) Prepare the original wafer; 2) Trench etching, growing an oxide layer in the trench; 3) etching the oxide layer to form a first trench, and filling the first trench with polysilicon to form a shield gate; 4) etching the shield gate to a certain depth to form a second groove, retaining a certain width of the shield gate on one side during etching, and etching the other side to the oxide layer of step 2) to form an extended portion extending on one side, and the unetched portion at the bottom forms a gate body, wherein the certain width is retained according to the process conditions, and the width and depth of the second groove are set according to the size parameters of the control gate; 5) Deposit an oxide layer on the second trench obtained by etching in step 4), and then etch the oxide layer to form a filling space and gate oxide layer for the control gate. After filling the gate polysilicon, a control gate is obtained, and then the subsequent electrode process of the shielded gate field effect transistor is performed to obtain the shielded gate field effect transistor that eliminates voltage clamping. For example, after preparing the shielding gate and the control gate, P+ implantation and annealing → N+ implantation and annealing → interlayer oxide layer deposition → contact hole making (etching oxide layer and Si) → metal filling → passivation layer deposition, and finally a complete SGT is obtained.

[0036] Compared with the structure of the first embodiment, the structure of the second and third embodiments with the extension part led out on one side reduces the input capacitance by half, which can further improve the switching speed. At the same time, the led shielding grid is placed on one side of the control grid, which is conducive to increasing the width of the led shielding grid, such as Fig.13 On the one hand, it is more suitable for low-voltage SGT devices. On the other hand, since only one-side lead-out is required, under limited trench width, the widened shield gate top width can ease the difficulty of subsequent contact hole and metal filling processes. Compared with the first embodiment, the requirements for subsequent filling, etching and packaging processes of SGT devices can be reduced. At the same time, taking the conditions of ordinary SGT60V devices as the benchmark, such as Fig.14 It can be seen that the single-side lead-out solution can also achieve the lateral charge coupling effect and achieve the same blocking effect as the traditional SGT.

[0037] Fig.11 and Fig.13 It also shows the strength of the device's collision ionization rate, represented by color. The collision ionization rate is the number of electron-hole pairs ionized by carrier collision per unit distance. When the electric field of the semiconductor junction is strong enough, the electrons or holes obtain enough kinetic energy to excite the valence band electrons to the conduction band through collision, forming electron-hole pairs. This process will lead to an avalanche multiplication effect, affecting the breakdown voltage of the power device. The improved design of the SGT structure of the present invention does not affect the device's collision ionization, and the collision ionization situation is similar to that of the traditional SGT.

[0038] Furthermore, under the condition that the space required by the control gate is satisfied and the process can be achieved, the wider the top width of the extension portion of the present invention is, the more beneficial it is to the subsequent contact hole preparation process. It is preferred to retain as large a width as possible during preparation.

[0039] The present invention designs the shielded gate field effect transistor and leads out the shielded gate, which can reduce the clamping problem caused by uneven potential and avoid abnormalities in fast switching applications that affect the terminal use effect. The present invention can eliminate the influence of voltage clamping while achieving the same lateral charge coupling effect as the traditional SGT.

Claims

1. A shielded gate field effect transistor for eliminating voltage clamping, characterized in that It includes a shielding gate, a control gate and a source metal. The shielding gate and the control gate are located in the groove. The shielding gate includes a gate body part and an extension part. The gate body part is located below the control gate. The extension part extends upward from the gate body part and is led out from the left and right sides of the control gate to the top of the groove. The shielding gate forms a "concave" shape. The control gate is sandwiched in the middle of the extension part. The top of the extension part is in contact with the source metal through a contact hole contact structure.

2. A shielded gate field effect transistor for eliminating voltage clamping according to claim 1, characterized in that The extension part extends upward from the gate body part, and is led out from the left side or the right side of the control gate to the top of the groove. The top of the extension part contacts the source metal through a contact hole contact structure.

3. A shielded gate field effect transistor for eliminating voltage clamping according to claim 1 or 2, characterized in that The extended portion of the shielding grid is arranged side by side with the control grid, and the contact hole contact structure is arranged along the top surface of the extended portion, presenting a long strip shape arranged side by side.

4. A method for preparing a shielded gate field effect transistor for eliminating voltage clamping as claimed in claim 1 or 2, characterized in that The following steps are involved: 1) Prepare the original wafer; 2) Trench etching to grow an oxide layer in the trench; 3) etching the oxide layer to form a first trench, and filling the first trench with polysilicon to form a shield gate; 4) etching the shield gate to form a second groove, retaining the shield gate on the left and right sides or one side during etching to form an extended portion, and the unetched portion forms a gate body; 5) depositing an oxide layer on the second trench etched in step 4), then etching the oxide layer to form a filling space for the control gate and a gate oxide layer, filling the gate polysilicon to obtain a control gate, and then undergoing a subsequent electrode process of a shielded gate field effect transistor to obtain the shielded gate field effect transistor that eliminates voltage clamping.

5. The method for preparing a shielded gate field effect transistor for eliminating voltage clamping according to claim 4, characterized in that The shielding gate extension part and the control gate form a parallel structure in the trench. The top width of the extension part is kept as large as possible to facilitate the preparation process of the contact hole while meeting the space required by the control gate.

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