Groove MOSFET device and manufacturing method thereof

Abstract

The invention provides a trench MOSFET device and a manufacturing method thereof, and relates to the technical field of semiconductors. Comprising an N-type substrate; a first N-type epitaxial layer; the oxide layer is located on the surface layer of the first N-type epitaxial layer, and a low-K dielectric layer is arranged in the oxide layer; the second N-type epitaxial layer is positioned on the surface of the first N-type epitaxial layer and is provided with a groove region; the trench region is provided with a gate oxide layer and gate polycrystalline silicon, the gate oxide layer is located on the side wall of the trench region and surrounds the gate polycrystalline silicon, and the bottom of the gate polycrystalline silicon is in contact with the oxide layer; the P-type well region is located in the second N-type epitaxial layer, the N-type doped region and the PP region are located on the surface layer of the second N-type epitaxial layer, and the interlayer dielectric layer is located on the surface of the grid polycrystalline silicon. The ohmic contact layer is positioned on the surfaces of the PP region and the N-type doped region; and the first metal layer is positioned on the surfaces of the ohmic contact layer and the interlayer dielectric layer. The method has the advantages that the gate-oxide failure probability is greatly reduced, and the gate-oxide reliability and the device robustness are improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a trench MOSFET device and a method for manufacturing the same. Background Art

[0002] For Si IGBT or Si MOSFET, the trench gate structure design has obvious performance advantages over the planar gate structure, but for SiC MOSFET, this advantage is no longer significant.

[0003] According to Gauss's theorem, the electric field strength on the gate SiO2 surface of the SiC MOSFET is about 2.5 times that of the corresponding SiC surface (E ox =2.5E sic ), because silicon carbide materials are known for their high critical breakdown electric field strength (about 10 times that of silicon materials), the electric field strength that the gate SiO2 in SiC MOSFET withstands is extremely high, an order of magnitude higher than the electric field strength that the gate SiO2 in Si MOSFET / IGBT withstands. Therefore, the reliability of the gate SiO2 in SiC MOSFET faces serious challenges.

[0004] On this basis, the gate oxide reliability problem in trench SiC MOSFET design is more serious, because the trench gate corner close to 90° further aggravates the concentration of power lines, and the gate oxide layer here is extremely susceptible to breakdown.

[0005] In summary, the prior art has the problems that the corners of the trench MOSFET are easily broken down, the gate oxide failure rate is high, and the device reliability and robustness are poor. Summary of the invention

[0006] The purpose of the present application is to provide a trench MOSFET device and a method for manufacturing the same, so as to solve the problems existing in the prior art that the corners of the trench gate MOSFET are easily broken down, the gate oxide failure rate is high, and the device reliability and robustness are poor.

[0007] In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows: On the one hand, an embodiment of the present application provides a trench MOSFET device, wherein the trench MOSFET device comprises: N-type substrate; A first N-type epitaxial layer located on the surface of the substrate; An oxide layer located on the surface of the first N-type epitaxial layer, wherein a low-K dielectric layer is disposed in the oxide layer; A second N-type epitaxial layer is located on the surface of the first N-type epitaxial layer, the second N-type epitaxial layer is provided with a trench region; a gate oxide layer and gate polysilicon are provided in the trench region, the gate oxide layer is located on the sidewall of the trench region and is provided around the gate polysilicon, and the bottom of the gate polysilicon is in contact with the oxide layer; wherein the thickness of the oxide layer is greater than the thickness of the gate oxide layer, the width of the oxide layer is greater than the width of the trench region, and the width of the low-K dielectric layer is less than the width of the trench region; A P-type well region located in the second N-type epitaxial layer and an N-type doped region and a PP region located on the surface of the second N-type epitaxial layer, wherein the N-type doped region is located on the surface of the P-type well region, and both sides of the N-type doped region and the P-type well region are in contact with the PP region and the gate oxide layer respectively; An interlayer dielectric layer located on the surface of the gate polysilicon; An ohmic contact layer located on the surface of the PP region and the N-type doped region; A first metal layer located on the surface of the ohmic contact layer and the interlayer dielectric layer; A second metal layer is located on the back side of the substrate.

[0008] Optionally, the PP region extends to the first N-type epitaxial layer, and a bottom of the PP region is deeper than the oxide layer.

[0009] Optionally, the trench MOSFET devices are symmetrically arranged about a central axis of the trench region.

[0010] Optionally, the gate polysilicon includes a first polysilicon layer, a second polysilicon layer and a third polysilicon layer arranged layer by layer from bottom to top, and the doping concentration of the second polysilicon layer is greater than the doping concentration of the first polysilicon layer and the third polysilicon layer; A bottom height of the second polysilicon is not lower than a bottom height of the P-type well region, and a top height of the second polysilicon is not higher than a top height of the P-type well region.

[0011] Optionally, the depth of the second polysilicon is half of the depth of the P-type well region, and the top height of the second polysilicon is level with the top height of the P-type well region.

[0012] Optionally, the second polysilicon layer includes a first sublayer and a second sublayer, the first sublayer and the second sublayer are spaced apart, the first sublayer contacts the gate oxide layer on the left side of the trench region, and the second sublayer contacts the gate oxide layer on the right side of the trench region.

[0013] Optionally, the depth of the low-K dielectric layer is equal to the depth of the oxide layer.

[0014] Optionally, the oxide layer is configured as an arc-shaped structure.

[0015] On the other hand, an embodiment of the present application further provides a method for manufacturing a trench MOSFET device, which is used to manufacture the above-mentioned trench MOSFET device, and the method comprises: Providing an N-type substrate; Fabricating a first N-type epitaxial layer based on the surface of the substrate; Forming a first trench based on a surface layer of the first N-type epitaxial layer, and forming an oxide layer based on the first trench; A second N-type epitaxial layer is fabricated based on the surface of the first N-type epitaxial layer, wherein the second N-type epitaxial layer is provided with a trench region; a gate oxide layer and gate polysilicon are provided in the trench region, wherein the gate oxide layer is located on the sidewall of the trench region and is arranged around the gate polysilicon, and the bottom of the gate polysilicon is in contact with the oxide layer; wherein the thickness of the oxide layer is greater than the thickness of the gate oxide layer, the width of the oxide layer is greater than the width of the trench region, and the width of the low-K dielectric layer is less than the width of the trench region; the second N-type epitaxial layer further comprises a P-type well region and an N-type doped region and a PP region located on the surface layer of the second N-type epitaxial layer, wherein the N-type doped region is located on the surface of the P-type well region, and both sides of the N-type doped region and the P-type well region are in contact with the PP region and the gate oxide layer respectively; Fabricating an interlayer dielectric layer based on the surface of the gate polysilicon; Fabricating an ohmic contact layer based on the surfaces of the PP region and the N-type doped region; Fabricate a first metal layer based on the surfaces of the ohmic contact layer and the interlayer dielectric layer; A second metal layer is formed on the back side of the substrate.

[0016] Optionally, the step of manufacturing the second N-type epitaxial layer based on the surface of the first N-type epitaxial layer includes: Growing a second N-type epitaxial layer based on the surface of the first N-type epitaxial layer; wherein a trench region is provided in the second N-type epitaxial layer, and the trench region exposes the oxide layer; Based on the second N-type epitaxial layer, ion implantation in the P-type well region, ion implantation in the N-type doping region, ion implantation in the PP region and ion implantation in the terminal region are sequentially performed, and high-temperature furnace tube annealing is performed; Etching the oxide layer based on the bottom of the trench region to form a second trench; Filling the low-K dielectric layer based on the second trench and etching back; Oxidizing the sidewalls of the trench region to form a gate oxide layer; Polysilicon deposition and etching are performed based on the trench region to form a complete gate structure.

[0017] Compared with the prior art, this application has the following beneficial effects: The present application provides a trench MOSFET device and a manufacturing method thereof, wherein the trench MOSFET device comprises: an N-type substrate; a first N-type epitaxial layer located on the surface of the substrate; an oxide layer located on the surface of the first N-type epitaxial layer, wherein a low-K dielectric layer is arranged in the oxide layer; a second N-type epitaxial layer located on the surface of the first N-type epitaxial layer, wherein the second N-type epitaxial layer is provided with a trench region; a gate oxide layer and gate polysilicon are arranged in the trench region, wherein the gate oxide layer is located on the sidewall of the trench region and surrounds the gate polysilicon, and the bottom of the gate polysilicon contacts the oxide layer; wherein the thickness of the oxide layer is The thickness of the low-K dielectric layer is greater than the thickness of the gate oxide layer, the width of the oxide layer is greater than the width of the trench region, and the width of the low-K dielectric layer is less than the width of the trench region; the P-type well region located in the second N-type epitaxial layer and the N-type doped region and PP region located on the surface of the second N-type epitaxial layer, the N-type doped region is located on the surface of the P-type well region, and the two sides of the N-type doped region and the P-type well region are respectively in contact with the PP region and the gate oxide layer; the interlayer dielectric layer located on the surface of the gate polysilicon; the ohmic contact layer located on the surface of the PP region and the N-type doped region; the first metal layer located on the surface of the ohmic contact layer and the interlayer dielectric layer; the second metal layer located on the back of the substrate.

[0018] On the one hand, since a thicker oxide layer is provided at the bottom of the gate polysilicon, and the width of the oxide layer is greater than the width of the trench area, the peak electric field strength at the corner of the trench can be effectively reduced, the probability of gate oxide failure is greatly reduced, and the gate oxide reliability and device robustness are improved. At the same time, the thick oxide at the bottom of the gate polysilicon increases the gate-drain parasitic capacitance C gd The equivalent thickness of the gate-drain parasitic capacitance C gd , which improves the Miller effect of the device, increases the switching frequency of the device, reduces the switching loss of the device, and also prevents the device from mis-conducting under high dV / dt conditions. On the other hand, since a low-K dielectric layer is provided in the oxide layer, the gate-drain parasitic capacitance C gd The effect of equivalent area and equivalent thickness can further reduce the gate-drain parasitic capacitance C of the device. gd , increasing the device switching frequency, reducing the device power loss, and further preventing the device mis-turn-on problem caused by high dV / dt.

[0019] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 It is a cross-sectional schematic diagram of a trench MOSFET in the prior art.

[0022] Figure 2 A schematic diagram of a first cross-sectional structure of a trench MOSFET device provided in an embodiment of the present application.

[0023] Figure 3 This is an equivalent circuit diagram of a trench MOSFET device provided in an embodiment of the present application.

[0024] Figure 4 A schematic diagram of parameters of a trench MOSFET device provided in an embodiment of the present application.

[0025] Figure 5 A schematic diagram of a second cross-sectional structure of a trench MOSFET device provided in an embodiment of the present application.

[0026] Figure 6 A third cross-sectional structural schematic diagram of a trench MOSFET device provided in an embodiment of the present application.

[0027] Figure 7 A fourth cross-sectional structural schematic diagram of a trench MOSFET device provided in an embodiment of the present application.

[0028] Figure 8 This is a schematic diagram of the cross-sectional structure corresponding to the production of the first N-type epitaxial layer provided in an embodiment of the present application.

[0029] Fig. 9 This is a schematic diagram of the cross-sectional structure corresponding to the production of the oxide layer provided in an embodiment of the present application.

[0030] Fig.10 This is a schematic diagram of the cross-sectional structure corresponding to the production of the second N-type epitaxial layer provided in an embodiment of the present application.

[0031] Fig.11 This is a schematic diagram of the cross-sectional structure corresponding to the high-temperature furnace tube after annealing provided in an embodiment of the present application.

[0032] Fig.12 This is a schematic diagram of the corresponding cross-sectional structure after the second groove is manufactured according to an embodiment of the present application.

[0033] icon: 110-substrate; 120-first N-type epitaxial layer; 130-oxide layer; 140-low-K dielectric layer; 150-second N-type epitaxial layer; 160-gate polysilicon; 161-first polysilicon layer; 162-second polysilicon layer; 163-third polysilicon layer; 1621-first sublayer; 1622-second sublayer; 170-gate oxide layer; 180-P-type well region; 190-N-type doped region; 200-PP region; 210-interlayer dielectric layer; 220-ohmic contact layer; 230-first metal layer; 240-second metal layer. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0035] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0036] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0037] It should be noted that, in this document, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0038] In the description of the present application, it should be noted that the terms "upper", "lower", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the product of the application is usually placed when in use. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0039] As described in the background technology, in the trench SiC MOSFET, the trench gate corner close to 90° further aggravates the concentration of the electric line, so the trench MOSFET corner is easily broken down, the gate oxide failure rate is high, and the device reliability and robustness are poor.

[0040] For example, see Figure 1 , is a cross-sectional schematic diagram of a trench MOSFET in the prior art. When the device is in a high blocking voltage state, the electric field at the bottom corner of the trench gate (position A in the figure) is more concentrated, which is very likely to exceed the maximum critical electric field strength, thereby causing the gate oxide layer to be broken down, affecting the reliability of the device. Therefore, it is of great significance to design and manufacture a trench MOSFET with high gate oxide reliability and low failure rate.

[0041] In view of this, in order to solve the above problems, an embodiment of the present application provides a trench MOSFET device, which optimizes the structure of the gate oxide layer corners so that the gate oxide layer corners are not easily broken down, thereby reducing the gate oxide failure rate and improving the reliability and robustness of the device.

[0042] The following is an exemplary description of the trench MOSFET device provided by the present application: As an alternative implementation, see Figure 2 The trench MOSFET device comprises: an N-type substrate 110; a first N-type epitaxial layer 120 located on the surface of the substrate 110; an oxide layer 130 located on the surface of the first N-type epitaxial layer 120, wherein a low-K dielectric layer 140 is arranged in the oxide layer 130; a second N-type epitaxial layer 150 located on the surface of the first N-type epitaxial layer 120, wherein the second N-type epitaxial layer 150 is provided with a trench region; a gate oxide layer 170 and a gate polysilicon 160 are arranged in the trench region, wherein the gate oxide layer 170 is located on the sidewall of the trench region and is arranged around the gate polysilicon 160, and the bottom of the gate polysilicon 160 is in contact with the oxide layer 130; wherein the thickness of the oxide layer 130 is greater than the thickness of the gate oxide layer 170, and the width of the oxide layer 130 is greater than the width of the gate oxide layer 170. The width of the low-K dielectric layer 140 is smaller than the width of the trench region; the P-type well region 180 located in the second N-type epitaxial layer 150 and the N-type doped region 190 and the PP region 200 located on the surface of the second N-type epitaxial layer 150, the N-type doped region 190 is located on the surface of the P-type well region 180, and the two sides of the N-type doped region 190 and the P-type well region 180 are in contact with the PP region 200 and the gate oxide layer 170 respectively; the interlayer dielectric layer 210 located on the surface of the gate polysilicon 160; the ohmic contact layer 220 located on the surface of the PP region 200 and the N-type doped region 190; the first metal layer 230 located on the surface of the ohmic contact layer 220 and the interlayer dielectric layer 210; the second metal layer 240 located on the back side of the substrate 110.

[0043] Figure 2In the figure, N+ sub represents an N-type substrate, N- epi represents an N-type epitaxial layer, N+ CSL1 represents an N+ type extension layer, and the N- epitaxial layer and the N+ type extension layer constitute a first N-type epitaxial layer 120 .

[0044] It should be noted that, in the present application, “X is located on the surface layer of Y” means that X is located in Y and exposed above Y; and “X is located on the surface of Y” means that X and Y are two independent parts, X is located above Y, and X and Y are in contact.

[0045] On the one hand, since a thicker oxide layer 130 is provided at the bottom of the gate polysilicon 160, and the width of the oxide layer 130 is greater than the width of the trench area, the peak electric field strength at the trench corner can be effectively reduced, the probability of gate oxide failure is greatly reduced, and the gate oxide reliability and device robustness are improved. At the same time, the thick oxide at the bottom of the gate polysilicon 160 increases the gate-drain parasitic capacitance C gd The equivalent thickness of the gate-drain parasitic capacitance C gd , improves the Miller effect of the device, increases the switching frequency of the device, reduces the switching loss of the device, and also prevents the device from mis-conduction under high dV / dt conditions. Specifically, according to the delay formula t=Rg-int *C gd , t represents the delay time, Rg-int represents the gate polysilicon equivalent resistance, it can be seen that when the gate-drain parasitic capacitance C gd When the delay time is reduced, the switching frequency of the device can be increased. On the other hand, since the oxide layer 130 is provided with a low-K dielectric layer 140, the gate-drain parasitic capacitance C gd The effect of equivalent area and equivalent thickness can further reduce the gate-drain parasitic capacitance C of the device. gd , increasing the device switching frequency, reducing the device power loss, and further preventing the device mis-turn-on problem caused by high dV / dt.

[0046] The first N-type epitaxial layer 120 and the second N-type epitaxial layer 150 provided in the present application may both be SiC epitaxial layers.

[0047] In the trench MOSFET device provided in the present application, the oxide layer 130 is configured as an arc structure. By configuring the thicker oxide layer 130 at the bottom of the gate polysilicon to be arc-shaped, a buffering effect can be provided for the drain-source high voltage electric field, further reducing the electrical stress borne by the oxide layer at the corner of the trench gate, and greatly improving the breakdown voltage and avalanche reliability of the device.

[0048] Moreover, the width of the oxide layer 130 is greater than the width of the trench area, and the bottom of the trench can be wrapped by the oxide layer 130, thereby alleviating the concentration of electric lines at the corners of the trench gate, thereby effectively reducing the peak electric field strength at the corners of the trench, greatly reducing the probability of gate oxide failure, and improving gate oxide reliability and device robustness.

[0049] It should be noted that the width of the oxide layer 130 described in the present application refers to the maximum width of the oxide layer 130 .

[0050] Furthermore, in the device, the gate polysilicon 160 is regarded as one plate, and the drain (i.e., the second metal layer 240) is regarded as another plate, which can constitute the gate-drain parasitic capacitance of the entire device. After the oxide layer 130 is set, the dielectric constant between the two plates can be effectively lowered (the dielectric constant of SiC is about 9.7, and the dielectric constant of the oxide layer 130 is about 3.9). According to the formula C=ε*A / d, C represents the capacitance value, ε represents the dielectric constant of the dielectric, A represents the facing area of ​​the two plates, and d represents the distance between the two plates.

[0051] It can be seen that after the oxide layer 130 is provided, the gate-drain parasitic capacitance C is reduced. gd , improves the Miller effect of the device, increases the switching frequency of the device, and reduces the switching loss of the device. At the same time, please refer to Figure 3 , is the equivalent circuit diagram of the trench MOSFET device. In the figure, Rg-int represents the gate polysilicon equivalent resistance, C gd Represents the gate-drain parasitic capacitance, C gs Represents the gate-source parasitic capacitance, C DS Represents the drain-source parasitic capacitance. When the gate-drain parasitic capacitance C gd After the reduction, the problem of device mis-conduction caused by high dV / dt conditions can be effectively prevented.

[0052] At the same time, depositing a low-K dielectric layer 140 in the oxide layer 130 can further reduce the dielectric constant between the two plates, thereby further reducing the gate-drain parasitic capacitance C of the device. gd , thereby increasing the switching frequency of the device and reducing the power loss of the device, and further preventing the device from mis-turning on due to high dV / dt. It should be noted that the dielectric constant of the low-K dielectric layer 140 described in the present application is at least smaller than the dielectric constant of the oxide layer 130.

[0053] In addition, for the parameter design of the low-K dielectric layer 140, please refer to Figure 4In the figure, H0 represents the thickness of the oxide layer, Hd represents the thickness of the low-K dielectric layer, Lw represents the width of the low-K dielectric layer, L0 represents the maximum width of the oxide layer, and Lp represents the width of the trench region. In terms of parameter setting, it is necessary to satisfy that the width of the low-K dielectric layer 140 is smaller than the width of the trench region, that is, Lw<Lp, and at the same time, it is necessary to satisfy L0>Lp. The thickness of the low-K dielectric layer 140 needs to be less than or equal to the thickness of the oxide layer 130, that is, Hd≤H0. By reducing the gate-drain parasitic capacitance C gd The equivalent dielectric constant of the device can be further reduced to further reduce the gate-drain parasitic capacitance C gd Moreover, in theory, the smaller the width Lw of the low-K dielectric layer 140 and the larger the thickness Hd, the lower the gate-drain parasitic capacitance C of the device. gd In view of this, as an implementation method, the present application sets the depth of the low-K dielectric layer 140 to be equal to the depth of the oxide layer 130, that is, Hd=H0.

[0054] The PP region 200 has the functions of reducing base resistance and improving device breakdown characteristics. In one implementation, see Figure 5 , the PP region 200 extends to the first N-type epitaxial layer 120, and the bottom of the PP region 200 is deeper than the oxide layer 130. Through this setting, the thick oxide layer 130 at the bottom of the gate polysilicon 160 can cooperate with the "pinch-off" of the PP region 200 and the depletion region of the N-type epitaxial layer to shield the protective gate oxide layer 170, play a buffering role on the drain-source high voltage electric field, reduce the electrical stress on the oxide layer at the corner of the trench gate, and improve the breakdown voltage and avalanche reliability of the device. And when the low-K dielectric thickness Hd = the thickness of the thick oxide layer at the bottom of the gate polysilicon H0, that is, the bottom is flat, according to Gauss's theorem, the trench gate oxide layer can further withstand the largest possible peak electric field, greatly improving the breakdown voltage and avalanche reliability of the device.

[0055] It should be noted that the trench MOSFET device provided in the present application is symmetrically arranged about the central axis of the trench region, that is, the overall structure of the PP region 200, the oxide layer 130 and the low-K dielectric layer 140 is symmetrical to the gate trench structure, which can balance the material internal stress and thermal stress of the device and improve the reliability and robustness of the device.

[0056] In one implementation, see Figure 6 The gate polysilicon 160 includes a first polysilicon layer 161, a second polysilicon layer 162 and a third polysilicon layer 163 arranged layer by layer from bottom to top. Figure 6In the figure, Poly represents polysilicon. The doping concentration of the second polysilicon layer 162 is greater than the doping concentration of the first polysilicon layer 161 and the third polysilicon layer 163. For example, the first polysilicon layer 161 and the third polysilicon layer 163 are both doped with N+, and the second polysilicon layer 162 is doped with N++. In practical applications, the production of a low-high-low three-stage polysilicon layer can be achieved by adjusting the deposition process. In addition, the bottom height of the second polysilicon is not lower than the bottom height of the P-type well region 180, and the top height of the second polysilicon is not higher than the top height of the P-type well region 180.

[0057] By introducing the second polysilicon layer 162 with a higher doping concentration, on the one hand, the purpose of changing the work function can be achieved, thereby enhancing the device gate control capability and the corresponding minority carrier inversion effect, and reducing the threshold voltage V th , reducing the channel resistance R ch , thereby reducing the switching speed of the device and the switching loss of the device. On the other hand, it helps to make the electric field distribution in the gate oxide layer SiO2 more uniform, reduce the electric field concentration phenomenon, and avoid excessive electric field strength in certain local areas of SiO2, thereby reducing the risk of gate oxide breakdown and improving the reliability of the device.

[0058] Specifically, when in high dV / dt conditions, such as grid voltage fluctuations and spike voltages generated by line stray inductance at the moment of switching, the gate-drain parasitic capacitance C gd The coupled transition current flows through the gate resistor Rg-int, causing the gate-source voltage V GS When the gate-source voltage V GS Exceeding the device threshold voltage V th Therefore, it is necessary to minimize the gate-drain parasitic capacitance C gd , the gate resistance Rg-int can effectively reduce the probability of device mis-turn-on. By introducing a second polysilicon layer with a higher doping concentration, on the one hand, the gate polysilicon equivalent resistance Rg-int can be reduced, thereby reducing the probability of device mis-turn-on and improving the reliability and robustness of the device. On the other hand, according to the delay time t=Rg-int*C gd Formula, reducing the gate polysilicon equivalent resistance Rg-int can increase the device switching speed and reduce the device switching loss. That is, in this application, by providing the oxide layer 130, the low-K dielectric layer 140 and the second polysilicon layer 162, the gate-drain parasitic capacitance C can be reduced at the same time. gd , the effect of gate resistance Rg-int, which can greatly increase the switching frequency of the device.

[0059] Regarding the parameters of the second polysilicon layer 162, the present application sets them as follows: H2+H3≤H NP +H PW; Wherein, H2 represents the thickness of the second polysilicon layer 162, H3 represents the thickness of the third polysilicon layer 163, H NP represents the thickness of the N-type doping region 190, H pw represents the thickness of the P-type well region 180. And the bottom of the second polysilicon layer 162 cannot exceed the bottom of the P-type well region 180. At the same time, H3≥H NP , that is, the top of the second polysilicon layer 162 cannot exceed the top of the P-type well region 180, so the entire second polysilicon layer 162 is limited to the surface of the channel region of the P-type well region, which is conducive to flexibly adjusting the gate resistance Rg-int and the threshold voltage V by adjusting the size of H2 and H3. th , channel resistance R ch , gate oxide breakdown and other characteristics, thereby flexibly improving the electrical performance of the device such as switching speed, switching loss, as well as the reliability and robustness of the device.

[0060] At the same time, within the range allowed by the device electrical performance and reliability, the distance H1 (the difference between the thickness of the selective epitaxial layer and the thickness of the P-type well region 180 and the N-type doped region 190, H2) between the second polysilicon layer 162 and the oxide layer 130 at the bottom of the gate polysilicon 160 and the low-K dielectric is epi -H NP -H PW ) The larger the better, which can reduce the internal material stress of the overall gate structure and the thermal stress after annealing activation, greatly improving the reliability and robustness of the device.

[0061] On this basis, the depth of the second polysilicon layer 162 set in the present application is half the depth of the P-type well region 180, and the top height of the second polysilicon layer 162 is level with the top height of the P-type well region 180. The thickness of the first polysilicon layer 161 is maximized, and the material internal stress of the overall gate structure (mainly the stress between the oxide layer 130 at the bottom of the gate polysilicon 160 and the low-K dielectric layer 140) and the thermal stress after annealing activation can be reduced to the greatest extent, greatly improving the reliability and robustness of the device.

[0062] It should be noted that under this setting, the delay time t=Rg-int*C gd The minimum gate material internal stress and thermal stress after annealing activation are minimized, so the reliability and robustness of the device can reach the best state.

[0063] As an implementation, see Figure 7, the second polysilicon layer 162 can also be made into two parts, namely, the second polysilicon layer 162 includes a first sublayer 1621 and a second sublayer 1622, the first sublayer 1621 and the second sublayer 1622 are arranged at intervals, and the first sublayer 1621 contacts the gate oxide layer 170 on the left side of the trench area, and the second sublayer 1622 contacts the gate oxide layer 170 on the right side of the trench area.

[0064] It can be understood that the present application can flexibly adjust the gate resistance Rg-int and the threshold voltage V by flexibly adjusting the values ​​of H1, H2, and H3. th , channel resistance R ch , gate oxide breakdown and other characteristics, and can also achieve the effect of adjusting the internal stress and thermal stress of the device material, flexibly adjust and improve the electrical properties such as device switching speed, switching loss, as well as the reliability and robustness of the device.

[0065] Based on the above implementation, the embodiment of the present application further provides a method for manufacturing a trench MOSFET device, which is used to manufacture the above trench MOSFET device. The method includes: S102, providing an N-type substrate.

[0066] S104, forming a first N-type epitaxial layer based on the substrate surface.

[0067] S106 , forming a first trench based on the surface layer of the first N-type epitaxial layer, and forming an oxide layer based on the first trench.

[0068] S108, a second N-type epitaxial layer is manufactured based on the surface of the first N-type epitaxial layer, wherein the second N-type epitaxial layer is provided with a trench region; a gate oxide layer and gate polysilicon are provided in the trench region, the gate oxide layer is located on the sidewall of the trench region and is provided around the gate polysilicon, and the bottom of the gate polysilicon is in contact with the oxide layer; wherein the thickness of the oxide layer is greater than the thickness of the gate oxide layer, the width of the oxide layer is greater than the width of the trench region, and the width of the low-K dielectric layer is less than the width of the trench region; the second N-type epitaxial layer also includes a P-type well region and an N-type doped region and a PP region located on the surface layer of the second N-type epitaxial layer, the N-type doped region is located on the surface of the P-type well region, and the two sides of the N-type doped region and the P-type well region are in contact with the PP region and the gate oxide layer respectively.

[0069] S110, forming an interlayer dielectric layer based on the surface of the gate polysilicon.

[0070] S112, manufacturing an ohmic contact layer based on the surfaces of the PP region and the N-type doped region.

[0071] S114, manufacturing a first metal layer based on the surfaces of the ohmic contact layer and the interlayer dielectric layer.

[0072] S116, manufacturing a second metal layer based on the back side of the substrate.

[0073] The trench MOSFET device provided by the present application is exemplarily described below with reference to the accompanying drawings: First, see Figure 8 , a first N-type epitaxial layer is fabricated based on the substrate surface, wherein N+ sub represents an N-type substrate, N- epi represents an N-type epitaxial layer, and N+ CSL1 represents an N+ type extension layer. N-type ion implantation is performed in the N-type epitaxial layer to form the N+ CSL1 layer shown in the figure. It should be noted that the first N-type epitaxial layer described in the present application includes an N- epi layer and an N+ CSL1 layer.

[0074] Afterwards, see Fig. 9 , a first groove is made based on the surface layer of the first N-type epitaxial layer, and an oxide layer is made based on the first groove. Among them, by adjusting the photolithography and etching process parameters, the first groove can be structurally arc-shaped, which can buffer the drain-source high voltage electric field, further reduce the electrical stress of the oxide layer at the corner of the trench gate, and greatly improve the breakdown voltage and avalanche reliability of the device. In addition, after etching the first groove, the oxide layer can be formed by thermal oxidation process or deposition of SiO2 and etching back process.

[0075] Next, a second N-type epitaxial layer is formed based on the surface of the first N-type epitaxial layer. S108 includes: A second N-type epitaxial layer is grown on the surface of the first N-type epitaxial layer; wherein a trench region is provided in the second N-type epitaxial layer, and the oxide layer is exposed in the trench region. Fig.10 , N+ CSL2 represents the second N-type epitaxial layer. Since an oxide layer is provided in the middle region, when the second N-type epitaxial layer is generated, the second N-type epitaxial layer is selectively grown on the left and right sides, and a trench region is formed above the oxide layer.

[0076] Afterwards, based on the second N-type epitaxial layer, P-type well region ion implantation, N-type doping region ion implantation, PP region ion implantation and terminal region ion implantation are sequentially performed, and high-temperature furnace tube annealing is performed. The structure after annealing is as follows Fig.11 It should be noted that the depth of ion implantation in the PP region can be adjusted according to actual needs. When the bottom of the PP region is deeper than the oxide layer, it can buffer the drain-source high voltage electric field, reduce the electrical stress on the oxide layer at the corner of the trench gate, and improve the breakdown voltage and avalanche reliability of the device.

[0077] Then, the low-K dielectric layer is fabricated. The oxide layer is first etched based on the bottom of the trench region to form a second trench. Fig.12 As shown, a low-K dielectric layer is then filled in the second trench and etched back.

[0078] Then, oxidation is performed based on the sidewall of the trench area to form a gate oxide layer. Polysilicon deposition and etching are performed based on the trench area to form gate polysilicon. It should be noted that when a multi-layer gate polysilicon structure needs to be made, the deposition process can be adjusted to form a first polysilicon layer, a second polysilicon layer and a third polysilicon layer arranged layer by layer from bottom to top, and the doping concentration of the second polysilicon layer is greater than the doping concentration of the first polysilicon layer and the third polysilicon layer.

[0079] Finally, the interlayer dielectric layer, the ohmic contact layer, the first metal layer and the second metal layer are manufactured, which will not be described in detail here.

[0080] In summary, the present application provides a trench MOSFET device and a manufacturing method thereof, wherein the trench MOSFET device comprises: an N-type substrate; a first N-type epitaxial layer located on the surface of the substrate; an oxide layer located on the surface of the first N-type epitaxial layer, wherein a low-K dielectric layer is provided in the oxide layer; a second N-type epitaxial layer located on the surface of the first N-type epitaxial layer, wherein the second N-type epitaxial layer is provided with a trench region; a gate oxide layer and a gate polysilicon are provided in the trench region, wherein the gate oxide layer is located on the sidewall of the trench region and surrounds the gate polysilicon, and the bottom of the gate polysilicon is in contact with the oxide layer; wherein the oxide layer The thickness is greater than the thickness of the gate oxide layer, the width of the oxide layer is greater than the width of the trench area, and the width of the low-K dielectric layer is less than the width of the trench area; the P-type well region located in the second N-type epitaxial layer and the N-type doped region and PP region located on the surface of the second N-type epitaxial layer, the N-type doped region is located on the surface of the P-type well region, and the two sides of the N-type doped region and the P-type well region are in contact with the PP region and the gate oxide layer respectively; the interlayer dielectric layer located on the surface of the gate polysilicon; the ohmic contact layer located on the surface of the PP region and the N-type doped region; the first metal layer located on the surface of the ohmic contact layer and the interlayer dielectric layer; the second metal layer located on the back of the substrate. On the one hand, since a thicker oxide layer is provided at the bottom of the gate polysilicon, and the width of the oxide layer is greater than the width of the trench area, the peak electric field strength at the corner of the trench can be effectively reduced, the probability of gate oxide failure is greatly reduced, and the gate oxide reliability and device robustness are improved. At the same time, the thick oxide at the bottom of the gate polysilicon increases the gate-drain parasitic capacitance C gd The equivalent thickness of the gate-drain parasitic capacitance C gd , which improves the Miller effect of the device, increases the switching frequency of the device, reduces the switching loss of the device, and also prevents the device from mis-conducting under high dV / dt conditions. On the other hand, since a low-K dielectric layer is provided in the oxide layer, the gate-drain parasitic capacitance C gd The effect of equivalent area and equivalent thickness can further reduce the gate-drain parasitic capacitance C of the device. gd , increasing the device switching frequency, reducing the device power loss, and further preventing the device mis-turn-on problem caused by high dV / dt.

[0081] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0082] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above, and that the present application can be implemented in other specific forms without departing from the spirit or essential features of the present application. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present application. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A trench MOSFET device, characterized in that: The trench MOSFET device comprises: N-type substrate; A first N-type epitaxial layer located on the surface of the substrate; An oxide layer located on the surface of the first N-type epitaxial layer, wherein a low-K dielectric layer is disposed in the oxide layer; A second N-type epitaxial layer is located on the surface of the first N-type epitaxial layer, the second N-type epitaxial layer is provided with a trench region; a gate oxide layer and gate polysilicon are provided in the trench region, the gate oxide layer is located on the sidewall of the trench region and is provided around the gate polysilicon, and the bottom of the gate polysilicon is in contact with the oxide layer; wherein the thickness of the oxide layer is greater than the thickness of the gate oxide layer, the width of the oxide layer is greater than the width of the trench region, and the width of the low-K dielectric layer is less than the width of the trench region; A P-type well region located in the second N-type epitaxial layer and an N-type doped region and a PP region located on the surface of the second N-type epitaxial layer, wherein the N-type doped region is located on the surface of the P-type well region, and both sides of the N-type doped region and the P-type well region are in contact with the PP region and the gate oxide layer respectively; An interlayer dielectric layer located on the surface of the gate polysilicon; An ohmic contact layer located on the surface of the PP region and the N-type doped region; A first metal layer located on the surface of the ohmic contact layer and the interlayer dielectric layer; A second metal layer is located on the back side of the substrate.

2. The trench MOSFET device according to claim 1, characterized in that The PP region extends to the first N-type epitaxial layer, and a bottom of the PP region is deeper than the oxide layer.

3. The trench MOSFET device according to claim 1, characterized in that: The trench MOSFET devices are symmetrically arranged about the central axis of the trench region.

4. The trench MOSFET device according to claim 1, characterized in that: The gate polysilicon includes a first polysilicon layer, a second polysilicon layer and a third polysilicon layer arranged layer by layer from bottom to top, and the doping concentration of the second polysilicon layer is greater than the doping concentration of the first polysilicon layer and the third polysilicon layer; A bottom height of the second polysilicon is not lower than a bottom height of the P-type well region, and a top height of the second polysilicon is not higher than a top height of the P-type well region.

5. The trench MOSFET device according to claim 4, characterized in that: The depth of the second polysilicon is half of the depth of the P-type well region, and the top height of the second polysilicon is level with the top height of the P-type well region.

6. The trench MOSFET device according to claim 4, characterized in that: The second polysilicon layer includes a first sublayer and a second sublayer, the first sublayer and the second sublayer are spaced apart, the first sublayer contacts the gate oxide layer on the left side of the trench region, and the second sublayer contacts the gate oxide layer on the right side of the trench region.

7. The trench MOSFET device according to claim 1, characterized in that: The depth of the low-K dielectric layer is equal to the depth of the oxide layer.

8. The trench MOSFET device according to claim 1, wherein: The oxide layer is configured as an arc-shaped structure.

9. A method for manufacturing a trench MOSFET device, characterized in that: For manufacturing a trench MOSFET device according to any one of claims 1 to 8, the method comprises: Providing an N-type substrate; Fabricating a first N-type epitaxial layer based on the surface of the substrate; Forming a first trench based on a surface layer of the first N-type epitaxial layer, and forming an oxide layer based on the first trench; A second N-type epitaxial layer is fabricated based on the surface of the first N-type epitaxial layer, wherein the second N-type epitaxial layer is provided with a trench region; a gate oxide layer and gate polysilicon are provided in the trench region, wherein the gate oxide layer is located on the sidewall of the trench region and is arranged around the gate polysilicon, and the bottom of the gate polysilicon is in contact with the oxide layer; wherein the thickness of the oxide layer is greater than the thickness of the gate oxide layer, the width of the oxide layer is greater than the width of the trench region, and the width of the low-K dielectric layer is less than the width of the trench region; the second N-type epitaxial layer further comprises a P-type well region and an N-type doped region and a PP region located on the surface layer of the second N-type epitaxial layer, wherein the N-type doped region is located on the surface of the P-type well region, and both sides of the N-type doped region and the P-type well region are in contact with the PP region and the gate oxide layer respectively; Fabricating an interlayer dielectric layer based on the surface of the gate polysilicon; Fabricating an ohmic contact layer based on the surfaces of the PP region and the N-type doped region; Fabricate a first metal layer based on the surfaces of the ohmic contact layer and the interlayer dielectric layer; A second metal layer is formed on the back side of the substrate.

10. The method for manufacturing a trench MOSFET device according to claim 9, wherein: The step of manufacturing a second N-type epitaxial layer based on the surface of the first N-type epitaxial layer comprises: Growing a second N-type epitaxial layer based on the surface of the first N-type epitaxial layer; wherein a trench region is provided in the second N-type epitaxial layer, and the oxide layer is exposed in the trench region; Based on the second N-type epitaxial layer, ion implantation in the P-type well region, ion implantation in the N-type doping region, ion implantation in the PP region and ion implantation in the terminal region are sequentially performed, and high-temperature furnace tube annealing is performed; Etching the oxide layer based on the bottom of the trench region to form a second trench; Filling the low-K dielectric layer based on the second trench and etching back; Oxidizing the sidewalls of the trench region to form a gate oxide layer; Polysilicon deposition and etching are performed based on the trench region to form a complete gate structure.

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