SiC VDMOSFET device with three layers of photomasks and substrate preparation process

Abstract

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses a SiC VDMOSFET (vertical double-diffused metal oxide semiconductor field effect transistor) device with three layers of photomasks and a substrate preparation process, the SiC VDMOSFET device comprises a plurality of MOS cells which are parallel to one another, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a metal grid electrode and a source electrode, the semiconductor epitaxial layer comprises an N substrate layer and an N drift layer, the semiconductor device is characterized in that the metal grid electrode comprises an upper grid electrode which is longitudinally arranged on the upper layer and a lower grid electrode which is transversely arranged on the lower layer. The metal gate is divided into the longitudinally arranged upper gate and the transversely arranged lower gate, and the P well layer, the P + doping layer and the N well layer of the transverse source region and the upper P well structure of the longitudinal source region are combined, so that the electric field distribution and the carrier transmission path are optimized, the conduction efficiency of the device is improved, the leakage current is reduced, and the reliability of the device is improved. And meanwhile, the voltage endurance capability is enhanced through upper and lower partitions of the N well layer.

Description

Technical Field

[0001] The present invention relates to the technical field of MOS semiconductors, and in particular to a SiC VDMOSFET device with a three-layer mask and a base preparation process. Background Art

[0002] In the field of power electronics technology, Si-based power devices have always been the main products of power electronics due to their significant advantages such as high reserves in nature, mature preparation and purification processes, stable single crystal structure, high reliability and low price.

[0003] "Triple mask" refers to the three-layer photolithography step, especially the three-layer photolithography process for the gate and source. The manufacture of SiCVD MOSFET usually requires multiple photolithography steps, but through process innovation, it can be reduced to three layers to reduce costs and improve yield.

[0004] The existing patent discloses a SiC VDMOSFET device and a preparation method (publication number CN118538611A), which relates to the field of semiconductor technology. In the SiC VDMOSFET device, the original gate is separated into two independent gates by metal. In the technology disclosed in the patent, the electric field under high voltage is prone to concentration effect, which greatly reduces the voltage resistance and anti-interference performance of the device. Summary of the invention

[0005] In order to solve the existing technical problems, the present invention provides a SiC VDMOSFET device with a three-layer mask and a base preparation process, which solves the problems in the above-mentioned background technology.

[0006] To solve the above technical problems, according to one aspect of the present invention, more specifically, a SiC VDMOSFET device with three-layer photomask includes a plurality of mutually parallel MOS cells, wherein the MOS cells include a drain, a semiconductor epitaxial layer, a metal gate, and a source, wherein the semiconductor epitaxial layer includes an N substrate layer and an N drift layer, and is characterized in that: the metal gate includes an upper gate located in the upper layer and arranged vertically, and a lower gate located in the lower layer and arranged horizontally; A P-well layer, a P+ doping layer and an N-well layer are formed in the lateral source region of a single MOS cell by ion implantation; An upper P well is formed in the longitudinal source region of a single MOS cell by ion implantation inside the N well layer; wherein the upper P well divides the N well layer into an upper N well and a lower N well.

[0007] Furthermore, a lower isolation cone, a lower isolation ring 1 and a lower isolation ring 2 are sequentially formed by deposition from the inside to the outside on the lower surface of the N substrate layer of the single MOS cell; The cross-sectional heights of the lower isolation cone, the lower isolation ring 1 and the lower isolation ring 2 decrease in sequence.

[0008] Furthermore, a doping cone is formed on the lower surface of the N substrate layer of a single MOS cell by ion implantation, wherein the doping concentration of the doping cone is 2 to 3 times lower than the doping concentration of the N drift layer.

[0009] Furthermore, an upper isolation cone, an upper isolation ring 1 and an upper isolation ring 2 are sequentially formed in an upper region of the N substrate layer of a single MOS cell from inside to outside by ion implantation; The cross-sectional heights of the upper isolation cone, the upper isolation ring 1 and the upper isolation ring 2 increase in sequence.

[0010] A preparation process of a SiC VDMOSFET device with a three-layer mask comprises the following steps: S1, the first layer of lithography is used to define the source area, isolate the device area and form the MOS cell and terminal protection area; S2, the second layer of photolithography is used to form the gate structure and define the gate area to form the gate oxide layer and the metal gate; S3, the third layer of photolithography is used to make the source or metal gate contact and metallize, so as to form an ohmic contact of the source or metal gate and complete the metal interconnection; S4. Conduct electrical performance testing on SiC VDMOSFET devices that have completed metal interconnection, and package devices that pass the preliminary testing.

[0011] Furthermore, in step S4, the electrical performance of the SiC VDMOSFET device is determined according to the switching loss, turn-on delay time and change in on-resistance of the SiC VDMOSFET device, as follows: In the formula, represents the performance coefficient of the tested SiC VDMOSFET device, Indicates the amount of energy loss when the detected device is turned on. Indicates the delay time of turning on the detected device. It indicates the resistance change of the tested device when the temperature rises from 20℃ to 150℃.

[0012] Furthermore, when It means that the electrical performance of the device meets the preliminary test requirements; when This means that the electrical performance of the device does not meet the preliminary test requirements.

[0013] The present invention provides a SiC VDMOSFET device with a three-layer mask and a base preparation process. Compared with the prior art, the method has the following effects: 1. The present invention optimizes the electric field distribution and carrier transmission path by dividing the metal gate into an upper gate arranged vertically and a lower gate arranged horizontally, and combining the P-well layer, P+ doping layer, N-well layer in the lateral source region and the upper P-well structure in the longitudinal source region. This design improves the conduction efficiency of the device and reduces the leakage current. At the same time, the voltage resistance is enhanced by dividing the N-well layer into upper and lower partitions, and it is suitable for high-power scenarios.

[0014] 2. The present invention deposits a lower isolation cone, a lower isolation ring 1 and a lower isolation ring 2 with decreasing cross-sectional heights on the lower surface of the N substrate layer in sequence. This stepped isolation structure significantly improves the electrical isolation effect between different regions of the device, reduces parasitic capacitance and leakage risks, thereby improving the stability and reliability of the device, especially under high-voltage working conditions.

[0015] 3. The present invention effectively adjusts the resistance gradient between the drift layer and the substrate by injecting a low-concentration doping cone (the concentration is 2 to 3 times lower than that of the N drift layer) into the lower surface of the N substrate layer. This improvement optimizes the current distribution, inhibits the formation of local hot spots, improves the heat dissipation performance of the device, and reduces the resistance change in high temperature environments, thereby improving long-term working stability.

[0016] 4. The present invention forms an upper isolation cone, an upper isolation ring 1 and an upper isolation ring 2 with increasing cross-sectional heights in the upper region of the N substrate layer. This structure further enhances the uniformity of the electric field distribution inside the device, reduces the electric field concentration effect under high voltage, enhances the voltage resistance and anti-interference performance of the device, and is suitable for harsh working conditions such as high frequency and high temperature. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Schematic diagram of the structure of the SiC VDMOSFET device in the present invention; Figure 2 For the present invention Figure 1 Middle A area cross-section; Figure 3 For the present invention Figure 1 Middle B area cross-section; Figure 4 This is a schematic diagram of the structure of Embodiment 2 of the present invention; Figure 5 For the present invention Figure 4 Cross-section of the middle C region; Figure 6 This is a schematic diagram of the structure of Embodiment 3 of the present invention; Figure 7 It is a structural schematic diagram of embodiment 4 of the present invention.

[0018] In the figure: 1. drain; 2. N substrate layer; 3. N drift layer; 4. metal gate; 5. source; 6. P well layer; 7. P+ doped layer; 8. N well layer; 9. lower isolation cone; 10. lower isolation ring 1; 11. lower isolation ring 2; 12. doped cone; 13. upper isolation cone; 14. upper isolation ring 1; 15. upper isolation ring 2; 41. upper gate; 42. lower gate; 61. upper P well; 81. upper N well; 82. lower N well. DETAILED DESCRIPTION

[0019] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0020] like Figure 1-7 As shown, a preparation process of a SiC VDMOSFET device with a three-layer mask comprises the following steps: Step 1: The first layer of photolithography is used to define the source area, isolate the device area and form the MOS cell and terminal protection area.

[0021] Step 2: The second layer of photolithography is used to form the gate structure and define the gate region to form a gate oxide layer and a metal gate 4.

[0022] Step 3: The third layer of photolithography is used to contact and metalize the source 5 or the metal gate 4, thereby forming an ohmic contact of the source 5 or the metal gate 4 and completing the metal interconnection.

[0023] Step 4: Conduct electrical performance tests on SiC VDMOSFET devices that have completed metal interconnection, and package devices that have passed the preliminary test. The electrical performance of SiC VDMOSFET devices is determined based on the switching loss, turn-on delay time, and change in on-resistance of the SiC VDMOSFET devices, including: In the formula, represents the performance coefficient of the tested SiC VDMOSFET device, Indicates the amount of energy loss when the detected device is turned on. Indicates the delay time of turning on the detected device. It indicates the resistance change of the tested device when the temperature rises from 20℃ to 150℃.

[0024] when It means that the electrical performance of the device meets the preliminary test requirements; when This means that the electrical performance of the device does not meet the preliminary test requirements.

[0025] The electrical performance of any SiC VDMOSFET device is tested. The energy loss of the tested device when it is turned on is (µJ), the delay time of the device being tested turning on (ns), the resistance change of the tested device from 20℃ to 150℃ is (Resistance change = (device resistance at 150°C - device resistance at 20°C) ÷ device resistance at 20°C × 100%). Then we have: From the above calculation, we can know that the performance coefficient of the tested SiC VDMOSFET device is , then the electrical performance of the SiC VDMOSFET device meets the preliminary test requirements.

[0026] Example 1 like Figure 1 -3, according to one aspect of the present invention, a SiCVDMOSFET device with three-layer photomask is provided, comprising a plurality of mutually parallel MOS cells, the MOS cell comprising a drain 1, a semiconductor epitaxial layer, a metal gate 4, and a source 5, the semiconductor epitaxial layer comprising an N substrate layer 2 and an N drift layer 3, the metal gate 4 comprising an upper gate 41 arranged vertically in the upper layer and a lower gate 42 arranged horizontally in the lower layer; a P well layer 6, a P+ doping layer 7, and an N well layer 8 are formed in the horizontal source region of a single MOS cell by ion implantation; an upper P well 61 is formed in the vertical source region of a single MOS cell by ion implantation inside the N well layer 8; wherein the upper P well 61 divides the N well layer 8 into an upper N well 81 and a lower N well 82. By dividing the metal gate into an upper gate arranged vertically and a lower gate arranged horizontally, and combining the P well layer, P+ doping layer, N well layer in the horizontal source region and the upper P well structure in the vertical source region, the electric field distribution and the carrier transmission path are optimized. This design improves the conduction efficiency of the device and reduces leakage current. At the same time, it enhances the voltage resistance by partitioning the upper and lower N-well layers, making it suitable for high-power scenarios.

[0027] Example 2 like Figure 4 , 5 As shown, a lower isolation cone 9, a lower isolation ring 10 and a lower isolation ring 2 11 are sequentially formed from the inside to the outside by deposition on the lower surface of the N substrate layer 2 of a single MOS cell; wherein the cross-sectional heights of the lower isolation cone 9, the lower isolation ring 10 and the lower isolation ring 2 11 decrease in sequence. The lower isolation cone 9, the lower isolation ring 10 and the lower isolation ring 2 11 with decreasing cross-sectional heights are sequentially deposited on the lower surface of the N substrate layer 2. This stepped isolation structure significantly improves the electrical isolation effect between different regions of the device, reduces parasitic capacitance and leakage risks, thereby improving the stability and reliability of the device, especially under high-voltage working conditions.

[0028] Example 3 like Figure 6As shown in the figure, a doping cone 12 is formed on the lower surface of the N substrate layer 2 of a single MOS cell by ion implantation, wherein the doping concentration of the doping cone 12 is 2 to 3 times lower than the doping concentration of the N drift layer 3. By implanting a low-concentration doping cone 12 (with a concentration lower than 2 to 3 times that of the N drift layer 3) on the lower surface of the N substrate layer 2, the resistance gradient between the drift layer and the substrate is effectively adjusted. This improvement optimizes the current distribution, suppresses the formation of local hot spots, improves the heat dissipation performance of the device, and reduces the resistance change in high temperature environments, thereby improving long-term working stability.

[0029] Example 4 like Figure 7 As shown, the upper isolation cone 13, the upper isolation ring 14 and the upper isolation ring 2 15 are formed in sequence from the inside to the outside through ion implantation in the upper region of the N substrate layer 2 of a single MOS cell; wherein the cross-sectional heights of the upper isolation cone 13, the upper isolation ring 14 and the upper isolation ring 2 15 are increased in sequence. The upper isolation cone 13, the upper isolation ring 14 and the upper isolation ring 2 15 with increasing cross-sectional heights are formed in the upper region of the N substrate layer 2. This structure further enhances the uniformity of the electric field distribution inside the device, reduces the electric field concentration effect under high voltage, enhances the voltage resistance and anti-interference performance of the device, and is suitable for harsh working conditions such as high frequency and high temperature.

[0030] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A SiC VDMOSFET device with a three-layer mask, comprising a plurality of mutually parallel MOS cells, wherein the MOS cells comprise a drain (1), a semiconductor epitaxial layer, a metal gate (4), and a source (5), wherein the semiconductor epitaxial layer comprises an N substrate layer (2) and an N drift layer (3), characterized in that: The metal gate (4) comprises an upper gate (41) located in an upper layer and arranged in a longitudinal direction, and a lower gate (42) located in a lower layer and arranged in a transverse direction; A P-well layer (6), a P+ doping layer (7) and an N-well layer (8) are formed in the lateral source region of a single MOS cell by ion implantation; An upper P well (61) is formed in the longitudinal source region of a single MOS cell by ion implantation inside the N well layer (8); wherein the upper P well (61) divides the N well layer (8) into an upper N well (81) and a lower N well (82).

2. The SiC VDMOSFET device with three-layer photomask according to claim 1, characterized in that: A lower isolation cone (9), a lower isolation ring 1 (10) and a lower isolation ring 2 (11) are sequentially formed on the lower surface of the N substrate layer (2) of a single MOS cell from the inside to the outside by deposition; The cross-sectional heights of the lower isolation cone (9), the lower isolation ring 1 (10) and the lower isolation ring 2 (11) decrease in sequence.

3. The SiC VDMOSFET device with three-layer photomask according to claim 1, characterized in that: A doping cone (12) is formed on the lower surface of the N substrate layer (2) of a single MOS cell by ion implantation, wherein the doping concentration of the doping cone (12) is 2 to 3 times lower than the doping concentration of the N drift layer (3).

4. The SiC VDMOSFET device with three-layer photomask according to claim 1, characterized in that: An upper isolation cone (13), an upper isolation ring 1 (14) and an upper isolation ring 2 (15) are sequentially formed in an upper region of an N substrate layer (2) of a single MOS cell from the inside to the outside through ion implantation; The cross-sectional heights of the upper isolation cone (13), the upper isolation ring 1 (14) and the upper isolation ring 2 (15) increase in sequence.

5. A process for preparing a SiC VDMOSFET device with a three-layer mask, characterized in that: Applicable to the SiC VDMOSFET device according to any one of claims 1 to 4, the preparation process of the SiC VDMOSFET device with three-layer mask comprises the following steps: S1, the first layer of lithography is used to define the source area, isolate the device area and form the MOS cell and terminal protection area; S2, the second layer of photolithography to form the gate structure, define the gate area to form the gate oxide layer and the metal gate (4); S3, the third layer of photolithography is used to contact and metalize the source electrode (5) or the metal gate electrode (4), thereby forming an ohmic contact of the source electrode (5) or the metal gate electrode (4) and completing the metal interconnection; S4. Conduct electrical performance testing on SiC VDMOSFET devices that have completed metal interconnection, and package devices that pass the preliminary testing.

6. The process for preparing a SiC VDMOSFET device with a three-layer photomask according to claim 1, characterized in that: In step S4, the electrical performance of the SiC VDMOSFET device is determined according to the switching loss, turn-on delay time and change in on-resistance of the SiC VDMOSFET device, as follows: In the formula, represents the performance coefficient of the tested SiC VDMOSFET device, Indicates the amount of energy loss when the detected device is turned on. Indicates the delay time of turning on the detected device. It indicates the resistance change of the tested device when the temperature rises from 20℃ to 150℃.

7. The process for preparing a SiC VDMOSFET device with a three-layer mask according to claim 6, characterized in that: when It means that the electrical performance of the device meets the preliminary test requirements; when This means that the electrical performance of the device does not meet the preliminary test requirements.

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