Semiconductor device

Abstract

The invention discloses a semiconductor device. The semiconductor device includes: a substrate including an epitaxial layer; a first gate and a second gate disposed on the substrate; a first type body region disposed in the substrate between the first gate and the second gate; a pillar region extending from the first type body region toward the lower surface of the substrate and disposed within the epitaxial layer; and a first region and a second region of the pillar region, each including a portion whose width decreases along a first direction from the upper surface toward the lower surface of the substrate and then increases. The first region is disposed between the first type body region and the second region, the first region includes a first width that is the smallest width among the widths of the pillar regions and a second width that is larger than the first width, and the second region includes a third width that is larger than the first width and smaller than the second width. The first region and the second region are distinguished by a second width as a boundary.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and in particular, to a semiconductor device having a super junction structure. Background Art

[0002] The contents described in this section merely provide background information related to the present embodiment and do not constitute prior art.

[0003] A semiconductor device having a super junction structure may be one of high voltage / power semiconductor devices used in a power integrated circuit (IC) device for power conversion and power control systems.

[0004] Semiconductor devices with superjunction structures may oscillate during the process of turning on or off power devices. Oscillations may cause improper operation of the switch and / or damage to the device. In order to reduce oscillations, it is necessary to reduce the switching speed by increasing the gate resistance and the capacitance of the device (the capacitance between the gate and the drain). However, increasing the gate resistance and the capacitance of the device may have the disadvantage of reducing the efficiency of the switch.

[0005] Therefore, there is a need to develop a semiconductor device that can reduce oscillation while reducing the capacitance of the device. Summary of the invention

[0006] Technical issues

[0007] An object of the present invention is to provide a semiconductor device capable of reducing oscillation of the semiconductor device when the capacitance of the semiconductor device is low.

[0008] The purpose of the present invention is not limited to the above-mentioned purpose. Other purposes and advantages of the present invention that are not mentioned can be understood through the following description, and can be more clearly understood through the embodiments of the present invention. Moreover, it is obvious that the purpose and advantages of the present invention can be achieved by the schemes and combinations thereof shown in the scope of the invention claims.

[0009] Technical Solution

[0010] The semiconductor device of the embodiment of the present invention comprises: a substrate including an epitaxial layer; a first gate and a second gate arranged on the substrate; a first type body region arranged in the substrate between the first gate and the second gate; a pillar region extending from the first type body region to the lower surface of the substrate and arranged in the epitaxial layer; and a first region and a second region of the pillar region, each including a portion whose width decreases and then increases along a first direction from the upper surface of the substrate toward the lower surface. The first region is arranged between the first type body region and the second region, the first region includes a first width as the minimum width among the widths of the pillar region and a second width larger than the first width, the second region includes a third width larger than the first width and smaller than the second width, and the first region and the second region are distinguished by the second width as a boundary.

[0011] Furthermore, the first region is a region which decreases from the fourth width along the first direction to the first width and then increases from the first width along the first direction to the second width; the second region is a region which decreases from the second width along the first direction to the third width and then increases from the third width along the first direction to the fifth width; and the third region directly below the second region includes a portion of the pillar region where the width of the pillar region decreases from the fifth width along the first direction.

[0012] Furthermore, the first width is smaller than the fourth width and the fifth width.

[0013] Furthermore, the first region is arranged directly below the first type main body region, and the second region and the third region are separated by the fifth width.

[0014] Furthermore, a first thickness of the first region measured along the first direction is greater than a second thickness of the second region measured along the first direction.

[0015] Furthermore, the first region is arranged directly below the first type body region.

[0016] Furthermore, the second region is arranged directly below the first region.

[0017] The semiconductor device of the embodiment of the present invention comprises: a substrate including an epitaxial layer; a first gate and a second gate arranged on the substrate; a first type body region arranged in the substrate between the first gate and the second gate; a pillar region extending from the first type body region to the lower surface of the substrate and arranged in the epitaxial layer; and a first region and a second region of the pillar region, each including a portion whose width decreases and then increases along a first direction from the upper surface of the substrate toward the lower surface. The first region is arranged between the first type body region and the second region, and a first thickness of the first region measured along the first direction is greater than a second thickness of the second region measured along the first direction.

[0018] Furthermore, the first region includes a first width which is the minimum width among the widths of the pillar region and a second width which is larger than the first width, and the second region includes a third width which is larger than the first width and smaller than the second width, and the first region and the second region are distinguished by the second width.

[0019] Furthermore, the first region is a region which decreases from the fourth width along the first direction to the first width and then increases from the first width along the first direction to the second width; the second region is a region which decreases from the second width along the first direction to the third width and then increases from the third width along the first direction to the fifth width; and the third region directly below the second region includes a portion of the pillar region where the width of the pillar region decreases from the fifth width along the first direction.

[0020] Furthermore, the first width is smaller than the fourth width and the fifth width.

[0021] Furthermore, the first region is arranged directly below the first type main body region, and the second region and the third region are separated by the fifth width.

[0022] Furthermore, the first region is arranged directly below the first type body region.

[0023] Furthermore, the second region is arranged directly below the first region.

[0024] The semiconductor device of the embodiment of the present invention comprises: a substrate including an epitaxial layer; a first gate and a second gate arranged on the substrate; a first type body region arranged in the substrate between the first gate and the second gate; a pillar region extending from the first type body region to the lower surface of the substrate and arranged in the epitaxial layer; and a first region and a second region of the pillar region, each including a portion whose width decreases and then increases along a first direction from the upper surface of the substrate toward the lower surface. The first region is arranged between the first type body region and the second region, the first region includes a first width as the minimum width among the widths of the pillar region and a second width larger than the first width, the second region includes a third width larger than the first width and smaller than the second width, a first thickness of the first region measured along the first direction is larger than a second thickness of the second region measured along the first direction, and the first region is arranged directly below the first type body region.

[0025] Furthermore, the first region is a region which decreases from the fourth width along the first direction to the first width and then increases from the first width along the first direction to the second width; the second region is a region which decreases from the second width along the first direction to the third width and then increases from the third width along the first direction to the fifth width; and the third region directly below the second region includes a portion of the pillar region where the width of the pillar region decreases from the fifth width along the first direction.

[0026] Furthermore, the first width is smaller than the fourth width and the fifth width.

[0027] Furthermore, the second region and the third region are separated by the fifth width.

[0028] Furthermore, the first region is arranged directly below the first type main body region, and the first region and the second region are separated by the second width.

[0029] Furthermore, the second region is arranged directly below the first region.

[0030] Effects of the Invention

[0031] The semiconductor device of the present invention can reduce the capacitance of the semiconductor device (capacitance between the gate and the drain) in a low operating voltage region and increase the capacitance in a high operating voltage region, thereby improving the operating stability and reliability of the semiconductor device.

[0032] The specific effects of the present invention will be described together with the above contents in the following description of specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 FIG. 1 is a cross-sectional view of a semiconductor device for illustrating an embodiment of the present invention.

[0034] Figure 2 To enlarge Figure 1 Magnified view of area A in FIG.

[0035] Figure 3 To enlarge Figure 2 Magnified view of area B in FIG.

[0036] Figure 4 To enlarge Figure 2 Magnified view of region C.

[0037] Figure 5 To enlarge Figure 2 Magnified view of area D in FIG.

[0038] Figure 6 , Figure 7 and Figure 8 A diagram for explaining the effects of the semiconductor device according to the embodiment of the present invention. DETAILED DESCRIPTION

[0039] The terms or words used in this specification and the scope of protection of the invention should not be interpreted limited to the usual or dictionary meanings. Based on the principle that the inventor can define terms or words in order to explain his invention in the best way, they should be interpreted with the meaning and concept consistent with the technical idea of ​​the present invention. In addition, the embodiments recorded in this specification and the structures shown in the drawings are only one embodiment of the present invention and cannot fully represent the technical idea of ​​the present invention. It should be understood that at the time of filing this application, there may be a variety of equivalents and variations that can replace them and applicable examples.

[0040] The terms "first", "second", "A", "B" and the like used in this specification and the scope of protection of the invention may be used to describe a variety of structural elements, but the above structural elements are not limited by the above terms. The above terms are used for the purpose of distinguishing one structural element from other structural elements. For example, without departing from the scope of the present invention, the first structural element may be named as the second structural element, and similarly, the second structural element may also be named as the first structural element. The term "and / or" includes a combination of multiple related recorded items or any item in multiple related recorded items.

[0041] The terms used in this specification and the scope of the invention are only used to illustrate specific embodiments and are not intended to limit the present invention. If the context does not clearly indicate otherwise, the singular expression includes the plural expression. In this application, the terms "including" or "having" are only used to indicate the existence of features, numbers, steps, operations, structural elements, accessories or combinations thereof recorded in the specification, rather than excluding in advance the existence or additional possibilities of other features, numbers, steps, operations, structural elements, accessories or combinations thereof.

[0042] If not otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs.

[0043] Terms with the same definition as in commonly used dictionaries should be interpreted as having the same meaning as that in the context of the relevant description, and in the present application, if there is no clear definition, they should not be interpreted as ideal or excessive formal meanings. In addition, the various structures, processes, procedures or methods included in the various embodiments of the present invention can be shared within the scope that they are not technically contradictory.

[0044] Below, refer to Figures 1 to 8 A semiconductor device according to an embodiment of the present invention is described.

[0045] Figure 1 FIG. 1 is a cross-sectional view of a semiconductor device for illustrating an embodiment of the present invention.

[0046] Reference Figure 1 The semiconductor device of the embodiment of the present invention may include a substrate 100, an epitaxial layer 110, a first gate 121, a second gate 122, a gate insulating film 130, an interlayer insulating film 140, a first type body region 150, a pillar region 160 and a source region 170.

[0047] The substrate 100 may be, for example, bulk silicon or silicon-on-insulator (SOI). Alternatively, the substrate 100 may be a silicon substrate, or may include other substances, for example, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. The substrate 100 may include an upper surface 100U and a lower surface 100L.

[0048] The substrate 100 may include an epitaxial layer 110. For example, the epitaxial layer 110 may include n-type impurities.

[0049] The first gate 121 and the second gate 122 may be disposed on the substrate 100. The first gate 121 and the second gate 122 may be disposed apart from each other. A gate insulating film 130 may be disposed between the first gate 121 and the upper surface 100U of the substrate 100 and between the second gate 122 and the upper surface 100U of the substrate 100. The gate insulating film 130 may include an insulating material. The interlayer insulating film 140 may be disposed in a manner of wrapping the first gate 121 and the second gate 122.

[0050] The first type body region 150 may be disposed in the substrate 100 between the first gate 121 and the second gate 122. The first type body region 150 may be disposed on the pillar region 160. The first type body region 150 may be electrically connected to the pillar region 160. The first type body region 150 may include p-type impurities.

[0051] The source region 170 may be selectively disposed on an upper portion of the first type body region 150. For example, the source region 170 may include n-type impurities.

[0052] The pillar region 160 may extend from the first type body region to the lower surface 100L of the substrate 100. The pillar region 160 may be arranged in the epitaxial layer 110. The pillar region 160 may be a region where p-type dopants are ion-implanted. The pillar region 160 may have a columnar shape of stacked p-type ion implanted regions in the epitaxial layer 110. The epitaxial layer 110 of the substrate 100 may include a plurality of pillar regions 160. In the case where a plurality of pillar regions 160 are included in the epitaxial layer 110, the plurality of pillar regions 160 may be separated from each other. In this case, the epitaxial layer 110 may be arranged between one pillar region 160 and another pillar region 160.

[0053] The pillar region 160 may include a first region R1, a second region R2, and a third region R3. The first region R1 and the second region R2 may be disposed on the third region R3. The second region R2 may be a region between the first region R1 and the third region R3. The first region R1 may be disposed between the first type body region 150 and the second region R2.

[0054] In some embodiments, the first region R1 may be disposed directly below the first type body region 150. For example, the first region R1 may be the uppermost portion of the pillar region 160. The first region R1 may include an upper end portion of the pillar region 160. The upper end portion of the pillar region 160 may be an end portion adjacent to the upper surface 100U of the substrate 100. The first region R1 may include a boundary between the first type body region 150 and the pillar region 160. For example, the boundary may be an upper end portion of the pillar region 160.

[0055] The first region R1 , the second region R2 , and the third region R3 of the pillar region 160 may respectively include a portion where the cross-sectional width of the pillar region 160 decreases and then increases along a first direction from the upper surface 100U toward the lower surface 100L of the substrate 100 , and a portion where the cross-sectional width increases and then decreases.

[0056] Figure 2 To enlarge Figure 1 Magnified view of area A in FIG. Figure 3 To enlarge Figure 2 Magnified view of area B in FIG. Figure 4 To enlarge Figure 2 Magnified view of region C. Figure 5 To enlarge Figure 2 Magnified view of area D in FIG.

[0057] Reference Figure 1 and Figure 2 The first region R1 of the pillar region 160 of the semiconductor device according to the embodiment of the present invention may be a region including a first width W1 and a second width W2.

[0058] The first width W1 may be the smallest width among the widths of the pillar region 160. The first region R1 of the pillar region 160 gradually decreases along the first direction to the first width W1 from the fourth width W4, which is the width of the starting portion of the pillar region 160, and then gradually increases along the first direction to the second width W2 from the first width W1. The first width W1 may be smaller than the second width W2. With the second width W2 as a reference, the width of the pillar region 160 along the first direction may be further reduced.

[0059] The fourth width W4 may be the width of the support region 160 at a position directly below the first type body region 150. The second width W2 may be the same as or different from the fourth width W4.

[0060] Reference Figure 3 , the first region R1 may include a first portion R11, and the first portion R11 includes a first width W1. The first portion R11 of the first region R1 may include a sixth width W6 and a seventh width W7. The first portion R11 may decrease from the sixth width W6 to the first width W1 along the first direction and then increase to the seventh width W7.

[0061] Refer again Figure 1 and Figure 2 The second region R2 may be a region disposed directly below the first region R1.

[0062] Reference Figure 4, the first region R1 and the second region R2 can be distinguished by the second width W2. The second portion R22 may include a portion of the first region R1 and a portion of the second region R2. The second portion R22 may include an eighth width W8 and a ninth width W9. A portion of the first region R1 included in the second portion R22 may have an eighth width W8. A portion of the second region R2 included in the second portion R22 may have a ninth width W9. The second portion R22 may increase from the eighth width W8 to the second width W2 along the first direction and then decrease to the ninth width W9.

[0063] Refer again Figure 1 and Figure 2 The second region R2 may be a region starting with the second width W2 and including the third width W3 and the fifth width W5.

[0064] The second region R2 may gradually decrease from the second width W2 to the third width W3 along the first direction, and then gradually increase from the third width W3 to the fifth width W5 along the first direction. The third width W3 may be greater than the first width W1 and smaller than the second width W2 and the fourth width W4. The fifth width W5 may be greater than the first width W1 and the third width W3. The fifth width W5 may be the same as or different from the second width W2 and the fourth width W4, respectively.

[0065] Reference Figure 5 , the second region R2 may include a third portion R33, and the third portion R33 includes a third width W3. The third portion R33 of the second region R2 may include a tenth width W10 and an eleventh width W11. The third portion R33 may decrease from the tenth width W10 to the third width W3 along the first direction, and then increase to the eleventh width W11.

[0066] Refer again Figure 1 and Figure 2 , the third region R3 may include at least a portion of the pillar region 160 below the second region R2 starting from the fifth width W5. The third region R3 may be disposed directly below the second region R2. The second region R2 and the third region R3 may be distinguished by the fifth width W5. The third region R3 may include a portion of the pillar region 160 whose width decreases along the first direction starting from the fifth width W5.

[0067] A first thickness D1 of the first region R1 measured along the first direction may be greater than a second thickness D2 of the second region R2 measured along the first direction. For example, a thickness of a portion of the epitaxial layer 110 corresponding to the first region R1 (e.g., the first thickness D1) may be thicker than a thickness of another portion of the epitaxial layer 110 corresponding to the second region R2 (e.g., the second thickness D2).

[0068] For example, the thickness of the pillar region 160 from the portion having the fourth width W4 to the portion having the second width W2 along the first direction may be the first thickness D1. The portion having the fourth width W4 may be the portion from the first type body region 150 to the pillar region 160. The second width W2 may be the width when the first width W1 is gradually reduced along the first direction from the fourth width W4, then gradually increased from the first width W1, and then the width begins to decrease, and then increases from the first width W1 to the maximum.

[0069] For example, the thickness along the first direction from the portion having the second width W2 to the portion having the fifth width W5 of the pillar region 160 may be the second thickness D2. The fifth width W5 may be the width when the third width W3 is gradually reduced along the first direction from the second width W2, then gradually increased from the third width W3, and then decreased, and then increased from the third width W3 to the maximum.

[0070] Figure 6 , Figure 7 and Figure 8 A diagram for explaining the effects of the semiconductor device according to the embodiment of the present invention.

[0071] Figure 6 and Figure 7 The x-axis of the graph shown may be time (unit: arbitrary unit (AU)), and the y-axis may be voltage (unit: AU). Figure 8 The x-axis of the graph shown may be voltage (unit: AU) and the y-axis may be capacitance (Crss (unit: AU)).

[0072] Reference Figure 6 In the case where the first region R1 does not include the first width W1 as the minimum width and the first thickness D1 is not greater than the second thickness D2, the semiconductor device may oscillate after a specific time (e.g., tx) regardless of whether it is in a low voltage region or a high voltage region. In this case, the first peak voltage Vp1 may occur after a specific time.

[0073] Reference Figure 7 In the case where the first region R1 includes the first width W1 as the minimum width and the first thickness D1 is greater than the second thickness D2, the semiconductor device operates stably in the low voltage region L, and oscillates in the high voltage region H, but the semiconductor device is not stable. Figure 6 The first region R1 immediately below the first type body region 150 near the start of the pillar region 160 includes the minimum width (first width W1) of the pillar region 160, thereby reducing oscillation of the semiconductor device.

[0074] Reference Figure 8 The first curve G1 is a curve showing the capacitance of the semiconductor device in which a portion of the pillar region 160 corresponding to the first region R1 of the semiconductor device according to the embodiment of the present invention has a width greater than the first width W1, and a thickness of the portion of the pillar region 160 corresponding to the first region R1 of the semiconductor device according to the embodiment of the present invention is not greater than the thickness of other regions. The second curve G2 is a curve showing the capacitance of the semiconductor device in which a portion of the pillar region 160 corresponding to the first region R1 of the semiconductor device according to the embodiment of the present invention has a minimum width equal to the first width W1, and a thickness of the portion of the pillar region 160 corresponding to the first region R1 of the semiconductor device according to the embodiment of the present invention is not greater than the thickness of other regions. The third curve G3 is a curve showing the capacitance of the semiconductor device according to the embodiment of the present invention.

[0075] According to the third curve G3, the semiconductor device of the embodiment of the present invention shows an overall high capacitance compared to the semiconductor device of the first curve G1 and the semiconductor device of the second curve G2. According to the third curve G3, the capacitance of the semiconductor device of the embodiment of the present invention gradually increases from low voltage to high voltage compared to the semiconductor device of the first curve G1 and the semiconductor device of the second curve G2.

[0076] The semiconductor device according to the embodiment of the present invention can reduce capacitance at low voltage and increase capacitance at high voltage, thereby improving the working stability and reliability of the semiconductor device.

[0077] The above description is only an illustrative description of the technical idea of ​​the present embodiment. A person skilled in the art of the present embodiment can make various modifications and variations without departing from the essential characteristics of the present embodiment. Therefore, the present embodiment is only used to illustrate the technical idea of ​​the present embodiment, and is not intended to be limiting. The scope of the technical idea of ​​the present embodiment is not limited to these embodiments. The protection scope of the present embodiment shall be interpreted by the protection scope of the accompanying invention claims, and all technical ideas within the equivalent scope shall also be interpreted as included in the scope of the rights of the present embodiment.

Claims

1. A semiconductor device, characterized in that: include: a substrate including an epitaxial layer; A first gate and a second gate are disposed on the substrate; A first type body region is arranged in the substrate between the first gate and the second gate; a pillar region extending from the first type body region toward the lower surface of the substrate and disposed in the epitaxial layer; and The first region and the second region of the pillar region each include a portion whose width decreases and then increases along a first direction from the upper surface of the substrate toward the lower surface. The first region is arranged between the first type body region and the second region. The first region includes a first width which is the smallest width among the widths of the pillar region and a second width which is larger than the first width. The second region includes a third width that is larger than the first width and smaller than the second width, The first area and the second area are separated by the second width.

2. The semiconductor device according to claim 1, wherein: The first region is a region that decreases from the fourth width along the first direction to the first width and then increases from the first width along the first direction to the second width. The second region is a region that decreases from the second width along the first direction to the third width and then increases from the third width along the first direction to the fifth width. The third region directly below the second region includes a portion of the pillar region where the width of the pillar region decreases from the fifth width along the first direction.

3. The semiconductor device according to claim 2, wherein: The first width is smaller than the fourth width and the fifth width.

4. The semiconductor device according to claim 2, wherein: The first region is arranged directly below the first type body region. The second region and the third region are separated by the fifth width.

5. The semiconductor device according to claim 2, wherein: A first thickness of the first region measured along the first direction is greater than a second thickness of the second region measured along the first direction.

6. The semiconductor device according to claim 1, wherein: The first region is arranged directly below the first type body region.

7. The semiconductor device according to claim 6, wherein: The second region is arranged directly below the first region.

8. A semiconductor device, characterized in that: include: a substrate including an epitaxial layer; A first gate and a second gate are disposed on the substrate; A first type body region is arranged in the substrate between the first gate and the second gate; a pillar region extending from the first type body region toward the lower surface of the substrate and disposed in the epitaxial layer; and The first region and the second region of the pillar region each include a portion whose width decreases and then increases along a first direction from the upper surface of the substrate toward the lower surface. The first region is arranged between the first type body region and the second region. A first thickness of the first region measured along the first direction is greater than a second thickness of the second region measured along the first direction.

9. The semiconductor device according to claim 8, wherein: The first region includes a first width which is the smallest width among the widths of the pillar region and a second width which is larger than the first width. The second region includes a third width that is larger than the first width and smaller than the second width, The first area and the second area are separated by the second width.

10. The semiconductor device according to claim 9, wherein: The first region is a region that decreases from the fourth width along the first direction to the first width and then increases from the first width along the first direction to the second width. The second region is a region that decreases from the second width along the first direction to the third width and then increases from the third width along the first direction to the fifth width. The third region directly below the second region includes a portion of the pillar region where the width of the pillar region decreases from the fifth width along the first direction.

11. The semiconductor device according to claim 10, wherein: The first width is smaller than the fourth width and the fifth width.

12. The semiconductor device according to claim 10, wherein: The first region is arranged directly below the first type body region. The second region and the third region are separated by the fifth width.

13. The semiconductor device according to claim 8, wherein: The first region is arranged directly below the first type body region.

14. The semiconductor device according to claim 13, wherein: The second region is arranged directly below the first region.

15. A semiconductor device, characterized in that: include: a substrate including an epitaxial layer; A first gate and a second gate are disposed on the substrate; A first type body region is arranged in the substrate between the first gate and the second gate; a pillar region extending from the first type body region toward the lower surface of the substrate and disposed in the epitaxial layer; and The first region and the second region of the pillar region each include a portion whose width decreases and then increases along a first direction from the upper surface of the substrate toward the lower surface. The first region is arranged between the first type body region and the second region. The first region includes a first width which is the smallest width among the widths of the pillar region and a second width which is larger than the first width. The second region includes a third width that is larger than the first width and smaller than the second width, A first thickness of the first region measured along the first direction is greater than a second thickness of the second region measured along the first direction, The first region is arranged directly below the first type body region.

16. The semiconductor device according to claim 15, wherein: The first region is a region that decreases from the fourth width along the first direction to the first width and then increases from the first width along the first direction to the second width. The second region is a region that decreases from the second width along the first direction to the third width and then increases from the third width along the first direction to the fifth width. The third region directly below the second region includes a portion of the pillar region where the width of the pillar region decreases from the fifth width along the first direction.

17. The semiconductor device according to claim 16, wherein: The first width is smaller than the fourth width and the fifth width.

18. The semiconductor device according to claim 16, wherein: The second region and the third region are separated by the fifth width.

19. The semiconductor device according to claim 15, wherein: The first region is arranged directly below the first type body region. The first area and the second area are separated by the second width.

20. The semiconductor device according to claim 15, wherein: The second region is arranged directly below the first region.

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