Forming method and structure of gate dielectric layer and semiconductor structure

Abstract

The invention provides a gate dielectric layer, a semiconductor structure forming method and a structure, and the formation of the gate dielectric layer comprises the steps: providing a substrate which comprises a high-voltage device region and a low-voltage device region, and forming an isolation structure and a first dielectric layer on the substrate; removing the first dielectric layer in the low-voltage device region and the first dielectric layer in the non-gate region of the high-voltage device region through an etching process; forming a second dielectric layer on the surface of the substrate; and respectively forming a gate structure and a corresponding gate dielectric layer in the high-voltage device region and the low-voltage device region on the substrate. According to the technical scheme, the first dielectric layer located below the grid electrode of the high-voltage device area is reserved through photoetching and etching to serve as the high-voltage grid dielectric layer, and then the second dielectric layer with the thin thickness is formed to be used for preparing the low-voltage grid dielectric layer. Therefore, the hidden danger that the gate cannot be completely wrapped by the follow-up side wall due to undercutting easily generated when the redundant dielectric layer is removed in the gate etching process in the prior art or the residual gate dielectric layer can be avoided.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a method and structure for forming a gate dielectric layer and a semiconductor structure. Background Art

[0002] With the rapid development of integrated circuit manufacturing technology, the device density and integration of integrated circuit chips are constantly increasing. The integration of high-voltage devices and low-voltage devices in the same chip is essential. Usually, a complete set of semiconductor devices includes at least one core device (Core) and at least one input-output device (IO) integrated on the same semiconductor substrate. The core device is used to realize the main functions of the integrated circuit, and the device voltage is usually low, while the input-output element provides signal input and output, and the device voltage is usually high.

[0003] Since the two devices have different device voltage requirements, the thickness of the gate dielectric layer that needs to be formed in the high-voltage device area will be much greater than that in the low-voltage device area, which will lead to defects in the subsequent gate etching and dielectric layer removal. For example, undercut may occur in the low-voltage device area, resulting in an incomplete gate dielectric layer, which in turn affects the insulation performance between the gate and the channel; while in the high-voltage device area, oxide residue may occur, which will make it impossible for the subsequent sidewall process to completely wrap the gate, and then lead to the risk of gate erosion in the subsequent wet process.

[0004] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0005] The purpose of the present invention is to provide a method and structure for forming a gate dielectric layer and a semiconductor structure, so as to avoid undercutting during the formation of the gate dielectric layer of low-voltage devices and high-voltage devices or the hidden danger of the subsequent sidewall being unable to completely wrap the gate due to the residual gate dielectric layer, so as to obtain a better process window.

[0006] In order to solve the above problems, in a first aspect, a method for forming a gate dielectric layer is provided, comprising the following steps:

[0007] S1. Providing a substrate, wherein the substrate includes a high-voltage device region and a low-voltage device region, and an isolation structure and a first dielectric layer are formed on the substrate;

[0008] S2, removing the first dielectric layer located in the low voltage device area and the first dielectric layer in the non-gate area of ​​the high voltage device area by an etching process;

[0009] S3, forming a second dielectric layer on the surface of the substrate, wherein the thickness of the second dielectric layer is lower than that of the first dielectric layer;

[0010] S4. Forming a gate structure and a corresponding gate dielectric layer in the high voltage device region and the low voltage device region on the substrate.

[0011] The technical solution first retains the first dielectric layer under the gate in the high-voltage device area as a high-voltage gate dielectric layer through photolithography and etching, and then forms a thinner second dielectric layer for preparing a low-voltage gate dielectric layer. This can avoid the undercut that is easily produced when removing excess dielectric layers after etching the gate in the prior art, or the hidden danger of the subsequent sidewall being unable to completely wrap the gate due to the residual dielectric layer.

[0012] In step S2, an etching mask is formed on the first dielectric layer in the gate region of the high-voltage device region, and the first dielectric layer in the low-voltage device region and the first dielectric layer in the non-gate region of the high-voltage device region are removed by an etching process; the etching process is any one of dry etching, wet etching and non-plasma gas phase reaction etching.

[0013] In step S2, the step of forming the etching mask includes: forming a photoresist layer on the surface of the substrate; patterning the photoresist layer, and retaining the photoresist on the first dielectric layer in the gate region of the high-voltage device region as an etching mask.

[0014] In step S4, the steps of forming the gate structure and the corresponding gate dielectric layer include: forming a polysilicon layer and a hard mask layer in sequence on the surface of the substrate; forming a patterned photoresist layer on the surface of the hard mask layer; using the patterned photoresist layer as an etching mask, through a combination of a dry etching process and a wet etching process, removing the hard mask layer, the polysilicon layer, the second dielectric layer on the surface of the substrate in the high-voltage device area, and the second dielectric layer on the surface of the substrate in the gate area of ​​the low-voltage device area, to obtain the gate structure and the corresponding gate dielectric layer.

[0015] The first dielectric layer is a silicon oxide layer or a nitrogen-containing silicon oxide layer, and the first dielectric layer is formed by a thermal oxidation process or an in-situ water vapor oxidation process; the second dielectric layer is a silicon oxide layer or a nitrogen-containing silicon oxide layer, and the silicon oxide layer or the nitrogen-containing silicon oxide layer is formed by an in-situ water vapor oxidation process.

[0016] In step S3, a second dielectric layer is formed on the substrate surface located in the low voltage device region and the substrate surface in the non-gate region of the high voltage device region.

[0017] The second dielectric layer further includes a high dielectric material layer and a metal barrier layer located on the silicon oxide layer or the silicon oxide layer containing nitride.

[0018] In a second aspect, the present application provides a method for forming a semiconductor structure, including a method for forming a gate dielectric layer as described in any one of the first aspects, and after step S4, further including forming a sidewall structure.

[0019] In a third aspect, the present application further provides a semiconductor structure prepared according to a method for forming a gate dielectric layer as described in any one of the first aspects.

[0020] In a fourth aspect, the present application further provides a semiconductor structure, which is prepared according to the method for forming a semiconductor structure described in the second aspect.

[0021] Compared with the prior art, the beneficial effects of the present invention mainly include the following: the technical solution can avoid the hidden dangers of undercutting that is easily generated when removing excess dielectric layers after gate etching in the prior art, or the subsequent sidewall failing to completely wrap the gate due to residual gate dielectric layers, and only needs to modify the photomask in the step of etching the first dielectric layer to solve the hidden dangers of the subsequent sidewall failing to completely wrap the gate due to possible residual dielectric layers in the subsequent gate etching and the undercutting problem, without the need to add additional process steps, and has high compatibility with existing processes, strong practicality, and can obtain a better process window. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 The figure is a schematic diagram of a formation process of a semiconductor structure in the prior art.

[0024] Figure 2 A schematic diagram of a formation process of a semiconductor structure provided by the present invention. DETAILED DESCRIPTION

[0025] The above and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or back, etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and not to limit the present invention.

[0026] The following will describe the various embodiments of the present application in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present application, many technical details are provided in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solution claimed in the present application can be implemented.

[0027] Figure 1 FIG. 1 is a schematic diagram of a semiconductor structure forming process in the prior art. Figure 1 In a, first, a substrate 100 is provided, and the substrate 100 is a silicon substrate; a low-voltage device area 101 and a high-voltage device area 102 are defined on the substrate 100, that is, the substrate 100 includes at least one low-voltage device area 101 and a high-voltage device area 102; an isolation structure 110 is also formed on the substrate 100, and the isolation structure 110 protrudes from the surface of the substrate 100; then a first dielectric layer 120 is formed on the surface of the substrate 100, and the first dielectric layer 120 covers the surface of the substrate 100 corresponding to the low-voltage device area 101 and the high-voltage device area 102.

[0028] It can be understood that the low-voltage device area 101 here is usually also called the core device area (Core), that is, the corresponding area for forming the core device; the high-voltage device area 102 is usually called the input-output device area (IO), that is, the corresponding area for forming the input-output device; the isolation structure 110 is usually a shallow trench isolation structure, which is obtained by etching the substrate 100 to form a groove and then filling it with silicon dioxide (in some cases, it also includes forming a pad oxide layer first, this structure is the prior art, and will not be elaborated here); the first dielectric layer 120 is usually made of silicon dioxide or nitrogen-containing silicon oxide, and its formation process is the prior art and will not be elaborated here.

[0029] Please continue to refer to Figure 1 b, removing the first dielectric layer 120 on the surface of the substrate 100 in the low voltage device area 101. Specifically, it generally includes forming a mask layer (such as a photoresist layer, not shown in the figure) on the surface of the high voltage device area 102 of the substrate 100, using the mask layer as an etching mask, and removing all the first dielectric layer 120 in the low voltage device area 101 through an etching process (such as dry etching, wet etching and non-plasma gas phase reaction etching), while the first dielectric layer 120 in the high voltage device area 102 continues to remain due to the protection of the etching mask.

[0030] Please continue to refer to Figure 1In step c, after removing the remaining mask layer, a second dielectric layer 130 is continuously formed on the surface of the substrate 100, the second dielectric layer 130 covers the surface of the substrate 100 in the low voltage device region 101, and the thickness of the second dielectric layer 130 is less than that of the first dielectric layer 120. Here, the formation of the second dielectric layer 130 can be achieved by an in-situ steam oxidation process.

[0031] Please continue to refer to Figure 1 d in the figure, a gate structure 140 is formed correspondingly in the gate regions of the low voltage device region 101 and the high voltage device region 102. Specifically, it generally includes forming a polysilicon layer and a hard mask layer on the surface of the substrate 100, and then patterning the polysilicon layer and the hard mask layer by a dry etching process to form the gate structure 140.

[0032] Please continue to refer to Figure 1 In the embodiment, after the gate structure 140 is formed, the dielectric layer outside the gate region needs to be removed, and only the portion at the bottom of the gate structure 140 is retained to form a gate dielectric layer. The existing process is to remove the excess dielectric layer by wet etching, including the portion of the first dielectric layer 120 located in the high-voltage device region 102 and the portion of the second dielectric layer 130 located in the low-voltage device region 101.

[0033] It can be understood that the removal of the dielectric layers in the two regions is carried out in the same etching process, and the etching rates of the dielectric layers in different regions are basically the same. However, since the thickness of the first dielectric layer 120 is greater than the thickness of the second dielectric layer 130, it is impossible to simultaneously ensure that both regions obtain ideal removal results.

[0034] Depending on the etching time, the second dielectric layer 130 may be over-etched or the first dielectric layer 120 may be under-etched. For example, when the etching time is long, the second dielectric layer 130 may be over-etched, causing the wet solution to corrode the bottom of the gate structure 140, forming an undercut phenomenon 150, resulting in an incomplete gate dielectric layer, which in turn affects the insulation performance between the gate and the channel, and is prone to tunneling leakage problems; similarly, if the etching time is short, the first dielectric layer 120 is under-etched, resulting in the first dielectric layer 120 outside the gate structure 140 not being completely removed to form oxide residues 160, which will make it impossible for the subsequent sidewall process to completely wrap the gate structure 140 and the gate dielectric layer, and then cause the risk of corroding the gate during the subsequent wet process (such as wet cleaning), such as Figure 1 As shown in f.

[0035] The steps in the following embodiments do not correspond one to one with the summary of the invention.

[0036] Embodiment 1

[0037] The present invention provides a method and structure for forming a gate dielectric layer and a semiconductor structure. Figure 2 Shown is a schematic diagram of a formation process of a semiconductor structure provided by an embodiment of the present invention.

[0038] refer to Figure 2 This embodiment first provides a method for forming a gate dielectric layer, comprising the following steps:

[0039] Step 1: providing a substrate 200 , the substrate comprising a low voltage device region 201 and a high voltage device region 202 , and an isolation structure 210 and a first dielectric layer 220 are formed on the substrate 200 .

[0040] Please refer to Figure 2 In a, the provided substrate 200 is a silicon substrate, and a low-voltage device area 201 and a high-voltage device area 202 are defined on the substrate 200, that is, the substrate 200 includes at least one low-voltage device area 201 and a high-voltage device area 202; an isolation structure 210 has been pre-formed on the substrate 200, and the isolation structure 210 protrudes from the surface of the substrate 200; a first dielectric layer 220 is also formed on the surface of the substrate 200, and the first dielectric layer 220 covers the surface of the substrate 200 corresponding to the low-voltage device area 201 and the high-voltage device area 202.

[0041] It can be understood that the low-voltage device area 201 here is usually also called the core device area (Core), that is, the corresponding area for forming the core device; the high-voltage device area 202 is usually called the input-output device area (IO), that is, the corresponding area for forming the input-output device; the isolation structure 210 is usually a shallow trench isolation structure, which is obtained by etching the substrate 200 to form a groove and then filling it with silicon dioxide (in some cases, it also includes forming a cushion oxide layer first, this structure is the prior art, and will not be elaborated here); the first dielectric layer 220 is usually made of silicon dioxide or nitrogen-containing silicon oxide, and its formation process is the prior art, and will not be elaborated here. The first dielectric layer 220 is used to form a high-voltage gate dielectric layer later, and its thickness is relatively large.

[0042] In this embodiment, the formation process of the provided substrate 200 and the structure on the substrate 200 is not limited. For example, the isolation structure 210 may be formed first and then the first dielectric layer 220 may be formed, or the first dielectric layer 220 may be formed first and then the isolation structure 210 may be formed.

[0043] Step 2: forming an etching mask 230 in the gate region of the high voltage device region 202 .

[0044] Please continue to refer to Figure 2b in the figure, an etching mask 230 is formed in the gate region of the high voltage device region 202 in the substrate 200. It can be understood that in the present application, the gate region refers to the region on the substrate 200 where the gate structure is to be formed later, including the gate region located in the high voltage device region 202 and the gate region located in the low voltage device region 201; similarly, the non-gate region refers to the remaining region outside the gate region. Specifically, a layer of photoresist is first spin-coated on the surface of the substrate 200 to form a photoresist layer, and then the patterning of the photoresist layer is completed through exposure, development and other processes, and an etching mask 230 is formed on the first dielectric layer 220 of the gate region on the above-mentioned substrate 200. The etching mask 230 can protect the first dielectric layer 220 thereunder from being etched during the subsequent etching process.

[0045] Step 3: Remove the remaining portion of the first dielectric layer 220 by etching.

[0046] Please continue to refer to Figure 2 In step c, the substrate 200 is etched to remove the first dielectric layer 220. Under the protection of the etching mask 230, the first dielectric layer 220 corresponding to the gate region of the high voltage device region 202 is retained, while the first dielectric layer 220 of the remaining regions (i.e., including the non-gate region of the high voltage device region 202 and the low voltage device region 201 on the substrate 200) is removed. The etching process used in this step can be any one of dry etching, wet etching and non-plasma gas phase reaction etching (i.e., Certas gas phase etching).

[0047] Step 4: Form a second dielectric layer 240 on the surface of the substrate 200 .

[0048] Please continue to refer to Figure 2 d in the figure, after removing the remaining etching mask 230, a second dielectric layer 240 is formed on the surface of the substrate 200, and the second dielectric layer 240 covers the surface of the substrate 200 in the low-voltage device area 201 and the surface of the substrate 200 in the non-gate area in the high-voltage device area 202, and the thickness of the second dielectric layer 240 is less than the first dielectric layer 220.

[0049] In this embodiment, an in-situ steam oxidation process (ISSG, In Situ Steam Generation) is used to prepare the second dielectric layer 240. This process only reacts with silicon on the surface of the silicon substrate to form a high-quality silicon oxide layer. Therefore, the second dielectric layer 240 of the required thickness can be accurately grown at the oxide-free positions of the low-voltage device area 201 and the high-voltage device area 202, and the thickness of the second dielectric layer 240 formed in the low-voltage device area 201 and the high-voltage device area 202 can be ensured to be the same.

[0050] In this embodiment, a common gate oxide dielectric layer (i.e., a silicon oxide layer or a silicon oxide layer containing nitrogen) is used as the second dielectric layer 240 to form a gate dielectric layer. In fact, the present invention is also applicable to the HKMG structure. In this case, the structure of the second dielectric layer 240 formed will be changed accordingly. In this case, the second dielectric layer 240 includes a gate oxide dielectric layer (i.e., a silicon oxide layer or a silicon oxide layer containing nitrogen), a high dielectric material layer (e.g., HfO2, HfSiO, or HfSiON, etc.), and a metal barrier layer (BBM, bottom barrier The formation process generally includes: forming a gate oxide dielectric layer in the corresponding area by ISSG, and then forming a high dielectric material layer on the surface of the gate oxide dielectric layer by atomic layer deposition (ALD), and then forming a metal barrier layer on the surface of the high dielectric material layer by ALD or physical vapor deposition (PVD) or chemical vapor deposition (CVD) process; finally, the gate dielectric layer formed on the low voltage device area 201 and the high voltage device area 202 has the same structure composition, including a gate oxide dielectric layer, a high dielectric material layer and a metal barrier layer.

[0051] Step 5: Form a gate structure 250 and a corresponding gate dielectric layer.

[0052] It should be noted that the formation of the gate structure 250 and the corresponding gate dielectric layer in step 5 is a prior art, and an example is used to briefly illustrate the process below. Other methods may also be used, and this application does not make strict limitations on this. Please continue to refer to Figure 2 In the embodiment of the present invention, a gate structure 250 and a corresponding gate dielectric layer are formed in the gate regions of the low-voltage device region 201 and the high-voltage device region 202 of the substrate 200 by a combination of dry etching and wet etching. Specifically, a polysilicon layer 251 and a hard mask layer 252 are sequentially formed on the surface of the substrate 200, and then the polysilicon layer 251 and the hard mask layer 252 are patterned by an etching process to form the gate structure 250, and then the second dielectric layer 240 in the non-gate region is removed by an etching process, and only the bottom portion of the gate structure 250 is retained to form the corresponding gate dielectric layer.

[0053] In the present embodiment, the second dielectric layer 240 is a silicon oxide layer or a silicon oxide layer containing nitrogen, and the removal of the structure is usually processed by wet etching to remove the second dielectric layer 240 located in the high-voltage device area 202 to obtain the high-voltage gate dielectric layer 221, and remove the second dielectric layer 240 located in the non-gate area of ​​the low-voltage device area 201 to obtain the low-voltage gate dielectric layer 241. It can be understood that in other embodiments, when the structure of the second dielectric layer 240 includes a gate oxide dielectric layer (i.e., a silicon oxide layer or a silicon oxide layer containing nitrogen), a high dielectric material layer, and a metal barrier layer, it is usually removed by dry etching to the surface of the gate oxide dielectric layer, and then the remaining gate oxide dielectric layer is removed by wet etching.

[0054] In this embodiment, the hard mask layer 252 can generally be made of silicon nitride material or silicon oxide material, and can be a single-layer structure or a combination of multi-layer structures, which is not limited in this application.

[0055] At this point, the preparation of the gate dielectric layer has been completed, and the gate dielectric layer includes a high-voltage gate dielectric layer 221 located at the bottom of the gate structure 250 in the high-voltage device area 202 and a low-voltage gate dielectric layer 241 located at the bottom of the gate structure 250 in the low-voltage device area 201 .

[0056] It can be understood that through the method for forming the gate dielectric layer provided in the present application, what is etched and removed in this step 5 is the second dielectric layer 240, and the thickness of the second dielectric layer 240 in the two regions is consistent, thereby avoiding the hidden danger of undercut (Undercut) or oxide residue (Oxide Residue) caused by the difference in dielectric layer thickness in the prior art, which causes the subsequent side wall to fail to completely wrap the gate, thereby ensuring the performance of the device.

[0057] Compared with the prior art, the method for forming a gate dielectric layer provided in the present application only needs to modify the mask in the step of etching the first dielectric layer to solve the possible dielectric layer residue and undercut problems in the subsequent gate etching, without adding additional process steps. It has high compatibility with the existing process, strong practicality, and can obtain a better process window.

[0058] The present application also provides a method for forming a semiconductor structure, which first includes steps 1 to 5 in the aforementioned method for forming a gate dielectric layer, and further includes the following step 6:

[0059] Step 6: forming a sidewall structure 260 .

[0060] It is understood that the formation of the sidewall structure 260 can be performed using existing sidewall processes, and generally silicon nitride is selected as a material, which will not be described in detail here. Figure 2 In g, due to the use of the gate dielectric layer forming method provided in the present application, when the sidewall structure 260 is formed in this step, the bottom of the gate can be completely wrapped, thereby ensuring the performance of the device.

[0061] The present application also provides a semiconductor structure, which is prepared by the method for forming a gate dielectric layer in the present application.

[0062] The present application also provides another semiconductor structure, which is prepared by a semiconductor structure forming method in the present application.

[0063] In order to facilitate the description, some common English nouns or letters used in the present invention are only used for exemplary reference rather than restrictive interpretation or specific usage, and the protection scope of the present invention should not be limited by their possible Chinese translations or specific letters.

[0064] It should also be noted that, in this document, relational terms such as "first" and "second" are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

Claims

1. A method for forming a gate dielectric layer, characterized in that: The steps include: S1. Providing a substrate, wherein the substrate includes a high-voltage device region and a low-voltage device region, and an isolation structure and a first dielectric layer are formed on the substrate; S2, removing the first dielectric layer located in the low voltage device area and the first dielectric layer in the non-gate area of ​​the high voltage device area by an etching process; S3, forming a second dielectric layer on the surface of the substrate, wherein the thickness of the second dielectric layer is lower than that of the first dielectric layer; S4. Forming a gate structure and a corresponding gate dielectric layer in the high voltage device region and the low voltage device region on the substrate.

2. The method for forming a gate dielectric layer according to claim 1, characterized in that: In step S2, an etching mask is formed on the first dielectric layer in the gate region of the high-voltage device region, and the first dielectric layer in the low-voltage device region and the first dielectric layer in the non-gate region of the high-voltage device region are removed by an etching process; the etching process is any one of dry etching, wet etching and non-plasma gas phase reaction etching.

3. The method for forming a gate dielectric layer according to claim 2, characterized in that: In step S2, the step of forming the etching mask includes: forming a photoresist layer on the surface of the substrate; The photoresist layer is patterned, and the photoresist on the first dielectric layer in the gate region of the high-voltage device region is retained as an etching mask.

4. The method for forming a gate dielectric layer according to claim 1, characterized in that: In step S4, the steps of forming the gate structure and the corresponding gate dielectric layer include: forming a polysilicon layer and a hard mask layer in sequence on the surface of the substrate; forming a patterned photoresist layer on the surface of the hard mask layer; Using the patterned photoresist layer as an etching mask, the hard mask layer, the polysilicon layer, the second dielectric layer on the substrate surface of the high-voltage device area, and the second dielectric layer on the substrate surface of the gate area of ​​the low-voltage device area are removed by a combination of dry etching and wet etching processes to obtain the gate structure and the corresponding gate dielectric layer.

5. The method for forming a gate dielectric layer according to claim 4, characterized in that: The first dielectric layer is a silicon oxide layer or a nitrogen-containing silicon oxide layer, and the first dielectric layer is formed by a thermal oxidation process or an in-situ water vapor oxidation process; The second dielectric layer is a silicon oxide layer or a silicon oxide layer containing nitrogen, and the silicon oxide layer or the silicon oxide layer containing nitrogen is formed by an in-situ water vapor oxidation process.

6. The method for forming a gate dielectric layer according to claim 5, characterized in that: In step S3, a second dielectric layer is formed on the substrate surface located in the low voltage device region and the substrate surface in the non-gate region of the high voltage device region.

7. The method for forming a gate dielectric layer according to claim 5, characterized in that: The second dielectric layer further includes a high dielectric material layer and a metal barrier layer located on the silicon oxide layer or the silicon oxide layer containing nitride.

8. A method for forming a semiconductor structure, comprising the method for forming a gate dielectric layer according to any one of claims 1 to 7, characterized in that: After step S4, the process further includes forming a sidewall structure.

9. A semiconductor structure, characterized in that: It is prepared according to the method for forming a gate dielectric layer according to any one of claims 1 to 7.

10. A semiconductor structure, characterized in that: The semiconductor structure is prepared according to the method for forming a semiconductor structure according to claim 8.

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