Field effect transistor and preparation method
By setting the ferroelectric layer and semiconductor layer in a perpendicular direction on the substrate, forming a transverse gate structure and abolishing the dielectric layer, the problem of complex structure of the existing ferroelectric field effect transistor is solved, and structural simplification and functional improvement are achieved.
Patent Information
- Application Number
- CN202510161276.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-13
- Publication Date
- 2025-05-13
AI Technical Summary
The existing ferroelectric field effect transistors have complex structures, which leads to difficult and high cost in preparation processes, and requires fine control of multi-layer structures, affecting large-scale production and application.
By setting the ferroelectric layer and the semiconductor layer on the substrate in a direction perpendicular to each other, the projected overlapping parts of the two on the substrate contact each other, forming a transverse gate structure, canceling the dielectric layer, and simplifying the structure.
The structure of the ferroelectric field effect transistor is simplified, reducing the difficulty and cost of the preparation process, and improving the functionality and production efficiency of the device.
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Figure CN119997587A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a field effect transistor and a preparation method thereof. Background Art
[0002] As a new type of memory device and neuromorphic computing device, ferroelectric field effect transistor has the advantages of high speed, low power consumption, non-destructive reading and writing, and high-density integration. Ferroelectric field effect transistors are usually designed as vertical gate structures or lateral gate structures. In order to reduce the problem of large leakage current in vertical gate structures, lateral gate structures are preferred.
[0003] In the horizontal wire gate structure, in order to prevent the gate from connecting to the channel of the semiconductor layer, an additional dielectric layer is added between the ferroelectric layer and the semiconductor layer for isolation. This will increase the number of stacked layers of the overall device structure, making the overall structure more complex. The thickness of each layer of the structure needs to be carefully controlled, which increases the difficulty and cost of manufacturing the device, and is not conducive to mass production and application. Summary of the invention
[0004] The main purpose of the present application is to provide a field effect transistor and a preparation method thereof, aiming to solve the technical problem of how to make the structure of a ferroelectric field effect transistor simpler.
[0005] To achieve the above object, an embodiment of the present application provides a field effect transistor, the field effect transistor comprising:
[0006] A substrate, wherein one side of the substrate is provided with a gate region, a ground region, a source region and a drain region which are not in contact with each other;
[0007] A ferroelectric layer is disposed on the substrate along a first direction, and two ends of the ferroelectric layer are respectively connected to the gate region and the ground region;
[0008] A semiconductor layer is disposed on the substrate along the second direction, and two ends of the semiconductor layer are respectively connected to the source region and the drain region;
[0009] The first direction is perpendicular to the second direction, a projection of the ferroelectric layer and a projection of the semiconductor layer intersect in a preset area, and the ferroelectric layer and the semiconductor layer in the preset area are in contact with each other.
[0010] In one embodiment, the ferroelectric layer comprises a two-dimensional ferroelectric crystal.
[0011] In one embodiment, the semiconductor layer includes a two-dimensional semiconductor crystal.
[0012] In one embodiment, the substrate comprises a silicon dioxide substrate.
[0013] In one embodiment, the gate region, the ground region, the source region, and the drain region are each provided with a metal electrode, and the electrode materials of the metal electrodes include titanium and gold, and the gold covers the outer surface of the titanium.
[0014] In one embodiment, the ferroelectric layer is located above the semiconductor layer.
[0015] The present application also proposes a method for preparing the field effect transistor, the steps of the method for preparing the field effect transistor comprising:
[0016] Selecting a preset substrate, a ferroelectric material, and a semiconductor material respectively;
[0017] Placing the ferroelectric material on a preset tape and performing image processing to obtain a two-dimensional ferroelectric material;
[0018] Transferring the semiconductor material to the preset substrate and performing imaging processing to obtain a two-dimensional semiconductor material;
[0019] Transferring the two-dimensional ferroelectric material to above the plane where the two-dimensional semiconductor material is located to form a heterostructure, wherein the two-dimensional ferroelectric material and the two-dimensional semiconductor material are arranged perpendicular to each other and two ends of the two-dimensional ferroelectric material do not contact two ends of the two-dimensional semiconductor material;
[0020] The heterostructure is subjected to photolithography, electroplating and solvent cleaning in sequence to obtain a corresponding lateral gate ferroelectric field effect transistor.
[0021] In one embodiment, the step of transferring the two-dimensional ferroelectric material to above the plane where the two-dimensional semiconductor material is located to form a heterostructure comprises:
[0022] Extracting the two-dimensional ferroelectric material on the preset tape through the PDMS film;
[0023] By using a transfer table and an optical microscope, the PDMS film is moved to the top of the two-dimensional semiconductor material, and the PDMS film is attached to the top of the two-dimensional semiconductor material at an angle perpendicular to the two-dimensional semiconductor, and the two ends of the two-dimensional ferroelectric material are kept not in contact with the two ends of the two-dimensional semiconductor material;
[0024] The PDMS film is removed to form the heterostructure.
[0025] In one embodiment, the step of sequentially performing photolithography, electroplating and solvent cleaning on the heterostructure to obtain a corresponding lateral gate iron field effect transistor comprises:
[0026] Coating a photoresist on the surface of the heterostructure;
[0027] Based on a preset electrode pattern, exposing and developing the photoresist to obtain a preset electrode area on the surface of the heterostructure;
[0028] Electroplating the preset electrode area with a preset metal material;
[0029] The heterostructure after the electroplating treatment is cleaned by a preset solvent to obtain the lateral gate ferroelectric field effect transistor.
[0030] In one embodiment, the lateral gate ferroelectric field effect transistor includes a gate, a drain, a source and a ground electrode, and after the steps of sequentially performing photolithography, electroplating and solvent cleaning on the heterostructure to obtain the corresponding lateral gate ferroelectric field effect transistor, the steps further include:
[0031] A first preset electric field is set between the gate and the ground electrode, and a second preset electric field is set between the source and the drain, and a test current between the source and the drain is collected;
[0032] Determining an electrical property test result of the lateral gate iron field effect transistor based on the test current, the first preset electric field, and the second preset electric field;
[0033] Based on the electrical test result, it is determined whether the lateral gate iron field effect transistor is a good product.
[0034] An embodiment of the present application provides a field effect transistor and a preparation method thereof, wherein the field effect transistor comprises: a substrate, wherein one side of the substrate is provided with a gate region, a ground region, a source region and a drain region which are not in contact with each other; a ferroelectric layer, which is arranged on the substrate along a first direction, and wherein two ends of the ferroelectric layer are respectively connected to the gate region and the ground region; a semiconductor layer, which is arranged on the substrate along a second direction, and wherein two ends of the semiconductor layer are respectively connected to the source region and the drain region; wherein the first direction is perpendicular to the second direction, and the projection of the ferroelectric layer and the projection of the semiconductor layer intersect in a preset region, and the ferroelectric layer and the semiconductor layer in the preset region are in contact with each other.
[0035] On the substrate, the ferroelectric layer and the semiconductor layer are arranged in a first direction and a second direction perpendicular to each other, respectively, so that the overlapping parts of the projections of the two on the substrate are in contact with each other, and the gate area and the ground area connected at both ends of the ferroelectric layer and the source area and the drain area connected at both ends of the semiconductor layer are not in contact with each other. Through the above arrangement, the ferroelectric layer forms a lateral gate structure, and the carrier concentration of the semiconductor layer can be regulated based on the lateral gate electric field to achieve the functions of switching and storage. At the same time, since the ferroelectric layer and the semiconductor layer are arranged perpendicular to each other, the gate electric field is more evenly distributed in the semiconductor layer, reducing the leakage current caused by the electric field concentration effect. There is no need to set a dielectric layer between the ferroelectric layer and the semiconductor layer, and the overall structure is simple and the functionality is better. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.
[0037] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.
[0038] Figure 1 A schematic diagram of the structure of the field effect transistor embodiment 1 of the present application;
[0039] Figure 2 A schematic diagram of a process flow diagram provided for Embodiment 1 of the method for preparing a field effect transistor of the present application;
[0040] Figure 3 A schematic diagram of the process flow of the second embodiment of the method for preparing a field effect transistor of the present application.
[0041] The purpose, features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION
[0042] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.
[0043] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.
[0044] This application proposes a first embodiment of a field effect transistor, please refer to Figure 1 , the field effect transistor comprises:
[0045] A substrate 10, wherein one side of the substrate 10 is provided with a gate region 11, a ground region 12, a source region 13 and a drain region 14 which are not in contact with each other;
[0046] A ferroelectric layer 20 is disposed on the substrate 10 along a first direction, and two ends of the ferroelectric layer 20 are respectively connected to the gate region 11 and the ground region 12;
[0047] A semiconductor layer 30 is disposed on the substrate 10 along a second direction, and two ends of the semiconductor layer 30 are respectively connected to the source region 13 and the drain region 14;
[0048] The first direction is perpendicular to the second direction, a projection of the ferroelectric layer 20 and a projection of the semiconductor layer 30 intersect in a preset area, and the ferroelectric layer 20 and the semiconductor layer 30 are in contact with each other in the preset area.
[0049] It should be understood that, in the present embodiment, the substrate 10 is the basic supporting structure of the field effect transistor, and can also be understood as the starting structural layer of the entire device. Other materials, such as a ferroelectric layer 20 and a semiconductor layer 30, can be built on the substrate 10; the ferroelectric layer 20 refers to a material layer composed of ferroelectric materials, which can produce a ferroelectric effect, that is, spontaneous polarization occurs when no external electric field is applied, and the spontaneous polarization phenomenon can be reversed or redirected under the action of an external electric field; the semiconductor layer 30 refers to a material layer composed of semiconductor materials, which can realize functions such as current transmission and carrier control.
[0050] It is worth noting that in the present embodiment, the substrate 10 can specifically be a silicon dioxide substrate, which has stable chemical properties, is resistant to high temperature and high pressure, and has high reliability; the ferroelectric layer 20 can be composed of a two-dimensional ferroelectric crystal, and each unit cell of the ferroelectric material inside it is spread out as an extreme plane structure. Correspondingly, the semiconductor layer 30 can be composed of a two-dimensional semiconductor crystal, and each unit cell of the semiconductor material inside it is spread out as an extreme plane structure, which can facilitate the control of the thickness parameters of the ferroelectric layer 20 and the semiconductor layer 30.
[0051] It should be noted that you can refer to Figure 1 , the first direction and the second direction refer to two mutually perpendicular directions, which can be specifically two mutually perpendicular directions in a plane (perpendicular to the Z-axis plane) on which the ferroelectric layer 20 and / or the semiconductor layer 30 are located on the substrate 10. In this embodiment, the ferroelectric layer 20 is disposed on the substrate 10 along the first direction (Y-axis direction), and the semiconductor layer 30 is disposed on the substrate 10 along the second direction (X-axis direction).
[0052] It should be understood that the substrate 10 may also be provided with a gate region 11, a ground region 12, a source region 13 and a drain region 14. The gate region 11 is provided with a metal electrode serving as a gate of a field effect transistor. Correspondingly, the source region 13 is provided with a metal electrode serving as a source of the field effect transistor, the drain region 14 is provided with a metal electrode serving as a drain of the field effect transistor, and the ground region 12 is provided with a metal electrode for connecting a ground line to provide a reference potential. In the present embodiment, the gate region 11 and the ground region 12 are respectively provided at both ends of the ferroelectric layer 20, so that the ferroelectric layer 20 forms a lateral gate structure, and the gate region 11 can be connected to the ground region 12 through the ferroelectric layer 20, and the source region 13 and the drain region 14 are respectively provided at both ends of the semiconductor layer 30, and the source region 13 can be connected to the drain region 14 through the semiconductor layer 30.
[0053] It is worth emphasizing that, in the present embodiment, the gate region 11, the source region 13, the drain region 14 and the grounding region 12 are all at a certain distance from each other and do not contact each other. It can also be considered that the "source region 13-semiconductor layer 30-drain region 14" and the "gate region 11-ferroelectric layer 20-grounding region 12" are arranged on the substrate 10 in the shape of a "cross". Figure 1 As shown in the right picture, the right picture is a simplified diagram of the left picture in the top view.
[0054] It should be noted that, in the present embodiment, the ferroelectric layer 20 can be located above the semiconductor layer 30 and the substrate 10, or between the semiconductor layer 30 and the substrate 10, and the projection of the ferroelectric layer 20 on the substrate 10 and the projection of the semiconductor layer 30 on the substrate 10 have a certain overlap area, i.e., a preset area. The semiconductor layer 30 and the ferroelectric layer 20 in the preset area are in direct contact, and no dielectric layer is required for isolation.
[0055] In a specific implementation, since the ferroelectric layer 20 has a ferroelectric effect, it can undergo spontaneous polarization without applying an external electric field, and can be reversed or redirected when an external electric field is applied, so the structure can achieve storage characteristics; when an external electric field is applied to the gate region 11 and the metal electrodes in the grounding region 12 (i.e., applying a gate electric field), since the ferroelectric layer 20 is in direct contact with the semiconductor layer 30, the carrier concentration in the semiconductor layer 30 can be controlled based on the ferroelectric effect of the ferroelectric layer 20, thereby achieving switching characteristics, that is, the device using this structure can still be compatible with storage characteristics and switching characteristics.
[0056] As a preferred method, since the semiconductor layer 30 is generally deposited directly on the substrate 10, and the ferroelectric layer 20 generally needs to be transferred from the outside to the substrate 10, the ferroelectric layer 20 can be set above the semiconductor layer 30. This structure is convenient for mass production and further reduces the process difficulty of device preparation.
[0057] In addition, the electrode regions of the structural device do not contact each other, and the semiconductor layer 30 connected between the drain region 14 and the source region 13 is arranged in a vertical cross-stacked form relative to the ferroelectric layer 20 connected between the gate region 11 and the ground region 12, which makes it difficult for the gate region 11 to contact the semiconductor layer 30. Therefore, the dielectric layer used for isolation in the traditional structure can be eliminated, and there will be no situation where the metal electrode (gate) in the gate region 11 and the semiconductor layer 30 contact each other and cause the device to fail.
[0058] It is worth noting that, in the present embodiment, the metal electrodes corresponding to the gate region 11, the ground region 12, the source region 13 and the drain region 14 can be obtained by electroplating through an electron beam evaporation process, and the electroplating process can use metal materials, including titanium and gold. In a specific implementation, a layer of titanium can be plated on the surface of each electrode region first to improve the adhesion between the material layers and improve the reliability and stability of the device structure; then a layer of gold is plated on the surface of the titanium. Gold has excellent corrosion resistance and conductivity, can protect the electrode from oxidation, and can also reduce the impedance of the device. As a preferred method, the thickness of titanium in each electrode region can be set to about 10nm, and the thickness of gold can be set to about 50nm.
[0059] An embodiment of the present application provides a field effect transistor, which includes: a substrate, one side of which is provided with a gate region, a ground region, a source region and a drain region that are not in contact with each other; a ferroelectric layer, which is arranged on the substrate along a first direction, and the two ends of the ferroelectric layer are respectively connected to the gate region and the ground region; a semiconductor layer, which is arranged on the substrate along a second direction, and the two ends of the semiconductor layer are respectively connected to the source region and the drain region; wherein the first direction is perpendicular to the second direction, the projection of the ferroelectric layer and the projection of the semiconductor layer intersect in a preset area, and the ferroelectric layer and the semiconductor layer in the preset area are in contact with each other.
[0060] On the substrate, the ferroelectric layer and the semiconductor layer are arranged in a first direction and a second direction perpendicular to each other, respectively, so that the overlapping parts of the projections of the two on the substrate are in contact with each other, and the gate area and the ground area connected at both ends of the ferroelectric layer and the source area and the drain area connected at both ends of the semiconductor layer are not in contact with each other. Through the above arrangement, the ferroelectric layer forms a lateral gate structure, and the carrier concentration of the semiconductor layer can be regulated based on the lateral gate electric field to achieve the functions of switching and storage. At the same time, since the ferroelectric layer and the semiconductor layer are arranged perpendicular to each other, the gate electric field is more evenly distributed in the semiconductor layer, reducing the leakage current caused by the electric field concentration effect. There is no need to set a dielectric layer between the ferroelectric layer and the semiconductor layer, and the overall structure is simple and the functionality is better.
[0061] The present application also provides a method for preparing a field effect transistor. Figure 2 , the field effect transistor preparation method comprises:
[0062] Step S10, selecting a preset substrate, a ferroelectric material, and a semiconductor material respectively;
[0063] It is easy to understand that in this embodiment, before preparing the field effect transistor, it is necessary to first select the preparation materials, and select a clean, appropriately sized preset substrate, ferroelectric material and semiconductor material as raw materials for preparing the field effect transistor, wherein the selected ferroelectric material can be a sheet-like two-dimensional ferroelectric single crystal, and the specific length and width dimensions can be approximately 0.3 cm.
[0064] Step S20, placing the ferroelectric material on a preset tape and performing imaging processing to obtain a two-dimensional ferroelectric material;
[0065] It should be noted that the preset tape can be a tape with high-intensity tear resistance, easy to stick, waterproof and moisture-proof and high temperature resistance, such as Scotch tape. In this embodiment, a ferroelectric material of a suitable size can be placed in a preset tape and folded repeatedly to form a multi-layer structure, and then peeled off to form multiple layers of two-dimensional ferroelectric sheets of different or equal thicknesses. After imaging it according to a specific image, a two-dimensional ferroelectric material can be obtained. Among them, the planar shape of the two-dimensional ferroelectric material can be a rectangle or other specific graphics of other designs.
[0066] Step S30, transferring the semiconductor material to the preset substrate, performing image processing, and obtaining a two-dimensional semiconductor material;
[0067] It should be noted that, in this embodiment, while the ferroelectric material is being processed, the selected semiconductor material can be transferred to a preset substrate by means of deposition, and in this process, the thickness of the semiconductor material deposited on the preset substrate needs to be controlled. Subsequently, the corresponding two-dimensional semiconductor material can be obtained by imaging the deposited material on the preset substrate. Similar to the two-dimensional ferroelectric material, the planar shape of the two-dimensional semiconductor material can also be a rectangle or other specific graphics of other designs.
[0068] Step S40, transferring the two-dimensional ferroelectric material to above the plane where the two-dimensional semiconductor material is located to form a heterostructure, wherein the two-dimensional ferroelectric material and the two-dimensional semiconductor material are arranged perpendicular to each other and two ends of the two-dimensional ferroelectric material do not contact two ends of the two-dimensional semiconductor material;
[0069] It should be noted that organic silica gel refers to a high molecular weight silicon compound obtained by polymerization reaction, which has excellent properties such as transparency, strong flexibility and strong corrosion resistance, and can be used to extract the two-dimensional ferroelectric material pasted on the preset tape. Heterostructure refers to a special structure formed by depositing two or more layers of thin films of different materials on the same substrate in sequence. In this embodiment, the two-dimensional ferroelectric material can be extracted from the preset tape by organic silica gel, and a two-dimensional ferroelectric material of suitable thickness is selected and moved parallel to the top of the preset substrate. At this time, the horizontal angle of the organic silica gel can be rotated so that the projection of the two-dimensional ferroelectric material on the preset substrate and the projection of the semiconductor material on the preset substrate are kept in a mutually perpendicular "cross" state (the four endpoints are set at a certain distance from each other and do not contact each other), and the organic silica gel is vertically attached to the surface of the two-dimensional semiconductor, that is, the two-dimensional ferroelectric material is stacked on the top of the two-dimensional semiconductor in a mutually perpendicular and staggered form. After standing for a period of time, the organic silica gel is removed to obtain a heterostructure composed of a "ferroelectric layer", a "semiconductor layer" and a "preset substrate" stacked from top to bottom.
[0070] It is worth noting that in this embodiment, after the two-dimensional ferroelectric material is extracted by organic silica gel, the two-dimensional ferroelectric material on the organic silica gel can be observed by an optical microscope to screen out the two-dimensional ferroelectric material of suitable thickness. The thickness of the two-dimensional ferroelectric material can be preliminarily distinguished according to its color. The thinner the thickness, the closer the color displayed is to the color of the substrate. Generally, the two-dimensional ferroelectric material of suitable thickness is grayish.
[0071] Step S50, performing photolithography, electroplating and solvent cleaning on the heterostructure in sequence to obtain a corresponding lateral gate ferroelectric field effect transistor.
[0072] It should be noted that, in the present embodiment, after obtaining the heterostructure, a surface coating of a two-dimensional ferroelectric material and a two-dimensional semiconductor material can be applied with a photoresist, and photolithography is performed, so as to obtain four electrode areas that do not contact each other on both sides of the two-dimensional ferroelectric material and the two-dimensional semiconductor material. Subsequently, the electrode area is electroplated, and after electroplating, the entire heterostructure is cleaned by a preset solvent to remove impurities such as the photoresist, and the required field effect transistor can be prepared. The field effect transistor prepared in this way, the ferroelectric material in its internal structure forms a ferroelectric layer, and the ferroelectric layer forms a lateral gate structure between the metal electrode in the gate area and the metal electrode in the grounding area, so it can also be considered as a lateral gate ferroelectric field effect transistor.
[0073] The embodiment of the present application provides a method for preparing a field effect transistor, wherein after selecting a preset substrate, a ferroelectric material and a semiconductor material, the selected ferroelectric material is placed on a preset tape for graphic processing to obtain a two-dimensional ferroelectric material, and after transferring the selected semiconductor material to the selected preset substrate for graphic processing to obtain a two-dimensional semiconductor material, the two-dimensional ferroelectric material is aligned with the two-dimensional semiconductor material and transferred to the top of the two-dimensional semiconductor material at a mutually perpendicular angle, and it is ensured that the two ends of the two-dimensional ferroelectric material after the transfer do not contact the two ends of the two-dimensional semiconductor material, thereby forming a heterostructure formed from top to bottom by the ferroelectric material, the semiconductor material and the preset substrate. Then, the surface of the heterostructure is subjected to photolithography and electroplating to form corresponding electrodes, and after solvent cleaning, a lateral gate ferroelectric field effect transistor can be obtained.
[0074] Since there is no dielectric layer in the prepared lateral gate ferroelectric field effect transistor, it is only necessary to transfer the semiconductor material to a preset substrate in a specific pattern, and then build the ferroelectric material of the specific pattern on the semiconductor material at a relatively vertical angle to obtain a heterostructure that can realize the basic functions of the device. Subsequently, the heterostructure is subjected to simple photolithography, electroplating, and cleaning to prepare the final lateral gate ferroelectric field effect transistor. While ensuring that the function of the device is not affected, the dielectric layer inside the device is eliminated, the control accuracy requirements of the thickness of each layer structure are reduced, the production process is simpler, and the cost is reduced.
[0075] Based on the first embodiment of the method for preparing a field effect transistor of the present application, in the second embodiment of the method for preparing a field effect transistor of the present application, the same or similar contents as those in the first embodiment can be referred to the above description, and will not be described in detail later. Figure 3 , the step of transferring the two-dimensional ferroelectric material to above the plane where the two-dimensional semiconductor material is located to form a heterostructure comprises:
[0076] Step S41, extracting the two-dimensional ferroelectric material on the preset tape through the PDMS film;
[0077] It should be noted that, in this embodiment, the organic silica gel can be a polydimethylsiloxane film (PDMS), that is, a PDMS film, which is colorless, non-toxic, odorless, transparent, resistant to high temperature and corrosion, and has excellent stability and reliability. In a specific implementation, the PDMS film can be attached to a preset tape, and after moderate pressing and standing for a few minutes, the PDMS film can be separated from the preset tape, and the two-dimensional ferroelectric material on the preset tape can be extracted onto the PDMS film.
[0078] Step S42, moving the PDMS film to above the two-dimensional semiconductor material through a transfer table and an optical microscope, and attaching the PDMS film to above the two-dimensional semiconductor material at an angle perpendicular to the two-dimensional semiconductor, while keeping the two ends of the two-dimensional ferroelectric material and the two ends of the two-dimensional semiconductor material not in contact with each other;
[0079] Step S43, removing the PDMS film to form the heterostructure.
[0080] It should be noted that in this embodiment, a transfer table can be used to move the PDMS film to the top of the two-dimensional semiconductor material by dry transfer technology under an optical microscope, and the PDMS film is attached to the surface above the two-dimensional semiconductor material while keeping the projection of the two-dimensional ferroelectric material and the projection of the two-dimensional semiconductor perpendicular to each other. After standing for a certain period of time, the PDMS film is removed to transfer the two-dimensional ferroelectric material to the top of the two-dimensional semiconductor material at a desired angle, thereby forming a desired heterogeneous structure.
[0081] Further, in this embodiment, the steps of sequentially performing photolithography, electroplating and solvent cleaning on the heterostructure to obtain a corresponding lateral gate ferroelectric field effect transistor include:
[0082] Step S51, coating photoresist on the surface of the heterostructure;
[0083] It should be noted that, in this embodiment, after obtaining the heterostructure, photoresist can be coated on the surface of the heterostructure on which the two-dimensional ferroelectric material and the two-dimensional semiconductor material are stacked, and high-speed coating and high-temperature heating and solidification can be performed.
[0084] As a preferred case, the model of the photoresist may be AZ5214; the coating process may be achieved by a coating machine, and the parameters of high-speed coating may be 5000r / min, lasting for 30s; the high-temperature heating process may be achieved by a heating table, and the heating parameters are 100°C, lasting for 1min.
[0085] Step S52, exposing and developing the photoresist based on a preset electrode pattern to obtain a preset electrode area on the surface of the heterostructure;
[0086] It should be noted that the preset electrode pattern is a projection pattern corresponding to each electrode area on a preset substrate, which is set based on the shape of the two-dimensional ferroelectric material and the two-dimensional semiconductor material, and is mainly distributed at both ends of the two-dimensional ferroelectric material and the two-dimensional semiconductor material. The preset electrode area is the area on the preset substrate used to build the gate, drain, source and ground electrodes. In this embodiment, the solidified photoresist can be exposed and developed based on the preset electrode pattern, so that the photoresist distributed at both ends of the two-dimensional ferroelectric material and the two-dimensional semiconductor material undergoes a chemical reaction, and then a preset electrode area that can be electroplated can be formed on the surface of the heterostructure.
[0087] Step S53, electroplating the preset electrode area with a preset metal material;
[0088] It is easy to understand that, in this embodiment, the preset metal material can be plated on the preset electrode area through an electron beam evaporation process, thereby forming a corresponding metal electrode.
[0089] As a preferred example, the preset metal material may include titanium and gold. A layer of titanium is first plated to improve the adhesion between the structures, and then a layer of gold is plated to improve the conductivity.
[0090] Step S54, cleaning the heterostructure after the electroplating process with a preset solvent to obtain the lateral gate ferroelectric field effect transistor.
[0091] It should be noted that the preset solvent is an organic solvent that can dissolve organic matter such as photoresist, and can be an acetone solution. In this embodiment, after electroplating, the heterostructure can be cleaned by the preset solvent to remove impurities such as photoresist on the heterostructure, and the field effect transistor finally obtained is the required lateral gate ferroelectric field effect transistor.
[0092] Further, in this embodiment, the lateral gate ferroelectric field effect transistor includes a gate, a drain, a source and a ground electrode, and after the step of sequentially performing photolithography, electroplating and solvent cleaning on the heterostructure to obtain the corresponding lateral gate ferroelectric field effect transistor, the step further includes:
[0093] Step S61, setting a first preset electric field between the gate and the ground electrode, and setting a second preset electric field between the source and the drain, and collecting a test current between the source and the drain;
[0094] Step S62, determining an electrical property test result of the lateral gate iron field effect transistor based on the test current, the first preset electric field and the second preset electric field;
[0095] Step S63: judging whether the lateral gate iron field effect transistor is a good product based on the electrical test result.
[0096] It should be noted that, in this embodiment, after the lateral gate iron field effect transistor is prepared, an electrical property test may be performed on it to determine whether the prepared finished product is a good product.
[0097] It is easy to understand that it can be combined with Figure 1 It is understood that in this embodiment, a first preset electric field with a voltage of Vg (the specific voltage is not limited) can be applied from the outside between the gate and the ground electrode of the finished product (connecting the ground electrode in the grounding area to the ground wire), and a second preset electric field with a voltage of Vds (the specific voltage is not limited) can be applied from the outside between the source and the drain (connecting the source in the source area to the ground wire), and the value of the test current generated between the source and the drain is collected. Since the ferroelectric material inside it has a ferroelectric effect, the carrier concentration in the channel formed by the semiconductor material can be controlled, so there is a certain correspondence between the value of the test current and the size of the first preset electric field and the size of the second preset electric field. During the test, the corresponding change curves between the three can be used as electrical test results. By comparing the electrical test results with the ideal change curve, the difference between the two can be used to determine whether the currently prepared lateral gate ferroelectric field effect transistor is a good product.
[0098] The above are only preferred embodiments of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent processing scope of the present application.
Claims
1. A field effect transistor, characterized in that: The field effect transistor comprises: A substrate, wherein one side of the substrate is provided with a gate region, a ground region, a source region and a drain region which are not in contact with each other; A ferroelectric layer is disposed on the substrate along a first direction, and two ends of the ferroelectric layer are respectively connected to the gate region and the ground region; A semiconductor layer is disposed on the substrate along the second direction, and two ends of the semiconductor layer are respectively connected to the source region and the drain region; The first direction is perpendicular to the second direction, a projection of the ferroelectric layer and a projection of the semiconductor layer intersect in a preset area, and the ferroelectric layer and the semiconductor layer in the preset area are in contact with each other.
2. The field effect transistor according to claim 1, characterized in that The ferroelectric layer includes a two-dimensional ferroelectric crystal.
3. The field effect transistor according to claim 1, characterized in that The semiconductor layer includes a two-dimensional semiconductor crystal.
4. The field effect transistor according to claim 1, characterized in that The substrate includes a silicon dioxide substrate.
5. The field effect transistor according to claim 1, wherein: The gate region, the ground region, the source region and the drain region are respectively provided with a metal electrode, and the electrode materials of the metal electrode include titanium and gold, and the gold covers the outer surface of the titanium.
6. The field effect transistor according to any one of claims 1 to 5, characterized in that The ferroelectric layer is located above the semiconductor layer.
7. A method for preparing a field effect transistor, characterized in that: The steps of the field effect transistor preparation method include: Selecting a preset substrate, a ferroelectric material, and a semiconductor material respectively; Placing the ferroelectric material on a preset tape and performing image processing to obtain a two-dimensional ferroelectric material; Transferring the semiconductor material to the preset substrate and performing imaging processing to obtain a two-dimensional semiconductor material; Transferring the two-dimensional ferroelectric material to above the plane where the two-dimensional semiconductor material is located to form a heterostructure, wherein the two-dimensional ferroelectric material and the two-dimensional semiconductor material are arranged perpendicular to each other and two ends of the two-dimensional ferroelectric material do not contact two ends of the two-dimensional semiconductor material; The heterostructure is subjected to photolithography, electroplating and solvent cleaning in sequence to obtain a corresponding lateral gate ferroelectric field effect transistor.
8. The method for preparing a field effect transistor according to claim 7, characterized in that: The step of transferring the two-dimensional ferroelectric material to above the plane where the two-dimensional semiconductor material is located to form a heterostructure comprises: Extracting the two-dimensional ferroelectric material on the preset tape through the PDMS film; By using a transfer table and an optical microscope, the PDMS film is moved to the top of the two-dimensional semiconductor material, and the PDMS film is attached to the top of the two-dimensional semiconductor material at an angle perpendicular to the two-dimensional semiconductor, and the two ends of the two-dimensional ferroelectric material are kept not in contact with the two ends of the two-dimensional semiconductor material; The PDMS film is removed to form the heterostructure.
9. The method for preparing a field effect transistor according to claim 7, wherein: The step of sequentially performing photolithography, electroplating and solvent cleaning on the heterostructure to obtain a corresponding lateral gate iron field effect transistor comprises: Coating a photoresist on the surface of the heterostructure; Based on a preset electrode pattern, exposing and developing the photoresist to obtain a preset electrode area on the surface of the heterostructure; Electroplating the preset electrode area with a preset metal material; The heterostructure after the electroplating treatment is cleaned by a preset solvent to obtain the lateral gate ferroelectric field effect transistor.
10. The method for preparing a field effect transistor according to claim 7, characterized in that: The lateral gate ferroelectric field effect transistor comprises a gate, a drain, a source and a ground electrode. After the steps of sequentially performing photolithography, electroplating and solvent cleaning on the heterostructure to obtain the corresponding lateral gate ferroelectric field effect transistor, the method further comprises: A first preset electric field is set between the gate and the ground electrode, and a second preset electric field is set between the source and the drain, and a test current between the source and the drain is collected; Determining an electrical property test result of the lateral gate iron field effect transistor based on the test current, the first preset electric field, and the second preset electric field; Based on the electrical test result, it is determined whether the lateral gate iron field effect transistor is a good product.