Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and the method comprises the steps: providing a substrate, and forming a gate structure, a side wall and an active / drain region on the substrate; forming a protective layer which covers the substrate and at least covers part of the side wall, close to the substrate, of the side wall; removing a part of the side wall which is not covered by the protective layer; removing the protective layer; forming metal silicide on the gate structure and / or the source / drain region; and forming a dielectric layer covering the gate structure, the side wall, the source / drain region and the substrate, and forming a contact hole exposing the metal silicide in the dielectric layer. The stress proximity technology is arranged before the metal silicide is formed, and when part of the side wall is removed, the protection layer is adopted to protect the substrate and part of the side wall close to the substrate, so that the loss of the substrate can be avoided on the basis of improving the filling window and improving the stress, and the reliability of the device is improved. Therefore, the loss of the metal silicide caused by the removal of the side wall is avoided, the etching through phenomenon of the metal silicide is avoided, and finally the performance of the semiconductor device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, in order to achieve higher computing speed, larger data storage capacity and more functions, semiconductor devices are developing towards higher component density and higher integration. Therefore, the gate of complementary metal oxide semiconductor (CMOS) transistors has become thinner and shorter than before. However, the size change of the gate will affect the electrical performance of semiconductor devices. At present, the electrical performance of semiconductor devices is mainly improved by controlling the carrier mobility. A key element of this technology is to control the stress in the transistor channel. For example, by properly controlling the stress, the mobility of carriers (electrons in n-channel transistors and holes in p-channel transistors) is increased, thereby increasing the drive current.

[0003] Among various technologies that enhance carrier mobility by introducing stress, stress proximity technology (SPT) is a sidewall thinning process after the completion of self-aligned silicide and before the formation of the contact etch stop layer (CESL). SPT expands the filling space of the subsequently formed CESL and dielectric layer (ILD), increases the process window of ILD, and increases the proximity of CESL to polysilicon (poly), which is conducive to the transfer of stress from CESL to the channel, thereby improving the mobility of NMOS devices.

[0004] Stress Memorization Technique (SMT) is to deposit a stress layer on the semiconductor device, and then perform a high-temperature annealing process to memorize the stress on the semiconductor device. The stress layer is then removed, but the stress memorized in the semiconductor device will still be conducted into the channel, thereby improving the mobility of the NMOS device.

[0005] At present, generally after completing the self-aligned metal silicide barrier (SAB) process, a metal layer is deposited on the surface of the wafer, and then annealed to form metal silicide (Salicide). Then the sidewall is thinned by etching process to increase the subsequent filling window and increase stress. Then the stress layer is deposited to complete the stress memory technology.

[0006] However, the loss of metal silicide needs to be strictly controlled when etching the sidewalls. If the loss of metal silicide is too much, the subsequent contact hole etching window will be too small, and the metal silicide may be etched through, resulting in excessive resistance, which will ultimately affect the performance of the semiconductor device. Summary of the invention

[0007] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can reduce the loss of metal silicide on the basis of improving the filling window and raising the stress.

[0008] To solve the above technical problems, according to a first aspect of the present invention, a method for manufacturing a semiconductor device is provided, comprising the following steps:

[0009] Providing a substrate, wherein a gate structure is formed on the substrate, sidewalls of the gate structure are formed with sidewalls, and source / drain regions are formed in the substrate on both sides of the gate structure;

[0010] forming a protective layer, wherein the protective layer covers the substrate and at least covers a portion of the sidewall of the spacer close to the substrate;

[0011] removing the portion of the side wall not covered by the protective layer;

[0012] removing the protective layer;

[0013] forming a metal silicide, wherein the metal silicide is located on the gate structure and / or the source / drain region; and

[0014] A dielectric layer is formed, the dielectric layer covers the gate structure, the sidewalls, the source / drain regions and the substrate, and contact holes are formed in the dielectric layer to expose the source / drain regions and / or the metal silicide on the gate structure.

[0015] Optionally, the method of forming a protective layer, wherein the protective layer covers the substrate and at least covers a portion of the sidewall of the sidewall close to the substrate, includes:

[0016] forming a protective material layer, wherein the protective material layer covers the gate structure, the sidewalls and the substrate;

[0017] A portion of the thickness of the protective material layer is removed, and the remaining protective material layer serves as the protective layer.

[0018] Optionally, the protective material layer is a photoresist layer, an anti-reflective coating or a water-soluble organic carbon layer.

[0019] Optionally, isotropic etching is used to remove the portion of the sidewalls not covered by the protective layer, and the etching amount of the sidewalls in a direction parallel to the substrate is consistent with the etching amount in a direction perpendicular to the substrate.

[0020] Optionally, after removing the protective layer and before forming the metal silicide, the manufacturing method further includes:

[0021] forming a stress layer, wherein the stress layer covers the gate structure, the sidewalls and the substrate;

[0022] performing a high temperature annealing process; and

[0023] The stress layer is removed.

[0024] Optionally, after removing the stress layer and before forming the metal silicide, the manufacturing method further includes:

[0025] Forming a self-aligned metal silicide barrier layer, wherein the self-aligned metal silicide barrier layer covers the gate structure, the sidewall and the substrate;

[0026] A portion of the self-aligned metal silicide barrier layer is removed to expose a region where metal silicide needs to be formed.

[0027] Optionally, the method of removing part of the self-aligned metal silicide barrier layer to expose the area where the metal silicide needs to be formed includes:

[0028] Forming a patterned photoresist layer, wherein the patterned photoresist layer covers the area where metal silicide does not need to be formed and exposes the area where metal silicide needs to be formed;

[0029] Using the patterned photoresist layer as a mask, etching and removing the self-aligned metal silicide blocking layer in the area where metal silicide is to be formed; and

[0030] The patterned photoresist layer is removed.

[0031] Optionally, the method of forming the metal silicide includes:

[0032] forming a metal layer, wherein the metal layer covers the gate structure, the sidewalls, the source / drain regions and the substrate;

[0033] performing a high temperature annealing process; and

[0034] The metal layer is removed.

[0035] Optionally, in the step of providing a substrate, a height difference between the sidewall and the gate structure is greater than or equal to 2 nm and less than or equal to 4 nm.

[0036] In order to solve the above technical problem, according to a second aspect of the present invention, a semiconductor device is provided, which is manufactured by the semiconductor device manufacturing method as described above.

[0037] In summary, in the semiconductor device and its manufacturing method provided by the present invention, a protective layer covering the substrate and at least covering the part of the sidewall of the sidewall close to the substrate is first formed, and then the part of the sidewall not covered by the protective layer is removed, and then the protective layer is removed, and then the metal silicide is formed. In the present invention, the stress proximity technology is set before the formation of the metal silicide, and when removing part of the sidewall, the protective layer is used to protect the substrate and the part of the sidewall of the sidewall close to the substrate. On the basis of improving the filling window and increasing the stress, it is possible to avoid the loss of the substrate when removing part of the sidewall, thereby avoiding the loss of the metal silicide caused by the removal of the sidewall, avoiding the occurrence of the metal silicide etching phenomenon, and finally improving the performance of the semiconductor device. At the same time, when removing part of the sidewall, the part of the sidewall of the sidewall close to the substrate is protected by the protective layer, and while the height of the sidewall is reduced and the sidewall is thinned, the bottom size of the sidewall can be ensured to remain unchanged, thereby ensuring that the width of the subsequently formed metal silicide does not change. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0039] Figures 1 to 5 It is a schematic structural diagram of each step of a method for manufacturing a semiconductor device.

[0040] Figure 6 It is a flow chart of a method for manufacturing a semiconductor device provided by one embodiment of the present invention.

[0041] Figures 7 to 18 It is a schematic structural diagram of each step of a method for manufacturing a semiconductor device provided by an embodiment of the present invention.

[0042] Description of reference numerals:

[0043] Figures 1 to 5 In the figure: 10 - substrate; 11 - isolation structure; 12 - gate structure; 13 - sidewall; 131 - first sidewall; 132 - second sidewall; 14 - metal layer; 15 - metal silicide; 16 - dielectric layer; 17 - contact hole.

[0044] Figures 7 to 18 In the figure: 100-substrate; 110-isolation structure; 120-gate structure; 130-side wall; 131-first side wall; 132-second side wall; 140-protective material layer; 150-protective layer; 160-stress layer; 170-self-aligned metal silicide barrier layer; 180-patterned photoresist layer; 190-metal layer; 200-metal silicide; 210-dielectric layer; 220-contact hole. DETAILED DESCRIPTION

[0045] Figures 1 to 5 This is a schematic diagram of the steps of a method for manufacturing a semiconductor device. Figure 1 As shown, a plurality of gate structures 12 are formed on a substrate 10, and sidewalls of the gate structures 12 are formed with sidewall spacers 13, wherein the sidewall spacers 13 include a first sidewall spacer 131 and a second sidewall spacer 132. Source / drain regions (not shown) are formed in the substrate 10 on both sides of the gate structures 12, and adjacent gate structures 12 are isolated from each other by isolation structures 11.

[0046] Please refer to Figure 2 As shown, a metal layer 14 is formed, and the metal layer 14 covers the gate structure 12, the sidewall 13 and the substrate 10. The metal layer 14 is, for example, a nickel-platinum layer. Then, the metal layer 14 is annealed so that the metal in the metal layer 14 reacts with the silicon in the gate 13 and the substrate 10 to form a metal silicide 15, and then the remaining unreacted metal layer 14 is removed to form a structure as shown in FIG. Figure 3 A metal silicide 15 is formed on the top of the gate 13 and the surface of the substrate 10 (ie, the source / drain region).

[0047] Please refer to Figure 4 As shown, the sidewall spacer 13 is thinned by etching to increase the subsequent filling window and increase the stress. However, in the process of etching the sidewall spacer 13, the metal silicide 15 will be damaged.

[0048] Please refer to Figure 5 As shown, a dielectric layer 16 is formed, and the dielectric layer 16 covers the metal silicide 15, the sidewall 13 and the substrate 10. Then, a contact hole 17 is formed in the dielectric layer 16 to expose the metal silicide 15 on the substrate 10. Since a portion of the metal silicide 15 is lost during the etching of the sidewall 13 in the previous step, the etching window for forming the contact hole 17 in this step is too small, that is, the etching amount when forming the contact hole 17 needs to be strictly controlled to prevent the metal silicide 15 from being lost again. Excessive etching will cause the metal silicide 15 to be etched through, such as Figure 5 As shown, this will result in excessive resistance, ultimately affecting the performance of the semiconductor device.

[0049] In view of the above problems, the present invention provides a semiconductor device and a method for manufacturing the same, which can reduce the loss of metal silicide on the basis of improving the filling window and raising the stress, thereby improving the device performance.

[0050] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0051] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, unless the content clearly indicates otherwise. As used in the present invention, the term "or" is generally used in a sense that includes "and / or", unless the content clearly indicates otherwise. As used in the present invention, the term "several" is generally used in a sense that includes "at least one", unless the content clearly indicates otherwise. As used in the present invention, the term "at least two" is generally used in a sense that includes "two or more", unless the content clearly indicates otherwise. In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features.

[0052] Figure 6 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 6 As shown, the method for manufacturing a semiconductor device provided in this embodiment includes the following steps:

[0053] Step S1: providing a substrate, wherein a gate structure is formed on the substrate, sidewalls of the gate structure are formed with sidewalls, and source / drain regions are formed in the substrate on both sides of the gate structure;

[0054] Step S2: forming a protective layer, wherein the protective layer covers the substrate and at least covers a portion of the sidewall of the sidewall close to the substrate;

[0055] Step S3: removing the portion of the side wall not covered by the protective layer;

[0056] Step S4: removing the protective layer;

[0057] Step S5: forming a metal silicide, wherein the metal silicide is located on the gate structure and / or the source / drain region; and

[0058] Step S6: forming a dielectric layer, the dielectric layer covering the gate structure, the sidewalls, the source / drain regions and the substrate, and forming contact holes in the dielectric layer to expose the source / drain regions and / or the metal silicide on the gate structure.

[0059] Figures 7 to 18 FIG. 1 is a schematic diagram of the structure of each step of a method for manufacturing a semiconductor device provided by an embodiment of the present invention. Figure 6 and Figures 7 to 18 The method for manufacturing a semiconductor device provided by an embodiment of the present invention is described in detail.

[0060] In step S1, refer to Figure 7 As shown, a substrate 100 is provided, a gate structure 120 is formed on the substrate 100 , a sidewall of the gate structure 120 is formed with a spacer 130 , and source / drain regions (not shown) are formed in the substrate 100 on both sides of the gate structure 120 .

[0061] In this embodiment, the material of the substrate 100 can be single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium compound or silicon on insulator (SOI), etc., and an isolation structure 110 is formed in the substrate 100, and the isolation structure 110 is, for example, a shallow trench isolation structure. The gate structure 120 includes a gate dielectric layer and a gate electrode, the material of the gate dielectric layer is silicon oxide, and the material of the gate electrode is polycrystalline silicon. Source / drain regions (not shown) are formed in the substrate 100, and the source / drain regions are located in the substrate 100 on both sides of the gate structure 120.

[0062] A sidewall 130 is formed on the sidewall of the gate structure 120, and the sidewall 130 may include a first sidewall 131 and a second sidewall 132. The first sidewall 131 is located on the sidewall of the gate structure 120 and on a portion of the substrate 100 close to the gate structure 120, and the second sidewall 132 is located on the first sidewall 131. The material of the first sidewall 131 may be silicon oxide, and the material of the second sidewall 132 may be silicon nitride.

[0063] In one embodiment of the present invention, the substrate 100 includes a region I where metal silicide needs to be formed and a region II where metal silicide does not need to be formed. The region I where metal silicide needs to be formed refers to the gate structure 120 and the source / drain region formed thereon where metal silicide needs to be formed, and the region II where metal silicide does not need to be formed refers to all regions thereon where metal silicide does not need to be formed. It can be understood that in another embodiment of the present invention, all regions of the substrate 100 can be the region I where metal silicide needs to be formed.

[0064] The sidewall 130 has a height difference with the gate structure 120. Under standard conditions (baseline, BSL), the top surface of the sidewall 130 is lower than the top surface of the gate structure 120, and the height difference is greater than 10nm. In this embodiment, when etching to form the sidewall 130, the height of the sidewall 130 can be increased by adjusting the over-etching (OE) time, bias RF power (Bias RF) or chamber pressure (Pressure) and other methods, that is, the height difference between the sidewall 130 and the gate structure 120 is reduced. For example, the height of the sidewall 130 is increased by 6nm to 8nm, so that the height difference between the sidewall 130 and the gate structure 120 is greater than or equal to 2nm and less than or equal to 4nm, that is, the height of the sidewall 130 is lower than the height of the gate structure 120, and the height difference is greater than or equal to 2nm and less than or equal to 4nm. If the height difference between the side wall 130 and the gate structure 120 is large, the side wall of the gate structure 120 is exposed more, and the subsequent formation of metal silicide will cause the thickness of the metal silicide on the gate structure 120 to be thicker. The thickness of the metal silicide needs to be controlled within a certain range. Therefore, compared with standard conditions, the height of the side wall 130 needs to be slightly increased to reduce the height difference between the side wall 130 and the gate structure 120.

[0065] In step S2, please refer to Fig. 9 As shown, a protection layer 150 is formed, and the protection layer 150 covers the substrate 100 and at least covers a portion of the sidewall of the spacer 130 close to the substrate 100 .

[0066] For example, please refer to Figure 8 As shown, a protective material layer 140 is formed, and the protective material layer 140 covers the gate structure 120, the sidewall 130, the source / drain region and the substrate 100. The protective material layer 140 fills the grooves between the adjacent gate structures 120 and forms a relatively flat surface, that is, the top surface of the protective material layer 140 is higher than the top surface of the gate structure 120. The protective material layer 140 can be a photoresist layer, an anti-reflective coating (BARC) or a water-soluble organic carbon layer (SOC), but is not limited thereto. In this embodiment, the protective material layer 140 is a photoresist layer.

[0067] Then, please refer to Figure 8 and Fig. 9 As shown, a portion of the protective material layer 140 is removed, and the remaining protective material layer 140 is used as the protective layer 150. In this embodiment, the protective material layer 140 can be etched with a high selectivity gas such as oxygen (O2) or sulfur dioxide (SO2), and the thickness of the formed protective layer 150 can be 10nm to 20nm, but is not limited thereto.

[0068] In step S3, please refer to Fig.10 As shown, the portion of the sidewall 130 not covered by the protection layer 150 is removed.

[0069] In this embodiment, isotropic etching is used to remove the portion of the sidewall 130 that is not covered by the protective layer 150, and the etching amount b of the sidewall 130 in the direction parallel to the substrate 100 (i.e., the horizontal direction) is consistent with the etching amount a in the direction perpendicular to the substrate 100 (i.e., the vertical direction). For example, a gas specially used for etching silicon nitride, such as fluoromethane (CH3F), isotropically etching is used to remove a portion of the sidewall 130, and the etching amount of the sidewall 130 in the horizontal and vertical directions can be 4nm to 6nm. After the etching is completed, the height of the sidewall 130 meets the standard conditions, that is, the height difference between the sidewall 130 and the gate structure 120 meets the requirements.

[0070] In the embodiment of the present invention, the sidewall 130 is etched to remove part of the sidewall 130, that is, the sidewall 130 is thinned, thereby improving the subsequent filling window and increasing the stress. When the sidewall 130 is removed, the protective layer 150 is used to protect the substrate 100, thereby avoiding damage to the substrate 100 when removing part of the sidewall 130, thereby avoiding damage to the metal silicide formed subsequently due to the removal of the sidewall 130, thereby avoiding the occurrence of metal silicide etching through, and ultimately improving the performance of the semiconductor device.

[0071] At the same time, when part of the side wall 130 is removed, part of the side wall of the side wall 130 close to the substrate 100 is protected by the protective layer 150, and while the height of the side wall 130 is reduced and the side wall is thinned, the bottom size of the side wall 130 can be kept unchanged, so that the size of the side wall 130 finally formed meets the requirements and the width of the subsequently formed metal silicide is ensured not to change.

[0072] In step S4, please refer to Fig.10 and Fig.11 As shown, the protection layer 150 is removed.

[0073] In this embodiment, a high selectivity gas such as oxygen (O 2 ) / sulfur dioxide (SO 2 ) may be used to remove the protective layer 150 .

[0074] Next, please refer to Fig.12 and Fig.13 As shown, after removing the protection layer 150 , a stress memory technology may be further performed.

[0075] For example, please refer to Fig.12As shown, a stress layer 160 is formed, and the stress layer 160 covers the gate structure 120, the sidewall 130, the source / drain region and the substrate 100. In this embodiment, the stress layer 160 includes a stack of a silicon oxide layer and a silicon nitride layer, the silicon oxide layer conformally covers the gate structure 120, the sidewall 130, the source / drain region and the substrate 100, and the silicon nitride layer conformally covers the silicon oxide layer, but is not limited thereto.

[0076] Then, a high temperature annealing process is performed, and the high temperature annealing process can be a rapid thermal annealing (RTA) or a laser pulse annealing (LSA) process. During the annealing process, stress will be generated, and these stresses will be memorized. In the next process, the stress layer 160 will be removed, but the stress memorized in the gate structure 120 will still be conducted to the channel, which is beneficial to improving the carrier mobility.

[0077] Finally, please refer to Fig.12 and Fig.13 As shown, the stress layer 160 is removed.

[0078] Please refer to Fig.14 As shown, in the embodiment of the present invention, after removing the stress layer 160, the manufacturing method further includes: forming a self-aligned metal silicide barrier layer 170, the self-aligned metal silicide barrier layer 170 conformally covers the gate structure 120, the sidewall 130, the source / drain region and the substrate 100. The self-aligned metal silicide barrier layer 170 includes a stack of silicon oxide layers and silicon nitride layers. Then, a photoresist layer (not shown) is formed, the photoresist layer covers the self-aligned metal silicide barrier layer 170, and then the photoresist layer is exposed and developed to form a patterned photoresist layer 180. The patterned photoresist layer 180 covers the region II where metal silicide does not need to be formed, and exposes the region I where metal silicide needs to be formed. Then, using the patterned photoresist layer 180 as a mask, the exposed self-aligned metal silicide barrier layer 170 is removed, that is, the self-aligned metal silicide barrier layer 170 in the region I where metal silicide needs to be formed is removed. Finally, the patterned photoresist layer 180 is removed to form a Fig.15 The structure shown.

[0079] It should be noted that Fig.15 The subsequent schematic diagrams all show the region I where metal silicide needs to be formed, but do not show the region II where metal silicide does not need to be formed. Figures 15 to 18 Displayed Fig.14 Region I where metal silicide needs to be formed.

[0080] In step S5, please refer to Fig.17As shown, a metal silicide 200 is formed, and the metal silicide 200 is located on the gate structure 120 and / or the source / drain region.

[0081] For example, first, please refer to Fig.16 As shown, a metal layer 190 is formed, and the metal layer 190 conformally covers the gate structure 120, the sidewall 130, the source / drain region and the substrate 100. The material of the metal layer 190 may include nickel, platinum, cobalt, titanium or alloys thereof, and may be formed by physical vapor deposition or evaporation.

[0082] Then, please refer to Fig.16 and Fig.17 As shown, a high temperature annealing process is performed so that the metal in the metal layer 190 reacts with the gate structure 120 and the silicon in the source / drain region to form a metal silicide 200. In this process, the silicon oxide or silicon nitride on the sidewall 130 or the surface of the substrate 100 does not react with the metal layer 190, so that the remaining unreacted metal layer 190 can be removed by selective etching later.

[0083] Next, please refer to Fig.17 As shown, the unreacted metal layer 190 is removed. Exemplarily, the metal layer 190 on the surface of the substrate 100 that has not reacted with silicon is removed by selective wet etching. Then, the substrate 100 may be annealed again to convert the high-resistivity metal silicide formed by the last annealing into a low-resistivity metal silicide.

[0084] In this embodiment, the metal silicide 200 is formed on both the gate structure 120 and the source / drain regions.

[0085] In step S6, please refer to Fig.18 As shown, a dielectric layer 210 is formed, the dielectric layer 210 covers the gate structure 120, the sidewalls 130, the source / drain regions and the substrate 100, and a contact hole 220 is formed in the dielectric layer 210 to expose the source / drain regions and / or the metal silicide 200 on the gate structure 120.

[0086] Exemplarily, before forming the dielectric layer 210, a contact hole etch stop layer (not shown) can be formed first, and the contact hole etch stop layer conformally covers the gate structure 120, the side wall 130, the source / drain region and the substrate 100, that is, the contact hole etch stop layer conformally covers the substrate 100 and the various structures formed on the substrate 100.

[0087] Then, the dielectric layer 210 is formed, and the dielectric layer 210 covers the gate structure 120, the sidewall 130, the source / drain region and the substrate 100. In this embodiment, the dielectric layer 210 covers the contact hole etching stop layer. The material of the dielectric layer 210 can be silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant dielectric material, or any other suitable dielectric material, or a combination thereof, but is not limited thereto. The dielectric layer 210 can be formed by thermal oxidation, low pressure chemical vapor deposition, low temperature chemical vapor deposition, rapid temperature chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition and other process methods.

[0088] Then, a contact hole 220 is formed in the dielectric layer 210 to expose the metal silicide 200 on the source / drain region and / or the gate structure 120. Exemplarily, a photoresist layer is formed on the dielectric layer 210, and the photoresist layer is exposed and developed to form a patterned photoresist layer. Then, using the patterned photoresist layer as a mask, the dielectric layer 210 and the contact hole etching stop layer are etched until the metal silicide 200 on the source / drain region is exposed, and a plurality of contact holes 220 are formed in the dielectric layer 210. Finally, the patterned photoresist layer is removed to form a structure as shown in FIG. Fig.18 In this embodiment, only the contact hole 220 on the source / drain region is shown.

[0089] In this embodiment, since the part of the sidewall 130 not covered by the protective layer 150 has been removed in step S3, that is, the sidewall 130 has been thinned, the filling window when forming the contact hole etching stop layer and the dielectric layer 210 is improved and the stress is increased. At the same time, the stress proximity technology is set before the formation of the metal silicide 200, and when removing part of the sidewall 130, the protective layer 150 is used to protect the substrate 100 and the part of the sidewall of the sidewall 130 close to the substrate 100. Therefore, on the basis of improving the filling window and increasing the stress, it is possible to avoid the loss of the substrate 100 when removing part of the sidewall 130, thereby avoiding the loss of the metal silicide 200 caused by the removal of the sidewall 130, avoiding the occurrence of the metal silicide 200 etching through phenomenon, and finally improving the performance of the semiconductor device.

[0090] At the same time, when part of the side wall 130 is removed, part of the side wall of the side wall 130 close to the substrate 100 is protected by the protective layer 150. While the height of the side wall 130 is reduced and the side wall is thinned, the bottom size of the side wall 130 can be kept unchanged, thereby ensuring that the width of the subsequently formed metal silicide 200 will not change.

[0091] Correspondingly, the present invention also provides a semiconductor device manufactured by the method for manufacturing the semiconductor device as described above.

[0092] In summary, in the semiconductor device and its manufacturing method provided by the present invention, a protective layer covering the substrate and at least covering the part of the sidewall of the sidewall close to the substrate is first formed, and then the part of the sidewall not covered by the protective layer is removed, and then the protective layer is removed, and then the metal silicide is formed. In the present invention, the stress proximity technology is set before the formation of the metal silicide, and when removing part of the sidewall, the protective layer is used to protect the substrate and the part of the sidewall of the sidewall close to the substrate. On the basis of improving the filling window and increasing the stress, it is possible to avoid the loss of the substrate when removing part of the sidewall, thereby avoiding the loss of the metal silicide caused by the removal of the sidewall, avoiding the occurrence of the metal silicide etching phenomenon, and finally improving the performance of the semiconductor device. At the same time, when removing part of the sidewall, the part of the sidewall of the sidewall close to the substrate is protected by the protective layer, and while the height of the sidewall is reduced and the sidewall is thinned, the bottom size of the sidewall can be ensured to remain unchanged, thereby ensuring that the width of the subsequently formed metal silicide does not change.

[0093] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: Providing a substrate, wherein a gate structure is formed on the substrate, sidewalls of the gate structure are formed with sidewalls, and source / drain regions are formed in the substrate on both sides of the gate structure; forming a protective layer, wherein the protective layer covers the substrate and at least covers a portion of the sidewall of the spacer close to the substrate; removing the portion of the side wall not covered by the protective layer; removing the protective layer; forming a metal silicide, wherein the metal silicide is located on the gate structure and / or the source / drain region; as well as A dielectric layer is formed, the dielectric layer covers the gate structure, the sidewalls, the source / drain regions and the substrate, and contact holes are formed in the dielectric layer to expose the source / drain regions and / or the metal silicide on the gate structure.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The method of forming a protective layer, wherein the protective layer covers the substrate and at least covers a portion of the sidewall of the spacer close to the substrate, comprises: forming a protective material layer, wherein the protective material layer covers the gate structure, the sidewalls and the substrate; A portion of the thickness of the protective material layer is removed, and the remaining protective material layer serves as the protective layer.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The protective material layer is a photoresist layer, an anti-reflective coating or a water-soluble organic carbon layer.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The portion of the sidewall not covered by the protective layer is removed by isotropic etching, and the etching amount of the sidewall in a direction parallel to the substrate is consistent with the etching amount in a direction perpendicular to the substrate.

5. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, characterized in that: After removing the protective layer and before forming the metal silicide, the manufacturing method further includes: forming a stress layer, wherein the stress layer covers the gate structure, the sidewalls, the source / drain regions and the substrate; performing a high temperature annealing process; and The stress layer is removed.

6. The method for manufacturing a semiconductor device according to claim 5, characterized in that: After removing the stress layer and before forming the metal silicide, the manufacturing method further includes: Forming a self-aligned metal silicide barrier layer, wherein the self-aligned metal silicide barrier layer covers the gate structure, the sidewalls, the source / drain regions and the substrate; A portion of the self-aligned metal silicide barrier layer is removed to expose a region where metal silicide needs to be formed.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The method of removing part of the self-aligned metal silicide barrier layer to expose the area where the metal silicide needs to be formed includes: forming a patterned photoresist layer, wherein the patterned photoresist layer covers the area where metal silicide does not need to be formed and exposes the area where metal silicide needs to be formed; Using the patterned photoresist layer as a mask, etching and removing the self-aligned metal silicide blocking layer in the area where metal silicide is to be formed; and The patterned photoresist layer is removed.

8. The method for manufacturing a semiconductor device according to claim 7, characterized in that: The method of forming metal silicide includes: forming a metal layer, wherein the metal layer covers the gate structure, the sidewalls, the source / drain regions and the substrate; performing a high temperature annealing process; and The metal layer is removed.

9. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, characterized in that: In the step of providing a substrate, a height difference between the sidewall and the gate structure is greater than or equal to 2 nm and less than or equal to 4 nm.

10. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 9.

Images