Semiconductor element and manufacturing method thereof

Abstract

The invention discloses a semiconductor element and a manufacturing method thereof, and the method for manufacturing the semiconductor element mainly comprises the steps: providing a substrate comprising a core region and an input / output (I / O) region, then forming a first metal gate in the core region and a second metal gate in the I / O region, the first metal gate comprises a first gate dielectric layer, and the second metal gate comprises a second gate dielectric layer. The second metal gate includes a second gate dielectric layer, and the first gate dielectric layer and the second gate dielectric layer have different shapes, for example, the first gate dielectric layer includes an I shape and the second gate dielectric layer includes a U shape.

Description

Technical Field

[0001] The present invention relates to a method for forming a semiconductor element, and more particularly to a method for forming gate dielectric layers of different shapes in different regions. Background Art

[0002] In the existing semiconductor industry, polysilicon is widely used in semiconductor devices such as metal-oxide-semiconductor (MOS) transistors as a standard gate filling material. However, as the size of MOS transistors continues to shrink, the traditional polysilicon gate has problems such as the boron penetration effect, which leads to reduced device performance, and the unavoidable depletion effect, which increases the equivalent gate dielectric thickness and reduces the gate capacitance, leading to the decline of device driving ability. Therefore, the semiconductor industry has tried to use new gate filling materials, such as using work function metals to replace traditional polysilicon gates as control electrodes that match high-k gate dielectric layers.

[0003] However, in the current metal gate transistor manufacturing process, the electrical performance of the input / output (I / O) region and the core region is not ideal due to the influence of the preset gate dielectric layer thickness. For example, when hollowing out the polysilicon gate in the two regions, the epitaxial layer is often lost and voids are formed due to the wet cleaning process. Therefore, how to improve the current metal gate manufacturing process to solve this problem is an important issue today. Summary of the invention

[0004] An embodiment of the present invention discloses a method for manufacturing a semiconductor element, which mainly provides a substrate including a core area and an input / output (I / O) area, and then forms a first metal gate in the core area and a second metal gate in the I / O area, wherein the first metal gate includes a first gate dielectric layer, the second metal gate includes a second gate dielectric layer, and the first gate dielectric layer and the second gate dielectric layer include different shapes, for example, the first gate dielectric layer includes an I shape and the second gate dielectric layer includes a U shape.

[0005] Another embodiment of the present invention discloses a semiconductor element, which mainly includes a substrate having a core area and an input / output (I / O) area, a first metal gate arranged in the core area and a second metal gate arranged in the I / O area, wherein the first metal gate includes a first gate dielectric layer, the second metal gate includes a second gate dielectric layer, and the first gate dielectric layer and the second gate dielectric layer include different shapes. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figures 1 to 8 The figure is a schematic diagram of a method for manufacturing a semiconductor device according to a preferred embodiment of the present invention.

[0007] Explanation of symbols

[0008] 12: Base

[0009] 14: Core Area

[0010] 16:I / O area

[0011] 20: Fin structure

[0012] 22: Gate structure

[0013] 24: Gate dielectric layer

[0014] 26: Gate material layer

[0015] 28: Gap wall

[0016] 30: Source / Drain Region

[0017] 32: Epitaxial layer

[0018] 34: Contact hole etching stop layer

[0019] 36: Interlayer dielectric layer

[0020] 38: Groove

[0021] 40: Gate dielectric layer

[0022] 42: Vertical part

[0023] 44: Vertical part

[0024] 46: Horizontal

[0025] 48: Patterned Mask

[0026] 50: Gate dielectric layer

[0027] 52: High dielectric constant dielectric layer

[0028] 54: Work function metal layer

[0029] 56: Low impedance metal layer

[0030] 58:Metal Gate

[0031] 58: Hard mask

[0032] 62:Metal gate

[0033] 64: Contact plug

[0034] 66: Stop layer DETAILED DESCRIPTION

[0035] Please refer to Figures 1 to 8 , Figures 1 to 8 Schematic diagram of a method for manufacturing a semiconductor device according to a preferred embodiment of the present invention. Figure 1 As shown, a substrate 12 is first provided, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, and a core region 14 and an input / output (I / O) region 16 are defined on the substrate. In the present embodiment, the core region 14 and the I / O region 16 are preferably transistor regions of the same conductivity type, such as both are PMOS transistor regions or both are NMOS transistor regions. Each core region 14 and I / O region 16 of the substrate 12 has at least one fin structure 20, wherein the bottom of the fin structure 20 is coated with an insulating material such as silicon oxide to form a shallow trench isolation (not shown). It should be noted that although the present embodiment takes the manufacture of a non-planar field effect transistor such as a fin structure as an example, it is not limited to this. The present invention can also be applied to a general planar field effect transistor, and this embodiment also falls within the scope of the present invention.

[0036] According to one embodiment of the present invention, the fin structure 20 can be manufactured by sidewall image transfer (SIT) technology, and the procedure generally includes: providing a layout pattern to a computer system, and defining the corresponding pattern in a photomask through appropriate calculations. Subsequently, a plurality of equidistant and equal-width patterned sacrificial layers can be formed on the substrate through photolithography and etching processes, so that their individual appearances are strip-shaped. Thereafter, deposition and etching processes are sequentially performed to form spacers on each sidewall of the patterned sacrificial layer. Subsequently, the patterned sacrificial layer is removed, and an etching process is performed under the coverage of the spacers, so that the pattern formed by the spacers is transferred to the substrate, and then a fin structure cutting process (fin cut) is performed to obtain the desired patterned structure, such as a strip-shaped patterned fin structure.

[0037] In addition, the formation method of the fin structure 20 may include first forming a patterned mask (not shown) on the substrate 12, and then performing an etching process to transfer the pattern of the patterned mask to the substrate 12 to form the fin structure 20. In addition, the formation method of the fin structure 20 may also include first forming a patterned hard mask layer (not shown) on the substrate 12, and using an epitaxial process to grow a semiconductor layer such as silicon germanium on the substrate 12 exposed from the patterned hard mask layer, and this semiconductor layer can serve as the corresponding fin structure 20. These embodiments of forming the fin structure 20 are all within the scope of the present invention.

[0038] Then, a gate structure 22 or a dummy gate may be formed on the substrate 12 in the core region 14 and the I / O region 16, respectively. In the present embodiment, the gate structure 22 is preferably formed by sequentially forming a gate dielectric layer 24, a gate material layer 26, and a selective hard mask (not shown) on the substrate 12, and performing a pattern transfer process using a patterned photoresist (not shown) as a mask, removing a portion of the gate material layer 26 and a portion of the gate dielectric layer 24 by a single etching or successive etching steps, and then stripping the patterned photoresist to form at least one gate structure 22 consisting of a patterned gate dielectric layer 24 and a patterned gate material layer 26 on the fin structure 20 in the core region 14 and the I / O region 16, respectively. In the present embodiment, the gate dielectric layer 24 may include silicon oxide and the gate material layer 26 may include polysilicon, but is not limited thereto.

[0039] Then, at least one spacer 28 is formed on the sidewall of each gate structure 22, a source / drain region 30 and / or an epitaxial layer 32 are formed in the fin structure 20 and / or the substrate 12 on both sides of the spacer 28, and a metal silicide (not shown) is selectively formed on the surface of the source / drain region 30 and / or the epitaxial layer 32. In the present embodiment, the spacer 28 may be a single spacer or a composite spacer, for example, it may include a biased spacer (not shown) and a main spacer (not shown), and the spacer 28 may be selected from a group consisting of silicon oxide, silicon nitride, silicon oxynitride and silicon carbide, but is not limited thereto. The source / drain region 30 and the epitaxial layer 32 may include different dopants or different materials according to the conductivity type of the transistor to be prepared. For example, the source / drain region 30 may include P-type dopants or N-type dopants, and the epitaxial layer 32 may include silicon germanium, silicon carbide or silicon phosphide.

[0040] Then, a contact etch stop layer (CESL) 34 made of silicon nitride may be selectively formed on the substrate 12 and covers the gate structure 22, and an interlayer dielectric layer 36 is formed on the CESL 34. Then, a planarization process is performed, such as using chemical mechanical polishing (CMP) to remove a portion of the interlayer dielectric layer 36 and a portion of the contact etch stop layer 34 and expose the gate material layer 26 made of polysilicon material, so that the upper surface of the gate material layer 26 in the core region 14 and the I / O region 16 is flush with the upper surface of the contact etch stop layer 34 and the interlayer dielectric layer 36.

[0041] Then as Figure 2As shown, a metal gate replacement (RMG) process is performed to convert each gate structure 22 into a metal gate. For example, a selective dry etching or wet etching process may be performed first, such as using an etching solution such as ammonium hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH) to remove the gate material layer 26 and the gate dielectric layer 24 in the gate structure 22 in the core region 14 and the I / O region 16 to form a groove 38 in the interlayer dielectric layer 36. Since the gate dielectric layer 24 grown in the core region 14 and the I / O region 16 before the groove 38 is formed is composed of thinner silicon oxide, it is better to completely remove the gate dielectric layer 24 in the two regions and expose the surface of the substrate 12 after removing the gate material layer 26 composed of polysilicon by etching in this stage.

[0042] like Figure 3 As shown, an oxide growth process such as a rapid thermal oxidation (RTO) process or an in-situ steam generation (ISSG) process is then performed to form a gate dielectric layer 40 composed of silicon oxide in the recesses 38 of the core region 14 and the I / O region 16, respectively.

[0043] It should be noted that the oxide growth process performed in this stage preferably adjusts the oxygen flow rate and time to allow the oxygen to react with the inner sidewall of the spacer 28 and the surface of the fin structure 20 or the substrate 12 at the same time to form a gate dielectric layer 40 with a U-shaped cross-section, wherein the gate dielectric layer 40 formed in the core area 14 and the gate dielectric layer 40 formed in the I / O area 16 in this stage preferably have the same thickness, and the thickness of the gate dielectric layer 40 contacting the inner sidewall of the spacer 28 in each region is preferably slightly lower than the thickness of the gate dielectric layer 40 on the surface of the substrate 12 or the fin structure 20. From a detailed perspective, the gate dielectric layer 40 formed in the core area 14 and the I / O area 16 each includes two vertical portions 42, 44 and a horizontal portion 46 connecting the two vertical portions 42, 44, wherein the width or thickness of each vertical portion 42, 44 extending along the horizontal direction is smaller than the thickness of the horizontal portion 46 extending along the vertical direction. In the present embodiment, the oxygen flow rate during the oxide growth process is preferably between 20 and 24 standard liters per minute (slm) or more preferably about 22 slm, and the oxygen flow time is preferably between 20 and 25 seconds.

[0044] In addition, in this embodiment, regardless of whether the spacer 28 is a single-layer or multi-layer spacer, the spacer 28 that contacts the gate dielectric layer 40 on the innermost side preferably includes silicon carbide nitride (SiCN). Therefore, when the gate dielectric layer 40 is formed by the aforementioned oxide growth process, the introduced oxygen reacts with the inner sidewall of the spacer 28 composed of silicon carbide nitride to form vertical portions 42 and 44 of the gate dielectric layer 40 composed of silicon oxycarbonitride (SiOCN). At the same time, the oxygen reacts with the surface of the fin structure 20 or the substrate 12 composed of silicon to form a horizontal portion 46 of the gate dielectric layer 40 composed of silicon oxide. In other words, after the oxygen introduced during the oxide growth process reacts with the inner sidewalls of the spacer 28 and the surface of the fin structure 20 or the substrate 12 to form the gate dielectric layer 40, the two vertical portions 42, 44 and the horizontal portion 46 of the gate dielectric layer 40 preferably include different materials, wherein the two vertical portions 42, 44 are both composed of SiOCN and the horizontal portion 46 is composed of silicon oxide.

[0045] Then as Figure 4 As shown, a patterned mask 48 such as a patterned photoresist is formed on the I / O region 16 to expose the interlayer dielectric layer 36 of the core region 14 and the gate dielectric layer 40 in the groove 38 .

[0046] like Figure 5 As shown, an etching process is then performed using the patterned mask 48 as a mask to remove all gate dielectric layers 40 in the recess 38 of the core region 14 and expose the inner sidewalls of the spacer 28 and the fin structure 20 or the surface of the substrate 12. The patterned mask 48 is then removed.

[0047] like Figure 6 As shown, another oxide growth process such as RTO process or ISSG process can then be performed without forming an additional patterned mask to form another gate dielectric layer 50 on the fin structure 20 or substrate 12 in the core region 14. It should be noted that in this stage, it is preferred to adjust the oxygen flow rate and time of the oxide growth process to be slightly lower than Figure 3 The oxygen flow rate and time of the oxide growth process are controlled so that the oxygen introduced only reacts with the surface of the fin structure 20 or the substrate 12 in the core region 14 but does not react with the inner sidewall of the spacer 28 to form a gate dielectric layer. That is, the gate dielectric layer 50 formed in the core region 14 in this stage is only formed on the surface of the fin structure 20 or the substrate 12 but not formed on the inner sidewall of the spacer 28. Since the oxygen introduced in this stage only reacts with the surface of the fin structure 20 or the substrate 12 to form the gate dielectric layer 50, the formed gate dielectric layer 50 is preferably composed of silicon oxide.

[0048] From a structural point of view, after the oxide growth process is performed in this stage, a gate dielectric layer 50 and a gate dielectric layer 40 are respectively disposed on the core region 14 and the I / O region 16, wherein the gate dielectric layer 50 of the core region 14 and the gate dielectric layer 40 of the I / O region 16 preferably have different shapes. More specifically, the gate dielectric layer 50 of the core region 14 includes an I-shaped cross section extending along the horizontal direction, and the gate dielectric layer 40 of the I / O region 16 includes a U-shaped cross section, and the thickness of the gate dielectric layer 50 of the core region 14 is preferably greater than the thickness of the two vertical portions 42 and 44 of the gate dielectric layer 40 in the I / O region 16 but less than the thickness of the horizontal portion 46. In the present embodiment, the thickness of the gate dielectric layer 50 in the core region 14 is preferably between 6 and 8 angstroms or more preferably about 7 angstroms, the thickness of the vertical portion 42 or the vertical portion 44 of the gate dielectric layer 40 in the I / O region 16 is preferably between 4 and 6 angstroms or more preferably about 5 angstroms, and the thickness of the horizontal portion 46 of the gate dielectric layer 40 in the I / O region 16 is preferably between 30 and 40 angstroms or more preferably about 34 angstroms.

[0049] like Figure 7 As shown, a high dielectric constant dielectric layer 52, a work function metal layer 54 and a low impedance metal layer 56 are sequentially formed in the groove, and then a planarization process is performed, such as using CMP to remove part of the low impedance metal layer 56, part of the work function metal layer 54 and part of the high dielectric constant dielectric layer 52 to form a metal gate 62.

[0050] In the present embodiment, the high-k dielectric layer 52 comprises a dielectric material having a dielectric constant greater than 4, for example, selected from hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalum oxide (strontium bismuth tantalum oxide), and strontium tantalum oxide (strontium bismuth tantalum oxide). tantalate,SrBi2Ta2O9,SBT), lead zirconate titanate (leadzirconate titanate,PbZr x Ti 1-xO3, PZT), barium strontium titanate (Ba x Sr 1- x TiO3, BST), or a combination thereof.

[0051] The work function metal layer 54 is preferably used to adjust the work function of the metal gate so that it is suitable for an N-type transistor (NMOS) or a P-type transistor (PMOS). If the transistor is an N-type transistor, the work function metal layer 54 can be made of a metal material with a work function of 3.9 electron volts (eV) to 4.3 eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl) or TiAlC (titanium aluminum carbide), etc., but not limited thereto; if the transistor is a P-type transistor, the work function metal layer 54 can be made of a metal material with a work function of 4.8 eV to 5.2 eV, such as titanium nitride (TiN), tantalum nitride (TaN) or tantalum carbide (TaC), etc., but not limited thereto. Another barrier layer (not shown) may be included between the work function metal layer 54 and the low resistance metal layer 56, wherein the barrier layer may be made of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc. The low resistance metal layer 56 may be selected from low resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., or a combination thereof.

[0052] Next, a portion of the high-k dielectric layer 52, a portion of the work function metal layer 54, and a portion of the low-resistance metal layer 56 may be removed to form a groove (not shown), and then a hard mask 58 is filled in the groove and the hard mask 58 is flush with the surface of the interlayer dielectric layer 36, wherein the hard mask 58 may be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride. It should be noted that in this stage, when a portion of the high-k dielectric layer 52, a portion of the work function metal layer 54, and a portion of the low-resistance metal layer 56 are removed by etching to form the groove, due to the difference in material selection ratio, the top surface of the low-resistance metal layer 56 is preferably slightly higher than the top surfaces of the high-k dielectric layer 52 and the work function metal layer 54.

[0053] Then as Figure 8As shown, a contact plug manufacturing process can be performed to form a contact plug 64 to electrically connect the core area 14 and the source / drain region 30 of the I / O area 16, and then a stop layer 66 is formed on the interlayer dielectric layer 36. In this embodiment, the contact plug 64 can be formed by first removing part of the interlayer dielectric layer 36 and part of the contact hole etching stop layer 34 to form a contact hole (not shown), and then depositing a barrier layer (not shown) and a metal layer (not shown) on the substrate 12 in sequence to fill the contact hole. Then, a planarization process, such as CMP, is used to remove part of the metal layer, part of the barrier layer and even part of the interlayer dielectric layer 36 to form a contact plug 64 in the contact hole, and the upper surface of the contact plug 64 is preferably flush with the upper surface of the interlayer dielectric layer 36. In this embodiment, the barrier layer is preferably selected from the group consisting of titanium, tantalum, titanium nitride, tantalum nitride and tungsten nitride, the metal layer is preferably selected from the group consisting of aluminum, titanium, tantalum, tungsten, niobium, molybdenum and copper, and the stop layer 66 preferably includes an oxide such as tetraethyl orthosilicate (TEOS), but is not limited thereto. Thus, the fabrication of a semiconductor device according to one embodiment of the present invention is completed.

[0054] Please refer to Figure 8 , Figure 8 A schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention is also disclosed. Figure 8 As shown, the semiconductor device mainly includes a substrate having a core area 14 and an I / O area 16, a metal gate 62 is arranged in the core area 14, another metal gate 62 is arranged in the I / O area 16, spacers 28 are respectively arranged beside the metal gates 62, and an interlayer dielectric layer 36 surrounds the metal gates 62, wherein the metal gate 62 of the core area 14 includes a gate dielectric layer 50 arranged between the substrate 12 and the high dielectric constant dielectric layer 52, the metal gate 62 of the I / O area 16 includes a gate dielectric layer 40 arranged between the substrate 12 and the high dielectric constant dielectric layer 52, and the gate dielectric layer 50 and the gate dielectric layer 40 have different shapes.

[0055] From a detailed perspective, the gate dielectric layer 50 of the core region 14 includes an I-shaped cross-section extending along the horizontal direction, while the gate dielectric layer 40 of the I / O region 16 includes a U-shaped cross-section, wherein the gate dielectric layer 40 of the I / O region 16 includes two vertical portions 42, 44 and a horizontal portion 46 connecting the two vertical portions 42, 44, and the thickness of the gate dielectric layer 50 of the core region 14 is preferably greater than the thickness of the two vertical portions 42, 44 of the gate dielectric layer 40 of the I / O region 16 but less than the thickness of the horizontal portion 46.

[0056] In summary, the present invention mainly forms a gate structure or a dummy gate made of polysilicon on the core area and / or the I / O area, and an interlayer dielectric layer surrounds the gate structure, then hollows out the gate structure made of polysilicon in each area to form a groove, and then performs an oxide growth process to form a gate dielectric layer with a U-shaped cross-section in the groove. According to a preferred embodiment of the present invention, by adjusting the oxygen flow rate and time introduced in the oxide growth process, the oxygen can react with the inner side wall of the spacer 28 and the surface of the fin structure 20 or the substrate 12 at the same time to form a gate dielectric layer with a U-shaped cross-section, and this U-shaped gate dielectric layer helps to repair the defect of epitaxial layer loss and formation of voids caused by the wet cleaning process when the polysilicon gate is generally hollowed out.

[0057] It should be noted that in the above-mentioned embodiment, after forming the gate dielectric layer 40 with a U-shaped cross section in the core region and the I / O region, a photolithography and etching process is performed to remove the gate dielectric layer in the core region (eg Figures 4 to 5 and forming another thinner gate electrode layer 50, but not limited thereto. According to other embodiments of the present invention, Figure 3 After forming the gate dielectric layer 40 with a U-shaped cross section in the core region and the I / O region, the U-shaped gate dielectric layer in the core region is not removed and the Figure 7 The manufacturing process is to form a high dielectric constant dielectric layer, a work function metal layer and a low impedance metal layer on the U-shaped gate dielectric layer in the core area and the I / O area at the same time. This variation also falls within the scope of the present invention.

[0058] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: Include: Providing a substrate including a core area and an input / output (I / O) area; and A first metal gate is formed in the core region and a second metal gate is formed in the I / O region, wherein the first metal gate comprises a first gate dielectric layer, the second metal gate comprises a second gate dielectric layer, and the first gate dielectric layer and the second gate dielectric layer comprise different shapes.

2. The method of claim 1, further comprising: forming a first gate structure in the core region and a second gate structure in the I / O region; forming a first spacer beside the first gate structure and a second spacer beside the second gate structure; forming an interlayer dielectric layer surrounding the first gate structure and the second gate structure; Removing the first gate structure and the second gate structure to form a first groove in the core area and a second groove in the I / O area; forming a third gate dielectric layer in the first groove and a second gate dielectric layer in the second groove; forming a patterned mask in the I / O region; removing the third gate dielectric layer in the first groove; forming the first gate dielectric layer in the first groove; as well as A high-k dielectric layer, a work function metal layer and a low-resistance metal layer are formed in the first groove and the second groove to form the first metal gate and the second metal gate. 3 . The method of claim 2 , wherein the second gate dielectric layer and the third gate dielectric layer comprise the same shape. 4 . The method of claim 2 , wherein each of the second gate dielectric layer and the third gate dielectric layer comprises a U-shape. The method of claim 1 , wherein the first gate dielectric layer comprises an I-shape.

6. The method of claim 1, wherein the second gate dielectric layer comprises: A first vertical portion and a second vertical portion; and The horizontal portion connects the first vertical portion and the second vertical portion. The method of claim 6 , wherein the first vertical portion and the second vertical portion comprise the same material. The method of claim 6 , wherein the first vertical portion and the horizontal portion comprise different materials.

9. A semiconductor element, characterized in that: Include: a substrate, including a core area and an input / output (I / O) area; and The first metal gate is disposed in the core region and the second metal gate is disposed in the I / O region, wherein the first metal gate comprises a first gate dielectric layer, the second metal gate comprises a second gate dielectric layer, and the first gate dielectric layer and the second gate dielectric layer comprise different shapes.

10. The semiconductor device according to claim 9, further comprising: A first spacer is disposed beside the first metal gate and a second spacer is disposed beside the second metal gate; and The interlayer dielectric layer surrounds the first metal gate and the second metal gate. The semiconductor device as claimed in claim 9 , wherein the first gate dielectric layer comprises an I-shape. 12 . The semiconductor device as claimed in claim 9 , wherein the second gate dielectric layer comprises a U-shape.

13. The semiconductor device as claimed in claim 9, wherein the second gate dielectric layer comprises: A first vertical portion and a second vertical portion; and The horizontal portion connects the first vertical portion and the second vertical portion. The semiconductor device as claimed in claim 13 , wherein the first vertical portion and the second vertical portion comprise the same material. The semiconductor device as claimed in claim 13 , wherein the first vertical portion and the horizontal portion comprise different materials.

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