Preparation method of stacked transistor, stacked transistor and semiconductor device

Abstract

The invention provides a preparation method of a stacked transistor, the stacked transistor and a semiconductor device. The method comprises the following steps: forming an active structure on a semiconductor substrate, wherein the active structure comprises a first part and a second part; a first transistor and a second transistor which are stacked in the first direction are formed based on the first part, and the polarities of the first transistor and the second transistor are opposite; reversing and removing the semiconductor substrate; based on the second part, a third transistor and a fourth transistor which are stacked in the first direction are formed, and the polarities of the third transistor and the fourth transistor are opposite; an isolation structure exists between any two adjacent transistors in the first transistor, the second transistor, the third transistor and the fourth transistor; etching the isolation structure between any two of the first transistor, the second transistor, the third transistor and the fourth transistor to form a through hole; and depositing a metal material in the through hole to form an interconnected through hole structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor chip manufacturing, and in particular to a method for preparing a stacked transistor, a stacked transistor and a semiconductor device. Background Art

[0002] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors integrate two or more layers of transistors in a vertical space to further increase the integration density of transistors, becoming one of the important technologies to continue the miniaturization of integrated circuit size.

[0003] In some schemes for preparing stacked transistors, the active regions of the upper and lower layers of the same source transistors are formed by etching, and the stacked transistors are made on the front and back sides of the wafer by flipping the wafer. This can also be called a "self-aligned flip transistor" scheme. However, although the "self-aligned flip transistor" realizes the integration of multiple layers of transistors in a vertical space, there is still room for optimization in the interconnection between the multiple layers of transistors. Summary of the invention

[0004] The present application provides a method for preparing a stacked transistor, a stacked transistor and a semiconductor device, which vertically interconnect each transistor in the stacking direction using a "self-aligned flip transistor" to realize a more complex standard logic unit, thereby creating conditions for large-scale integration of the "self-aligned flip transistor".

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a stacked transistor, comprising: forming an active structure on a semiconductor substrate, the active structure comprising a first part and a second part; based on the first part, forming a first transistor and a second transistor stacked along a first direction, wherein the first transistor and the second transistor have opposite polarities; the first direction is a direction perpendicular to the semiconductor substrate; flipping and removing the semiconductor substrate; based on the second part, forming a third transistor and a fourth transistor stacked along the first direction, wherein the third transistor and the fourth transistor have opposite polarities; there is an isolation structure between any two adjacent transistors among the first transistor, the second transistor, the third transistor and the fourth transistor; etching the isolation structure between any two transistors among the first transistor, the second transistor, the third transistor and the fourth transistor to form a through hole, wherein the projection of the through hole along the first direction falls within the projection of the source and drain metals of any two transistors along the first direction; depositing metal material in the through hole to form an interconnected through hole structure, wherein the interconnected through hole structure is used to connect the source and drain metals in any two transistors.

[0006] In some possible embodiments, based on the first part, a first transistor and a second transistor stacked along a first direction are formed, including: depositing an insulating material on a semiconductor substrate to form an initial isolation structure, wherein the initial isolation structure surrounds the second part and the first part is exposed outside the initial isolation structure; based on the first part, forming a second source-drain structure, a second interlayer dielectric layer, and a second gate structure on the initial isolation structure; wherein the second interlayer dielectric layer wraps the second source-drain structure; forming a second source-drain metal on the second source-drain structure; depositing an insulating material on the second source-drain metal to form a first isolation structure; based on the first part, forming a first source-drain structure, a first interlayer dielectric layer, and a first gate structure on the first isolation structure; wherein the first interlayer dielectric layer wraps the first source-drain structure; forming a first source-drain metal on the first source-drain structure.

[0007] In some possible embodiments, based on the second part, a third transistor and a fourth transistor stacked along the first direction are formed, including: thinning the initial isolation structure to form a second isolation structure between the second transistor and the third transistor; based on the second part, forming a third source-drain structure, a third interlayer dielectric layer and a third gate structure on the second isolation structure; wherein the third interlayer dielectric layer wraps the third source-drain structure; a third source-drain metal is formed on the third source-drain structure; an insulating material is deposited on the third source-drain metal to form a third isolation structure; based on the first part, a fourth source-drain structure, a fourth interlayer dielectric layer and a fourth gate structure are formed on the third isolation structure; wherein the fourth interlayer dielectric layer wraps the fourth source-drain structure; a fourth source-drain metal is formed on the fourth source-drain structure; wherein the first isolation structure, the second isolation structure and the third isolation structure are included in the isolation structure.

[0008] In some possible embodiments, etching the isolation structure between any two transistors among the first transistor, the second transistor, the third transistor and the fourth transistor to form a through hole includes at least one of the following: etching the first interlayer dielectric layer and the first isolation structure in sequence until the second source-drain metal is exposed to form a first through hole; etching the third interlayer dielectric layer and the second isolation structure in sequence until the second source-drain metal is exposed to form a second through hole; etching the fourth interlayer dielectric layer and the third isolation structure in sequence until the third source-drain metal is exposed to form a third through hole; etching the third interlayer dielectric layer, the second isolation structure, the second interlayer dielectric layer, the first isolation structure and the first interlayer dielectric layer in sequence until the first source-drain metal is exposed to form a fourth through hole; etching the fourth interlayer dielectric layer, the third isolation structure, the third interlayer dielectric layer, the second isolation structure and the second interlayer dielectric layer in sequence until the second source-drain metal is exposed to form a fifth through hole; etching the fourth interlayer dielectric layer, the third isolation structure, the third interlayer dielectric layer, the second isolation structure, the second interlayer dielectric layer, the first isolation structure and the first interlayer dielectric layer in sequence until the first source-drain metal is exposed to form a sixth through hole.

[0009] In some possible embodiments, etching the isolation structure between any two transistors among the first transistor, the second transistor, the third transistor, and the fourth transistor to form a through hole includes any of the following: etching the first interlayer dielectric layer and the first isolation structure in sequence until the second source-drain metal is exposed to form a first through hole, and etching the third interlayer dielectric layer and the second isolation structure in sequence until the second source-drain metal is exposed to form a second through hole; etching the first interlayer dielectric layer and the first isolation structure in sequence until the second source-drain metal is exposed to form a first through hole, and etching the fourth interlayer dielectric layer and the third isolation structure in sequence until the third source-drain metal is exposed to form a second through hole. The first interlayer dielectric layer and the first isolation structure are sequentially etched until the second source-drain metal is exposed to form a first through hole, the third interlayer dielectric layer and the second isolation structure are sequentially etched until the second source-drain metal is exposed to form a second through hole, and the fourth interlayer dielectric layer and the third isolation structure are sequentially etched until the third source-drain metal is exposed to form a third through hole; the first interlayer dielectric layer and the first isolation structure are sequentially etched until the second source-drain metal is exposed to form a first through hole, and the fourth interlayer dielectric layer, the third isolation structure, the third interlayer dielectric layer, the second isolation structure and the second interlayer dielectric layer are sequentially etched until the second source-drain metal is exposed to form a third through hole. The third interlayer dielectric layer and the second isolation structure are sequentially etched until the second source-drain metal is exposed to form a fifth through hole; the third interlayer dielectric layer and the second isolation structure are sequentially etched until the second source-drain metal is exposed to form a second through hole, and the fourth interlayer dielectric layer and the third isolation structure are sequentially etched until the third source-drain metal is exposed to form a third through hole; the third interlayer dielectric layer and the second isolation structure are sequentially etched until the second source-drain metal is exposed to form a second through hole, and the fourth interlayer dielectric layer, the third isolation structure, the third interlayer dielectric layer, the second isolation structure, the second interlayer dielectric layer, the first isolation structure and the first interlayer dielectric layer are sequentially etched until the first source-drain metal is exposed to form a sixth through hole; the fourth interlayer dielectric layer and the third isolation structure are sequentially etched until the second source-drain metal is exposed to form a sixth through hole. The third interlayer dielectric layer and the third isolation structure are etched until the third source-drain metal is exposed to form a third through hole, and the third interlayer dielectric layer, the second isolation structure, the second interlayer dielectric layer, the first isolation structure and the first interlayer dielectric layer are etched in sequence until the first source-drain metal is exposed to form a fourth through hole; the third interlayer dielectric layer, the second isolation structure, the second interlayer dielectric layer, the first isolation structure and the first interlayer dielectric layer are etched in sequence until the first source-drain metal is exposed to form a fourth through hole, and the fourth interlayer dielectric layer, the third isolation structure, the third interlayer dielectric layer, the second isolation structure and the second interlayer dielectric layer are etched in sequence until the second source-drain metal is exposed to form a fifth through hole.

[0010] In some possible embodiments, depositing a metal material in a through hole to form an interconnected through hole structure includes at least one of the following: depositing a metal material in a first through hole to form a first interconnected through hole structure, wherein the first interconnected through hole structure is used to connect the first source-drain metal and the second source-drain metal; depositing a metal material in a second through hole to form a second interconnected through hole structure, wherein the second interconnected through hole structure is used to connect the second source-drain metal and the third source-drain metal; depositing a metal material in a third through hole to form a third interconnected through hole structure, wherein the third interconnected through hole structure is used to connect the third source-drain metal and the fourth source-drain metal; depositing a metal material in a fourth through hole to form a fourth interconnected through hole structure, wherein the fourth interconnected through hole structure is used to connect the first source-drain metal and the third source-drain metal; depositing a metal material in a fifth through hole to form a fifth interconnected through hole structure, wherein the fifth interconnected through hole structure is used to connect the second source-drain metal and the fourth source-drain metal; depositing a metal material in a sixth through hole to form a sixth interconnected through hole structure, wherein the sixth interconnected through hole structure is used to connect the first source-drain metal and the fourth source-drain metal.

[0011] In some possible embodiments, a first source-drain metal is formed on the first source-drain structure, including: depositing a dielectric material on the first source-drain structure to form a first interlayer dielectric layer, and etching the first interlayer dielectric layer until the first source-drain structure is exposed to form a first source-drain metal groove; depositing a metal material in the first through hole to form a first interconnected through hole structure, including: depositing a metal material in the first source-drain metal groove and the first through hole to form a first source-drain metal and a first interconnected through hole structure, respectively.

[0012] In some possible embodiments, a third source-drain metal is formed on the third source-drain structure, including: depositing a dielectric material on the third source-drain structure to form a third interlayer dielectric layer, and etching the third interlayer dielectric layer until the third source-drain structure is exposed to form a third source-drain metal groove; depositing a metal material in the second through hole to form a second interconnected through hole structure, including: depositing a metal material in the third source-drain metal groove and the second through hole to form a third source-drain metal and a second interconnected through hole structure, respectively; depositing a metal material in the fourth through hole to form a fourth interconnected through hole structure, including: depositing a metal material in the third source-drain metal groove and the fourth through hole to form a third source-drain metal and a fourth interconnected through hole structure, respectively.

[0013] In some possible embodiments, a fourth source-drain metal is formed on the fourth source-drain structure, including: depositing a dielectric material on the fourth source-drain structure to form a fourth interlayer dielectric layer, and etching the fourth interlayer dielectric layer until the fourth source-drain structure is exposed to form a fourth source-drain metal groove; depositing a metal material in the third through hole to form a third interconnected through hole structure, including: depositing a metal material in the fourth source-drain metal groove and the third through hole to form a fourth source-drain metal and a third interconnected through hole structure, respectively; depositing a metal material in the fifth through hole to form a fifth interconnected through hole structure, including: depositing a metal material in the fourth source-drain metal groove and the fifth through hole to form a fourth source-drain metal and a fifth interconnected through hole structure, respectively; depositing a metal material in the sixth through hole to form a sixth interconnected through hole structure, including: depositing a metal material in the fourth source-drain metal groove and the sixth through hole to form a fourth source-drain metal and a sixth interconnected through hole structure, respectively.

[0014] In a second aspect, an embodiment of the present application provides a stacked transistor, comprising: a first transistor and a second transistor stacked along a first direction, the first transistor and the second transistor having different polarities; a third transistor and a fourth transistor stacked along the first direction, the third transistor and the fourth transistor having different polarities; an isolation structure existing between any two adjacent transistors among the first transistor, the second transistor, the third transistor and the fourth transistor; and an interconnected via structure, wherein the interconnected via structure is used to connect the source and drain metals of any two transistors among the first transistor, the second transistor, the third transistor and the fourth transistor by penetrating the isolation structure.

[0015] In some possible embodiments, the first transistor, the second transistor, the third transistor and the fourth transistor are arranged in sequence along the first direction; the interconnection through-hole structure includes: at least one of the first interconnection through-hole structure, the second interconnection through-hole structure, the third interconnection through-hole structure, the fourth interconnection through-hole structure, the fifth interconnection through-hole structure and the sixth interconnection through-hole structure; wherein the first interconnection through-hole structure is used to connect the first source-drain metal of the first transistor and the second source-drain metal of the second transistor; the second interconnection through-hole structure is used to connect the second source-drain metal of the second transistor and the third source-drain metal of the third transistor; the third interconnection through-hole structure is used to connect the third source-drain metal of the third transistor and the fourth source-drain metal of the fourth transistor; the fourth interconnection through-hole structure is used to connect the first source-drain metal of the first transistor and the third source-drain metal of the third transistor; the fifth interconnection through-hole structure is used to connect the second source-drain metal of the second transistor and the fourth source-drain metal of the fourth transistor; the sixth interconnection through-hole structure is used to connect the first source-drain metal of the first transistor and the fourth source-drain metal of the fourth transistor.

[0016] In some possible embodiments, the first transistor, the second transistor, the third transistor and the fourth transistor are arranged in sequence along the first direction; the interconnected through-hole structure includes any of the following: the first interconnected through-hole structure and the second interconnected through-hole structure; the first interconnected through-hole structure and the third interconnected through-hole structure; the first interconnected through-hole structure, the second interconnected through-hole structure and the third interconnected through-hole structure; the first interconnected through-hole structure and the fifth interconnected through-hole structure; the second interconnected through-hole structure and the third interconnected through-hole structure; the second interconnected through-hole structure and the sixth interconnected through-hole structure; the third interconnected through-hole structure and the fourth interconnected through-hole structure; the fourth interconnected through-hole structure and the fifth interconnected through-hole structure; wherein the first interconnected through-hole The structure is used to connect the first source-drain metal of the first transistor and the second source-drain metal of the second transistor; the second interconnection through-hole structure is used to connect the second source-drain metal of the second transistor and the third source-drain metal of the third transistor; the third interconnection through-hole structure is used to connect the third source-drain metal of the third transistor and the fourth source-drain metal of the fourth transistor; the fourth interconnection through-hole structure is used to connect the first source-drain metal of the first transistor and the third source-drain metal of the third transistor; the fifth interconnection through-hole structure is used to connect the second source-drain metal of the second transistor and the fourth source-drain metal of the fourth transistor; the sixth interconnection through-hole structure is used to connect the first source-drain metal of the first transistor and the fourth source-drain metal of the fourth transistor.

[0017] In some possible implementations, the first interconnection via structure, the second interconnection via structure, the third interconnection via structure, the fourth interconnection via structure, the fifth interconnection via structure, and the sixth interconnection via structure are located on the first side or the second side of the first source-drain structure of the first transistor in the second direction;

[0018] The first side and the second side are two opposite sides of the first source-drain structure, and the second direction is perpendicular to the first direction.

[0019] In a third aspect, an embodiment of the present application provides a semiconductor device, which includes: a stacked transistor as described in the above embodiment.

[0020] In an embodiment of the present application, by forming an active structure with a certain depth on a semiconductor substrate, it is possible to realize that the active areas of a plurality of transistors arranged along a first direction of vertically stacked transistors are self-aligned. Subsequently, a first transistor and a second transistor vertically stacked along a first direction and having different polarities can be prepared based on the first part of the active structure, and the semiconductor substrate is etched after flipping, so that a third transistor and a fourth transistor vertically stacked along a first direction and having different polarities can be prepared based on the second part of the active structure. It can be seen that by forming a pair of stacked transistors on the front side of the wafer and another pair of stacked transistors on the back side of the wafer, it is possible to prepare more transistors using the front and back sides of the wafer, thereby increasing the integration density of the transistors and further improving the integration performance of the transistors. Finally, by etching the isolation structure between any two transistors among the first transistor, the second transistor, the third transistor and the fourth transistor, an interconnected through-hole structure is formed, so that the isolation structure between any two transistors is penetrated, thereby connecting any two transistors in the first direction through the interconnected through-hole structure and the source-drain metal of any two transistors, which helps to realize large-scale integration of stacked transistors.

[0021] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0023] Figure 1 is a top view of a stacked transistor according to an embodiment of the present application;

[0024] Figure 2 A schematic diagram of an implementation process of a method for preparing a stacked transistor according to an embodiment of the present application;

[0025] Figures 3 to 25 is a schematic diagram of a preparation process of a stacked transistor according to an embodiment of the present application;

[0026] Fig.26 It is a schematic diagram of the structure of a stacked transistor according to an embodiment of the present application.

[0027] Fig. 27 It is a schematic diagram of the structure of a stacked transistor according to an embodiment of the present application.

[0028] Figures 10, stacked transistor; 101, front vertical stacked transistor; 1011, front metal interconnect layer; 102, back vertical stacked transistor; 1021, back metal interconnect layer; 11, first transistor; 12, second transistor; 13, third transistor; 14, fourth transistor; 111, first pseudo gate sidewall; 112, first source-drain structure; 113, first interlayer dielectric layer; 114, first gate structure; 115, first source-drain metal; 121, second pseudo gate sidewall; 122 , second source-drain structure; 123, second interlayer dielectric layer; 124, second gate structure; 125, second source-drain metal; 127, front dielectric layer; 131, third pseudo-gate sidewall; 132, third source-drain structure; 133, third interlayer dielectric layer; 134, third gate structure; 135, third source-drain metal; 141, fourth pseudo-gate sidewall; 142, fourth source-drain structure; 143, fourth interlayer dielectric layer; 144, fourth gate structure; 145, fourth source-drain metal; 147, reverse dielectric layer;

[0029] 20. semiconductor substrate; 21. first part; 211. first sacrificial layer; 212. third part; 213. fourth part; 214. second sacrificial layer; 22. second part; 222. fifth part; 223. sixth part; 23. stacked structure; 24. isolation layer; 25. shallow trench isolation structure; 26. first pseudo gate structure; 27. first trench; 28. first isolation structure; 29. ​​first initial trench; 30. first barrier layer; 31. second barrier layer; 32. insulating layer; 33. carrier wafer; 34. third isolation structure; 35. fourth barrier layer; 36. second pseudo gate structure; 40. second isolation structure; 51. first interconnection through hole structure; 52. second interconnection through hole structure; 53. third interconnection through hole structure; 54. fourth interconnection through hole structure; 55. fifth interconnection through hole structure; 56. sixth interconnection through hole structure. DETAILED DESCRIPTION

[0030] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0031] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot topic in the current industry research and development. Stacked transistors can achieve the integration of two or more layers of transistors in a vertical space through three-dimensional transistor stacking, which helps to further improve the integration density of transistors and improve circuit performance. It is considered to be one of the important technologies for continuing the miniaturization of integrated circuit size.

[0032] In one embodiment, there are two schemes for manufacturing the stacked transistors, the first is a monolithic scheme, and the second is a sequential scheme.

[0033] The sequential solution is based on wafer bonding and is processed layer by layer. However, thanks to wafer bonding, the device structure, channel crystal orientation and even channel material used in the upper and lower transistors can be optimized accordingly to obtain better and more matched device performance. The main challenges faced by the sequential stacking transistor process include: (1) preparation of high-quality upper transistor active layer; (2) thinning and defect control of the upper bonded wafer; (3) alignment errors between the upper and lower transistors, which requires extremely high lithography accuracy.

[0034] In the monolithic stacked transistor technology, wafer bonding technology is not used. Instead, N-channel field effect transistors (NFET) and P-channel field effect transistors (PFET) are made on the same substrate, which also determines that the transistors on the same layer must be of the same type, that is, NFET or PFET. In addition, the upper and lower layers of transistors are strictly in the same plane space, and there is no alignment deviation. Obviously, the advantage of monolithic stacked transistors is higher integration density. However, its disadvantages are also obvious: (1) The process is complex and requires a lot of process technology development and optimization; (2) The polarity of each layer of transistors is fixed, and it must rely on two layers of transistors to form a basic CMOS circuit, which has poor design flexibility.

[0035] In order to solve the technical problems of the above two solutions, a "self-aligned flip transistor" solution is proposed. The "self-aligned flip transistor" solution forms the active area of ​​the upper and lower layers of the same source transistors by etching, and realizes the production of stacked transistors on the front and back of the wafer by flipping the wafer to overcome the shortcomings of the above two solutions. However, although the "self-aligned flip transistor" realizes the integration of multiple layers of transistors in the vertical space, there is still room for optimization in the interconnection between the multiple layers of transistors. Therefore, a more advanced preparation process is needed to realize the "self-aligned flip transistor" to vertically interconnect each transistor in the stacking direction, so as to realize more complex standard logic units and create conditions for the large-scale integration of "self-aligned flip transistors".

[0036] In a first aspect, an embodiment of the present application provides a stacked transistor. Figure 1 FIG. 1 is a top view of a stacked transistor according to an embodiment of the present application, see Figure 1 As shown, the top view only shows the fin structure, gate structure and source-drain structure of the stacked transistor 10. It is understandable that the structure of the fin structure may be different based on the type of the stacked transistor.

[0037] Exemplarily, when the stacked transistor 10 is a fin field effect transistor, the fin structure can be formed by depositing a single semiconductor material. When the stacked transistor 10 is a gate-all-around nanosheet (GAANanosheet), the fin structure can be formed by alternately depositing a semiconductor material and a sacrificial layer material; for example, it can be formed by alternately depositing a silicon layer and a silicon germanium layer. This embodiment of the present application is not limited to this.

[0038] Figure 2 FIG. 1 is a schematic diagram of an implementation process of a method for preparing a stacked transistor according to an embodiment of the present application, see Figure 2 As shown, the method for preparing a stacked transistor may include:

[0039] Step S201, forming an active structure on a semiconductor substrate, the active structure comprising a first part and a second part;

[0040] Step S202, based on the first part, forming a first transistor and a second transistor stacked along a first direction, wherein the first transistor and the second transistor have opposite polarities; the first direction is a direction perpendicular to the semiconductor substrate;

[0041] Step S203, flipping the wafer and removing the semiconductor substrate;

[0042] Step S204, based on the second part, forming a third transistor and a fourth transistor stacked along the first direction, wherein the third transistor and the fourth transistor have opposite polarities; and an isolation structure exists between any two adjacent transistors among the first transistor, the second transistor, the third transistor and the fourth transistor;

[0043] Step S205, etching an isolation structure between any two transistors among the first transistor, the second transistor, the third transistor and the fourth transistor to form a through hole, wherein a projection of the through hole along the first direction falls within a projection of source and drain metals of any two transistors along the first direction;

[0044] Step S206 , depositing metal material in the through hole to form an interconnected through hole structure, wherein the interconnected through hole structure is used to connect source and drain metals in any two transistors.

[0045] It should be noted that Figure 2 The steps shown in the operation are not exclusive, and other steps may be performed before, after or between any steps in the operation shown; Figure 2 The steps shown in the figure can be adjusted in sequence according to actual needs.

[0046] It can be understood that by forming an active structure with a certain depth on the semiconductor substrate, the active areas of multiple transistors arranged along the first direction of the vertically stacked transistors can be self-aligned. Subsequently, a first transistor and a second transistor vertically stacked along the first direction and having different polarities can be prepared based on the first part of the active structure, and the semiconductor substrate can be etched after flipping, so that a third transistor and a fourth transistor vertically stacked along the first direction and having different polarities can be prepared based on the second part of the active structure. It can be seen that by forming a pair of stacked transistors on the front side of the wafer and another pair of stacked transistors on the back side of the wafer, more transistors can be prepared using the front and back sides of the wafer, thereby increasing the integration density of the transistors and further improving the integration performance of the transistors. Finally, by etching the isolation structure between any two transistors among the first transistor, the second transistor, the third transistor and the fourth transistor, an interconnected through-hole structure is formed, so that the isolation structure between any two transistors is penetrated, thereby connecting any two transistors in the first direction through the interconnected through-hole structure and the source and drain metal of any two transistors, which helps to achieve large-scale integration of stacked transistors.

[0047] Figures 3 to 25 FIG. 1 is a schematic diagram of a preparation process of a first stacked transistor according to an embodiment of the present application. For ease of understanding, Figures 3 to 25 (a) shows the Figure 1 The cross-sectional view along the dashed line AA'. Figures 3 to 25 (b) shows the Figure 1 The cross-sectional view along the dotted line BB', Figures 3 to 25 (c) shows the Figure 1 The cross-sectional view along the dotted line CC' Figures 1 to 25 The method for preparing the stacked transistor provided in the embodiment of the present application and the prepared stacked transistor are exemplarily described.

[0048] In step S201, see Figure 4 As shown, an active structure is formed on a semiconductor substrate 20 .

[0049] It is understandable that material layer deposition, epitaxial growth and other processes may be performed on the semiconductor substrate 20 to form a stacked structure 23 on the semiconductor substrate 20, such as Figure 3 Subsequently, a single etching process may be used to etch the stacked structure 23 to form an active structure on the semiconductor substrate 20 .

[0050] Here, the stacked structure 23 includes sacrificial layers and supporting layers stacked alternately in sequence. The materials used for the sacrificial layers and supporting layers can be selected according to actual needs, and the embodiments of the present application do not limit this. It should be noted that the supporting layer can be used to form an active structure.

[0051] In one embodiment, the stacked structure 23 may be formed by alternately depositing silicon material and silicon germanium material.

[0052] It can be understood that the active structure includes a first portion 21 and a second portion 22. The first portion 21 and the second portion 22 are stacked along a first direction (a direction perpendicular to the semiconductor substrate 20), and the second portion 22 is closer to the semiconductor substrate 20 than the first portion 21.

[0053] It can be understood that the first part 21 of the active structure is used in a subsequent step to form the active areas of the first transistor 11 and the second transistor 12 in the front vertical stacked transistor 101; the second part 22 of the active structure is used to form the active areas of the third transistor 13 and the fourth transistor 14 in the back vertical stacked transistor 102.

[0054] It should be noted that the front vertical stacked transistor 101 is formed based on the front side of the semiconductor substrate 20. After the stacked transistor 10 is prepared, the front vertical stacked transistor 101 is located at the bottom of the stacked transistor 10. The back vertical stacked transistor 102 is opposite to the front vertical stacked transistor 101.

[0055] In one embodiment, the type of transistor in the stacked transistor 10 may be a full-surround gate transistor. Then, the stacked structure 23 may be formed by alternately depositing silicon material and silicon germanium material. In one embodiment, the type of transistor in the stacked transistor 10 may be a fin field effect transistor. Of course, other types of transistors may also be used, which is not limited in the present embodiment.

[0056] In some embodiments, see Figure 4 As shown, an isolation layer 24 can be formed between the first portion 21 of the active structure and the second portion 22 of the active structure, thereby electrically isolating the first portion 21 of the active structure and the second portion 22 of the active structure, thereby avoiding current interference between the circuit of the front vertically stacked transistor 101 and the circuit of the back vertically stacked transistor 102.

[0057] In one embodiment, the isolation layer 24 may be a buried oxide layer or a dielectric layer. Here, the process of forming the buried oxide layer or the dielectric layer may be set according to actual needs, and the embodiment of the present application does not limit this. In one embodiment, the isolation layer 24 may be an ion implantation layer. Here, the process of forming the ion implantation layer may be set according to actual needs, and the embodiment of the present application does not limit this.

[0058] It is understandable that when the first part 21 of the active structure and the second part 22 of the active structure are formed by photolithography, a larger etching depth can be used. For example, the height of the first part 21 of the active structure and the second part 22 of the active structure obtained by etching can realize the formation of four transistors in the first direction. Of course, the height of the active structure can also be set according to actual conditions, and the embodiment of the present application is not limited to this.

[0059] It should be noted that the steps of the photolithography process may include: depositing a photoresist material, exposing and developing the photoresist material, removing a portion of the photoresist material, etching to remove a material layer corresponding to the portion of the photoresist material, etc.

[0060] In step S202, see Fig.18 As shown, based on the first portion 21 , a front-side vertically stacked transistor 101 is formed.

[0061] The front vertically stacked transistor 101 includes: a first transistor 11 and a second transistor 12 , the first transistor 11 and the second transistor 12 have different polarities, and the first transistor 11 and the second transistor 12 are self-aligned in a first direction.

[0062] It can be understood that the first transistor 11 and the second transistor 12 can be formed based on the first part 21 of the active structure. The first transistor 11 and the second transistor 12 have complementary polarities and are stacked along the first direction. At the same time, the front vertical stacked transistor 101 and the back vertical stacked transistor 102 are also stacked along the first direction, thereby greatly improving the integration of the stacked transistor 10 in the first direction.

[0063] In one embodiment, when the first transistor 11 is a P-type (P-channel) field effect transistor, the second transistor 12 may be an N-type (N-channel) field effect transistor; when the first transistor 11 is an N-type field effect transistor, the second transistor 12 may be a P-type field effect transistor.

[0064] It should be noted that the step of forming the front vertically stacked transistor 101 can be selected according to actual needs, and the embodiment of the present application does not limit this.

[0065] Exemplarily, the front vertically stacked transistor 101 may be formed by a monolithic solution or a sequential solution in a semiconductor manufacturing process.

[0066] In some embodiments, see Figure 5As shown, before forming the first transistor 11 and the second transistor 12, an insulating material may be deposited on the semiconductor substrate 20 to form a shallow trench isolation structure 25 (STI), wherein the shallow trench isolation structure encapsulates the second portion 22 of the active structure and exposes the first portion 21 of the active structure. The insulating material forming the shallow trench isolation structure 25 may be a silicon-based oxide (SiOx, where x is the number of oxygen atoms), such as silicon dioxide (SiO2).

[0067] It should be noted that the shallow trench isolation structure 25 is an initial isolation layer, and the shallow trench isolation structure 25 can be thinned after flipping to form a second isolation structure between the second transistor 12 and the third transistor 13 .

[0068] In one embodiment, the shallow trench isolation structure 25 may wrap the second portion 22 of the active structure and the isolation layer 24 , exposing the first portion 21 of the active structure.

[0069] In one embodiment, the second transistor 12 may be formed first, and then the first transistor 11 may be formed. The first transistor 11 is farther away from the semiconductor substrate 20 than the second transistor 12 .

[0070] In some embodiments, a first sacrificial layer 211 is formed in the middle of the first portion 21 of the active structure. With the first sacrificial layer 211 as the boundary, a portion of the first portion 21 that is farther from the semiconductor substrate 20 than the first sacrificial layer 211 is used to form the first transistor 11, and a portion of the first portion 21 that is closer to the semiconductor substrate 20 than the first sacrificial layer 211 is used to form the second transistor 12. Then, based on the first portion 21, a front vertical stacked transistor 101 is formed, including: based on the first portion 21, forming a first dummy gate structure 26 surrounding the first portion 21 and a dummy gate sidewall covering the first dummy gate structure 26. With the first dummy gate structure 26 as a hard mask, the first portion 21 located in the source and drain region is etched to form a first trench 27. A front source and drain structure of the front vertical stacked transistor 101 is formed in the first trench 27. The first sacrificial layer 211 and the first dummy gate structure 26 in the gate region are removed, and a front gate structure of the front vertical stacked transistor 101 is formed at the position where the first sacrificial layer 211 and the first dummy gate structure 26 are removed.

[0071] It can be understood that after the active structure is formed by performing step S201, the second portion 22 of the active structure can be wrapped by the shallow trench isolation structure 25, and the first portion 21 of the active structure can be exposed outside the shallow trench isolation structure 25. Subsequently, based on the exposed first portion 21 of the active structure, a dummy gate material such as polysilicon or amorphous silicon can be deposited to form a first dummy gate structure 26 surrounding the first portion 21 of the active structure. A sidewall material can also be deposited on the sidewall of the first dummy gate structure to form a dummy gate sidewall of the first dummy gate structure 26.

[0072] Among them, see Figure 6 As shown, a plurality of first dummy gate structures 26 are arranged along a second direction, and the second direction is perpendicular to the first direction. The second direction can be understood as the extension direction of the active structure (fin structure). Among them, in the extension direction of the active structure, the area between the dummy gate sidewalls of two adjacent first dummy gate structures 26 is the source-drain area, and the area where the first dummy gate structure 26 and its dummy gate sidewalls are located is the gate area.

[0073] It is understood that after forming the first dummy gate structure 26, the first portion 21 located in the source / drain region can be etched using the first dummy gate structure 26 as a hard mask to form a first trench 27 in the source / drain region, see Figures 6 to 9 Subsequently, a front source-drain structure of the front vertical stacked transistor 101 may be formed in the first trench 27 by epitaxial growth or deposition doping or other processes, see Figures 10 to 16 shown.

[0074] The front source-drain structure includes a first source-drain structure 112 of the first transistor 11, a first isolation structure 28 and a second source-drain structure 122 of the second transistor 12. The first isolation structure 28 is used to electrically isolate the first source-drain structure 112 from the second source-drain structure 122.

[0075] In one embodiment, see Figures 10 to 14 As shown, the second source-drain structure 122 may be first formed in the first trench 27 near the semiconductor substrate 20 , and then the first isolation structure 28 may be formed, and then the first source-drain structure 112 may be formed in the first trench 27 away from the semiconductor substrate 20 .

[0076] It is understood that after forming the front source-drain structure of the front vertical stacked transistor 101, the first dummy gate structure 26 and the first sacrificial layer 211 can be removed to achieve that only the active structure is retained in the gate region. Subsequently, a gate material is deposited at the position where the first dummy gate structure 26 and the first sacrificial layer 211 are removed to form the front gate structure of the front vertical stacked transistor 101, see Fig.15 shown.

[0077] The front gate structure includes a first gate structure 114 of the first transistor 11 and a second gate structure 124 of the second transistor 12, and the junction of the first gate structure 114 and the second gate structure 124 is located at the position where the first sacrificial layer 211 is removed. It can be understood that the first sacrificial layer 211 separates the first part 21 in the gate region into two parts, so that the separated first part 21 can simultaneously form the active area of ​​the first transistor 11 and the second transistor 12, and the junction of the first gate structure 114 of the first transistor 11 and the second gate structure 124 of the second transistor 12 can be located at the position where the first part 21 is separated, that is, at the position of the first sacrificial layer 211.

[0078] It can be understood that by forming the front source-drain structure and the front gate structure of the front vertical stacked transistor 101 , the front-end process of the front vertical stacked transistor 101 can be completed.

[0079] In some embodiments, the first portion 21 of the active structure further includes: a third portion 212 and a fourth portion 213, the first sacrificial layer 211 is located between the third portion 212 and the fourth portion 213, and the third portion 212 is closer to the semiconductor substrate 20 than the fourth portion 213. Then, using the first dummy gate structure 26 as a hard mask, etching the first portion 21 located in the source and drain regions to form the first trench 27 may include: using the first dummy gate structure 26 as a hard mask, etching the fourth portion 213 and the first sacrificial layer 211 located in the source and drain regions to expose the fourth portion 213 and the first sacrificial layer 211 in the gate region, and forming a first initial trench 29; forming a first barrier layer 30 on the sidewalls of the fourth portion 213 and the first sacrificial layer 211 in the gate region; etching the third portion 212 located below the first initial trench 29 to expose the third portion 212 in the gate region, and forming the first trench 27.

[0080] It can be understood that by etching the fourth portion 213 and the first sacrificial layer 211 in the source and drain regions, the fourth portion 213 and the first sacrificial layer 211 in the gate region can be exposed to form a first initial trench 29. Here, the bottom of the first initial trench 29 can be formed by the third portion 212 in the source and drain regions, and the groove wall of the first initial trench 29 can be formed by the fourth portion 213 and the first sacrificial layer 211 in the gate region. Subsequently, a first barrier layer 30 can be formed on the sidewalls of the fourth portion 213 and the first sacrificial layer 211 in the exposed gate region to isolate the fourth portion 213 and the first sacrificial layer 211 from the first initial trench 29. Subsequently, the third portion 212 located below the first initial trench 29 is etched to expose the third portion 212 in the gate region to obtain the first trench 27 required for subsequent steps, see Figures 7 and 8 .

[0081] It is understandable that in subsequent steps, based on the third portion 212 in the gate region, a second source-drain structure 122 can be formed in the first trench 27 (in the source-drain region) through an epitaxial growth process. Here, when forming the first trench 27, a first barrier layer 30 covering the fourth portion 213 and the first sacrificial layer 211 is formed. The first barrier layer 30 can effectively prevent the fourth portion 213 from also epitaxially growing an active structure, thereby ensuring the orderly preparation of the front vertical stacked transistor 101.

[0082] In one embodiment, the material forming the first barrier layer 30 may have a high selective etching property with the material forming the third portion 212 , so that the third portion 212 may be removed by a selective etching process.

[0083] For example, the third portion 212 may be formed of a silicon material, and the first barrier layer 30 may be formed of a silicon nitride material.

[0084] In some embodiments, the first portion 21 of the active structure further includes: a second sacrificial layer 214, and the second sacrificial layer 214 is closer to the semiconductor substrate 20 than the third portion 212. Then, etching the third portion 212 below the first initial trench 29 to expose the third portion 212 in the gate region and form the first trench 27, further includes: etching the third portion 212 and the second sacrificial layer 214 below the first initial trench 29 to expose the third portion 212 and the second sacrificial layer 214 in the gate region; forming a second barrier layer 31 on the sidewall of the second sacrificial layer 214 in the gate region, and forming the first trench 27.

[0085] It is understood that after forming the first barrier layer 30 covering the fourth portion 213 in the gate region and the sidewall of the first sacrificial layer 211, the third portion 212 and the second sacrificial layer 214 located below the first initial trench 29 may be etched to expose the third portion 212 and the second sacrificial layer 214 in the gate region. Subsequently, a second barrier layer 31 may be formed on the sidewall of the second sacrificial layer 214 in the gate region, thereby obtaining the first trench 27 required for subsequent steps, see Figures 7 to 9 .

[0086] It can be understood that the second barrier layer 31 has the same function as the first barrier layer 30 , which is to ensure that the second source-drain structure 122 can be epitaxially generated based on the third portion 212 .

[0087] It is understandable that, compared with the solution without the second sacrificial layer 214, the solution with the second sacrificial layer 214 can completely expose the third portion 212 in the gate region in the subsequent step of forming the gate structure, thereby facilitating the formation of a ring gate structure.

[0088] In one embodiment, the material forming the second barrier layer 31 may be a dummy gate material, thereby directly forming a dummy gate sidewall between the gate region and the source / drain region, thereby achieving electrical isolation between the gate structure and the source / drain structure of the front vertically stacked transistor 101 .

[0089] In some embodiments, before forming the first barrier layer 30 on the fourth portion 213 in the gate region and the sidewall of the first sacrificial layer 211, the method further includes: using an etching process to laterally etch the sidewall of the first sacrificial layer 211 in the exposed gate region to form a first groove. Filling the first groove with an insulating material to form a second dummy gate spacer 121 of the second transistor 12.

[0090] It is understood that before forming the first barrier layer 30, an etching process may be used to laterally etch the sidewall of the first sacrificial layer 211 in the exposed gate region to form a first groove opening toward the source and drain region. Subsequently, an insulating material may be filled in the first groove to form a second dummy gate spacer 121 of the second transistor 12, see Figure 7 .

[0091] Here, the depth of the first groove can be selected according to actual needs, and is not specifically limited in the embodiments of the present application.

[0092] It should be noted that after the insulating material is deposited in the first groove, it can be used to form a sidewall structure for isolating the gate structure from the source and drain structure. After the insulating material is filled in the first groove, at least a second dummy gate sidewall of the second transistor 12 can be formed, and the dummy gate sidewall of the first dummy gate structure 26 is used to form a first dummy gate sidewall 111 of the first transistor 11.

[0093] In some embodiments, after the first groove is filled with insulating material, a portion of the first groove forms the second dummy gate spacer of the second transistor 12 , and the other portion may form a portion of the first dummy gate spacer 111 of the first transistor 11 .

[0094] In some possible implementations, after forming the first trench 27 by adopting any of the above embodiments, a front source-drain structure of the front vertical stacked transistor 101 may be formed in the first trench 27. Specifically, the steps include: forming a second source-drain structure 122 in the first trench 27 by an epitaxial growth process based on the third portion 212 in the gate region; removing the first barrier layer 30 to expose the fourth portion 213 in the gate region; forming a first isolation structure 28 on the second source-drain structure 122, the first isolation structure 28 being opposite to the first sacrificial layer 211; and forming a first source-drain structure 112 in the first trench 27 by an epitaxial growth process based on the exposed fourth portion 213 in the gate region on the first isolation structure 28.

[0095] It can be understood that the third portion 212 in the gate region is not covered by the first barrier layer 30 and the second barrier layer 31, so that the third portion 212 in the gate region can be connected to the first trench 27, so that an active structure can be epitaxially grown along the second direction on the sidewall of the third portion 212 in the gate region to form a second source-drain structure 122 in the first trench 27. Then, the position of the second source-drain structure 122 can be opposite to the position of the third portion 212, see Fig.10 shown.

[0096] It is understood that after forming the second source-drain structure 122, the first barrier layer 30 can be removed to expose the fourth portion 213 in the gate region, see Fig.11 Subsequently, a source-drain isolation structure (ie, a first isolation structure 28) may be formed between the first source-drain structure 112 and the second source-drain structure 122, see Fig.13 Specifically, an insulating material may be deposited on the first source-drain structure 112 to form a first isolation structure 28. Then, the first isolation structure 28 is located between the first source-drain structure 112 and the second source-drain structure 122, that is, the first isolation structure 28 may be located opposite to the first sacrificial layer 211.

[0097] It can be understood that after forming the first isolation structure 28, an active structure can be epitaxially grown along the second direction on the sidewall of the fourth portion 213 in the gate region on the first isolation structure 28 based on the exposed fourth portion 213 in the gate region through an epitaxial growth process to form a first source-drain structure 112 in the first trench 27, see Fig.12 Then, the position of the first source-drain structure 112 may be opposite to the position of the fourth portion 213 .

[0098] Here, the process of epitaxially growing the active structure can be selected according to actual needs, and the embodiments of the present application do not specifically limit this.

[0099] It should be noted that the first source-drain structure 112 and the second source-drain structure 122 have different polarities, so that the front vertical stacked transistor 101 can be a complementary stacked transistor.

[0100] In some embodiments, after forming the second source-drain structure 122 in the first trench 27 by an epitaxial growth process, the method further includes: depositing a metal material on the second source-drain structure 122 to form a second source-drain metal 125 .

[0101] It is understood that after forming the second source-drain structure 122, a dielectric layer material may be deposited on the second source-drain structure 122 to form a second interlayer dielectric layer 123 of the second transistor 12. Subsequently, a hole may be opened in the second interlayer dielectric layer 123 until the second source-drain structure 122 is exposed. Subsequently, a metal material may be deposited on the second source-drain structure 122 until a second source-drain metal 125 is formed, see Fig.12 shown.

[0102] In some embodiments, forming the first isolation structure 28 on the second source-drain structure 122 includes: depositing an insulating material on the second source-drain metal 125 to form the first isolation structure 28 .

[0103] It is understood that after forming the second source-drain metal 125, an insulating material may be deposited on the second source-drain metal 125 and the second interlayer dielectric layer 123 to form a first isolation structure 28, see Fig.13 shown.

[0104] In some embodiments, the second source-drain metal 125 and the first isolation structure 28 may be positioned relative to the first sacrificial layer 211 to prevent the second source-drain metal 125 and the first isolation structure 28 from affecting exposure of the fourth portion 213 .

[0105] In some embodiments, after forming the first source-drain structure 112 in the first trench 27 by an epitaxial growth process, the method further includes: depositing a metal material on the first source-drain structure 112 to form a first source-drain metal 115 .

[0106] It is understandable that after forming the first source-drain structure 112, a dielectric layer material may be deposited on the first source-drain structure 112 to form a first interlayer dielectric layer 113 of the first transistor 11, see Fig.15 As shown. Subsequently, a front dielectric layer 127 may be deposited on the first interlayer dielectric layer 113, and holes may be opened on the front dielectric layer 127 and the first interlayer dielectric layer 113 until the first source-drain structure 112 is exposed. Subsequently, a metal material may be deposited on the first source-drain structure 112 until a first source-drain metal 115 is formed, see Fig.16 shown.

[0107] In some possible embodiments, the first sacrificial layer 211 and the first dummy gate structure 26 in the gate region are removed, and a front gate structure of the front vertically stacked transistor 101 is formed at the position where the first sacrificial layer 211 and the first dummy gate structure 26 are removed, including: removing the first dummy gate structure 26 to expose the third part 212, the first sacrificial layer 211 and the fourth part 213 in the gate region; removing the first sacrificial layer 211 in the gate region by an etching process to expose the first surface of the third part 212 and the second surface of the fourth part 213 to form a second gate structure 124 surrounding the third part 212; forming a first gate structure 114 surrounding the fourth part 213.

[0108] It can be understood that after forming the front source-drain structure of the front vertical stacked transistor 101, the front gate structure of the front vertical stacked transistor 101 can be formed by removing the first sacrificial layer 211 and the first dummy gate structure 26 in the gate region and filling the gate material. First, the first dummy gate structure 26 can be removed to expose the third portion 212, the first sacrificial layer 211 and the fourth portion 213 wrapped by the first dummy gate structure 26 in the gate region. Subsequently, an etching process can be used to remove the first sacrificial layer 211 in the exposed gate region to expose the surfaces of the third portion 212 and the fourth portion 213 that are connected to the first sacrificial layer 211, that is, to expose the first surface of the third portion 212 and the second surface of the fourth portion 213.

[0109] Here, the first surface of the third portion 212 is a surface of the third portion 212 away from the semiconductor substrate 20 , and the second surface of the fourth portion 213 is a surface of the fourth portion 213 close to the semiconductor substrate 20 .

[0110] It can be understood that after the first surface of the third portion 212 and the second surface of the fourth portion 213 are exposed, the third portion 212 and the fourth portion 213 in the gate region form a gap, and then, a gate material can be deposited in the gate region to form a second gate structure 124 surrounding the third portion 212 and a first gate structure 114 surrounding the fourth portion 213. The junction of the first gate structure 114 and the second gate structure 124 is located between the first surface and the second surface.

[0111] Here, the process of forming the first gate structure 114 surrounding the third portion 212 and the second gate structure 124 surrounding the fourth portion 213 can be selected according to actual needs, and the embodiment of the present application does not limit this.

[0112] Exemplarily, the process of forming the first gate structure 114 and the second gate structure 124 may include: depositing a gate dielectric material to form a gate dielectric layer of the first gate structure 114 and the second gate structure 124, and then depositing a second gate metal material to form the second gate structure 124; finally, depositing a first gate metal material to form the first gate structure 114.

[0113] In some embodiments, the first sacrificial layer 211 and the first dummy gate structure 26 in the gate region are removed, and a front gate structure of the front vertically stacked transistor 101 is formed at the position where the first sacrificial layer 211 and the first dummy gate structure 26 are removed, including: removing the first dummy gate structure 26 to expose the third part 212, the first sacrificial layer 211, the fourth part 213 and the second sacrificial layer 214 in the gate region; using an etching process to remove the first sacrificial layer 211 and the second sacrificial layer 214 in the gate region to form a second gate structure 124 surrounding the third part 212 with the first surface of the third part 212, the third surface of the third part 212 and the second surface of the fourth part 213; forming a first gate structure 114 surrounding the fourth part 213.

[0114] It is understood that after forming the front source-drain structure of the front vertical stacked transistor 101, the front gate structure of the front vertical stacked transistor 101 can be formed by removing the first sacrificial layer 211, the second sacrificial layer 214 and the first dummy gate structure 26 in the gate region and filling the gate material. First, the first dummy gate structure 26 can be removed to expose the third portion 212, the first sacrificial layer 211, the fourth portion 213 and the second sacrificial layer 214 in the gate region that are wrapped by the first dummy gate structure 26. Subsequently, an etching process can be used to remove the first sacrificial layer 211 and the second sacrificial layer 214 in the exposed gate region to expose the first surface and the third surface of the third portion 212, and the second surface of the fourth portion 213, see Fig.15 shown.

[0115] Among them, the first surface of the third part 212 is the surface of the third part 212 away from the semiconductor substrate 20, the third surface of the third part 212 is the surface of the third part 212 close to the semiconductor substrate 20, and the second surface of the fourth part 213 is the surface of the fourth part 213 close to the semiconductor substrate 20.

[0116] It can be understood that after removing the first dummy gate structure 26, the front and rear surfaces of the third portion 212 are completely exposed. After removing the first sacrificial layer 211 and the second sacrificial layer, the upper and lower surfaces of the third portion 212 are completely exposed. Then, the third portion 212 in the gate region is completely exposed, so that a second gate structure 124 surrounding the third portion 212 can be formed.

[0117] It can be understood that after removing the first dummy gate structure 26, the front and rear surfaces and the upper surface of the fourth portion 213 are completely exposed. At the same time, after removing the first sacrificial layer 211, the lower surface of the fourth portion 213 is completely exposed. Then, the fourth portion 213 in the gate region is completely exposed, so that the first gate structure 114 surrounding the fourth portion 213 can be formed.

[0118] It can be seen from one or more of the above-mentioned embodiments of forming the gate structure that when the transistor type is a full-surround gate field effect transistor, it is necessary to form a second sacrificial layer 214 in the first part 21 of the active structure; when the transistor type is a fin field effect transistor, it is not necessary to form the second sacrificial layer 214 in the first part 21 of the active structure, thereby reducing the preparation steps and improving the preparation efficiency.

[0119] In some embodiments, steps S205 to S206 may be performed while the first source-drain metal 115 is prepared. At this point, the first transistor 11 and the second transistor 12 are prepared in the stacked transistor 10, so the isolation structure (i.e., the first isolation structure 28) between the first transistor 11 and the second transistor 12 may be etched to form a first through hole; and then a metal material is deposited in the first through hole to form a first interconnection through hole structure 51 that can connect the source-drain metal (the first source-drain metal 115) of the first transistor 11 and the source-drain metal (the second source-drain metal 125) of the second transistor 12, as shown in FIG. Fig.17 shown.

[0120] It can be understood that the projection of the first through hole along the first direction falls within the projection of the first source-drain metal 115 and the second source-drain metal 125 along the first direction, so that the first interconnected through hole structure 51 formed according to the first through hole can achieve the connection between the first source-drain metal 115 and the second source-drain metal 125. For example, Fig.17 As shown, the projection of the first interconnection via structure 51 along the first direction falls within the projection of the first source-drain metal 115 and the second source-drain metal 125 along the first direction, and the first interconnection via structure 51 enables the first source-drain metal 115 and the second source-drain metal 125 to be vertically interconnected.

[0121] In some embodiments, the first through hole is formed by sequentially etching the first interlayer dielectric layer 113 and the first isolation structure 28 until the second source / drain metal 125 is exposed.

[0122] In some embodiments, forming the first source-drain metal 115 on the first source-drain structure 112 includes: depositing a dielectric material on the first source-drain structure 112 to form a first interlayer dielectric layer 123, and etching the first interlayer dielectric layer 123 until the first source-drain structure 112 is exposed to form a first source-drain metal groove. Then, depositing a metal material in the first through hole to form the first interconnection through hole structure 51 may include: depositing a metal material in the first source-drain metal groove and the first through hole to form the first source-drain metal 115 and the first interconnection through hole structure 51, respectively.

[0123] It can be understood that the first source-drain metal groove and the first through hole can be formed by an etching process, and then the metal material is deposited in the first source-drain metal groove and the first through hole by the same deposition process, so that the first source-drain metal 115 and the first interconnection through hole structure 51 can be formed simultaneously. In this way, the first source-drain metal 115 and the first interconnection through hole structure 51 are integrally formed, reducing the complexity of the preparation process.

[0124] It should be noted that the metal material forming the interconnection via structure may be the same as the material forming the source and drain metal.

[0125] In one embodiment, after forming the first gate structure 114 and the first source-drain metal 115, a front metal interconnect layer 1011 of the front vertical stacked transistor can be formed on the first gate structure 114 and the first source-drain metal 115 by using a standard back-end process of semiconductor manufacturing (such as deposition of dielectric between interconnect lines, formation of metal lines, formation of lead pads, etc.), see Fig.18 shown.

[0126] It should be noted that, for ease of explanation, the first source-drain structure mentioned in the embodiments of the present application is an abbreviation, specifically referring to the first source electrode structure and / or the first drain electrode structure. In addition, the second source-drain structure, the first source-drain metal, the second source-drain metal, etc. are similar to the first source-drain groove, where "source-drain" is an abbreviation for "source electrode and / or drain electrode".

[0127] In step S203, see Figure 19 to Figure 20 As shown, the semiconductor substrate 20 is flipped and removed.

[0128] It can be understood that after obtaining the front vertical stacked transistor 101, the front vertical stacked transistor 101 can be flipped over so that the completed front vertical stacked transistor 101 is located at the bottom, and the second part 22 of the active structure of the unfinished reverse vertical stacked transistor 102 can be located at the top, so as to facilitate the subsequent preparation of the reverse vertical stacked transistor 102.

[0129] In one embodiment, after the back-end process of the front vertical stacked transistor 101 is completed, the front vertical stacked transistor 101 can be bonded to the carrier wafer 33. For example, an insulating material (such as silicon oxide) can be deposited on the front vertical stacked transistor 101 to form an insulating layer 32, and the insulating layer 32 can be bonded to the carrier wafer 33. Then, the wafer is flipped. After the flip, the front vertical stacked transistor 101 is located at the bottom. Fig.19 shown.

[0130] In the embodiment of the present application, the bonded carrier wafer 33 can provide physical support for the flipped front vertical stacked transistor 101 after flipping over, effectively preventing the front vertical stacked transistor 101 from being broken by external force during the preparation of the reverse vertical stacked transistor 102.

[0131] In one embodiment, after flipping, the semiconductor substrate 20 may be removed by polishing or chemical mechanical planarization to expose the second portion 22 of the active structure.

[0132] It can be understood that in the process of removing the semiconductor substrate 20 by a process such as polishing or chemical mechanical planarization, the shallow trench isolation structure 25 can be exposed first. Fig. 20 As shown, the second portion 22 of the active structure is then exposed, see Fig.21 shown.

[0133] In step S204 , based on the second portion 22 , a reverse vertical stacked transistor 102 is formed.

[0134] It is understood that after removing the semiconductor substrate 20, the shallow trench isolation structure 25 can be thinned to form a second isolation structure 40, and the second isolation structure 40 can isolate the second transistor 12 and the third transistor 13 formed later. In addition, in the process of forming the second isolation structure 40, the sixth portion of the second portion 22 can be exposed first, such as Fig. 22 As shown, the second portion 22 of the active structure may then be exposed, as shown in FIG. Fig.23 shown.

[0135] It can be understood that after exposing the second part 22 of the active structure, the reverse vertical stacked transistor 102 can be formed by the same method as the front vertical stacked transistor 101, or by a method different from the method of forming the front vertical stacked transistor 101. The embodiment of the present application does not specifically limit this.

[0136] For example, Figure 23 to Figure 25 It is shown that the back side vertical stacked transistor 102 is formed by the same method as the front side vertical stacked transistor 101 .

[0137] It can be understood that the reverse vertical stacked transistor 102 includes a third transistor 13 and a fourth transistor 14 stacked along the first direction. The third transistor 13 includes a third dummy gate spacer 131, a third source-drain structure 132, a third interlayer dielectric layer 133, a third gate structure 134, and a third source-drain metal 135; the fourth transistor 14 includes a fourth dummy gate spacer 141, a fourth source-drain structure 142, a fourth interlayer dielectric layer 143, a fourth gate structure 144, and a fourth source-drain metal 145.

[0138] In some embodiments, the second portion 22 includes a third sacrificial layer, and the third sacrificial layer is located in the middle of the second portion 22; based on the second portion 22, a reverse vertical stacked transistor 102 is formed, including: based on the second portion 22, a plurality of second dummy gate structures 36 surrounding the second portion 22 and dummy gate sidewalls covering the second dummy gate structures 36 are formed, and the plurality of second dummy gate structures 36 are arranged along a second direction; using the second dummy gate structure 36 as a hard mask, etching the second portion 22 located in the source and drain region to form a second trench, wherein the region between the dummy gate sidewalls of two adjacent second dummy gate structures 36 is the source and drain region, and the region where the first dummy gate structure 26 and its dummy gate sidewall are located is the gate region; A reverse source-drain structure of the reverse vertical stacked transistor 102 is formed in the second trench, and the reverse source-drain structure includes a third source-drain structure 132 of the third transistor 13, a third isolation structure 34 and a fourth source-drain structure 142 of the fourth transistor 14; the third sacrificial layer and the second dummy gate structure 36 in the gate area are removed, and a reverse gate structure of the reverse vertical stacked transistor 102 is formed at the position where the third sacrificial layer and the second dummy gate structure 36 are removed, and the reverse gate structure includes a third gate structure 134 of the third transistor 13 and a fourth gate structure 144 of the fourth transistor 14, and the junction between the third gate structure 134 and the fourth gate structure 144 is located at the position where the third sacrificial layer is removed.

[0139] In some embodiments, the second portion 22 also includes: a fifth portion 222 and a sixth portion 223, the third sacrificial layer is located between the fifth portion 222 and the sixth portion 223, and the fifth portion 222 is closer to the semiconductor substrate than the sixth portion 223; using the second pseudo gate structure 36 as a hard mask, etching the second portion 22 located in the source and drain region to form a second trench, including: using the second pseudo gate structure 36 as a hard mask, etching the sixth portion 223 and the third sacrificial layer located in the source and drain region to expose the sixth portion 223 and the third sacrificial layer in the gate region and form a second initial trench; forming a third barrier layer on the side walls of the sixth portion 223 and the third sacrificial layer in the gate region; etching the fifth portion 222 located below the second initial trench to expose the fifth portion 222 in the gate region and form a second trench.

[0140] In some embodiments, the third sacrificial layer and the second dummy gate structure 36 in the gate region are removed, and a reverse gate structure of the reverse vertical stacked transistor 102 is formed at the position where the third sacrificial layer and the second dummy gate structure 36 are removed, including: removing the second dummy gate structure 36 to expose the fifth portion 222, the third sacrificial layer and the sixth portion 223 in the gate region; removing the third sacrificial layer in the gate region by an etching process to expose the fourth surface of the fifth portion 222 and the fifth surface of the sixth portion 223, wherein the fourth surface of the fifth portion 222 is the surface of the fifth portion 222 away from the semiconductor substrate, and the fifth surface of the sixth portion 223 is the surface of the sixth portion 223 close to the semiconductor substrate; forming a third gate structure 134 surrounding the fifth portion 222; forming a fourth gate structure 144 surrounding the sixth portion 223, wherein the junction between the third gate structure 134 and the fourth gate structure 144 is located between the fourth surface and the fifth surface.

[0141] In some embodiments, the second portion 22 also includes a fourth sacrificial layer, which is closer to the semiconductor substrate than the fifth portion 222; etching the fifth portion 222 located below the second initial trench to expose the fifth portion 222 in the gate area and form a second trench, and also includes: etching the fifth portion 222 and the fourth sacrificial layer located below the second initial trench to expose the fifth portion 222 and the fourth sacrificial layer in the gate area; forming a fourth barrier layer 35 on the side wall of the fourth sacrificial layer in the gate area, and forming a second trench.

[0142] In some embodiments, the third sacrificial layer and the second dummy gate structure 36 in the gate region are removed, and a reverse gate structure of the reverse vertical stacked transistor 102 is formed at the position where the third sacrificial layer and the second dummy gate structure 36 are removed, and the method further includes: removing the second dummy gate structure 36 to expose the fifth portion 222, the third sacrificial layer, the sixth portion 223 and the fourth sacrificial layer in the gate region; removing the third sacrificial layer and the fourth sacrificial layer in the gate region by an etching process to expose the fourth surface of the fifth portion 222, the sixth surface of the fifth portion 222 and the fifth surface of the sixth portion 223, wherein the fourth surface of the fifth portion 222 is the surface of the fifth portion 222 away from the semiconductor substrate, the sixth surface of the fifth portion 222 is the surface of the fifth portion 222 close to the semiconductor substrate, and the fifth surface of the sixth portion 223 is the surface of the sixth portion 223 close to the semiconductor substrate; forming a third gate structure 134 surrounding the fifth portion 222; and forming a fourth gate structure 144 surrounding the sixth portion 223.

[0143] In some embodiments, a reverse source-drain structure of a reverse vertically stacked transistor 102 is formed in the second trench, including: based on the fifth portion 222 in the gate region, a third source-drain structure is formed in the second trench by an epitaxial growth process, and the third source-drain structure is opposite to the fifth portion 222; the third barrier layer is removed to expose the sixth portion 223 in the gate region; a third isolation structure 34 is formed on the third source-drain structure, and the third isolation structure 34 is opposite to the third sacrificial layer; and above the third isolation structure 34, based on the exposed sixth portion 223 in the gate region, a fourth source-drain structure is formed in the second trench by an epitaxial growth process, and the fourth source-drain structure is opposite to the sixth portion 223.

[0144] In some embodiments, before forming a third barrier layer on the sixth portion 223 and the side wall of the third sacrificial layer in the gate region, the method also includes: using an etching process to laterally etch the side wall of the third sacrificial layer in the exposed gate region to form a second groove; filling the second groove with insulating material to form a third pseudo gate side wall 131 of the third transistor 13, the third pseudo gate side wall 131 completely covering the side wall of the third sacrificial layer in the gate region, and the pseudo gate side wall of the second pseudo gate structure 36 is used to form a fourth pseudo gate side wall 141 of the fourth transistor 14.

[0145] In some embodiments, after forming a third source-drain structure 132 in the second trench by an epitaxial growth process, the method further includes: depositing metal material on the third source-drain structure 132 to form a third source-drain metal 135; forming a third isolation structure 34 on the third source-drain structure 132, including: depositing insulating material on the third source-drain metal 135 to form a third isolation structure 34, the third source-drain metal 135 and the third isolation structure 34 being jointly opposite to the third sacrificial layer; after forming a fourth source-drain structure in the second trench by an epitaxial growth process, the method further includes: depositing metal material on the fourth source-drain structure 142 to form a fourth source-drain metal 145.

[0146] In some embodiments, after forming the fourth source-drain structure 142, a dielectric layer material may be deposited on the fourth source-drain structure 142 to form a fourth interlayer dielectric layer 143 of the fourth transistor 14. Subsequently, a reverse dielectric layer 147 may be deposited on the fourth interlayer dielectric layer 143, and holes may be opened in the reverse dielectric layer 147 and the fourth interlayer dielectric layer 143 until the fourth source-drain structure 142 is exposed. Subsequently, a metal material may be deposited on the fourth source-drain structure 142 until a fourth source-drain metal 145 is formed, see Fig.25 shown.

[0147] In some embodiments, steps S205 to S206 may be performed while the third source-drain metal 135 is prepared. At this point, the first transistor 11, the second transistor 12, and the third transistor 13 are prepared in the stacked transistor 10. Therefore, the isolation structure (i.e., the second isolation structure 40) between the second transistor 12 and the third transistor 13 may be etched to form a second through hole; and then a metal material is deposited in the second through hole to form a second interconnection through hole structure 52 that can connect the source-drain metal (the third source-drain metal 135) of the third transistor 13 and the source-drain metal (the second source-drain metal 125) of the second transistor 12, see Fig.24 shown.

[0148] It can be understood that the projection of the second through hole along the first direction falls within the projection of the third source-drain metal 135 and the second source-drain metal 125 along the first direction, so that the second interconnected through hole structure 52 formed according to the second through hole can connect the third source-drain metal 135 and the second source-drain metal 125.

[0149] In some embodiments, the second through hole is formed by sequentially etching the first interlayer dielectric layer 113 and the first isolation structure 28 until the second source / drain metal 125 is exposed.

[0150] In some embodiments, forming a third source-drain metal 135 on the third source-drain structure 132 includes: depositing a dielectric material on the third source-drain structure 132 to form a third interlayer dielectric layer 133, and etching the third interlayer dielectric layer 133 until the third source-drain structure 132 is exposed to form a third source-drain metal groove, then depositing a metal material in the second through hole to form a second interconnected through hole structure 52, which may include: depositing a metal material in the third source-drain metal groove and the second through hole to form the third source-drain metal 135 and the second interconnected through hole structure 52, respectively.

[0151] It can be understood that the third source-drain metal groove and the second through hole can be formed by an etching process, and then the third source-drain metal groove and the second through hole are deposited with a metal material by the same deposition process, so as to simultaneously form the third source-drain metal 135 and the second interconnection through hole structure 52. In this way, the third source-drain metal 135 and the second interconnection through hole structure 52 are integrally formed, reducing the complexity of the preparation process.

[0152] In some embodiments, steps S205 to S206 may be performed while the fourth source-drain metal 145 is prepared. At this point, the first transistor 11, the second transistor 12, the third transistor 13, and the fourth transistor 14 are prepared in the stacked transistor 10. Therefore, the isolation structure (i.e., the third isolation structure 34) between the fourth transistor 14 and the third transistor 13 may be etched to form a third through hole; and then a metal material may be deposited in the third through hole to form a third interconnection through hole structure 53 that can connect the source-drain metal (third source-drain metal 135) of the third transistor 13 and the source-drain metal (fourth source-drain metal 145) of the fourth transistor 14, see Fig.25 shown.

[0153] It can be understood that the projection of the third through hole along the first direction falls within the projection of the third source-drain metal 135 and the fourth source-drain metal 145 along the first direction, so that the third interconnected through hole structure 53 formed according to the third through hole can connect the third source-drain metal 135 and the fourth source-drain metal 145.

[0154] In some embodiments, the third through hole is formed by sequentially etching the fourth interlayer dielectric layer 143 and the third isolation structure 34 until the third source-drain metal 135 is exposed.

[0155] In some embodiments, forming a fourth source-drain metal 145 on the fourth source-drain structure 142 includes: depositing a dielectric material on the fourth source-drain structure 142 to form a fourth interlayer dielectric layer 143, and etching the fourth interlayer dielectric layer 143 until the fourth source-drain structure 142 is exposed to form a fourth source-drain metal groove. Then, depositing a metal material in the third through hole to form a third interconnected through hole structure 53 may include: depositing a metal material in the fourth source-drain metal groove and the third through hole to form a fourth source-drain metal 145 and a third interconnected through hole structure 53, respectively.

[0156] It can be understood that the fourth source-drain metal groove and the third through hole can be formed by an etching process, and then the fourth source-drain metal groove and the third through hole are deposited with a metal material by the same deposition process, so as to simultaneously form the fourth source-drain metal 145 and the third interconnection through hole structure 53. In this way, the fourth source-drain metal 145 and the third interconnection through hole structure 53 are integrally formed, reducing the complexity of the preparation process.

[0157] In some embodiments, after forming the fourth gate structure 144 and the fourth source-drain metal 145, a standard back-end process of semiconductor preparation (such as deposition of dielectric between interconnect lines, formation of metal lines, formation of lead pads, etc.) can be used on the fourth source-drain metal 145 and the fourth gate structure 144 to form a reverse metal interconnect layer 1021 of the reverse vertically stacked transistor 102.

[0158] It should be noted that the process of forming the reverse vertical stacked transistor 102 may refer to the description of one or more of the processes of forming the forward vertical stacked transistor 101 , and for the sake of brevity of the specification, it will not be repeated here.

[0159] At this point, the preparation of the stacked transistor 10 is completed.

[0160] In an embodiment of the present application, by forming an active structure with a certain depth on a semiconductor substrate, it is possible to realize that the active areas of a plurality of transistors arranged along a first direction of vertically stacked transistors are self-aligned. Subsequently, a first transistor and a second transistor vertically stacked along a first direction and having different polarities can be prepared based on the first part of the active structure, and the semiconductor substrate is etched after flipping, so that a third transistor and a fourth transistor vertically stacked along a first direction and having different polarities can be prepared based on the second part of the active structure. It can be seen that by forming a pair of stacked transistors on the front side of the wafer and another pair of stacked transistors on the back side of the wafer, it is possible to prepare more transistors using the front and back sides of the wafer, thereby increasing the integration density of the transistors and further improving the integration performance of the transistors. Finally, by etching an isolation structure between any two transistors among the first transistor, the second transistor, the third transistor and the fourth transistor, an interconnected through-hole structure is formed, so that the isolation structure between any two transistors is penetrated, thereby connecting any two transistors in the first direction through the interconnected through-hole structure and the source-drain metal of any two transistors, which helps to realize large-scale integration of stacked transistors.

[0161] Next, the interconnection via structure in the stacked transistor 10 is further described. Fig.26 FIG. 1 is a schematic diagram of a stacked transistor structure according to an embodiment of the present application. It can be understood that: Fig.26 Shown is the Figure 1 A fourth interconnection via structure 54 , a fifth interconnection via structure 55 , and a sixth interconnection via structure 56 may also be formed in the stacked transistor 10 .

[0162] In some possible implementations, steps S205 to S206 may be performed while preparing the third source-drain metal 135. At this point, the stacked transistor 10 is formed with the first transistor 11, the second transistor 12, and the third transistor 13. Fig.26As shown in (a), the isolation structure between the second transistor 12 and the third transistor 13 (i.e., the second isolation structure 40) and the isolation structure between the second transistor 12 and the first transistor 11 (i.e., the first isolation structure 28) can be etched to form a fourth through hole; and then a metal material is deposited in the fourth through hole to form a fourth interconnection through hole structure 54 capable of connecting the source-drain metal (the third source-drain metal 135) of the third transistor 13 and the source-drain metal (the first source-drain metal 115) of the first transistor 11.

[0163] It can be understood that the projection of the fourth through hole along the first direction falls within the projection of the first source-drain metal 115 and the third source-drain metal 135 along the first direction, so that the fourth interconnected through hole structure 54 formed according to the fourth through hole can realize the connection between the third source-drain metal 135 and the first source-drain metal 115. It can be understood that in order to form the fourth through hole, when preparing the second source-drain metal 125, the width of the projection of the second source-drain metal 125 along the first direction should be controlled, so that the projection of the fourth through hole along the first direction falls within the projection of the third source-drain metal 135 and the first source-drain metal 115 along the first direction, but does not fall within the projection of the second source-drain metal 125 along the first direction. In this way, it can be ensured that the first source-drain metal 115 can be vertically interconnected with the third source-drain metal 135.

[0164] In some embodiments, the fourth through hole is formed by sequentially etching the third interlayer dielectric layer 133 , the second isolation structure 40 , the second interlayer dielectric layer 123 , the first isolation structure 28 , and the first interlayer dielectric layer 113 until the first source-drain metal 115 is exposed.

[0165] In some embodiments, forming a third source-drain metal 135 on the third source-drain structure 132 includes: depositing a dielectric material on the third source-drain structure 132 to form a third interlayer dielectric layer 133, and etching the third interlayer dielectric layer 133 until the third source-drain structure 132 is exposed to form a third source-drain metal groove, then depositing a metal material in the fourth through hole to form a fourth interconnected through hole structure 54, which may include: depositing a metal material in the third source-drain metal groove and the fourth through hole to form a third source-drain metal 135 and a fourth interconnected through hole structure 54, respectively.

[0166] It can be understood that the third source-drain metal groove and the fourth through hole can be formed by an etching process, and then the third source-drain metal groove and the fourth through hole are deposited with a metal material by the same deposition process, so as to simultaneously form the third source-drain metal 135 and the fourth interconnection through hole structure 54. In this way, the third source-drain metal 135 and the fourth interconnection through hole structure 54 are integrally formed, reducing the complexity of the preparation process.

[0167] In some possible implementations, steps S205 to S206 may be performed while the fourth source-drain metal 145 is prepared. At this point, the stacked transistor 10 is formed with the first transistor 11, the second transistor 12, the third transistor 13, and the fourth transistor 14. Fig.26 As shown in (b), the isolation structure between the fourth transistor 14 and the third transistor 13 (i.e., the third isolation structure 34) and the isolation structure between the third transistor 13 and the second transistor 12 (i.e., the second isolation structure 40) can be etched to form a fifth through hole; and then a metal material is deposited in the fifth through hole to form a fifth interconnection through hole structure 55 capable of connecting the source-drain metal (the second source-drain metal 125) of the second transistor 12 and the source-drain metal (the fourth source-drain metal 145) of the fourth transistor 14.

[0168] It can be understood that the projection of the fifth through hole along the first direction falls within the projection of the second source-drain metal 125 and the fourth source-drain metal 145 along the first direction, so that the fifth interconnected through hole structure 55 formed according to the fifth through hole can realize the connection between the second source-drain metal 125 and the fourth source-drain metal 145. It can be understood that in order to form the fifth through hole, when preparing the third source-drain metal 135, the width of the projection of the third source-drain metal 135 along the first direction should be controlled, so that the projection of the fifth through hole along the first direction falls within the projection of the second source-drain metal 125 and the fourth source-drain metal 145 along the first direction, but does not fall within the projection of the third source-drain metal 135 along the first direction. In this way, the second source-drain metal 125 and the fourth source-drain metal 145 can be vertically interconnected.

[0169] In some embodiments, the fifth through hole is formed by sequentially etching the fourth interlayer dielectric layer 143 , the third isolation structure 34 , the third interlayer dielectric layer 133 , the second isolation structure 40 , and the second interlayer dielectric layer 123 until the second source-drain metal 125 is exposed.

[0170] In some embodiments, forming a fourth source-drain metal 145 on the fourth source-drain structure 142 includes: depositing a dielectric material on the fourth source-drain structure 142 to form a fourth interlayer dielectric layer 143, and etching the fourth interlayer dielectric layer 143 until the fourth source-drain structure 142 is exposed to form a fourth source-drain metal groove. Then, depositing a metal material in the fifth through hole to form a fifth interconnection through hole structure 55 may include: depositing a metal material in the fourth source-drain metal groove and the fifth through hole to form the fourth source-drain metal 145 and the fifth interconnection through hole structure 55, respectively.

[0171] It can be understood that the fourth source-drain metal groove and the fifth through hole can be formed by an etching process, and then the metal material is deposited in the fourth source-drain metal groove and the fifth through hole by the same deposition process, so as to simultaneously form the fourth source-drain metal 145 and the fifth interconnection through hole structure 55. In this way, the fourth source-drain metal 145 and the fifth interconnection through hole structure 55 are integrally formed, reducing the complexity of the preparation process.

[0172] In some possible implementations, step S205 to step S206 may be performed while preparing the fourth source-drain metal 145. At this time, the stacked transistor 10 is formed with the first transistor 11, the second transistor 12, the third transistor 13 and the fourth transistor 14. Therefore, Fig.26 As shown in (c), the isolation structure between the fourth transistor 14 and the third transistor 13 (i.e., the third isolation structure 34), the isolation structure between the third transistor 13 and the second transistor 12 (i.e., the second isolation structure 40), and the isolation structure between the second transistor 12 and the first transistor 11 (i.e., the first isolation structure 28) can be etched to form a sixth through hole; and then a metal material is deposited in the sixth through hole to form a sixth interconnection through hole structure 56 capable of connecting the source-drain metal (the first source-drain metal 115) of the first transistor 11 and the source-drain metal (the fourth source-drain metal 145) of the fourth transistor 14.

[0173] It can be understood that the projection of the sixth through hole along the first direction falls within the projection of the first source-drain metal 115 and the fourth source-drain metal 145 along the first direction, so that the sixth interconnection through hole structure 56 formed according to the sixth through hole can realize the connection between the first source-drain metal 115 and the fourth source-drain metal 145. It can be understood that in order to form the sixth through hole, when preparing and forming the third source-drain metal 135 and the second source-drain metal 125, the width of the projection of the third source-drain metal 135 and the second source-drain metal 125 along the first direction should be controlled, so that the projection of the sixth through hole along the first direction falls within the projection of the first source-drain metal 115 and the fourth source-drain metal 145 along the first direction, but does not fall within the projection of the third source-drain metal 135 and the second source-drain metal 125 along the first direction. In this way, the first source-drain metal 115 and the fourth source-drain metal 145 can be guaranteed to be vertically interconnected.

[0174] In some embodiments, a sixth through hole is formed by sequentially etching the fourth interlayer dielectric layer 143, the third isolation structure 34, the third interlayer dielectric layer 133, the second isolation structure 40, the second interlayer dielectric layer 123, the first isolation structure 28 and the first interlayer dielectric layer 113 until the first source-drain metal 115 is exposed.

[0175] In some embodiments, forming a fourth source-drain metal 145 on the fourth source-drain structure 142 includes: depositing a dielectric material on the fourth source-drain structure 142 to form a fourth interlayer dielectric layer 143, and etching the fourth interlayer dielectric layer 143 until the fourth source-drain structure 142 is exposed to form a fourth source-drain metal groove. Then, depositing a metal material in the sixth through hole to form a sixth interconnection through hole structure 56 may include: depositing a metal material in the fourth source-drain metal groove and the sixth through hole to form a fourth source-drain metal 145 and a sixth interconnection through hole structure 56, respectively.

[0176] It can be understood that the fourth source-drain metal groove and the sixth through hole can be formed by an etching process, and then the metal material is deposited in the fourth source-drain metal groove and the sixth through hole by the same deposition process, so as to simultaneously form the fourth source-drain metal 145 and the sixth interconnection through hole structure 56. In this way, the fourth source-drain metal 145 and the sixth interconnection through hole structure 56 are integrally formed, reducing the complexity of the preparation process.

[0177] Similarly, see Fig.26 As shown in (d) to (f) in the figure, the stacked transistor 10 further includes: a first interconnection via structure 51, a second interconnection via structure 52, and a third interconnection via structure 53. The formation process of the first interconnection via structure 51, the second interconnection via structure 52, and the third interconnection via structure 53 can refer to the description in one or more of the above embodiments, and will not be repeated here for the sake of brevity of the specification.

[0178] It should be noted that the stacked transistor 10 may include at least one of the first interconnected via structure 51, the second interconnected via structure 52, the third interconnected via structure 53, the fourth interconnected via structure 54, the fifth interconnected via structure 55, and the sixth interconnected via structure 56. When the stacked transistor 10 includes multiple interconnected via structures of the first interconnected via structure 51, the second interconnected via structure 52, the third interconnected via structure 53, the fourth interconnected via structure 54, the fifth interconnected via structure 55, and the sixth interconnected via structure 56, the multiple interconnected via structures may be arranged at intervals in the second direction to avoid mutual influence. In some embodiments, one or more interconnected via structures of the multiple interconnected via structures may be located on the first side of the source-drain structure (e.g., the first source-drain structure 112) in the stacked transistor 10, and the interconnected via structures of the multiple interconnected via structures other than the one or more interconnected via structures may be located on the second side of the first source-drain structure 112. The first side and the second side may be opposite sides of the first source-drain structure 112 in the second direction.

[0179] In some embodiments, in order to avoid the existence of too many interconnection via structures in the stacked transistor 10, thereby increasing the volume of the stacked transistor 10 and reducing the integration level of the stacked transistor 10, the interconnection via structures in the stacked transistor 10 can be reasonably planned to meet different logic circuits. On this basis, the stacked transistor 10 may include: one of the first group of interconnection via structures, the second group of interconnection via structures, the third group of interconnection via structures, the fourth group of interconnection via structures, the fifth group of interconnection via structures, the sixth group of interconnection via structures, the seventh group of interconnection via structures and the eighth group of interconnection via structures. Among them, the first group of interconnected through-hole structures includes: a first interconnected through-hole structure 51 and a second interconnected through-hole structure 52; the second group of interconnected through-hole structures includes: a first interconnected through-hole structure 51 and a third interconnected through-hole structure 53; the third group of interconnected through-hole structures includes: a first interconnected through-hole structure 51, a second interconnected through-hole structure 52 and a third interconnected through-hole structure 53; the fourth group of interconnected through-hole structures includes: a first interconnected through-hole structure 51 and a fifth interconnected through-hole structure 55; the fifth group of interconnected through-hole structures includes: a second interconnected through-hole structure 52 and a third interconnected through-hole structure 53; the sixth group of interconnected through-hole structures includes: a second interconnected through-hole structure 52 and a sixth interconnected through-hole structure 56; the seventh group of interconnected through-hole structures includes: a third interconnected through-hole structure 53 and a fourth interconnected through-hole structure 54; the eighth group of interconnected through-hole structures includes: a fourth interconnected through-hole structure 54 and a fifth interconnected through-hole structure 55.

[0180] For example, Fig. 27 FIG. 1 is a schematic diagram of a stacked transistor structure according to an embodiment of the present application. Fig. 27 As shown in (a) in FIG. 1 , the stacked transistor 10 may include: a first group of interconnected via structures, the first group of interconnected via structures consisting of a first interconnected via structure 51 and a second interconnected via structure 52. The first interconnected via structure 51 connects the first source-drain metal 115 and the second source-drain metal 125, respectively, and the second interconnected via structure 52 connects the second source-drain metal 125 and the third source-drain metal 135. It can be seen that the first source-drain metal 115, the second source-drain metal 125 and the third source-drain metal 135 can be connected through the first group of interconnected via structures.

[0181] See also Fig. 27 As shown in (b) in FIG. 1 , the stacked transistor 10 may include: a second group of interconnected via structures, the second group of interconnected via structures being composed of a first interconnected via structure 51 and a third interconnected via structure 53. The first interconnected via structure 51 respectively connects the first source-drain metal 115 and the second source-drain metal 125, and the third interconnected via structure 53 connects the third source-drain metal 135 and the fourth source-drain metal 145. It can be seen that the first source-drain metal 115 and the second source-drain metal 125 can be connected, and the third source-drain metal 135 and the fourth source-drain metal 145 can be connected through the second group of interconnected via structures.

[0182] See also Fig. 27 As shown in (c), the stacked transistor 10 may include: a third group of interconnected via structures, the third group of interconnected via structures consisting of a first interconnected via structure 51, a second interconnected via structure 52, and a third interconnected via structure 53. The first interconnected via structure 51 connects the first source-drain metal 115 and the second source-drain metal 125, respectively, the second interconnected via structure 52 connects the second source-drain metal 125 and the third source-drain metal 135, and the third interconnected via structure 53 connects the third source-drain metal 135 and the fourth source-drain metal 145. It can be seen that the first source-drain metal 115, the second source-drain metal 125, the third source-drain metal 135, and the fourth source-drain metal 145 can be connected through the third group of interconnected via structures.

[0183] See also Fig. 27 As shown in (d) in FIG. 1 , the stacked transistor 10 may include: a fourth group of interconnected via structures, the fourth group of interconnected via structures being composed of a first interconnected via structure 51 and a fifth interconnected via structure 55. The first interconnected via structure 51 respectively connects the first source-drain metal 115 and the second source-drain metal 125, and the fifth interconnected via structure 55 connects the second source-drain metal 125 and the fourth source-drain metal 145. It can be seen that the first source-drain metal 115, the second source-drain metal 125 and the fourth source-drain metal 145 can be connected through the fourth group of interconnected via structures.

[0184] See also Fig. 27 As shown in (e), the stacked transistor 10 may include: a fifth group of interconnected via structures, which are composed of a second interconnected via structure 52 and a third interconnected via structure 53. The second interconnected via structure 52 connects the second source-drain metal 125 and the third source-drain metal 135, and the third interconnected via structure 53 connects the third source-drain metal 135 and the fourth source-drain metal 145. It can be seen that the second source-drain metal 125, the third source-drain metal 135 and the fourth source-drain metal 145 can be connected through the fifth group of interconnected via structures.

[0185] See also Fig. 27 As shown in (f), the stacked transistor 10 may include: a sixth group of interconnected via structures, which are composed of a second interconnected via structure 52 and a sixth interconnected via structure 56. The second interconnected via structure 52 connects the second source-drain metal 125 and the third source-drain metal 135, and the sixth interconnected via structure 56 connects the first source-drain metal 115 and the fourth source-drain metal 145. It can be seen that the first source-drain metal 115 and the fourth source-drain metal 145 can be connected, and the second source-drain metal 125 and the third source-drain metal 135 can be connected through the sixth group of interconnected via structures.

[0186] See also Fig. 27 As shown in (g), the stacked transistor 10 may include: a seventh group of interconnected via structures, the seventh group of interconnected via structures consisting of a third interconnected via structure 53 and a fourth interconnected via structure 54. The third interconnected via structure 53 connects the third source-drain metal 135 and the fourth source-drain metal 145, and the fourth interconnected via structure 54 connects the first source-drain metal 115 and the third source-drain metal 135. It can be seen that the first source-drain metal 115, the third source-drain metal 135 and the fourth source-drain metal 145 can be connected through the seventh group of interconnected via structures.

[0187] See also Fig. 27 As shown in (h), the stacked transistor 10 may include: an eighth group of interconnected via structures, the eighth group of interconnected via structures consisting of a fourth interconnected via structure 54 and a fifth interconnected via structure 55. The fourth interconnected via structure 54 connects the first source-drain metal 115 and the third source-drain metal 135, and the fifth interconnected via structure 55 connects the second source-drain metal 125 and the fourth source-drain metal 145. It can be seen that the first source-drain metal 115 and the third source-drain metal 135 can be connected, and the second source-drain metal 125 and the fourth source-drain metal 145 can be connected through the seventh group of interconnected via structures.

[0188] It can be understood that the above-mentioned first interconnected through-hole structure 51, the second interconnected through-hole structure 52, the third interconnected through-hole structure 53, the fourth interconnected through-hole structure 54, the fifth interconnected through-hole structure 55 and the sixth interconnected through-hole structure 56 can be prepared by the first through-hole, the second through-hole, the third through-hole, the fourth through-hole, the fifth through-hole and the sixth through-hole, respectively. The preparation process of obtaining the first through-hole, the second through-hole, the third through-hole, the fourth through-hole, the fifth through-hole and the sixth through-hole can refer to the description in one or more of the above-mentioned embodiments, and for the sake of brevity of the specification, it will not be repeated here.

[0189] In the embodiments of the present application, while retaining the advantages of flip-chip complementary stacked transistors (such as greatly improving the integration density of transistors, taking into account the consistency of the active areas of the front and back transistors, defect density and alignment issues), the mid-channel interconnection of the flip-chip complementary stacked transistors is achieved, creating conditions for realizing complex logic design and large-scale integration based on flip-chip complementary stacked transistors.

[0190] In a second aspect, a stacked transistor 10 is provided in an embodiment of the present disclosure. The stacked transistor 10 can be used Figures 3 to 25 The method of one or more corresponding embodiments is prepared. Fig.25As shown, the stacked transistor 10 includes: a front vertically stacked transistor 101, including: a first transistor 11 and a second transistor 12, the first transistor 11 and the second transistor 12 have different polarities, the first transistor 11 and the second transistor 12 are self-aligned in a first direction, and the first direction is a direction perpendicular to the semiconductor substrate.

[0191] The reverse vertical stacked transistor 102 includes: a third transistor 13 and a fourth transistor 14, the third transistor 13 and the fourth transistor 14 have different polarities, and the third transistor 13 and the fourth transistor 14 are self-aligned in the first direction; wherein the front vertical stacked transistor 101 and the reverse vertical stacked transistor 102 are arranged opposite to each other, and the front vertical stacked transistor 101 and the reverse vertical stacked transistor 102 are self-aligned in the first direction. An isolation structure exists between any two adjacent transistors among the first transistor 11, the second transistor 12, the third transistor 13 and the fourth transistor 14.

[0192] Exemplarily, when the first transistor 11, the second transistor 12, the third transistor 13 and the fourth transistor 14 are arranged in the first direction as follows Fig.25 As shown, a first isolation structure 28 exists between the first transistor 11 and the second transistor 12 , a second isolation structure 40 exists between the second transistor 12 and the third transistor 13 , and a third isolation structure 34 exists between the third transistor 13 and the fourth transistor 14 .

[0193] The stacked transistor 10 further includes an interconnection via structure, wherein the interconnection via structure is used to connect source and drain metals of any two transistors among the first transistor 11 , the second transistor 12 , the third transistor 13 and the fourth transistor 14 by penetrating the isolation structure.

[0194] For example, see Fig.25 As shown, the first interconnection via structure 51 connects the first source-drain metal 115 and the second source-drain metal 125. The second interconnection via structure 52 connects the second source-drain metal 125 and the third source-drain metal 135. The third interconnection via structure 53 connects the third source-drain metal 135 and the fourth source-drain metal 145.

[0195] In some embodiments, the first transistor 11, the second transistor 12, the third transistor 13 and the fourth transistor 14 are arranged in sequence along the first direction; the interconnection through-hole structure includes: at least one of the first interconnection through-hole structure 51, the second interconnection through-hole structure 52, the third interconnection through-hole structure 53, the fourth interconnection through-hole structure 54, the fifth interconnection through-hole structure 55 and the sixth interconnection through-hole structure 56; wherein the first interconnection through-hole structure 51 is used to connect the first source-drain metal 115 and the second source-drain metal 125; the second interconnection through-hole structure 52 is used to connect the second source-drain metal 125 and the third source-drain metal 135; the third interconnection through-hole structure 53 is used to connect the third source-drain metal 135 and the fourth source-drain metal 145; the fourth interconnection through-hole structure 54 is used to connect the first source-drain metal and the third source-drain metal 135; the fifth interconnection through-hole structure 55 is used to connect the second source-drain metal 125 and the fourth source-drain metal 145; the sixth interconnection through-hole structure 56 is used to connect the first source-drain metal and the fourth source-drain metal 145.

[0196] It can be understood that the specific structures of the first interconnection through-hole structure 51, the second interconnection through-hole structure 52, the third interconnection through-hole structure 53, the fourth interconnection through-hole structure 54, the fifth interconnection through-hole structure 55 and the sixth interconnection through-hole structure 56 can be seen in Figure 25 to Figure 26 For the sake of brevity of the specification, the description of one or more embodiments shown will not be repeated here.

[0197] In some embodiments, the first transistor, the second transistor, the third transistor and the fourth transistor are arranged sequentially along the first direction; the stacked transistor 10 includes: one of the first group of interconnected through-hole structures, the second group of interconnected through-hole structures, the third group of interconnected through-hole structures, the fourth group of interconnected through-hole structures, the fifth group of interconnected through-hole structures, the sixth group of interconnected through-hole structures, the seventh group of interconnected through-hole structures and the eighth group of interconnected through-hole structures. Among them, the first group of interconnected through-hole structures includes: a first interconnected through-hole structure 51 and a second interconnected through-hole structure 52; the second group of interconnected through-hole structures includes: a first interconnected through-hole structure 51 and a third interconnected through-hole structure 53; the third group of interconnected through-hole structures includes: a first interconnected through-hole structure 51, a second interconnected through-hole structure 52 and a third interconnected through-hole structure 53; the fourth group of interconnected through-hole structures includes: a first interconnected through-hole structure 51 and a fifth interconnected through-hole structure 55; the fifth group of interconnected through-hole structures includes: a second interconnected through-hole structure 52 and a third interconnected through-hole structure 53; the sixth group of interconnected through-hole structures includes: a second interconnected through-hole structure 52 and a sixth interconnected through-hole structure 56; the seventh group of interconnected through-hole structures includes: a third interconnected through-hole structure 53 and a fourth interconnected through-hole structure 54; the eighth group of interconnected through-hole structures includes: a fourth interconnected through-hole structure 54 and a fifth interconnected through-hole structure 55.

[0198] Among them, the first interconnected through-hole structure 51 is used to connect the first source-drain metal 115 and the second source-drain metal 125; the second interconnected through-hole structure 52 is used to connect the second source-drain metal 125 and the third source-drain metal 135; the third interconnected through-hole structure 53 is used to connect the third source-drain metal 135 and the fourth source-drain metal 145; the fourth interconnected through-hole structure 54 is used to connect the first source-drain metal and the third source-drain metal 135; the fifth interconnected through-hole structure 55 is used to connect the second source-drain metal 125 and the fourth source-drain metal 145; the sixth interconnected through-hole structure 56 is used to connect the first source-drain metal and the fourth source-drain metal 145.

[0199] It can be understood that the specific structures of the first group of interconnected through-hole structures, the second group of interconnected through-hole structures, the third group of interconnected through-hole structures, the fourth group of interconnected through-hole structures, the fifth group of interconnected through-hole structures, the sixth group of interconnected through-hole structures, the seventh group of interconnected through-hole structures and the eighth group of interconnected through-hole structures can be found in Fig. 27 For the sake of brevity of the specification, the description of one or more embodiments shown will not be repeated here.

[0200] It is understandable that the stacked transistor in the embodiment of the present application can be used Figures 3 to 25 The corresponding one or more embodiments are prepared by the preparation method. The embodiment of the present application forms a front vertical stacked transistor on the front side of the wafer, the front vertical stacked transistor includes two stacked transistors, and forms a back vertical stacked transistor on the back side of the wafer, the back vertical stacked transistor includes two stacked transistors, so that the integration performance of the stacked transistor is further enhanced.

[0201] Furthermore, by realizing the mid-way interconnection of flip-chip complementary stacked transistors, on the basis of independent signal and power supply networks for the front and back transistors, there is greater flexibility and feasibility in circuit design, and great potential in the direction of collaborative optimization of process design. At the same time, the mid-way interconnection solution is compatible with existing mainstream device architectures and manufacturing processes (photolithography, high selectivity etching, etc.), and can realize the front and back stacking and mid-way interconnection of planar transistors, FinFETs, GAA Nanosheets, and even vertical transistors (VTFETs) and CFETs without the need for additional special process development. It is highly flexible and has strong extensibility from the perspective of semiconductor process node iteration, which is of great significance for the further extension of Moore's Law and has important industrial value and practical prospects.

[0202] In a third aspect, an embodiment of the present application provides a semiconductor device, including: a stacked transistor as in the above embodiment. The specific definition of the stacked transistor can be at least referred to in the above Figure 25 to Figure 27 The stacked transistors shown are not described in detail here.

[0203] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising: a circuit board and a semiconductor device as in the above embodiment, wherein the semiconductor device is disposed on the circuit board. The semiconductor device comprises the above stacked transistor. The specific definition of the stacked transistor can be at least referred to in the above Figure 25 to Figure 27 The structure shown will not be described in detail here.

[0204] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms is not necessarily for the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine different embodiments or examples described in the present application and the features of different embodiments or examples without contradiction.

[0205] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a stacked transistor, characterized in that: The method comprises: forming an active structure on a semiconductor substrate, the active structure comprising a first portion and a second portion; Based on the first part, a first transistor and a second transistor stacked along a first direction are formed, wherein the first transistor and the second transistor have opposite polarities; and the first direction is a direction perpendicular to the semiconductor substrate; Flipping and removing the semiconductor substrate; Based on the second part, a third transistor and a fourth transistor stacked along the first direction are formed, wherein the third transistor and the fourth transistor have opposite polarities; and an isolation structure exists between any two adjacent transistors among the first transistor, the second transistor, the third transistor and the fourth transistor; Etching an isolation structure between any two transistors among the first transistor, the second transistor, the third transistor and the fourth transistor to form a through hole, wherein a projection of the through hole along the first direction falls within a projection of source and drain metals of the any two transistors along the first direction; A metal material is deposited in the through hole to form an interconnected through hole structure, wherein the interconnected through hole structure is used to connect the source and drain metals in any two transistors.

2. The preparation method according to claim 1, characterized in that: The method of forming a first transistor and a second transistor stacked along a first direction based on the first portion includes: Depositing an insulating material on the semiconductor substrate to form an initial isolation structure, wherein the initial isolation structure surrounds the second portion and the first portion is exposed outside the initial isolation structure; Based on the first part, forming a second source-drain structure, a second interlayer dielectric layer and a second gate structure on the initial isolation structure; wherein the second interlayer dielectric layer wraps the second source-drain structure; forming a second source-drain metal on the second source-drain structure; Depositing an insulating material on the second source-drain metal to form a first isolation structure; On the first isolation structure, based on the first portion, a first source-drain structure, a first interlayer dielectric layer and a first gate structure are formed; wherein the first interlayer dielectric layer wraps the first source-drain structure; A first source-drain metal is formed on the first source-drain structure.

3. The preparation method according to claim 2, characterized in that: The method of forming a third transistor and a fourth transistor stacked along the first direction based on the second portion includes: thinning the initial isolation structure to form a second isolation structure between the second transistor and the third transistor; Based on the second part, a third source-drain structure, a third interlayer dielectric layer and a third gate structure are formed on the second isolation structure; wherein the third interlayer dielectric layer wraps the third source-drain structure; forming a third source-drain metal on the third source-drain structure; Depositing an insulating material on the third source-drain metal to form a third isolation structure; On the third isolation structure, based on the first part, a fourth source-drain structure, a fourth interlayer dielectric layer and a fourth gate structure are formed; wherein the fourth interlayer dielectric layer wraps the fourth source-drain structure; forming a fourth source-drain metal on the fourth source-drain structure; The first isolation structure, the second isolation structure and the third isolation structure are included in the isolation structure.

4. The preparation method according to claim 3, characterized in that: The etching of the isolation structure between any two transistors among the first transistor, the second transistor, the third transistor and the fourth transistor to form a through hole comprises at least one of the following: Sequentially etching the first interlayer dielectric layer and the first isolation structure until the second source and drain metal is exposed to form a first through hole; Sequentially etching the third interlayer dielectric layer and the second isolation structure until the second source and drain metal is exposed to form a second through hole; Sequentially etching the fourth interlayer dielectric layer and the third isolation structure until the third source and drain metal is exposed to form a third through hole; Sequentially etching the third interlayer dielectric layer, the second isolation structure, the second interlayer dielectric layer, the first isolation structure and the first interlayer dielectric layer until the first source and drain metal is exposed to form a fourth through hole; Sequentially etching the fourth interlayer dielectric layer, the third isolation structure, the third interlayer dielectric layer, the second isolation structure and the second interlayer dielectric layer until the second source and drain metal is exposed to form a fifth through hole; The fourth interlayer dielectric layer, the third isolation structure, the third interlayer dielectric layer, the second isolation structure, the second interlayer dielectric layer, the first isolation structure and the first interlayer dielectric layer are sequentially etched until the first source and drain metal is exposed to form a sixth through hole.

5. The preparation method according to claim 3, characterized in that: The etching of the isolation structure between any two transistors among the first transistor, the second transistor, the third transistor and the fourth transistor to form a through hole comprises any one of the following: Sequentially etching the first interlayer dielectric layer and the first isolation structure until the second source-drain metal is exposed to form a first through hole, and sequentially etching the third interlayer dielectric layer and the second isolation structure until the second source-drain metal is exposed to form a second through hole; Sequentially etching the first interlayer dielectric layer and the first isolation structure until the second source-drain metal is exposed to form a first through hole, and sequentially etching the fourth interlayer dielectric layer and the third isolation structure until the third source-drain metal is exposed to form a third through hole; The first interlayer dielectric layer and the first isolation structure are sequentially etched until the second source-drain metal is exposed to form a first through hole, the third interlayer dielectric layer and the second isolation structure are sequentially etched until the second source-drain metal is exposed to form a second through hole, and the fourth interlayer dielectric layer and the third isolation structure are sequentially etched until the third source-drain metal is exposed to form a third through hole; The first interlayer dielectric layer and the first isolation structure are sequentially etched until the second source-drain metal is exposed to form a first through hole, and the fourth interlayer dielectric layer, the third isolation structure, the third interlayer dielectric layer, the second isolation structure and the second interlayer dielectric layer are sequentially etched until the second source-drain metal is exposed to form a fifth through hole; The third interlayer dielectric layer and the second isolation structure are sequentially etched until the second source-drain metal is exposed to form a second through hole, and the fourth interlayer dielectric layer and the third isolation structure are sequentially etched until the third source-drain metal is exposed to form a third through hole; The third interlayer dielectric layer and the second isolation structure are sequentially etched until the second source-drain metal is exposed to form a second through hole, and the fourth interlayer dielectric layer, the third isolation structure, the third interlayer dielectric layer, the second isolation structure, the second interlayer dielectric layer, the first isolation structure and the first interlayer dielectric layer are sequentially etched until the first source-drain metal is exposed to form a sixth through hole; The fourth interlayer dielectric layer and the third isolation structure are sequentially etched until the third source-drain metal is exposed to form a third through hole, and the third interlayer dielectric layer, the second isolation structure, the second interlayer dielectric layer, the first isolation structure and the first interlayer dielectric layer are sequentially etched until the first source-drain metal is exposed to form a fourth through hole; The third interlayer dielectric layer, the second isolation structure, the second interlayer dielectric layer, the first isolation structure and the first interlayer dielectric layer are sequentially etched until the first source-drain metal is exposed to form a fourth through hole, and the fourth interlayer dielectric layer, the third isolation structure, the third interlayer dielectric layer, the second isolation structure and the second interlayer dielectric layer are sequentially etched until the second source-drain metal is exposed to form a fifth through hole.

6. The preparation method according to claim 4 or 5, characterized in that: The step of depositing a metal material in the through hole to form an interconnected through hole structure comprises at least one of the following: Depositing a metal material in the first through hole to form a first interconnected through hole structure, wherein the first interconnected through hole structure is used to connect the first source-drain metal and the second source-drain metal; Depositing a metal material in the second through hole to form a second interconnected through hole structure, wherein the second interconnected through hole structure is used to connect the second source-drain metal and the third source-drain metal; Depositing a metal material in the third through hole to form a third interconnected through hole structure, wherein the third interconnected through hole structure is used to connect the third source-drain metal and the fourth source-drain metal; Depositing a metal material in the fourth through hole to form a fourth interconnected through hole structure, wherein the fourth interconnected through hole structure is used to connect the first source-drain metal and the third source-drain metal; Depositing a metal material in the fifth through hole to form a fifth interconnected through hole structure, wherein the fifth interconnected through hole structure is used to connect the second source-drain metal and the fourth source-drain metal; A metal material is deposited in the sixth through hole to form a sixth interconnection through hole structure, wherein the sixth interconnection through hole structure is used to connect the first source-drain metal and the fourth source-drain metal.

7. The preparation method according to claim 6, characterized in that: The forming of a first source-drain metal on the first source-drain structure comprises: Depositing a dielectric material on the first source-drain structure to form a first interlayer dielectric layer, and etching the first interlayer dielectric layer until the first source-drain structure is exposed to form a first source-drain metal groove; The step of depositing a metal material in the first through hole to form a first interconnected through hole structure comprises: A metal material is deposited in the first source-drain metal groove and the first through hole to form the first source-drain metal and the first interconnection through hole structure respectively.

8. The preparation method according to claim 6, characterized in that: The forming of a third source-drain metal on the third source-drain structure comprises: Depositing a dielectric material on the third source-drain structure to form a third interlayer dielectric layer, and etching the third interlayer dielectric layer until the third source-drain structure is exposed to form a third source-drain metal groove; The step of depositing a metal material in the second through hole to form a second interconnected through hole structure comprises: Depositing metal material in the third source-drain metal groove and the second through hole to form the third source-drain metal and the second interconnect through hole structure respectively; The step of depositing a metal material in the fourth through hole to form a fourth interconnected through hole structure comprises: A metal material is deposited in the third source-drain metal groove and the fourth through hole to form the third source-drain metal and the fourth interconnection through hole structure, respectively.

9. The preparation method according to claim 6, characterized in that: The forming of a fourth source-drain metal on the fourth source-drain structure comprises: Depositing a dielectric material on the fourth source-drain structure to form a fourth interlayer dielectric layer, and etching the fourth interlayer dielectric layer until the fourth source-drain structure is exposed to form a fourth source-drain metal groove; The step of depositing a metal material in the third through hole to form a third interconnected through hole structure comprises: Depositing metal material in the fourth source-drain metal groove and the third through hole to form the fourth source-drain metal and the third interconnect through hole structure respectively; The step of depositing a metal material in the fifth through hole to form a fifth interconnected through hole structure comprises: Depositing metal material in the fourth source-drain metal groove and the fifth through hole to form the fourth source-drain metal and the fifth interconnection through hole structure respectively; The step of depositing a metal material in the sixth through hole to form a sixth interconnected through hole structure comprises: A metal material is deposited in the fourth source-drain metal groove and the sixth through hole to form the fourth source-drain metal and the sixth interconnection through hole structure, respectively.

10. A stacked transistor, prepared using the preparation method according to any one of claims 1 to 9, characterized in that: The stacked transistor comprises: A first transistor and a second transistor stacked along a first direction, wherein the first transistor and the second transistor have different polarities; A third transistor and a fourth transistor stacked along the first direction, wherein the third transistor and the fourth transistor have different polarities; an isolation structure exists between any two adjacent transistors among the first transistor, the second transistor, the third transistor and the fourth transistor; An interconnection via structure, wherein the interconnection via structure is used to pass through the isolation structure to connect the source and drain metals of any two transistors among the first transistor, the second transistor, the third transistor and the fourth transistor.

11. The stacked transistor according to claim 10, characterized in that The first transistor, the second transistor, the third transistor and the fourth transistor are arranged in sequence along the first direction; The interconnected via structure comprises at least one of a first interconnected via structure, a second interconnected via structure, a third interconnected via structure, a fourth interconnected via structure, a fifth interconnected via structure, and a sixth interconnected via structure; Among them, the first interconnection through-hole structure is used to connect the first source-drain metal of the first transistor and the second source-drain metal of the second transistor; the second interconnection through-hole structure is used to connect the second source-drain metal of the second transistor and the third source-drain metal of the third transistor; the third interconnection through-hole structure is used to connect the third source-drain metal of the third transistor and the fourth source-drain metal of the fourth transistor; the fourth interconnection through-hole structure is used to connect the first source-drain metal of the first transistor and the third source-drain metal of the third transistor; the fifth interconnection through-hole structure is used to connect the second source-drain metal of the second transistor and the fourth source-drain metal of the fourth transistor; the sixth interconnection through-hole structure is used to connect the first source-drain metal of the first transistor and the fourth source-drain metal of the fourth transistor.

12. The stacked transistor according to claim 10, characterized in that The first transistor, the second transistor, the third transistor and the fourth transistor are arranged in sequence along the first direction; and the interconnection via structure includes any one of the following: a first interconnected via structure and a second interconnected via structure; a first interconnected via structure and a third interconnected via structure; a first interconnected via structure, a second interconnected via structure, and a third interconnected via structure; a first interconnect via structure and a fifth interconnect via structure; a second interconnect via structure and a third interconnect via structure; a second interconnect via structure and a sixth interconnect via structure; a third interconnect via structure and a fourth interconnect via structure; a fourth interconnect via structure and a fifth interconnect via structure; Among them, the first interconnection through-hole structure is used to connect the first source-drain metal of the first transistor and the second source-drain metal of the second transistor; the second interconnection through-hole structure is used to connect the second source-drain metal of the second transistor and the third source-drain metal of the third transistor; the third interconnection through-hole structure is used to connect the third source-drain metal of the third transistor and the fourth source-drain metal of the fourth transistor; the fourth interconnection through-hole structure is used to connect the first source-drain metal of the first transistor and the third source-drain metal of the third transistor; the fifth interconnection through-hole structure is used to connect the second source-drain metal of the second transistor and the fourth source-drain metal of the fourth transistor; the sixth interconnection through-hole structure is used to connect the first source-drain metal of the first transistor and the fourth source-drain metal of the fourth transistor.

13. The stacked transistor according to claim 11 or 12, characterized in that: The first interconnection via structure, the second interconnection via structure, the third interconnection via structure, the fourth interconnection via structure, the fifth interconnection via structure and the sixth interconnection via structure are located on a first side or a second side of the first source-drain structure of the first transistor in the second direction; The first side and the second side are two opposite sides of the first source-drain structure, and the second direction is perpendicular to the first direction.

14. A semiconductor device, characterized in that: include: A stacked transistor as claimed in any one of claims 10 to 13.

Images