Method for manufacturing stacked transistor, stacked transistor, and semiconductor device

Abstract

The application provides a preparation method of stacked transistors, stacked transistors and a semiconductor device. The method comprises: forming an active structure on a semiconductor substrate, the active structure comprising a first part and a second part; based on the first part, forming a first transistor and a second transistor stacked along a first direction, the first transistor and the second transistor having opposite polarities; reversing and removing the semiconductor substrate; based on the second part, forming a third transistor and a fourth transistor stacked along the first direction, the third transistor and the fourth transistor having opposite polarities; there is an isolation structure between any two adjacent transistors in the first transistor, the second transistor, the third transistor and the fourth transistor; etching the isolation structure between any two transistors in the first transistor, the second transistor, the third transistor and the fourth transistor to form a via hole; and depositing a metal material in the via hole to form an interconnection via structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor chip manufacturing, and in particular to a method for fabricating stacked transistors, stacked transistors, and semiconductor devices. Background Technology

[0002] With Moore's Law continuously evolving, further miniaturizing transistors is a hot research topic in the industry. Stacked transistors, by integrating two or more layers of transistors in a vertical space, can further increase transistor integration density and have become one of the important technologies for continuing the miniaturization of integrated circuits.

[0003] In some methods for fabricating stacked transistors, the active regions of two homogeneous transistor layers are formed by etching, and the stacked transistors are fabricated on both sides of the wafer by flipping the wafer. This can also be called the "self-aligned flip-chip transistor" method. However, although the "self-aligned flip-chip transistor" method achieves the integration of multiple transistors in vertical space, there is still room for optimization in the interconnection between the multiple transistors. Summary of the Invention

[0004] This application provides a method for fabricating stacked transistors, stacked transistors, and semiconductor devices, which vertically interconnect each transistor in the stacking direction using "self-aligned flip transistors" to realize more complex standard logic units and create conditions for the large-scale integration of "self-aligned flip transistors".

[0005] In a first aspect, embodiments of this application provide a method for fabricating stacked transistors, comprising: forming an active structure on a semiconductor substrate, the active structure including a first portion and a second portion; forming a first transistor and a second transistor stacked along a first direction based on the first portion, wherein the first transistor and the second transistor have opposite polarities; the first direction is a direction perpendicular to the semiconductor substrate; washing and removing the semiconductor substrate; forming a third transistor and a fourth transistor stacked along the first direction based on the second portion, wherein the third transistor and the fourth transistor have opposite polarities; an isolation structure exists between any two adjacent transistors among the first transistor, second transistor, third transistor, and fourth transistor; etching the isolation structure located between any two transistors among the first transistor, second transistor, third transistor, and fourth transistor to form a via, wherein the projection of the via along the first direction falls within the projection of the source and drain metals of any two transistors along the first direction; depositing metal material in the via to form an interconnect via structure, wherein the interconnect via structure is used to connect the source and drain metals of any two transistors.

[0006] In some possible implementations, forming a first transistor and a second transistor stacked along a first direction based on the first portion includes: depositing an insulating material on a semiconductor substrate to form an initial isolation structure, wherein the initial isolation structure surrounds the second portion and the first portion is exposed outside the initial isolation structure; forming a second source / drain structure, a second interlayer dielectric layer, and a second gate structure on the initial isolation structure based on the first portion; wherein the second interlayer dielectric layer encapsulates the second source / drain structure; forming a second source / drain metal on the second source / drain structure; depositing an insulating material on the second source / drain metal to form a first isolation structure; and forming a first source / drain structure, a first interlayer dielectric layer, and a first gate structure on the first isolation structure based on the first portion; wherein the first interlayer dielectric layer encapsulates the first source / drain structure; and forming a first source / drain metal on the first source / drain structure.

[0007] In some possible implementations, based on the second portion, a third transistor and a fourth transistor stacked along a first direction are formed, including: thinning an initial isolation structure to form a second isolation structure between the second transistor and the third transistor; based on the second portion, forming a third source / drain structure, a third interlayer dielectric layer, and a third gate structure on the second isolation structure; wherein the third interlayer dielectric layer encapsulates the third source / drain structure; forming a third source / drain metal on the third source / drain structure; depositing an insulating material on the third source / drain metal to form the third isolation structure; and based on the first portion, forming a fourth source / drain structure, a fourth interlayer dielectric layer, and a fourth gate structure on the third isolation structure; wherein the fourth interlayer dielectric layer encapsulates the fourth source / drain structure; forming a fourth source / drain metal on the fourth source / drain structure; wherein the first isolation structure, the second isolation structure, and the third isolation structure are contained within the isolation structure.

[0008] In some possible implementations, etching an isolation structure between any two transistors among the first, second, third, and fourth transistors to form a via includes at least one of the following: sequentially etching a first interlayer dielectric layer and a first isolation structure until a second source / drain metal is exposed to form a first via; sequentially etching a third interlayer dielectric layer and a second isolation structure until a second source / drain metal is exposed to form a second via; sequentially etching a fourth interlayer dielectric layer and a third isolation structure until a third source / drain metal is exposed to form a third via; sequentially etching a third interlayer dielectric layer, a second isolation structure, a second interlayer dielectric layer, a first isolation structure, and a first interlayer dielectric layer until a first source / drain metal is exposed to form a fourth via; sequentially etching a fourth interlayer dielectric layer, a third isolation structure, a third interlayer dielectric layer, a second isolation structure, and a second interlayer dielectric layer until a second source / drain metal is exposed to form a fifth via; and sequentially etching a fourth interlayer dielectric layer, a third isolation structure, a third interlayer dielectric layer, a second isolation structure, a second interlayer dielectric layer, a first isolation structure, and a first interlayer dielectric layer until a first source / drain metal is exposed to form a sixth via.

[0009] In some possible implementations, etching the isolation structure between any two of the first, second, third, and fourth transistors to form a via includes any one of the following: sequentially etching the first interlayer dielectric layer and the first isolation structure until the second source / drain metal is exposed to form a first via; sequentially etching the third interlayer dielectric layer and the second isolation structure until the second source / drain metal is exposed to form a second via; sequentially etching the first interlayer dielectric layer and the first isolation structure until the second source / drain metal is exposed to form a first via; and sequentially etching the fourth interlayer dielectric layer and the third isolation structure until the third source / drain metal is exposed. The metal is etched to form a third via; the first interlayer dielectric layer and the first isolation structure are sequentially etched until the second source / drain metal is exposed to form a first via; the third interlayer dielectric layer and the second isolation structure are sequentially etched until the second source / drain metal is exposed to form a second via; and the fourth interlayer dielectric layer, the third isolation structure, the third interlayer dielectric layer, the second isolation structure, and the second interlayer dielectric layer are sequentially etched until the second source / drain metal is exposed to form a third via; the first interlayer dielectric layer and the first isolation structure are sequentially etched until the second source / drain metal is exposed to form a first via; and the fourth interlayer dielectric layer, the third isolation structure, the third interlayer dielectric layer, the second isolation structure, and the second interlayer dielectric layer are sequentially etched until the second source / drain metal is exposed to form a second via. The second source / drain metal is etched sequentially to form a fifth via; the third interlayer dielectric layer and the second isolation structure are etched sequentially until the second source / drain metal is exposed to form a second via; the fourth interlayer dielectric layer and the third isolation structure are etched sequentially until the third source / drain metal is exposed to form a third via; the third interlayer dielectric layer and the second isolation structure are etched sequentially until the second source / drain metal is exposed to form a second via; the fourth interlayer dielectric layer, the third isolation structure, the third interlayer dielectric layer, the second isolation structure, the second interlayer dielectric layer, the first isolation structure, and the first interlayer dielectric layer are etched sequentially until the first source / drain metal is exposed to form a sixth via; the fourth interlayer dielectric layer is etched sequentially... The third via is formed by etching the third interlayer dielectric layer and the third isolation structure until the third source / drain metal is exposed. The third via is formed by etching the third interlayer dielectric layer, the second isolation structure, the second interlayer dielectric layer, the first isolation structure, and the first interlayer dielectric layer until the first source / drain metal is exposed. The fourth via is formed by etching the third interlayer dielectric layer, the second isolation structure, the second interlayer dielectric layer, the first isolation structure, and the first interlayer dielectric layer until the first source / drain metal is exposed. The fifth via is formed by etching the fourth interlayer dielectric layer, the third isolation structure, the third interlayer dielectric layer, the second isolation structure, and the second interlayer dielectric layer until the second source / drain metal is exposed.

[0010] In some possible implementations, depositing metallic material in vias to form interconnect via structures includes at least one of the following: depositing metallic material in a first via to form a first interconnect via structure, wherein the first interconnect via structure is used to connect a first source / drain metal and a second source / drain metal; depositing metallic material in a second via to form a second interconnect via structure, wherein the second interconnect via structure is used to connect a second source / drain metal and a third source / drain metal; depositing metallic material in a third via to form a third interconnect via structure, wherein the third interconnect via structure is used to connect a third source / drain metal and a fourth source / drain metal; depositing metallic material in a fourth via to form a fourth interconnect via structure, wherein the fourth interconnect via structure is used to connect the first source / drain metal and the third source / drain metal; depositing metallic material in a fifth via to form a fifth interconnect via structure, wherein the fifth interconnect via structure is used to connect the second source / drain metal and the fourth source / drain metal; and depositing metallic material in a sixth via to form a sixth interconnect via structure, wherein the sixth interconnect via structure is used to connect the first source / drain metal and the fourth source / drain metal.

[0011] In some possible implementations, forming a first source / drain metal over a first source / drain structure includes: depositing a dielectric material over the first source / drain structure to form a first interlayer dielectric layer, and etching the first interlayer dielectric layer until the first source / drain structure is exposed to form a first source / drain metal groove; depositing a metal material in a first via to form a first interconnect via structure includes: depositing a metal material in the first source / drain metal groove and the first via to form the first source / drain metal and the first interconnect via structure, respectively.

[0012] In some possible implementations, forming a third source / drain metal over the third source / drain structure includes: depositing a dielectric material over the third source / drain structure to form a third interlayer dielectric layer, and etching the third interlayer dielectric layer until the third source / drain structure is exposed to form a third source / drain metal groove; depositing metal material in a second via to form a second interconnect via structure includes: depositing metal material in the third source / drain metal groove and the second via to form the third source / drain metal and the second interconnect via structure, respectively; and depositing metal material in a fourth via to form a fourth interconnect via structure includes: depositing metal material in the third source / drain metal groove and the fourth via to form the third source / drain metal and the fourth interconnect via structure, respectively.

[0013] In some possible implementations, forming a fourth source / drain metal over the fourth source / drain structure includes: depositing a dielectric material over the fourth source / drain structure to form a fourth interlayer dielectric layer, and etching the fourth interlayer dielectric layer until the fourth source / drain structure is exposed to form a fourth source / drain metal groove; depositing metal material in a third via to form a third interconnect via structure includes: depositing metal material in the fourth source / drain metal groove and the third via to form the fourth source / drain metal and the third interconnect via structure, respectively; depositing metal material in a fifth via to form a fifth interconnect via structure includes: depositing metal material in the fourth source / drain metal groove and the fifth via to form the fourth source / drain metal and the fifth interconnect via structure, respectively; and depositing metal material in a sixth via to form a sixth interconnect via structure includes: depositing metal material in the fourth source / drain metal groove and the sixth via to form the fourth source / drain metal and the sixth interconnect via structure, respectively.

[0014] Secondly, embodiments of this application provide a stacked transistor, the stacked transistor comprising: a first transistor and a second transistor stacked along a first direction, the first transistor and the second transistor having different polarities; a third transistor and a fourth transistor stacked along the first direction, the third transistor and the fourth transistor having different polarities; an isolation structure existing between any two adjacent transistors among the first transistor, the second transistor, the third transistor and the fourth transistor; and an interconnect via structure, wherein the interconnect via structure is used to connect the source and drain metals of any two transistors among the first transistor, the second transistor, the third transistor and the fourth transistor by penetrating the isolation structure.

[0015] In some possible implementations, the first transistor, the second transistor, the third transistor, and the fourth transistor are arranged sequentially along a first direction; the interconnect via structure includes at least one of the following: a first interconnect via structure, a second interconnect via structure, a third interconnect via structure, a fourth interconnect via structure, a fifth interconnect via structure, and a sixth interconnect via structure; wherein, the first interconnect via structure is used to connect the first source / drain metal of the first transistor and the second source / drain metal of the second transistor; the second interconnect via structure is used to connect the second source / drain metal of the second transistor and the third source / drain metal of the third transistor; the third interconnect via structure is used to connect the third source / drain metal of the third transistor and the fourth source / drain metal of the fourth transistor; the fourth interconnect via structure is used to connect the first source / drain metal of the first transistor and the third source / drain metal of the third transistor; the fifth interconnect via structure is used to connect the second source / drain metal of the second transistor and the fourth source / drain metal of the fourth transistor; and the sixth interconnect via structure is used to connect the first source / drain metal of the first transistor and the fourth source / drain metal of the fourth transistor.

[0016] In some possible implementations, the first transistor, the second transistor, the third transistor, and the fourth transistor are arranged sequentially along a first direction; the interconnect via structure includes any one of the following: a first interconnect via structure and a second interconnect via structure; a first interconnect via structure and a third interconnect via structure; a first interconnect via structure, a second interconnect via structure, and a third interconnect via structure; a first interconnect via structure and a fifth interconnect via structure; a second interconnect via structure and a third interconnect via structure; a second interconnect via structure and a sixth interconnect via structure; a third interconnect via structure and a fourth interconnect via structure; a fourth interconnect via structure and a fifth interconnect via structure; wherein, the first interconnect via... The structure is used to connect the first source-drain metal of the first transistor and the second source-drain metal of the second transistor; the second interconnect via structure is used to connect the second source-drain metal of the second transistor and the third source-drain metal of the third transistor; the third interconnect via structure is used to connect the third source-drain metal of the third transistor and the fourth source-drain metal of the fourth transistor; the fourth interconnect via structure is used to connect the first source-drain metal of the first transistor and the third source-drain metal of the third transistor; the fifth interconnect via structure is used to connect the second source-drain metal of the second transistor and the fourth source-drain metal of the fourth transistor; and the sixth interconnect via structure is used to connect the first source-drain metal of the first transistor and the fourth source-drain metal of the fourth transistor.

[0017] In some possible implementations, the first interconnect via structure, the second interconnect via structure, the third interconnect via structure, the fourth interconnect via structure, the fifth interconnect via structure, and the sixth interconnect via structure are located on the first side or the second side of the first source-drain structure of the first transistor in the second direction.

[0018] The first side and the second side are opposite sides of the first source-drain structure, and the second direction is perpendicular to the first direction.

[0019] Thirdly, embodiments of this application provide a semiconductor device, which includes: stacked transistors as described in the above embodiments.

[0020] In this embodiment, by forming an active structure of a certain depth on a semiconductor substrate, the active regions of multiple transistors arranged along a first direction in a vertically stacked manner can be self-aligned. Subsequently, a first transistor and a second transistor with different polarities, vertically stacked along the first direction, can be fabricated based on a first portion of the active structure. After wafer flipping, the semiconductor substrate is etched so that a third transistor and a fourth transistor with different polarities, vertically stacked along the first direction, can be fabricated based on a second portion of the active structure. It is evident that by forming a pair of stacked transistors on the front side of the wafer and another pair on the back side, more transistors can be fabricated using both sides of the wafer, thereby increasing the transistor integration density and further improving the transistor integration performance. Finally, by etching the isolation structure between any two transistors among the first, second, third, and fourth transistors, an interconnect via structure is formed, allowing the isolation structure between any two transistors to be penetrated. This interconnect via structure and the source / drain metal of any two transistors enable communication in the first direction, facilitating the large-scale integration of stacked transistors.

[0021] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0022] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0023] Figure 1 This is a top view of a stacked transistor according to an embodiment of this application;

[0024] Figure 2 This is a schematic diagram illustrating the implementation process of a method for fabricating stacked transistors according to an embodiment of this application;

[0025] Figures 3 to 25 This is a schematic diagram illustrating the fabrication process of a stacked transistor according to an embodiment of this application;

[0026] Figure 26 This is a schematic diagram of a stacked transistor structure according to an embodiment of this application.

[0027] Figure 27 This is a schematic diagram of a stacked transistor structure according to an embodiment of this application.

[0028] The figures above are as follows: 10. Stacked transistor; 101. Front vertical stacked transistor; 1011. Front metal interconnect layer; 102. Back vertical stacked transistor; 1021. Back metal interconnect layer; 11. First transistor; 12. Second transistor; 13. Third transistor; 14. Fourth transistor; 111. First dummy gate sidewall; 112. First source / drain structure; 113. First interlayer dielectric layer; 114. First gate structure; 115. First source / drain metal; 121. Second dummy gate sidewall; 122. 123. Second source / drain structure; 124. Second interlayer dielectric layer; 125. Second gate structure; 126. Second source / drain metal; 127. Front dielectric layer; 131. Third pseudo-gate sidewall; 132. Third source / drain structure; 133. Third interlayer dielectric layer; 134. Third gate structure; 135. Third source / drain metal; 141. Fourth pseudo-gate sidewall; 142. Fourth source / drain structure; 143. Fourth interlayer dielectric layer; 144. Fourth gate structure; 145. Fourth source / drain metal; 147. Back dielectric layer;

[0029] 20. Semiconductor substrate; 21. First part; 211. First sacrificial layer; 212. Third part; 213. Fourth part; 214. Second sacrificial layer; 22. Second part; 222. Fifth part; 223. Sixth part; 23. Stacked structure; 24. Isolation layer; 25. Shallow trench isolation structure; 26. First dummy gate structure; 27. First trench; 28. First isolation structure; 29. ​​First initial trench; 30. First barrier layer; 31. Second barrier layer; 32. Insulating layer; 33. Carrier wafer; 34. Third isolation structure; 35. Fourth barrier layer; 36. Second dummy gate structure; 40. Second isolation structure; 51. First interconnect via structure; 52. Second interconnect via structure; 53. Third interconnect via structure; 54. Fourth interconnect via structure; 55. Fifth interconnect via structure; 56. Sixth interconnect via structure. Detailed Implementation

[0030] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0031] With Moore's Law continuously evolving, further miniaturizing transistors is a hot research topic in the industry. Stacked transistors, through three-dimensional transistor stacking, can integrate two or more layers of transistors in vertical space, helping to further increase transistor integration density and improve circuit performance. It is considered one of the important technologies for continuing the miniaturization of integrated circuits.

[0032] In one embodiment, there are two methods for fabricating stacked transistors: the first is a monolithic method, and the second is a sequential method.

[0033] Sequential stacking is based on wafer bonding and is fabricated layer by layer. However, thanks to wafer bonding, the device structure, channel orientation, and even channel material of the upper and lower transistors can be optimized to obtain better and more matched device performance. The main challenges of sequential stacking transistors include: (1) fabrication of high-quality upper transistor active layers; (2) thinning and defect control of upper bonding wafers; and (3) alignment errors between the upper and lower transistors, which require extremely high photolithography precision.

[0034] In monolithic stacked transistor technology, wafer bonding technology is not used. Instead, N-channel field-effect transistors (NFETs) and P-channel field-effect transistors (PFETs) are fabricated on the same substrate. This also determines that transistors in the same layer must be of the same type, i.e., NFETs or PFETs. Furthermore, the upper and lower layers of transistors are strictly in the same plane space, with no alignment deviation. Obviously, the advantage of monolithic stacked transistors is higher integration density. However, its disadvantages are also obvious: (1) the process is complex, requiring a lot of process technology development and optimization; (2) the polarity of each layer of transistors is fixed, and two layers of transistors must be relied upon to form a basic CMOS circuit, resulting in poor design flexibility.

[0035] To address the technical issues of the two aforementioned schemes, a "self-aligned flip-chip transistor" scheme is proposed. This scheme forms the active regions of homogeneous transistors in upper and lower layers through etching and stacks transistors on both sides of the wafer through flipping, thus overcoming the shortcomings of the two schemes. However, while the "self-aligned flip-chip transistor" achieves the integration of multiple transistors in vertical space, there is still room for optimization in the interconnection between the multiple transistors. Therefore, more advanced fabrication processes are needed to achieve vertical interconnection of transistors in the stacking direction of the "self-aligned flip-chip transistor," enabling the realization of more complex standard logic cells and creating conditions for the large-scale integration of the "self-aligned flip-chip transistor."

[0036] In a first aspect, embodiments of this application provide a stacked transistor. Figure 1 This is a top view of a stacked transistor according to an embodiment of this application. See also... Figure 1 As shown in the top view, only the fin structure, gate structure, and source / drain structure of the stacked transistor 10 are shown. It is understood that the structure of the fin structure can vary depending on the type of stacked transistor.

[0037] For example, when the stacked transistor 10 is a fin field-effect transistor, the fin structure can be formed by deposition of a single semiconductor material. When the stacked transistor 10 is a gate-all-around nanosheet (GAANanosheet), the fin structure can be formed by alternating deposition of semiconductor material and sacrificial layer material; for example, it can be formed by alternating deposition of silicon and silicon-germanium layers. This application does not limit the scope of the embodiments.

[0038] Figure 2 This is a schematic diagram illustrating the implementation process of a method for fabricating stacked transistors according to an embodiment of this application. See also... Figure 2 As shown, the fabrication method of stacked transistors may include:

[0039] Step S201: An active structure is formed on a semiconductor substrate. The active structure includes a first part and a second part.

[0040] Step S202: Based on the first part, a first transistor and a second transistor are formed stacked along a first direction, wherein the polarities of the first transistor and the second transistor are opposite; the first direction is a direction perpendicular to the semiconductor substrate.

[0041] Step S203: Wash the wafer and remove the semiconductor substrate;

[0042] Step S204: Based on the second part, a third transistor and a fourth transistor are formed stacked along the first direction, wherein the polarities of the third transistor and the fourth transistor are opposite; an isolation structure exists between any two adjacent transistors among the first transistor, the second transistor, the third transistor, and the fourth transistor.

[0043] Step S205: Etch the isolation structure between any two transistors among the first transistor, second transistor, third transistor and fourth transistor to form a via, wherein the projection of the via along the first direction falls into the projection of the source and drain metals of any two transistors along the first direction.

[0044] Step S206: Deposit metal material in the via to form an interconnect via structure, wherein the interconnect via structure is used to connect the source and drain metals in any two transistors.

[0045] It should be noted that, Figure 2 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 2 The steps shown can be adjusted in order according to actual needs.

[0046] It is understandable that by forming an active structure of a certain depth on a semiconductor substrate, the active regions of multiple transistors arranged along a first direction in a vertically stacked manner can be self-aligned. Subsequently, a first transistor and a second transistor with different polarities, vertically stacked along the first direction, can be fabricated based on the first part of the active structure. After wafer flipping, the semiconductor substrate is etched so that a third transistor and a fourth transistor with different polarities, vertically stacked along the first direction, can be fabricated based on the second part of the active structure. Thus, by forming a pair of stacked transistors on the front side of the wafer and another pair on the back side, more transistors can be fabricated using both sides of the wafer, thereby increasing the transistor integration density and further improving the transistor integration performance. Finally, by etching the isolation structure between any two transistors among the first, second, third, and fourth transistors, an interconnect via structure is formed, allowing the isolation structure between any two transistors to be penetrated. This interconnect via structure and the source / drain metal of any two transistors enable communication in the first direction, facilitating the large-scale integration of stacked transistors.

[0047] Figures 3 to 25 This is a schematic diagram illustrating the fabrication process of a first type of stacked transistor according to an embodiment of this application. For ease of understanding, Figures 3 to 25 (a) in the middle shows along Figure 1 A cross-sectional view along the direction of the dashed line AA'. Figures 3 to 25 (b) shows along Figure 1 A cross-sectional view along the direction of the dashed line BB'. Figures 3 to 25 (c) in the middle shows the direction along Figure 1 A cross-sectional view along the direction of the dashed line CC'; the following will be combined with... Figures 1 to 25 The method for fabricating stacked transistors and the resulting stacked transistors provided in the embodiments of this application will be described by way of example.

[0048] In step S201, see Figure 4 As shown, an active structure is formed on the semiconductor substrate 20.

[0049] It is understandable that processes such as material layer deposition and epitaxial growth can be performed on the semiconductor substrate 20 to form a stacked structure 23 on the semiconductor substrate 20, such as... Figure 3 As shown. Subsequently, an etching process can be used to etch the stacked structure 23 to form an active structure on the semiconductor substrate 20.

[0050] Here, the stacked structure 23 includes sacrificial layers and support layers stacked alternately in sequence. The materials used for the sacrificial layers and support layers can be selected according to actual needs, and this embodiment does not limit this. It should be noted that the support layer can be used to form an active structure.

[0051] In one embodiment, the stacked structure 23 may be formed by alternating deposition of silicon and silicon-germanium materials.

[0052] It is understood that the active structure includes a first portion 21 and a second portion 22. The first portion 21 and the second portion 22 are stacked along a first direction (a direction perpendicular to the semiconductor substrate 20), with the second portion 22 being closer to the semiconductor substrate 20 relative to the first portion 21.

[0053] It is understood that the first part 21 of the active structure is used in subsequent steps to form the active regions of the first transistor 11 and the second transistor 12 in the front vertical stacked transistor 101; the second part 22 of the active structure is used to form the active regions of the third transistor 13 and the fourth transistor 14 in the back vertical stacked transistor 102.

[0054] It should be noted that the front-side vertically stacked transistor 101 is fabricated on the front side of the semiconductor substrate 20. After the stacked transistor 10 is fabricated, the front-side vertically stacked transistor 101 is located at the bottom layer of the stacked transistor 10. The back-side vertically stacked transistor 102 is the opposite of the front-side vertically stacked transistor 101.

[0055] In one embodiment, the transistors in the stacked transistor 10 may be all-around gate transistors. The stacked structure 23 may then be formed by alternating deposition of silicon and silicon-germanium materials. In one embodiment, the transistors in the stacked transistor 10 may be fin field-effect transistors. Of course, other types of transistors may also be used, and this application does not limit the specific types.

[0056] In some embodiments, see Figure 4 As shown, an isolation layer 24 can be formed between the first part 21 and the second part 22 of the active structure to electrically isolate the first part 21 and the second part 22 of the active structure, thereby avoiding current interference between the circuit of the front vertically stacked transistor 101 and the circuit of the back vertically stacked transistor 102.

[0057] In one embodiment, the isolation layer 24 may be a buried oxide layer or a dielectric layer. Here, the process for forming the buried oxide layer or dielectric layer can be set according to actual needs, and this embodiment does not limit this. In one embodiment, the isolation layer 24 may be an ion implantation layer. Here, the process for forming the ion implantation layer can be set according to actual needs, and this embodiment does not limit this.

[0058] It is understood that a large etching depth can be used when photolithography forms the first portion 21 and the second portion 22 of the active structure. For example, the combined height of the etched first portion 21 and the second portion 22 of the active structure can enable the formation of four transistors in the first direction. Of course, the height of the active structure can also be set according to actual conditions, and this embodiment does not limit this.

[0059] It should be noted that the steps of the photolithography process may include: depositing photoresist material, exposing and developing the photoresist material, removing a portion of the photoresist material, and etching the material layer corresponding to the portion of the photoresist material that has been removed.

[0060] In step S202, see Figure 18 As shown, a front-side vertically stacked transistor 101 is formed based on the first part 21.

[0061] The front-side vertically stacked transistor 101 includes a first transistor 11 and a second transistor 12, the first transistor 11 and the second transistor 12 having different polarities, and the first transistor 11 and the second transistor 12 being self-aligned in a first direction.

[0062] Understandably, a first transistor 11 and a second transistor 12 can be formed based on the first part 21 of the active structure. The first transistor 11 and the second transistor 12 have complementary polarities and are stacked along a first direction. At the same time, the front vertically stacked transistor 101 and the back vertically stacked transistor 102 are also stacked along the first direction, thereby greatly improving the integration density of the stacked transistors 10 in the first direction.

[0063] In one embodiment, when the first transistor 11 is a P-type (P-channel) field-effect transistor, the second transistor 12 may be an N-type (N-channel) field-effect transistor; when the first transistor 11 is an N-type field-effect transistor, the second transistor 12 may be a P-type field-effect transistor.

[0064] It should be noted that the steps for forming the front vertical stacked transistors 101 can be selected according to actual needs, and this application embodiment does not limit this.

[0065] For example, the front-side vertically stacked transistor 101 can be formed using a monolithic or sequential approach in semiconductor fabrication processes.

[0066] In some embodiments, see Figure 5As shown, before forming the first transistor 11 and the second transistor 12, an insulating material can be deposited on the semiconductor substrate 20 to form a shallow trench isolation (STI) structure. The shallow trench isolation structure encloses the second portion 22 of the active structure and exposes the first portion 21 of the active structure. The insulating material forming the shallow trench isolation structure 25 can be a silicon-based oxide (SiOx, where x is the number of oxygen atoms), such as silicon dioxide (SiO2).

[0067] It should be noted that the shallow trench isolation structure 25 is the initial isolation layer. The shallow trench isolation structure 25 can be thinned after wafer flipping to form a second isolation structure between the second transistor 12 and the third transistor 13.

[0068] In one embodiment, the shallow trench isolation structure 25 may enclose the second portion 22 of the active structure and the isolation layer 24, exposing the first portion 21 of the active structure.

[0069] In one embodiment, a second transistor 12 may be formed first, followed by the formation of a first transistor 11, which is further away from the semiconductor substrate 20 than the second transistor 12.

[0070] In some embodiments, a first sacrificial layer 211 is formed in the middle of the first portion 21 of the active structure. Using the first sacrificial layer 211 as a boundary, the portion of the first portion 21 farther from the semiconductor substrate 20 relative to the first sacrificial layer 211 is used to form a first transistor 11, and the portion of the first portion 21 closer to the semiconductor substrate 20 relative to the first sacrificial layer 211 is used to form a second transistor 12. Then, based on the first portion 21, a front-side vertical stacked transistor 101 is formed, including: forming a first dummy gate structure 26 surrounding the first portion 21 and a dummy gate sidewall covering the first dummy gate structure 26. Using the first dummy gate structure 26 as a hard mask, the first portion 21 located in the source / drain region is etched to form a first trench 27. The front-side source / drain structure of the front-side vertical stacked transistor 101 is formed within the first trench 27. The first sacrificial layer 211 and the first dummy gate structure 26 in the gate region are removed, and the front-side gate structure of the front-side vertical stacked transistor 101 is formed at the location where the first sacrificial layer 211 and the first dummy gate structure 26 are removed.

[0071] Understandably, after the active structure is formed in step S201, the second part 22 of the active structure can be enclosed by the shallow trench isolation structure 25, while the first part 21 of the active structure can be exposed outside the shallow trench isolation structure 25. Subsequently, based on the exposed first part 21 of the active structure, a first pseudo-gate structure 26 surrounding the first part 21 of the active structure can be formed by depositing pseudo-gate materials such as polycrystalline silicon or amorphous silicon. Sidewall material can also be deposited on the sidewalls of the first pseudo-gate structure to form the pseudo-gate sidewalls of the first pseudo-gate structure 26.

[0072] Among them, see Figure 6 As shown, multiple first dummy gate structures 26 are arranged along a second direction, which is perpendicular to the first direction. The second direction can be understood as the extension direction of the active structure (fin structure). In the extension direction of the active structure, the region between the dummy gate sidewalls of two adjacent first dummy gate structures 26 is the source / drain region, and the region where the first dummy gate structure 26 and its dummy gate sidewall are located is the gate region.

[0073] It is understandable that after forming the first pseudo-gate structure 26, the first pseudo-gate structure 26 can be used as a hard mask to form the first trench 27 in the source / drain region by etching the first portion 21 located in the source / drain region, see [link to relevant documentation]. Figures 6 to 9 As shown. Subsequently, the front-side source / drain structure of the front-side vertically stacked transistor 101 can be formed within the first trench 27 through processes such as epitaxial growth or deposition doping, see [reference]. Figures 10 to 16 As shown.

[0074] The front-side source-drain structure includes a first source-drain structure 112 of the first transistor 11, a first isolation structure 28, and a second source-drain structure 122 of the second transistor 12. The first isolation structure 28 is used to electrically isolate the first source-drain structure 112 and the second source-drain structure 122.

[0075] In one embodiment, see Figures 10 to 14 As shown, a second source / drain structure 122 can be formed first in the first trench 27 near the semiconductor substrate 20, followed by the formation of a first isolation structure 28, and then the formation of a first source / drain structure 112 in the first trench 27 away from the semiconductor substrate 20.

[0076] Understandably, after forming the front-side source-drain structure of the front-side vertically stacked transistor 101, the first dummy gate structure 26 and the first sacrificial layer 211 can be removed, thus retaining only the active structure in the gate region. Subsequently, gate material is deposited at the locations where the first dummy gate structure 26 and the first sacrificial layer 211 are removed to form the front-side gate structure of the front-side vertically stacked transistor 101, see [link to relevant documentation]. Figure 15 As shown.

[0077] The front gate structure includes a first gate structure 114 of the first transistor 11 and a second gate structure 124 of the second transistor 12. The junction of the first gate structure 114 and the second gate structure 124 is located at the position where the first sacrificial layer 211 is removed. It can be understood that the first sacrificial layer 211 divides the first portion 21 within the gate region into two parts, such that the separated first portion 21 can simultaneously form the active regions of the first transistor 11 and the second transistor 12. Furthermore, the junction of the first gate structure 114 of the first transistor 11 and the second gate structure 124 of the second transistor 12 can be located at the position where the first portion 21 is separated, i.e., at the position of the first sacrificial layer 211.

[0078] It is understandable that the front-end process of the front-side vertical stacked transistor 101 can be completed by forming the front-side source-drain structure and the front-side gate structure of the front-side vertical stacked transistor 101.

[0079] In some embodiments, the first portion 21 of the active structure further includes a third portion 212 and a fourth portion 213, with a first sacrificial layer 211 located between the third portion 212 and the fourth portion 213, and the third portion 212 being closer to the semiconductor substrate 20 than the fourth portion 213. Then, etching the first portion 21 located in the source / drain region using the first dummy gate structure 26 as a hard mask to form the first trench 27 may include: using the first dummy gate structure 26 as a hard mask, etching the fourth portion 213 and the first sacrificial layer 211 located in the source / drain region to expose the fourth portion 213 and the first sacrificial layer 211 in the gate region, and forming a first initial trench 29; forming a first barrier layer 30 on the sidewalls of the fourth portion 213 and the first sacrificial layer 211 in the gate region; etching the third portion 212 located below the first initial trench 29 to expose the third portion 212 in the gate region, and forming the first trench 27.

[0080] Understandably, by etching the fourth portion 213 and the first sacrificial layer 211 in the source / drain region, the fourth portion 213 and the first sacrificial layer 211 in the gate region can be exposed, forming a first initial trench 29. Here, the bottom of the first initial trench 29 can be formed by the third portion 212 in the source / drain region, and the walls of the first initial trench 29 can be formed by the fourth portion 213 and the first sacrificial layer 211 in the gate region. Subsequently, a first barrier layer 30 can be formed on the sidewalls of the exposed fourth portion 213 and the first sacrificial layer 211 in the gate region to isolate the fourth portion 213 and the first sacrificial layer 211 from the first initial trench 29. Subsequently, the third portion 212 located below the first initial trench 29 is etched to expose the third portion 212 in the gate region, obtaining the first trench 27 required for subsequent steps, see [link to relevant documentation]. Figures 7 to 8 .

[0081] Understandably, in subsequent steps, a second source / drain structure 122 can be formed within the first trench 27 (source / drain region) using an epitaxial growth process based on the third portion 212 within the gate region. Here, when forming the first trench 27, a first barrier layer 30 is formed covering the fourth portion 213 and the first sacrificial layer 211. The first barrier layer 30 can effectively prevent the fourth portion 213 from also epitaxially growing an active structure, thereby ensuring the orderly fabrication of the front-side vertically stacked transistors 101.

[0082] In one embodiment, the material forming the first barrier layer 30 may have high selective etchability with the material forming the third portion 212, thereby allowing the third portion 212 to be removed by a selective etching process.

[0083] For example, the third portion 212 may be formed of silicon material, and the first barrier layer 30 may be formed of silicon nitride material.

[0084] In some embodiments, the first portion 21 of the active structure further includes a second sacrificial layer 214, which is closer to the semiconductor substrate 20 than the third portion 212. Etching the third portion 212 below the first initial trench 29 to expose the third portion 212 within the gate region and forming the first trench 27 further includes etching the third portion 212 and the second sacrificial layer 214 below the first initial trench 29 to expose the third portion 212 and the second sacrificial layer 214 within the gate region; a second barrier layer 31 is formed on the sidewall of the second sacrificial layer 214 within the gate region, and the first trench 27 is formed.

[0085] Understandably, after forming the first barrier layer 30 covering the fourth portion 213 and the sidewalls of the first sacrificial layer 211 within the gate region, the third portion 212 and the second sacrificial layer 214 located below the first initial trench 29 can be etched to expose the third portion 212 and the second sacrificial layer 214 within the gate region. Subsequently, a second barrier layer 31 can be formed on the sidewalls of the second sacrificial layer 214 within the gate region to obtain the first trench 27 required for subsequent steps, see [link to relevant documentation]. Figures 7 to 9 .

[0086] It is understandable that the second barrier layer 31 has the same function as the first barrier layer 30, both of which are used to ensure that the second source / drain structure 122 can be generated epitaxially based on the third part 212.

[0087] Understandably, compared to the scheme without the second sacrificial layer 214, the scheme with the second sacrificial layer 214 can fully expose the third portion 212 in the gate region during the subsequent steps of forming the gate structure, thereby facilitating the formation of the gate ring structure.

[0088] In one embodiment, the material forming the second barrier layer 31 can be a pseudo-gate material, thereby directly forming a pseudo-gate sidewall between the gate region and the source / drain region, achieving electrical isolation between the gate structure and the source / drain structure of the front-side vertically stacked transistor 101.

[0089] In some embodiments, before forming the first barrier layer 30 on the fourth portion 213 and the sidewalls of the first sacrificial layer 211 in the gate region, the method further includes: using an etching process to laterally etch the sidewalls of the first sacrificial layer 211 in the exposed gate region to form a first trench. An insulating material is filled into the first trench to form a second dummy gate sidewall 121 of the second transistor 12.

[0090] Understandably, before forming the first barrier layer 30, an etching process can be used to laterally etch the sidewalls of the first sacrificial layer 211 in the exposed gate region to form a first groove with an opening facing the source / drain region. Subsequently, insulating material can be filled into the first groove to form the second dummy gate sidewall 121 of the second transistor 12, see [reference needed]. Figure 7 .

[0091] Here, the depth of the first groove can be selected according to actual needs, and this embodiment does not impose specific limitations on it.

[0092] It should be noted that after the insulating material is deposited in the first groove, it can be used to form a sidewall structure that isolates the gate structure from the source and drain structure. Specifically, after the insulating material is filled in the first groove, at least the second pseudo-gate sidewall of the second transistor 12 can be formed, and the pseudo-gate sidewall of the first pseudo-gate structure 26 is used to form the first pseudo-gate sidewall 111 of the first transistor 11.

[0093] In some embodiments, after the first groove is filled with insulating material, a portion forms the second pseudo-gate sidewall of the second transistor 12, and another portion may form a portion of the first pseudo-gate sidewall 111 of the first transistor 11.

[0094] In some possible implementations, after forming the first trench 27 using any of the above embodiments, a front-side source / drain structure of the front-side vertically stacked transistor 101 can be formed within the first trench 27. Specifically, this includes: forming a second source / drain structure 122 within the first trench 27 using an epitaxial growth process based on the third portion 212 within the gate region; removing the first barrier layer 30 to expose the fourth portion 213 within the gate region; forming a first isolation structure 28 on top of the second source / drain structure 122, the first isolation structure 28 being opposite to the first sacrificial layer 211; and forming a first source / drain structure 112 within the first trench 27 using an epitaxial growth process based on the exposed fourth portion 213 within the gate region, on top of the first isolation structure 28.

[0095] It is understood that the third portion 212 within the gate region is not covered by the first barrier layer 30 and the second barrier layer 31, allowing the third portion 212 within the gate region to communicate with the first trench 27. This enables the epitaxial growth of an active structure along the second direction on the sidewall of the third portion 212 within the gate region, thus forming a second source / drain structure 122 within the first trench 27. The position of the second source / drain structure 122 can then be opposite to the position of the third portion 212, as shown in [reference needed]. Figure 10 As shown.

[0096] Understandably, after forming the second source / drain structure 122, the first barrier layer 30 can be removed to expose the fourth portion 213 in the gate region, see [reference]. Figure 11 As shown. Subsequently, a source-drain isolation structure (i.e., the first isolation structure 28) can be formed between the first source-drain structure 112 and the second source-drain structure 122, see [reference]. Figure 13 As shown. Specifically, insulating material can be deposited on the first source-drain structure 112 to form a first isolation structure 28. The first isolation structure 28 is located between the first source-drain structure 112 and the second source-drain structure 122, that is, the position of the first isolation structure 28 can be opposite to the position of the first sacrificial layer 211.

[0097] It is understandable that after the first isolation structure 28 is formed, an active structure can be epitaxially grown on the sidewall of the fourth portion 213 of the exposed gate region on the first isolation structure 28, along the second direction, through an epitaxial growth process, thereby forming the first source / drain structure 112 within the first trench 27. (See [reference]). Figure 12 As shown. Therefore, the position of the first source-drain structure 112 can be opposite to the position of the fourth part 213.

[0098] Here, the process for epitaxially growing active structures can be selected according to actual needs, and this application embodiment does not specifically limit it.

[0099] It should be noted that the first source-drain structure 112 and the second source-drain structure 122 have different polarities, which allows the front-side vertically stacked transistor 101 to be a complementary stacked transistor.

[0100] In some embodiments, after forming the second source / drain structure 122 in the first trench 27 by an epitaxial growth process, the method further includes depositing a metal material on the second source / drain structure 122 to form a second source / drain metal 125.

[0101] It is understood that after forming the second source / drain structure 122, a dielectric layer material can be deposited on the second source / drain structure 122 to form the second interlayer dielectric layer 123 of the second transistor 12. Subsequently, vias can be made in the second interlayer dielectric layer 123 until the second source / drain structure 122 is exposed. Then, a metal material can be deposited on the second source / drain structure 122 until the second source / drain metal 125 is formed, see [reference needed]. Figure 12 As shown.

[0102] In some embodiments, forming a first isolation structure 28 on the second source-drain structure 122 includes depositing an insulating material on the second source-drain metal 125 to form the first isolation structure 28.

[0103] It is understood that after the second source / drain metal 125 is formed, an insulating material can be deposited on the second source / drain metal 125 and the second interlayer dielectric layer 123 to form the first isolation structure 28, see [link to relevant documentation]. Figure 13 As shown.

[0104] In some embodiments, the positions of the second source / drain metal 125 and the first isolation structure 28 can be positioned relative to the position of the first sacrificial layer 211, thereby preventing the second source / drain metal 125 and the first isolation structure 28 from affecting the exposure of the fourth portion 213.

[0105] In some embodiments, after forming the first source / drain structure 112 in the first trench 27 by an epitaxial growth process, the method further includes depositing a metal material on the first source / drain structure 112 to form a first source / drain metal 115.

[0106] It is understood that after forming the first source / drain structure 112, a dielectric layer material can be deposited on the first source / drain structure 112 to form the first interlayer dielectric layer 113 of the first transistor 11, see [reference]. Figure 15 As shown. Subsequently, a front dielectric layer 127 can be deposited on the first interlayer dielectric layer 113, and vias can be made in the front dielectric layer 127 and the first interlayer dielectric layer 113 until the first source / drain structure 112 is exposed. Subsequently, a metallic material can be deposited on the first source / drain structure 112 until the first source / drain metal 115 is formed, see [reference]. Figure 16 As shown.

[0107] In some possible implementations, the first sacrificial layer 211 and the first dummy gate structure 26 in the gate region are removed, and a front gate structure of the front vertical stacked transistor 101 is formed at the location where the first sacrificial layer 211 and the first dummy gate structure 26 are removed. This includes: removing the first dummy gate structure 26 to expose the third portion 212, the first sacrificial layer 211, and the fourth portion 213 in the gate region; using an etching process to remove the first sacrificial layer 211 in the gate region to expose the first surface of the third portion 212 and the second surface of the fourth portion 213, forming a second gate structure 124 surrounding the third portion 212; and forming a first gate structure 114 surrounding the fourth portion 213.

[0108] It is understandable that after forming the front source-drain structure of the front vertical stacked transistor 101, the front gate structure of the front vertical stacked transistor 101 can be formed by removing the first sacrificial layer 211 and the first dummy gate structure 26 in the gate region and filling the gate material. First, the first dummy gate structure 26 can be removed to expose the third portion 212, the first sacrificial layer 211, and the fourth portion 213 enclosed by the first dummy gate structure 26 in the gate region. Subsequently, an etching process can be used to remove the first sacrificial layer 211 in the exposed gate region to expose the surfaces of the third portion 212 and the fourth portion 213 that are in contact with the first sacrificial layer 211, that is, to expose the first surface of the third portion 212 and the second surface of the fourth portion 213.

[0109] Here, the first surface of the third part 212 is the surface of the third part 212 away from the semiconductor substrate 20, and the second surface of the fourth part 213 is the surface of the fourth part 213 close to the semiconductor substrate 20.

[0110] Understandably, after exposing the first surface of the third portion 212 and the second surface of the fourth portion 213, the third portion 212 and the fourth portion 213 within the gate region are spaced apart. Subsequently, gate material can be deposited within the gate region to form a second gate structure 124 surrounding the third portion 212 and a first gate structure 114 surrounding the fourth portion 213. The junction of the first gate structure 114 and the second gate structure 124 is located between the first and second surfaces.

[0111] Here, the process for forming the first gate structure 114 surrounding the third portion 212 and the second gate structure 124 surrounding the fourth portion 213 can be selected according to actual needs, and this application embodiment does not limit it.

[0112] For example, the process of forming the first gate structure 114 and the second gate structure 124 may include: depositing a gate dielectric material to form the gate dielectric layer of the first gate structure 114 and the second gate structure 124, then depositing a second gate metal material to form the second gate structure 124; and finally, depositing a first gate metal material to form the first gate structure 114.

[0113] In some embodiments, removing the first sacrificial layer 211 and the first dummy gate structure 26 within the gate region, and forming the front gate structure of the front vertical stacked transistor 101 at the location where the first sacrificial layer 211 and the first dummy gate structure 26 are removed, includes: removing the first dummy gate structure 26 to expose the third portion 212, the first sacrificial layer 211, the fourth portion 213, and the second sacrificial layer 214 within the gate region; using an etching process to remove the first sacrificial layer 211 and the second sacrificial layer 214 within the gate region, forming a second gate structure 124 surrounding the third portion 212 with the first surface of the third portion 212, the third surface of the third portion 212, and the second surface of the fourth portion 213; and forming a first gate structure 114 surrounding the fourth portion 213.

[0114] Understandably, after forming the front-side source-drain structure of the front-side vertically stacked transistor 101, the front-side gate structure of the front-side vertically stacked transistor 101 can be formed by removing the first sacrificial layer 211, the second sacrificial layer 214, and the first dummy gate structure 26 within the gate region, and then filling with gate material. First, the first dummy gate structure 26 can be removed to expose the third portion 212, the first sacrificial layer 211, the fourth portion 213, and the second sacrificial layer 214 within the gate region, which are enclosed by the first dummy gate structure 26. Subsequently, an etching process can be used to remove the first sacrificial layer 211 and the second sacrificial layer 214 within the exposed gate region to expose the first and third surfaces of the third portion 212, and the second surface of the fourth portion 213, see [reference needed]. Figure 15 As shown.

[0115] Wherein, the first surface of the third part 212 is the surface of the third part 212 away from the semiconductor substrate 20, the third surface of the third part 212 is the surface of the third part 212 close to the semiconductor substrate 20, and the second surface of the fourth part 213 is the surface of the fourth part 213 close to the semiconductor substrate 20.

[0116] It is understandable that removing the first dummy gate structure 26 completely exposes the front and rear surfaces of the third portion 212. Simultaneously, removing the first sacrificial layer 211 and the second sacrificial layer completely exposes the upper and lower surfaces of the third portion 212. Therefore, the third portion 212 within the gate region is completely exposed, allowing the formation of a second gate structure 124 surrounding the third portion 212.

[0117] It is understandable that removing the first dummy gate structure 26 completely exposes the front and rear surfaces and the upper surface of the fourth portion 213. Simultaneously, removing the first sacrificial layer 211 completely exposes the lower surface of the fourth portion 213. Therefore, the fourth portion 213 within the gate region is completely exposed, allowing the formation of the first gate structure 114 surrounding the fourth portion 213.

[0118] As can be seen from the above one or more embodiments of forming a gate structure, when the transistor type is a fully all-around gate field-effect transistor, it is necessary to form a second sacrificial layer 214 in the first part 21 of the active structure; when the transistor type is a fin field-effect transistor, it is not necessary to form a second sacrificial layer 214 in the first part 21 of the active structure, thereby reducing the fabrication steps and improving the fabrication efficiency.

[0119] In some embodiments, steps S205 to S206 can be performed simultaneously with the fabrication of the first source / drain metal 115. At this time, a first transistor 11 and a second transistor 12 are fabricated in the stacked transistor 10. Therefore, an isolation structure (i.e., the first isolation structure 28) located between the first transistor 11 and the second transistor 12 can be etched to form a first via. Then, metal material is deposited within the first via to form a first interconnect via structure 51 capable of connecting the source / drain metal of the first transistor 11 (first source / drain metal 115) and the source / drain metal of the second transistor 12 (second source / drain metal 125), as shown below. Figure 17 As shown.

[0120] Understandably, the projection of the first via along the first direction falls within the projections of the first source / drain metal 115 and the second source / drain metal 125 along the first direction, so that the first interconnect via structure 51 formed according to the first via can connect the first source / drain metal 115 and the second source / drain metal 125. For example, as... Figure 17 As shown, the projection of the first interconnect via structure 51 along the first direction falls into the projection of the first source / drain metal 115 and the second source / drain metal 125 along the first direction, and the first interconnect via structure 51 enables the first source / drain metal 115 and the second source / drain metal 125 to be vertically interconnected.

[0121] In some embodiments, a first via is formed by sequentially etching the first interlayer dielectric layer 113 and the first isolation structure 28 until the second source / drain metal 125 is exposed.

[0122] In some embodiments, forming a first source / drain metal 115 on the first source / drain structure 112 includes: depositing a dielectric material on the first source / drain structure 112 to form a first interlayer dielectric layer 123, and etching the first interlayer dielectric layer 123 until the first source / drain structure 112 is exposed to form a first source / drain metal recess. Similarly, depositing metal material in the first via to form a first interconnect via structure 51 may include: depositing metal material in the first source / drain metal recess and the first via to form the first source / drain metal 115 and the first interconnect via structure 51, respectively.

[0123] Understandably, the first source / drain metal groove and the first through-hole can be formed through an etching process. Subsequently, metal material can be deposited in the first source / drain metal groove and the first through-hole using the same deposition process, thereby simultaneously forming the first source / drain metal 115 and the first interconnecting through-hole structure 51. In this way, the first source / drain metal 115 and the first interconnecting through-hole structure 51 are integrally formed, reducing the complexity of the fabrication process.

[0124] It should be noted that the metal material forming the interconnect via structure can be the same as the material forming the source and drain metals.

[0125] In one embodiment, after forming the first gate structure 114 and the first source / drain metal 115, a front metal interconnect layer 1011 for the front vertical stacked transistors can be formed on the first gate structure 114 and the first source / drain metal 115 using standard back-end semiconductor fabrication processes (such as inter-interconnect dielectric deposition, metal line formation, lead-out pad formation, etc.). See [link to previous embodiment]. Figure 18 As shown.

[0126] It should be noted that, for ease of explanation, the first source / drain structure mentioned in the embodiments of this application is an abbreviation, specifically referring to the first source structure and / or the first drain structure. Furthermore, the second source / drain structure, the first source / drain metal, the second source / drain metal, etc., are all similar to the first source / drain groove, where "source / drain" is an abbreviation for "source and / or drain".

[0127] In step S203, see Figures 19 to 20 As shown, the semiconductor substrate 20 is flipped and removed.

[0128] It is understandable that after obtaining the front vertical stacked transistor 101, the front vertical stacked transistor 101 can be flipped so that the fabricated front vertical stacked transistor 101 is located at the bottom, and the second part 22 of the active structure of the unfabricated reverse vertical stacked transistor 102 can be located at the top, which facilitates the subsequent fabrication of the reverse vertical stacked transistor 102.

[0129] In one embodiment, after completing the back-end processes of the front-side vertically stacked transistor 101, the front-side vertically stacked transistor 101 can be bonded to the carrier wafer 33. For example, an insulating material (such as silicon oxide) can be deposited on the front-side vertically stacked transistor 101 to form an insulating layer 32, and the insulating layer 32 can be bonded to the carrier wafer 33. A wafer flipping process is then performed, after which the front-side vertically stacked transistor 101 is located at the bottom, see [reference]. Figure 19 As shown.

[0130] In this embodiment, the bonded carrier wafer 33 can provide physical support for the flipped front vertical stacked transistor 101 after the wafer is flipped, effectively preventing the front vertical stacked transistor 101 from being broken by external force during the fabrication of the back vertical stacked transistor 102.

[0131] In one embodiment, after wafer flipping, the semiconductor substrate 20 can be removed by processes such as polishing or chemical mechanical planarization to expose the second part 22 of the active structure.

[0132] Understandably, during the removal of the semiconductor substrate 20 using processes such as polishing or chemical mechanical planarization, the shallow trench isolation structure 25 can be exposed first, such as... Figure 20 As shown, the second part 22 of the active structure is then exposed, see [reference]. Figure 21 As shown.

[0133] In step S204, based on the second part 22, a reverse vertical stacked transistor 102 is formed.

[0134] Understandably, after removing the semiconductor substrate 20, the shallow trench isolation structure 25 can be thinned to form a second isolation structure 40, which can isolate the second transistor 12 and the subsequently formed third transistor 13. Furthermore, during the formation of the second isolation structure 40, the sixth portion of the second portion 22 can be exposed first, such as... Figure 22 As shown, the second part 22 of the active structure can then be exposed, as... Figure 23 As shown.

[0135] It is understood that after the second part 22 of the active structure is exposed, the reverse vertical stacked transistor 102 can be formed using the same method as forming the front vertical stacked transistor 101, or the reverse vertical stacked transistor 102 can be formed using a different method than forming the front vertical stacked transistor 101. This application embodiment does not specifically limit this.

[0136] For example, Figures 23 to 25 The reverse vertical stacked transistor 102 is shown to be formed using the same method as that used to form the front vertical stacked transistor 101.

[0137] It is understood that the reverse vertically stacked transistor 102 includes a third transistor 13 and a fourth transistor 14 stacked along the first direction. The third transistor 13 includes a third dummy gate sidewall 131, a third source-drain structure 132, a third interlayer dielectric layer 133, a third gate structure 134, and a third source-drain metal 135; the fourth transistor 14 includes a fourth dummy gate sidewall 141, a fourth source-drain structure 142, a fourth interlayer dielectric layer 143, a fourth gate structure 144, and a fourth source-drain metal 145.

[0138] In some embodiments, the second portion 22 includes a third sacrificial layer located in the middle of the second portion 22; based on the second portion 22, a reverse vertical stacked transistor 102 is formed, including: based on the second portion 22, forming a plurality of second dummy gate structures 36 surrounding the second portion 22 and dummy gate sidewalls covering the second dummy gate structures 36, the plurality of second dummy gate structures 36 being arranged along a second direction; using the second dummy gate structures 36 as a hard mask, etching the second portion 22 located in the source / drain region to form a second trench, wherein the region between the dummy gate sidewalls of two adjacent second dummy gate structures 36 is the source / drain region, and the region where the first dummy gate structure 26 and its dummy gate sidewall are located is the gate region; A reverse source-drain structure of a reverse vertically stacked transistor 102 is formed in the second trench. The reverse source-drain structure includes a third source-drain structure 132 of the third transistor 13, a third isolation structure 34, and a fourth source-drain structure 142 of the fourth transistor 14. The third sacrificial layer and the second dummy gate structure 36 in the gate region are removed. A reverse gate structure of the reverse vertically stacked transistor 102 is formed at the location where the third sacrificial layer and the second dummy gate structure 36 are removed. The reverse gate structure includes a third gate structure 134 of the third transistor 13 and a fourth gate structure 144 of the fourth transistor 14. The junction of the third gate structure 134 and the fourth gate structure 144 is located at the location where the third sacrificial layer is removed.

[0139] In some embodiments, the second portion 22 further includes: a fifth portion 222 and a sixth portion 223, with a third sacrificial layer located between the fifth portion 222 and the sixth portion 223, the fifth portion 222 being closer to the semiconductor substrate than the sixth portion 223; using the second dummy gate structure 36 as a hard mask, etching the second portion 22 located in the source / drain region to form a second trench includes: using the second dummy gate structure 36 as a hard mask, etching the sixth portion 223 and the third sacrificial layer located in the source / drain region to expose the sixth portion 223 and the third sacrificial layer in the gate region and forming a second initial trench; forming a third barrier layer on the sidewalls of the sixth portion 223 and the third sacrificial layer in the gate region; etching the fifth portion 222 located below the second initial trench to expose the fifth portion 222 in the gate region and forming the second trench.

[0140] In some embodiments, removing the third sacrificial layer and the second dummy gate structure 36 in the gate region, and forming a reverse gate structure of the reverse vertical stacked transistor 102 at the location where the third sacrificial layer and the second dummy gate structure 36 are removed, includes: removing the second dummy gate structure 36 to expose the fifth portion 222, the third sacrificial layer, and the sixth portion 223 in the gate region; using an etching process to remove the third sacrificial layer in the gate region to expose the fourth surface of the fifth portion 222 and the fifth surface of the sixth portion 223, wherein the fourth surface of the fifth portion 222 is the surface of the fifth portion 222 away from the semiconductor substrate, and the fifth surface of the sixth portion 223 is the surface of the sixth portion 223 close to the semiconductor substrate; forming a third gate structure 134 surrounding the fifth portion 222; and forming a fourth gate structure 144 surrounding the sixth portion 223, wherein the junction of the third gate structure 134 and the fourth gate structure 144 is located between the fourth surface and the fifth surface.

[0141] In some embodiments, the second portion 22 further includes a fourth sacrificial layer, which is closer to the semiconductor substrate than the fifth portion 222; etching the fifth portion 222 located below the second initial trench to expose the fifth portion 222 in the gate region and forming the second trench further includes: etching the fifth portion 222 and the fourth sacrificial layer located below the second initial trench to expose the fifth portion 222 and the fourth sacrificial layer in the gate region; forming a fourth barrier layer 35 on the sidewall of the fourth sacrificial layer in the gate region and forming the second trench.

[0142] In some embodiments, removing the third sacrificial layer and the second dummy gate structure 36 in the gate region, and forming a reverse gate structure of the reverse vertical stacked transistor 102 at the location where the third sacrificial layer and the second dummy gate structure 36 are removed, further includes: removing the second dummy gate structure 36 to expose the fifth portion 222, the third sacrificial layer, the sixth portion 223, and the fourth sacrificial layer in the gate region; using an etching process to remove the third sacrificial layer and the fourth sacrificial layer in the gate region to expose the fourth surface of the fifth portion 222, the sixth surface of the fifth portion 222, and the fifth surface of the sixth portion 223, wherein the fourth surface of the fifth portion 222 is the surface of the fifth portion 222 away from the semiconductor substrate, the sixth surface of the fifth portion 222 is the surface of the fifth portion 222 close to the semiconductor substrate, and the fifth surface of the sixth portion 223 is the surface of the sixth portion 223 close to the semiconductor substrate; forming a third gate structure 134 surrounding the fifth portion 222; and forming a fourth gate structure 144 surrounding the sixth portion 223.

[0143] In some embodiments, forming a reverse source / drain structure of a reverse vertically stacked transistor 102 within a second trench includes: forming a third source / drain structure within the second trench using an epitaxial growth process based on a fifth portion 222 within the gate region, the third source / drain structure being opposite to the fifth portion 222; removing a third barrier layer to expose a sixth portion 223 within the gate region; forming a third isolation structure 34 over the third source / drain structure, the third isolation structure 34 being opposite to a third sacrificial layer; and forming a fourth source / drain structure within the second trench using an epitaxial growth process over the third isolation structure 34, based on the exposed sixth portion 223 within the gate region, the fourth source / drain structure being opposite to the sixth portion 223.

[0144] In some embodiments, before forming a third barrier layer on the sixth portion 223 and the sidewalls of the third sacrificial layer in the gate region, the method further includes: using an etching process to laterally etch the sidewalls of the exposed third sacrificial layer in the gate region to form a second groove; filling the second groove with an insulating material to form a third dummy gate sidewall 131 of the third transistor 13, the third dummy gate sidewall 131 completely covering the sidewalls of the third sacrificial layer in the gate region, and the dummy gate sidewalls of the second dummy gate structure 36 being used to form a fourth dummy gate sidewall 141 of the fourth transistor 14.

[0145] In some embodiments, after forming a third source / drain structure 132 in a second trench by an epitaxial growth process, the method further includes: depositing a metal material on the third source / drain structure 132 to form a third source / drain metal 135; forming a third isolation structure 34 on the third source / drain structure 132, including: depositing an insulating material on the third source / drain metal 135 to form a third isolation structure 34, wherein the third source / drain metal 135 and the third isolation structure 34 are together opposite to a third sacrificial layer; after forming a fourth source / drain structure in a second trench by an epitaxial growth process, the method further includes: depositing a metal material on the fourth source / drain structure 142 to form a fourth source / drain metal 145.

[0146] In some embodiments, after forming the fourth source / drain structure 142, a dielectric layer material may be deposited on the fourth source / drain structure 142 to form the fourth interlayer dielectric layer 143 of the fourth transistor 14. Subsequently, a reverse dielectric layer 147 may be deposited on the fourth interlayer dielectric layer 143, and vias may be made in the reverse dielectric layer 147 and the fourth interlayer dielectric layer 143 until the fourth source / drain structure 142 is exposed. Subsequently, a metal material may be deposited on the fourth source / drain structure 142 until the fourth source / drain metal 145 is formed, see below. Figure 25 As shown.

[0147] In some embodiments, steps S205 to S206 can be performed simultaneously with the fabrication of the third source / drain metal 135. At this time, a first transistor 11, a second transistor 12, and a third transistor 13 are formed in the stacked transistor 10. Therefore, the isolation structure (i.e., the second isolation structure 40) located between the second transistor 12 and the third transistor 13 can be etched to form a second via. Then, metal material is deposited within the second via to form a second interconnect via structure 52 capable of connecting the source / drain metal (third source / drain metal 135) of the third transistor 13 and the source / drain metal (second source / drain metal 125) of the second transistor 12. See [link to documentation]. Figure 24 As shown.

[0148] Understandably, the projection of the second via along the first direction falls within the projection of the third source / drain metal 135 and the second source / drain metal 125 along the first direction, so that the second interconnecting via structure 52 formed according to the second via can connect the third source / drain metal 135 and the second source / drain metal 125.

[0149] In some embodiments, a second via is formed by sequentially etching the first interlayer dielectric layer 113 and the first isolation structure 28 until the second source / drain metal 125 is exposed.

[0150] In some embodiments, forming a third source / drain metal 135 on the third source / drain structure 132 includes: depositing a dielectric material on the third source / drain structure 132 to form a third interlayer dielectric layer 133, and etching the third interlayer dielectric layer 133 until the third source / drain structure 132 is exposed to form a third source / drain metal groove. Then, depositing metal material in the second via to form a second interconnect via structure 52 may include: depositing metal material in the third source / drain metal groove and the second via to form the third source / drain metal 135 and the second interconnect via structure 52, respectively.

[0151] Understandably, the third source / drain metal groove and the second via can be formed through etching. Subsequently, metal material can be deposited in the third source / drain metal groove and the second via using the same deposition process, thus simultaneously forming the third source / drain metal 135 and the second interconnect via structure 52. In this way, the third source / drain metal 135 and the second interconnect via structure 52 are integrally formed, reducing the complexity of the fabrication process.

[0152] In some embodiments, steps S205 to S206 can be performed simultaneously with the fabrication of the fourth source / drain metal 145. At this time, a first transistor 11, a second transistor 12, a third transistor 13, and a fourth transistor 14 are formed in the stacked transistor 10. Therefore, the isolation structure (i.e., the third isolation structure 34) located between the fourth transistor 14 and the third transistor 13 can be etched to form a third via. Then, metal material is deposited within the third via to form a third interconnect via structure 53 capable of connecting the source / drain metal (third source / drain metal 135) of the third transistor 13 and the source / drain metal (fourth source / drain metal 145) of the fourth transistor 14. See [link to documentation]. Figure 25 As shown.

[0153] Understandably, the projection of the third via along the first direction falls within the projection of the third source / drain metal 135 and the fourth source / drain metal 145 along the first direction, so that the third interconnecting via structure 53 formed by the third via can connect the third source / drain metal 135 and the fourth source / drain metal 145.

[0154] In some embodiments, a third via is formed by sequentially etching the fourth interlayer dielectric layer 143 and the third isolation structure 34 until the third source / drain metal 135 is exposed.

[0155] In some embodiments, forming a fourth source / drain metal 145 over the fourth source / drain structure 142 includes: depositing a dielectric material over the fourth source / drain structure 142 to form a fourth interlayer dielectric layer 143, and etching the fourth interlayer dielectric layer 143 until the fourth source / drain structure 142 is exposed to form a fourth source / drain metal recess. Similarly, depositing metal material in the third via to form a third interconnect via structure 53 may include: depositing metal material in the fourth source / drain metal recess and the third via to form the fourth source / drain metal 145 and the third interconnect via structure 53, respectively.

[0156] Understandably, the fourth source / drain metal groove and the third via can be formed through etching. Subsequently, metal material can be deposited in the fourth source / drain metal groove and the third via using the same deposition process, thus simultaneously forming the fourth source / drain metal 145 and the third interconnect via structure 53. In this way, the fourth source / drain metal 145 and the third interconnect via structure 53 are integrally formed, reducing the complexity of the fabrication process.

[0157] In some embodiments, after forming the fourth gate structure 144 and the fourth source / drain metal 145, a reverse metal interconnect layer 1021 of the reverse vertical stacked transistor 102 can be formed on the fourth source / drain metal 145 and the fourth gate structure 144 using standard back-end semiconductor fabrication processes (such as inter-interconnect dielectric deposition, metal line formation, lead-out pad formation, etc.).

[0158] It should be noted that the process for forming the reverse vertical stacked transistor 102 can refer to the description of one or more processes for forming the front vertical stacked transistor 101 mentioned above. For the sake of brevity, it will not be repeated here.

[0159] This completes the fabrication of stacked transistor 10.

[0160] In this embodiment, by forming an active structure of a certain depth on a semiconductor substrate, the active regions of multiple transistors arranged along a first direction in a vertically stacked manner can be self-aligned. Subsequently, a first transistor and a second transistor with different polarities, vertically stacked along the first direction, can be fabricated based on a first portion of the active structure. After wafer flipping, the semiconductor substrate is etched so that a third transistor and a fourth transistor with different polarities, vertically stacked along the first direction, can be fabricated based on a second portion of the active structure. It is evident that by forming a pair of stacked transistors on the front side of the wafer and another pair on the back side, more transistors can be fabricated using both sides of the wafer, thereby increasing the transistor integration density and further improving the transistor integration performance. Finally, by etching the isolation structure between any two transistors among the first, second, third, and fourth transistors, an interconnect via structure is formed, allowing the isolation structure between any two transistors to be penetrated. This interconnect via structure and the source / drain metal of any two transistors enable communication in the first direction, facilitating the large-scale integration of stacked transistors.

[0161] The interconnect via structure in the stacked transistor 10 is described below. Figure 26 This is a schematic diagram illustrating a stacked transistor structure according to an embodiment of this application. It will be understood that... Figure 26 The diagram shows along Figure 1 A cross-sectional view along the direction of the dashed line BB'. A fourth interconnect via structure 54, a fifth interconnect via structure 55, and a sixth interconnect via structure 56 can also be formed in the stacked transistor 10.

[0162] In some possible implementations, steps S205 to S206 can be performed simultaneously with the fabrication of the third source / drain metal 135. At this time, the first transistor 11, the second transistor 12, and the third transistor 13 are fabricated and formed in the stacked transistor 10; therefore, see [link to relevant documentation]. Figure 26As shown in (a), the isolation structure (i.e., the second isolation structure 40) located between the second transistor 12 and the third transistor 13 and the isolation structure (i.e., the first isolation structure 28) between the second transistor 12 and the first transistor 11 can be etched to form a fourth via; then, metal material is deposited in the fourth via to form a fourth interconnect via structure 54 that can connect the source and drain metal (third source and drain metal 135) of the third transistor 13 and the source and drain metal (first source and drain metal 115) of the first transistor 11.

[0163] Understandably, the projection of the fourth via along the first direction falls within the projections of the first source / drain metal 115 and the third source / drain metal 135 along the first direction, enabling the fourth interconnecting via structure 54 formed based on the fourth via to connect the third source / drain metal 135 and the first source / drain metal 115. Understandably, to form the fourth via, when fabricating the second source / drain metal 125, the width of the projection of the second source / drain metal 125 along the first direction should be controlled so that the projection of the fourth via along the first direction falls within the projections of the third source / drain metal 135 and the first source / drain metal 115 along the first direction, but not within the projection of the second source / drain metal 125 along the first direction. This ensures that the first source / drain metal 115 can be perpendicularly interconnected with the third source / drain metal 135.

[0164] In some embodiments, a fourth via is formed by sequentially etching the third interlayer dielectric layer 133, the second isolation structure 40, the second interlayer dielectric layer 123, the first isolation structure 28, and the first interlayer dielectric layer 113 until the first source / drain metal 115 is exposed.

[0165] In some embodiments, forming a third source / drain metal 135 on the third source / drain structure 132 includes: depositing a dielectric material on the third source / drain structure 132 to form a third interlayer dielectric layer 133, and etching the third interlayer dielectric layer 133 until the third source / drain structure 132 is exposed to form a third source / drain metal groove. Then, depositing metal material in the fourth via to form a fourth interconnect via structure 54 may include: depositing metal material in the third source / drain metal groove and the fourth via to form the third source / drain metal 135 and the fourth interconnect via structure 54, respectively.

[0166] Understandably, the third source / drain metal groove and the fourth interconnect via can be formed through etching. Subsequently, metal material can be deposited in the third source / drain metal groove and the fourth interconnect via using the same deposition process, thus simultaneously forming the third source / drain metal 135 and the fourth interconnect via structure 54. In this way, the third source / drain metal 135 and the fourth interconnect via structure 54 are integrally formed, reducing the complexity of the fabrication process.

[0167] In some possible implementations, steps S205 to S206 can be performed simultaneously with the fabrication of the fourth source / drain metal 145. At this time, the first transistor 11, the second transistor 12, the third transistor 13, and the fourth transistor 14 are fabricated and formed in the stacked transistor 10. Therefore, see [link to relevant documentation]. Figure 26 As shown in (b), the isolation structure (i.e., the third isolation structure 34) located between the fourth transistor 14 and the third transistor 13 and the isolation structure (i.e., the second isolation structure 40) between the third transistor 13 and the second transistor 12 can be etched to form a fifth via; then, metal material is deposited in the fifth via to form a fifth interconnect via structure 55 that can connect the source and drain metal (second source and drain metal 125) of the second transistor 12 and the source and drain metal (fourth source and drain metal 145) of the fourth transistor 14.

[0168] Understandably, the projection of the fifth via along the first direction falls within the projections of the second source / drain metal 125 and the fourth source / drain metal 145 along the first direction, enabling the fifth interconnecting via structure 55 formed based on the fifth via to connect the second source / drain metal 125 and the fourth source / drain metal 145. Understandably, to form the fifth via, when fabricating the third source / drain metal 135, the width of the projection of the third source / drain metal 135 along the first direction should be controlled so that the projection of the fifth via along the first direction falls within the projections of the second source / drain metal 125 and the fourth source / drain metal 145 along the first direction, but not within the projection of the third source / drain metal 135 along the first direction. This ensures that the second source / drain metal 125 and the fourth source / drain metal 145 are vertically interconnected.

[0169] In some embodiments, a fifth via is formed by sequentially etching the fourth interlayer dielectric layer 143, the third isolation structure 34, the third interlayer dielectric layer 133, the second isolation structure 40, and the second interlayer dielectric layer 123 until the second source / drain metal 125 is exposed.

[0170] In some embodiments, forming a fourth source / drain metal 145 over the fourth source / drain structure 142 includes: depositing a dielectric material over the fourth source / drain structure 142 to form a fourth interlayer dielectric layer 143, and etching the fourth interlayer dielectric layer 143 until the fourth source / drain structure 142 is exposed to form a fourth source / drain metal recess. Similarly, depositing metal material in a fifth via to form a fifth interconnect via structure 55 may include: depositing metal material in the fourth source / drain metal recess and the fifth via to form the fourth source / drain metal 145 and the fifth interconnect via structure 55, respectively.

[0171] Understandably, the fourth source / drain metal groove and the fifth via can be formed through etching. Subsequently, metal material can be deposited in the fourth source / drain metal groove and the fifth via using the same deposition process, thus simultaneously forming the fourth source / drain metal 145 and the fifth interconnect via structure 55. In this way, the fourth source / drain metal 145 and the fifth interconnect via structure 55 are integrally formed, reducing the complexity of the fabrication process.

[0172] In some possible implementations, steps S205 to S206 can be performed simultaneously with the fabrication of the fourth source / drain metal 145. At this time, the first transistor 11, the second transistor 12, the third transistor 13, and the fourth transistor 14 are fabricated and formed in the stacked transistor 10. Therefore, Figure 26 As shown in (c), the isolation structure (i.e., the third isolation structure 34) between the fourth transistor 14 and the third transistor 13, the isolation structure (i.e., the second isolation structure 40) between the third transistor 13 and the second transistor 12, and the isolation structure (i.e., the first isolation structure 28) between the second transistor 12 and the first transistor 11 can be etched to form a sixth via; then, metal material is deposited in the sixth via to form a sixth interconnect via structure 56 that can connect the source / drain metal (first source / drain metal 115) of the first transistor 11 and the source / drain metal (fourth source / drain metal 145) of the fourth transistor 14.

[0173] Understandably, the projection of the sixth via along the first direction falls within the projections of the first source / drain metal 115 and the fourth source / drain metal 145 along the first direction, enabling the sixth interconnecting via structure 56 formed based on the sixth via to connect the first source / drain metal 115 and the fourth source / drain metal 145. Understandably, to form the sixth via, when fabricating the third source / drain metal 135 and the second source / drain metal 125, the widths of their projections along the first direction should be controlled so that the projection of the sixth via along the first direction falls within the projections of the first source / drain metal 115 and the fourth source / drain metal 145 along the first direction, but not within the projections of the third source / drain metal 135 and the second source / drain metal 125 along the first direction. This ensures that the first source / drain metal 115 and the fourth source / drain metal 145 are vertically interconnected.

[0174] In some embodiments, a sixth via is formed by sequentially etching the fourth interlayer dielectric layer 143, the third isolation structure 34, the third interlayer dielectric layer 133, the second isolation structure 40, the second interlayer dielectric layer 123, the first isolation structure 28, and the first interlayer dielectric layer 113 until the first source / drain metal 115 is exposed.

[0175] In some embodiments, forming a fourth source / drain metal 145 over the fourth source / drain structure 142 includes: depositing a dielectric material over the fourth source / drain structure 142 to form a fourth interlayer dielectric layer 143, and etching the fourth interlayer dielectric layer 143 until the fourth source / drain structure 142 is exposed to form a fourth source / drain metal recess. Similarly, depositing metal material in the sixth via to form a sixth interconnect via structure 56 may include: depositing metal material in the fourth source / drain metal recess and the sixth via to form the fourth source / drain metal 145 and the sixth interconnect via structure 56, respectively.

[0176] Understandably, the fourth source / drain metal groove and the sixth interconnect via can be formed through etching. Subsequently, metal material can be deposited in the fourth source / drain metal groove and the sixth interconnect via using the same deposition process, thus simultaneously forming the fourth source / drain metal 145 and the sixth interconnect via structure 56. In this way, the fourth source / drain metal 145 and the sixth interconnect via structure 56 are integrally formed, reducing the complexity of the fabrication process.

[0177] Similarly, see Figure 26 As shown in (d) to (f), the stacked transistor 10 further includes: a first interconnect via structure 51, a second interconnect via structure 52, and a third interconnect via structure 53. The formation process of the first interconnect via structure 51, the second interconnect via structure 52, and the third interconnect via structure 53 can be referred to the description in one or more of the above embodiments, and will not be repeated here for the sake of brevity.

[0178] It should be noted that the stacked transistor 10 may include at least one of the above-mentioned first interconnect via structure 51, second interconnect via structure 52, third interconnect via structure 53, fourth interconnect via structure 54, fifth interconnect via structure 55, and sixth interconnect via structure 56. When the stacked transistor 10 includes multiple interconnect via structures among the first interconnect via structure 51, second interconnect via structure 52, third interconnect via structure 53, fourth interconnect via structure 54, fifth interconnect via structure 55, and sixth interconnect via structure 56, the multiple interconnect via structures may be arranged at intervals in the second direction to avoid mutual interference. In some embodiments, one or more of the multiple interconnect via structures may be located on the first side of the source / drain structure (e.g., the first source / drain structure 112) in the stacked transistor 10, and the multiple interconnect via structures other than the one or more interconnect via structures mentioned above may be located on the second side of the first source / drain structure 112. The first side and the second side may be two opposite sides of the first source / drain structure 112 in the second direction.

[0179] In some embodiments, to avoid having too many interconnect via structures in the stacked transistor 10, thereby increasing the volume of the stacked transistor 10 and reducing its integration level, the interconnect via structures in the stacked transistor 10 can be rationally planned to meet the needs of different logic circuits. Based on this, the stacked transistor 10 may include one of the following: a first group of interconnect via structures, a second group of interconnect via structures, a third group of interconnect via structures, a fourth group of interconnect via structures, a fifth group of interconnect via structures, a sixth group of interconnect via structures, a seventh group of interconnect via structures, and an eighth group of interconnect via structures. The first group of interconnect via structures includes: a first interconnect via structure 51 and a second interconnect via structure 52; the second group of interconnect via structures includes: a first interconnect via structure 51 and a third interconnect via structure 53; the third group of interconnect via structures includes: a first interconnect via structure 51, a second interconnect via structure 52 and a third interconnect via structure 53; the fourth group of interconnect via structures includes: a first interconnect via structure 51 and a fifth interconnect via structure 55; the fifth group of interconnect via structures includes: a second interconnect via structure 52 and a third interconnect via structure 53; the sixth group of interconnect via structures includes: a second interconnect via structure 52 and a sixth interconnect via structure 56; the seventh group of interconnect via structures includes: a third interconnect via structure 53 and a fourth interconnect via structure 54; and the eighth group of interconnect via structures includes: a fourth interconnect via structure 54 and a fifth interconnect via structure 55.

[0180] For example, Figure 27 This is a schematic diagram illustrating a stacked transistor structure according to an embodiment of this application. See also... Figure 27 As shown in (a), the stacked transistor 10 may include a first set of interconnect via structures, which consists of a first interconnect via structure 51 and a second interconnect via structure 52. The first interconnect via structure 51 connects to a first source / drain metal 115 and a second source / drain metal 125, respectively, and the second interconnect via structure 52 connects to the second source / drain metal 125 and a third source / drain metal 135. Therefore, the first set of interconnect via structures allows the first source / drain metal 115, the second source / drain metal 125, and the third source / drain metal 135 to be interconnected.

[0181] See Figure 27 As shown in (b), the stacked transistor 10 may include a second set of interconnect via structures, which consists of a first interconnect via structure 51 and a third interconnect via structure 53. The first interconnect via structure 51 connects to a first source / drain metal 115 and a second source / drain metal 125, respectively, and the third interconnect via structure 53 connects to a third source / drain metal 135 and a fourth source / drain metal 145. Therefore, the second set of interconnect via structures allows for communication between the first source / drain metal 115 and the second source / drain metal 125, as well as between the third source / drain metal 135 and the fourth source / drain metal 145.

[0182] See Figure 27 As shown in (c), the stacked transistor 10 may include a third set of interconnect via structures, which consists of a first interconnect via structure 51, a second interconnect via structure 52, and a third interconnect via structure 53. The first interconnect via structure 51 connects to the first source / drain metal 115 and the second source / drain metal 125, the second interconnect via structure 52 connects to the second source / drain metal 125 and the third source / drain metal 135, and the third interconnect via structure 53 connects to the third source / drain metal 135 and the fourth source / drain metal 145. Therefore, the third set of interconnect via structures allows the first source / drain metal 115, the second source / drain metal 125, the third source / drain metal 135, and the fourth source / drain metal 145 to be interconnected.

[0183] See Figure 27 As shown in (d), the stacked transistor 10 may include a fourth set of interconnect via structures, which consists of a first interconnect via structure 51 and a fifth interconnect via structure 55. The first interconnect via structure 51 connects to the first source / drain metal 115 and the second source / drain metal 125, respectively, and the fifth interconnect via structure 55 connects the second source / drain metal 125 and the fourth source / drain metal 145. Therefore, the fourth set of interconnect via structures allows the first source / drain metal 115, the second source / drain metal 125, and the fourth source / drain metal 145 to be interconnected.

[0184] See Figure 27 As shown in (e), the stacked transistor 10 may include a fifth set of interconnect via structures, which consists of a second interconnect via structure 52 and a third interconnect via structure 53. The second interconnect via structure 52 connects the second source / drain metal 125 and the third source / drain metal 135, and the third interconnect via structure 53 connects the third source / drain metal 135 and the fourth source / drain metal 145. Therefore, the fifth set of interconnect via structures allows the second source / drain metal 125, the third source / drain metal 135, and the fourth source / drain metal 145 to be interconnected.

[0185] See Figure 27 As shown in (f), the stacked transistor 10 may include a sixth set of interconnect via structures, which consists of a second interconnect via structure 52 and a sixth interconnect via structure 56. The second interconnect via structure 52 connects the second source / drain metal 125 and the third source / drain metal 135, and the sixth interconnect via structure 56 connects the first source / drain metal 115 and the fourth source / drain metal 145. Therefore, the sixth set of interconnect via structures enables communication between the first source / drain metal 115 and the fourth source / drain metal 145, as well as between the second source / drain metal 125 and the third source / drain metal 135.

[0186] See Figure 27 As shown in (g), the stacked transistor 10 may include a seventh set of interconnect via structures, which consists of a third interconnect via structure 53 and a fourth interconnect via structure 54. The third interconnect via structure 53 connects the third source / drain metal 135 and the fourth source / drain metal 145, and the fourth interconnect via structure 54 connects the first source / drain metal 115 and the third source / drain metal 135. Therefore, the seventh set of interconnect via structures allows the first source / drain metal 115, the third source / drain metal 135, and the fourth source / drain metal 145 to be interconnected.

[0187] See Figure 27 As shown in (h), the stacked transistor 10 may include an eighth set of interconnect via structures, which consists of a fourth interconnect via structure 54 and a fifth interconnect via structure 55. The fourth interconnect via structure 54 connects the first source / drain metal 115 and the third source / drain metal 135, and the fifth interconnect via structure 55 connects the second source / drain metal 125 and the fourth source / drain metal 145. Therefore, the seventh set of interconnect via structures enables the first source / drain metal 115 and the third source / drain metal 135 to be connected, as well as the second source / drain metal 125 and the fourth source / drain metal 145 to be connected.

[0188] It is understood that the first interconnect via structure 51, the second interconnect via structure 52, the third interconnect via structure 53, the fourth interconnect via structure 54, the fifth interconnect via structure 55, and the sixth interconnect via structure 56 described above can be prepared through the first via, the second via, the third via, the fourth via, the fifth via, and the sixth via, respectively. The preparation process of obtaining the first via, the second via, the third via, the fourth via, the fifth via, and the sixth via can be referred to the description in one or more of the above embodiments. For the sake of brevity, it will not be repeated here.

[0189] In the embodiments of this application, while retaining the advantages of flip-chip complementary stacked transistors (such as significantly increasing transistor integration density and taking into account issues such as consistency, defect density, and alignment of active regions of transistors on both sides), the mid-channel interconnect of flip-chip complementary stacked transistors is realized, creating conditions for realizing complex logic design and large-scale integration based on flip-chip complementary stacked transistors.

[0190] Secondly, in this disclosure, a stacked transistor 10 is provided, which can be employed as follows: Figures 3 to 25 Prepared by the method in one or more of the corresponding embodiments. See also Figure 25As shown, the stacked transistor 10 includes: a front-side vertically stacked transistor 101, including: a first transistor 11 and a second transistor 12, the first transistor 11 and the second transistor 12 have different polarities, and the first transistor 11 and the second transistor 12 are self-aligned in a first direction, which is a direction perpendicular to the semiconductor substrate.

[0191] The reverse vertically stacked transistor 102 includes a third transistor 13 and a fourth transistor 14, which have different polarities and are self-aligned in a first direction. The front vertically stacked transistor 101 and the reverse vertically stacked transistor 102 are arranged opposite to each other and are self-aligned in the first direction. An isolation structure exists between any two adjacent transistors among the first transistor 11, second transistor 12, third transistor 13, and fourth transistor 14.

[0192] For example, when the first transistor 11, the second transistor 12, the third transistor 13, and the fourth transistor 14 are arranged in the first direction as follows: Figure 25 As shown, there is a first isolation structure 28 between the first transistor 11 and the second transistor 12, a second isolation structure 40 between the second transistor 12 and the third transistor 13, and a third isolation structure 34 between the third transistor 13 and the fourth transistor 14.

[0193] The stacked transistor 10 further includes an interconnect via structure, wherein the interconnect via structure is used to connect the source and drain metals of any two of the first transistor 11, the second transistor 12, the third transistor 13, and the fourth transistor 14 through a through-isolation structure.

[0194] For example, see Figure 25 As shown, the first interconnect via structure 51 connects the first source / drain metal 115 and the second source / drain metal 125. The second interconnect via structure 52 connects the second source / drain metal 125 and the third source / drain metal 135. The third interconnect via structure 53 connects the third source / drain metal 135 and the fourth source / drain metal 145.

[0195] In some embodiments, the first transistor 11, the second transistor 12, the third transistor 13, and the fourth transistor 14 are arranged sequentially along a first direction; the interconnect via structure includes at least one of the following: a first interconnect via structure 51, a second interconnect via structure 52, a third interconnect via structure 53, a fourth interconnect via structure 54, a fifth interconnect via structure 55, and a sixth interconnect via structure 56; wherein the first interconnect via structure 51 is used to connect the first source / drain metal 115 and the second source / drain metal 125; the second interconnect via structure 52 is used to connect the second source / drain metal 125 and the third source / drain metal 135; the third interconnect via structure 53 is used to connect the third source / drain metal 135 and the fourth source / drain metal 145; the fourth interconnect via structure 54 is used to connect the first source / drain metal and the third source / drain metal 135; the fifth interconnect via structure 55 is used to connect the second source / drain metal 125 and the fourth source / drain metal 145; and the sixth interconnect via structure 56 is used to connect the first source / drain metal and the fourth source / drain metal 145.

[0196] It is understood that the specific structures of the first interconnect via structure 51, the second interconnect via structure 52, the third interconnect via structure 53, the fourth interconnect via structure 54, the fifth interconnect via structure 55, and the sixth interconnect via structure 56 can be found in [reference needed]. Figures 25 to 26 The descriptions of one or more embodiments shown are omitted here for the sake of brevity.

[0197] In some embodiments, the first transistor, the second transistor, the third transistor, and the fourth transistor are arranged sequentially along a first direction; the stacked transistor 10 includes one of the following: a first group of interconnect via structures, a second group of interconnect via structures, a third group of interconnect via structures, a fourth group of interconnect via structures, a fifth group of interconnect via structures, a sixth group of interconnect via structures, a seventh group of interconnect via structures, and an eighth group of interconnect via structures. The first group of interconnect via structures includes: a first interconnect via structure 51 and a second interconnect via structure 52; the second group of interconnect via structures includes: a first interconnect via structure 51 and a third interconnect via structure 53; the third group of interconnect via structures includes: a first interconnect via structure 51, a second interconnect via structure 52 and a third interconnect via structure 53; the fourth group of interconnect via structures includes: a first interconnect via structure 51 and a fifth interconnect via structure 55; the fifth group of interconnect via structures includes: a second interconnect via structure 52 and a third interconnect via structure 53; the sixth group of interconnect via structures includes: a second interconnect via structure 52 and a sixth interconnect via structure 56; the seventh group of interconnect via structures includes: a third interconnect via structure 53 and a fourth interconnect via structure 54; and the eighth group of interconnect via structures includes: a fourth interconnect via structure 54 and a fifth interconnect via structure 55.

[0198] Specifically, the first interconnect via structure 51 is used to connect the first source / drain metal 115 and the second source / drain metal 125; the second interconnect via structure 52 is used to connect the second source / drain metal 125 and the third source / drain metal 135; the third interconnect via structure 53 is used to connect the third source / drain metal 135 and the fourth source / drain metal 145; the fourth interconnect via structure 54 is used to connect the first source / drain metal and the third source / drain metal 135; the fifth interconnect via structure 55 is used to connect the second source / drain metal 125 and the fourth source / drain metal 145; and the sixth interconnect via structure 56 is used to connect the first source / drain metal and the fourth source / drain metal 145.

[0199] It is understandable that the specific structures of the first, second, third, fourth, fifth, sixth, seventh, and eighth interconnect via structures can be found in [reference needed]. Figure 27 The descriptions of one or more embodiments shown are omitted here for the sake of brevity.

[0200] It is understood that the stacked transistors in the embodiments of this application may employ... Figures 3 to 25 The stacked transistors are fabricated using the methods described in one or more of the corresponding embodiments. In this application, a front-side vertically stacked transistor (FSTP) is formed on the front side of the wafer, comprising two stacked transistors, and a back-side vertically stacked transistor (SSTP) is formed on the back side of the wafer, comprising two stacked transistors, thereby further enhancing the integration performance of the stacked transistors.

[0201] Furthermore, by realizing the mid-channel interconnect of flip-chip complementary stacked transistors, and based on the independent signal and power supply networks of the front and back transistors, greater flexibility and feasibility are available in circuit design, with great potential for collaborative optimization in process design. At the same time, this mid-channel interconnect scheme is compatible with existing mainstream device architectures and manufacturing processes (photolithography, high selectivity etching, etc.), enabling front and back stacking and mid-channel interconnection of planar transistors, FinFETs, GAA Nanosheets, and even vertical transistors (VTFETs) and CFETs, without requiring additional special process development. It offers high flexibility and strong scalability from the perspective of semiconductor process node iteration, which is significant for the further extension of Moore's Law and has important industrial value and practical prospects.

[0202] Thirdly, embodiments of this application provide a semiconductor device, including: a stacked transistor as described in the above embodiments. Specific limitations of the stacked transistor can be found at least in the above description. Figures 25 to 27 The stacked transistors shown will not be described in detail here.

[0203] Fourthly, embodiments of this application provide an electronic device, including: a circuit board and a semiconductor device as described in the above embodiments, the semiconductor device being disposed on the circuit board. The semiconductor device includes the stacked transistors described above. Specific limitations of the stacked transistors can be found at least in the above description. Figures 25 to 27 The structure shown will not be elaborated upon here.

[0204] In the description of this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments of this application. In this application, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine the different embodiments or examples described in this application, as well as the features of the different embodiments or examples.

[0205] The above are merely preferred embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for fabricating stacked transistors, characterized in that, The method includes: An active structure is formed on a semiconductor substrate, the active structure comprising a first part and a second part; Based on the first portion, a first transistor and a second transistor are formed stacked along a first direction, wherein the first transistor and the second transistor have opposite polarities; the first direction is a direction perpendicular to the semiconductor substrate; The semiconductor substrate is then poured and removed. Based on the second part, a third transistor and a fourth transistor are formed stacked along the first direction, wherein the third transistor and the fourth transistor have opposite polarities; an isolation structure exists between any two adjacent transistors among the first transistor, the second transistor, the third transistor, and the fourth transistor; Etching is performed between any two transistors to be interconnected among the first transistor, the second transistor, the third transistor, and the fourth transistor to form a via, wherein at least one transistor is present between any two transistors to be interconnected; the at least one transistor includes the second transistor and / or the third transistor; the projection of the via along the first direction falls within the projection of the source and drain metals of the any two transistors to be interconnected along the first direction, and the projection of the via along the first direction does not fall within the projection of the source and drain metals of the at least one transistor along the first direction; Metal material is deposited in the via to form an interconnect via structure, wherein the interconnect via structure includes at least one of a fourth interconnect via structure, a fifth interconnect via structure, and a sixth interconnect via structure, which are used to realize source-drain metal interconnects between a first transistor and a third transistor, a second transistor and a fourth transistor, and a first transistor and a fourth transistor, respectively.

2. The preparation method according to claim 1, characterized in that, The formation of a first transistor and a second transistor stacked along a first direction based on the first portion includes: An insulating material is deposited on the semiconductor substrate to form an initial isolation structure, wherein the initial isolation structure surrounds the second portion, and the first portion is exposed outside the initial isolation structure; Based on the first part, a second source / drain structure, a second interlayer dielectric layer, and a second gate structure are formed on the initial isolation structure; wherein, the second interlayer dielectric layer encapsulates the second source / drain structure; A second source / drain metal is formed on top of the second source / drain structure; An insulating material is deposited on the second source / drain metal to form a first isolation structure; On top of the first isolation structure, based on the first portion, a first source / drain structure, a first interlayer dielectric layer, and a first gate structure are formed; wherein, the first interlayer dielectric layer encapsulates the first source / drain structure; A first source / drain metal is formed on top of the first source / drain structure.

3. The preparation method according to claim 2, characterized in that, The formation of a third and fourth transistor stacked along the first direction based on the second portion includes: The initial isolation structure is thinned to form a second isolation structure between the second transistor and the third transistor; Based on the second part, a third source / drain structure, a third interlayer dielectric layer, and a third gate structure are formed on the second isolation structure; wherein, the third interlayer dielectric layer encapsulates the third source / drain structure; A third source / drain metal is formed on the third source / drain structure; An insulating material is deposited on the third source / drain metal to form a third isolation structure; On top of the third isolation structure, based on the first portion, a fourth source / drain structure, a fourth interlayer dielectric layer, and a fourth gate structure are formed; wherein, the fourth interlayer dielectric layer encapsulates the fourth source / drain structure; A fourth source / drain metal is formed on the fourth source / drain structure; The first isolation structure, the second isolation structure, and the third isolation structure are included in the isolation structure.

4. The preparation method according to claim 3, characterized in that, The etching of the isolation structure between any two transistors to be interconnected among the first transistor, the second transistor, the third transistor, and the fourth transistor to form a via includes at least one of the following: The third interlayer dielectric layer, the second isolation structure, the second interlayer dielectric layer, the first isolation structure, and the first interlayer dielectric layer are etched sequentially until the first source / drain metal is exposed to form a fourth via. The fourth interlayer dielectric layer, the third isolation structure, the third interlayer dielectric layer, the second isolation structure, and the second interlayer dielectric layer are etched sequentially until the second source / drain metal is exposed to form the fifth via. The fourth interlayer dielectric layer, the third isolation structure, the third interlayer dielectric layer, the second isolation structure, the second interlayer dielectric layer, the first isolation structure, and the first interlayer dielectric layer are etched sequentially until the first source / drain metal is exposed to form the sixth via.

5. The preparation method according to claim 4, characterized in that, The etching of the isolation structure between any two transistors to be interconnected among the first transistor, the second transistor, the third transistor, and the fourth transistor to form a via further includes at least one of the following: The first interlayer dielectric layer and the first isolation structure are etched sequentially until the second source / drain metal is exposed to form the first via. The third interlayer dielectric layer and the second isolation structure are etched sequentially until the second source / drain metal is exposed to form a second via; The fourth interlayer dielectric layer and the third isolation structure are etched sequentially until the third source / drain metal is exposed to form a third via.

6. The preparation method according to claim 3, characterized in that, The etching of the isolation structure and interlayer dielectric structure between any two transistors to be interconnected among the first transistor, the second transistor, the third transistor, and the fourth transistor to form vias includes any one of the following: The first interlayer dielectric layer and the first isolation structure are etched sequentially until the second source / drain metal is exposed to form a first via, and the fourth interlayer dielectric layer, the third isolation structure, the third interlayer dielectric layer, the second isolation structure, and the second interlayer dielectric layer are etched sequentially until the second source / drain metal is exposed to form a fifth via. The third interlayer dielectric layer and the second isolation structure are etched sequentially until the second source / drain metal is exposed to form a second via, and the fourth interlayer dielectric layer, the third isolation structure, the third interlayer dielectric layer, the second isolation structure, the second interlayer dielectric layer, the first isolation structure, and the first interlayer dielectric layer are etched sequentially until the first source / drain metal is exposed to form a sixth via; The fourth interlayer dielectric layer and the third isolation structure are etched sequentially until the third source / drain metal is exposed to form a third via, and the third interlayer dielectric layer, the second isolation structure, the second interlayer dielectric layer, the first isolation structure and the first interlayer dielectric layer are etched sequentially until the first source / drain metal is exposed to form a fourth via. The third interlayer dielectric layer, the second isolation structure, the second interlayer dielectric layer, the first isolation structure, and the first interlayer dielectric layer are etched sequentially until the first source / drain metal is exposed to form a fourth via, and the fourth interlayer dielectric layer, the third isolation structure, the third interlayer dielectric layer, the second isolation structure, and the second interlayer dielectric layer are etched sequentially until the second source / drain metal is exposed to form a fifth via.

7. The preparation method according to claim 5 or 6, characterized in that, The deposition of metallic material in the vias to form an interconnected via structure includes at least one of the following: Metal material is deposited in the first via to form a first interconnect via structure, wherein the first interconnect via structure is used to connect the first source / drain metal and the second source / drain metal; Metal material is deposited in the second via to form a second interconnect via structure, wherein the second interconnect via structure is used to connect the second source / drain metal and the third source / drain metal; Metal material is deposited in the third via to form a third interconnect via structure, wherein the third interconnect via structure is used to connect the third source / drain metal and the fourth source / drain metal; Metal material is deposited in the fourth via to form a fourth interconnect via structure, wherein the fourth interconnect via structure is used to connect the first source / drain metal and the third source / drain metal; Metal material is deposited in the fifth via to form a fifth interconnect via structure, wherein the fifth interconnect via structure is used to connect the second source / drain metal and the fourth source / drain metal; Metal material is deposited in the sixth via to form a sixth interconnect via structure, wherein the sixth interconnect via structure is used to connect the first source / drain metal and the fourth source / drain metal.

8. The preparation method according to claim 7, characterized in that, The formation of the first source / drain metal on the first source / drain structure includes: A dielectric material is deposited on the first source / drain structure to form a first interlayer dielectric layer, and the first interlayer dielectric layer is etched until the first source / drain structure is exposed to form a first source / drain metal groove. The step of depositing metallic material in the first via to form a first interconnect via structure includes: Metal material is deposited in the first source / drain metal groove and the first via to form the first source / drain metal and the first interconnect via structure, respectively.

9. The preparation method according to claim 7, characterized in that, The formation of the third source / drain metal on the third source / drain structure includes: A dielectric material is deposited on the third source / drain structure to form a third interlayer dielectric layer, and the third interlayer dielectric layer is etched until the third source / drain structure is exposed to form a third source / drain metal groove. The deposition of metallic material in the second via to form a second interconnect via structure includes: Metal material is deposited in the third source / drain metal groove and the second via to form the third source / drain metal and the second interconnect via structure, respectively; The deposition of metallic material in the fourth via to form a fourth interconnect via structure includes: Metal material is deposited in the third source / drain metal groove and the fourth interconnect via to form the third source / drain metal and the fourth interconnect via structure, respectively.

10. The preparation method according to claim 7, characterized in that, The formation of the fourth source / drain metal on the fourth source / drain structure includes: A dielectric material is deposited on the fourth source / drain structure to form a fourth interlayer dielectric layer, and the fourth interlayer dielectric layer is etched until the fourth source / drain structure is exposed to form a fourth source / drain metal recess. The deposition of metallic material in the third via to form a third interconnect via structure includes: Metal material is deposited in the fourth source / drain metal groove and the third interconnect via to form the fourth source / drain metal and the third interconnect via structure, respectively; The deposition of metallic material in the fifth via to form a fifth interconnect via structure includes: Metal material is deposited in the fourth source / drain metal groove and the fifth interconnect via to form the fourth source / drain metal and the fifth interconnect via structure, respectively; The deposition of metallic material in the sixth via to form the sixth interconnect via structure includes: Metal material is deposited in the fourth source / drain metal groove and the sixth interconnect via to form the fourth source / drain metal and the sixth interconnect via structure, respectively.

11. A stacked transistor, fabricated using the fabrication method according to any one of claims 1 to 10, characterized in that, The stacked transistors include: A first transistor and a second transistor are stacked along a first direction, wherein the first transistor and the second transistor have different polarities; A third transistor and a fourth transistor are stacked along the first direction, the third transistor and the fourth transistor having different polarities; an isolation structure exists between any two adjacent transistors among the first transistor, the second transistor, the third transistor and the fourth transistor; the first transistor, the second transistor, the third transistor and the fourth transistor are arranged sequentially along the first direction; An interconnect via structure, wherein each of the interconnect via structures is configured to connect the source and drain metals of two of the first transistor, the second transistor, the third transistor, and the fourth transistor by passing through the isolation structure; the interconnect via structure includes at least one of a fourth interconnect via structure, a fifth interconnect via structure, and a sixth interconnect via structure; the fourth interconnect via structure is configured to connect the first source and drain metal of the first transistor and the third source and drain metal of the third transistor; the fifth interconnect via structure is configured to connect the second source and drain metal of the second transistor and the fourth source and drain metal of the fourth transistor; and the sixth interconnect via structure is configured to connect the first source and drain metal of the first transistor and the fourth source and drain metal of the fourth transistor.

12. The stacked transistor according to claim 11, characterized in that, The interconnect via structure further includes at least one of a first interconnect via structure, a second interconnect via structure, and a third interconnect via structure; Wherein, the first interconnect via structure is used to connect the first source / drain metal of the first transistor and the second source / drain metal of the second transistor; the second interconnect via structure is used to connect the second source / drain metal of the second transistor and the third source / drain metal of the third transistor; the third interconnect via structure is used to connect the third source / drain metal of the third transistor and the fourth source / drain metal of the fourth transistor.

13. The stacked transistor according to claim 11, characterized in that, The interconnect via structure includes any one of the following: First interconnect via structure and fifth interconnect via structure; The second interconnect via structure and the sixth interconnect via structure; Third interconnect via structure and fourth interconnect via structure; The fourth interconnect via structure and the fifth interconnect via structure; Wherein, the first interconnect via structure is used to connect the first source / drain metal of the first transistor and the second source / drain metal of the second transistor; the second interconnect via structure is used to connect the second source / drain metal of the second transistor and the third source / drain metal of the third transistor; the third interconnect via structure is used to connect the third source / drain metal of the third transistor and the fourth source / drain metal of the fourth transistor; the fourth interconnect via structure is used to connect the first source / drain metal of the first transistor and the third source / drain metal of the third transistor; the fifth interconnect via structure is used to connect the second source / drain metal of the second transistor and the fourth source / drain metal of the fourth transistor; and the sixth interconnect via structure is used to connect the first source / drain metal of the first transistor and the fourth source / drain metal of the fourth transistor.

14. The stacked transistor according to claim 12 or 13, characterized in that, The first interconnect via structure, the second interconnect via structure, the third interconnect via structure, the fourth interconnect via structure, the fifth interconnect via structure, and the sixth interconnect via structure are located on the first side or the second side of the first source-drain structure of the first transistor in the second direction. Wherein, the first side and the second side are two sides opposite to the first source-drain structure, and the second direction is perpendicular to the first direction.

15. A semiconductor device, characterized in that, include: The stacked transistor as described in any one of claims 11 to 14.

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