Semiconductor structure and method of manufacturing the same

Abstract

The application provides a semiconductor structure and a preparation method thereof. The semiconductor structure comprises: a substrate layer; an N-type drift layer, the drift layer comprising an active region, a termination region and a transition region; a P-type main junction located in the termination region; a first P-type doped region located in the transition region, the first doped region having a doping concentration less than that of the main junction; and a gate structure comprising a gate dielectric layer and a gate electrode layer, the gate dielectric layer comprising a first part, a second part and a third part, the second part being located between the first part and the third part in a direction from the active region to the termination region, the second part being connected to the first part and the third part respectively, the first part being located on the active region, the second part being located on the transition region, the second part at the bottom of the gate electrode layer covering the first doped region, the third part being located on the main junction, and the thickness of the third part being greater than that of the first part.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor structure and its fabrication method. Background Technology

[0002] ESD (Electrostatic Discharge) damage to electronic products can be categorized into two types: sudden damage and latent damage. Sudden damage refers to severe damage to components, resulting in loss of function. This type of damage is usually detectable during quality inspection in the production process, primarily incurring rework and repair costs for the factory. Latent damage, on the other hand, refers to partial damage to components, where function is not yet lost and cannot be detected during production inspection. However, it can cause instability during use, leading to intermittent malfunctions and posing a greater threat to product quality. ESD is considered the biggest potential killer of electronic product quality, making ESD protection a crucial aspect of electronic product quality control. Summary of the Invention

[0003] The technical problem to be solved by this invention is how to improve the electrostatic discharge protection capability of semiconductor structures.

[0004] To address the aforementioned technical problems, this invention provides a semiconductor structure comprising: a substrate layer; an N-type drift layer including an active region, a termination region, and a transition region between the active region and the termination region; a P-type main junction located in the termination region of the drift layer; a first P-type doped region located in the transition region, wherein the doping concentration of the first doped region is less than the doping concentration of the main junction; and a gate structure located on the side of the drift layer away from the substrate layer. The gate structure comprises: a gate dielectric layer and a gate layer located on the side of the gate dielectric layer away from the drift layer. The gate dielectric layer includes a first portion, a second portion, and a third portion. The second portion is located between the first portion and the third portion in the direction from the active region to the termination region, and the second portion connects the first portion and the third portion. The first portion is located on the active region, the second portion is located on the transition region, the second portion at the bottom of the gate layer covers the first doped region, and the third portion is located on the main junction, wherein the thickness of the third portion is greater than the thickness of the first portion.

[0005] Optionally, the size of the first doped region in the direction from the transition region to the terminal region is 5 micrometers to 30 micrometers.

[0006] Optionally, the doping concentration of the first doped region is 5E16 atom / cm³. 3 -7E18atom / cm 3 The doping concentration of the main junction is 1E19 atom / cm³. 3 -1E20atom / cm3 .

[0007] Optionally, the semiconductor structure further includes: a P-type second doped region located between and adjacent to the first doped region, wherein the doping concentration of the second doped region is greater than that of the first doped region.

[0008] Optionally, the doping concentration of the second doped region is 1E19 atom / cm³. 3 -1E20atom / cm 3 .

[0009] Optionally, the semiconductor structure further includes: a plurality of spaced-apart P-type well regions located in the active region, wherein the drift layer between adjacent well regions is a JFET region; and an N-type source region located in the well region; wherein the gate layer on the active region extends from the JFET region to the source region.

[0010] This application also provides a method for fabricating a semiconductor structure, comprising: forming an N-type drift layer on one side of a substrate layer, the drift layer including an active region, a termination region, and a transition region located between the active region and the termination region; forming a P-type main junction in the termination region; forming a P-type first doped region in the transition region, the doping concentration of the first doped region being less than the doping concentration of the main junction; and forming a gate structure on the side of the drift layer away from the substrate layer; wherein the gate structure includes: a gate dielectric layer and a gate layer located on the side of the gate dielectric layer away from the drift layer, the gate dielectric layer including a first portion, a second portion, and a third portion, the second portion being located between the first portion and the third portion in the direction from the active region to the termination region, the second portion connecting the first portion and the third portion, the first portion being located on the active region, the second portion being located on the transition region, the second portion at the bottom of the gate layer covering the first doped region, the third portion being located on the main junction, and the thickness of the third portion being greater than the thickness of the first portion.

[0011] Optionally, it further includes: forming a second doped region of type P, the second doped region being located between and adjacent to the first doped region, the doping concentration of the second doped region being greater than the doping concentration of the first doped region.

[0012] Optionally, the step of forming the second doped region and the first doped region includes: forming a P-type initial doped region in the transition region; implanting N-type ions into a portion of the initial doped region, wherein the region of the initial doped region implanted with N-type ions forms the first doped region, and the remaining region of the initial doped region forms the second doped region.

[0013] Optionally, the main junction is formed during the formation of the initial doped region.

[0014] Optionally, it further includes: forming a plurality of spaced-apart P-type well regions in the active region, wherein the drift layer between adjacent well regions is a JFET region; forming an N-type source region in the well region; wherein the gate layer on the active region extends from the JFET region to the source region.

[0015] The technical solution of this application has the following technical effects:

[0016] The semiconductor structure provided by this invention has a third portion with a greater thickness than the first portion. A second portion connects the first and third portions, and the thickness variation in the second portion causes high internal stress. Since the doping concentration of the first p-type doped region is lower than that of the p-type main junction, the quality of the second portion covering the first doped region is improved, compensating for the impact of high internal stress on defects in the thickness variation region. Potential defects are less likely to form in the second portion during electrostatic discharge. In summary, this improves the electrostatic discharge protection capability of the semiconductor structure. Attached Figure Description

[0017] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 This is a three-dimensional schematic diagram of a semiconductor structure in related technologies;

[0019] Figure 2 This is a three-dimensional schematic diagram of a semiconductor structure in one embodiment of this application;

[0020] Figure 3 This is a top view of the main junction, first doped region, second doped region, well region, and JFET region in one embodiment of this application;

[0021] Figure 4 In one embodiment of this application Figure 3 A top view with a gate layer added to the base;

[0022] Figure 5 This is a top view of the gate dielectric layer in one embodiment of this application. Detailed Implementation

[0023] Semiconductor structures of related technologies, reference Figure 1The system includes: a substrate layer 100; a drift layer 110 located on one side of the substrate layer 100, the drift layer 110 including an active region A and a terminal region B adjacent to the active region A; a main junction 130 located in the terminal region B; a plurality of spaced well regions 120 located in the active region A, the well regions 120 being adjacent to the main junction 130, and the drift layer 110 between adjacent well regions 120 being a JFET region 121; and a gate structure including a gate dielectric layer 141 and a gate layer 142, the gate dielectric layer 141 including a first part, a second part, and a third part, the first part covering the active region A, the second part and the third part located on the main junction 130, the second part connecting the first part and the third part, the thickness of the third part being greater than the thickness of the first part, and the thickness of the second part gradually changing from the thickness of the first part to the thickness of the third part in the direction from the first part to the third part.

[0024] Research has revealed that the thickness of the second part gradually changes from that of the first part to that of the third part. This change in thickness causes greater internal stress and more growth defects in the second part. As a result, potential defects are more likely to form in the second part during electrostatic discharge, which reduces the electrostatic protection capability of the semiconductor structure.

[0025] Based on this, this application provides a semiconductor structure and its preparation method, which improves the electrostatic discharge protection capability of the semiconductor structure.

[0026] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0028] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can also refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0029] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0030] One embodiment of this application discloses a semiconductor structure, referencing... Figure 2 , Figure 3 and Figure 4 ,include:

[0031] Substrate layer 200;

[0032] The N-type drift layer 210 includes an active region A, a terminal region B1, and a transition region B2 located between the active region A and the terminal region B1.

[0033] The P-type main junction 250 is located in the terminal region B1 of the drift layer 210;

[0034] The first doped region 230 of the P-type located in the transition region B2 has a doping concentration that is less than that of the main junction 250.

[0035] A gate structure is located on the side of the drift layer 210 away from the substrate layer 200. The gate structure includes a gate dielectric layer 260 and a gate layer 270 located on the side of the gate dielectric layer 260 away from the drift layer 210. The gate dielectric layer 260 includes a first portion 2601, a second portion 2602, and a third portion 2603. The second portion 2602 is located between the first portion 2601 and the third portion 2603 in the direction from the active region A to the terminal region B1. The second portion 2602 connects the first portion 2601 and the third portion 2603. The first portion 2601 is located on the active region A, and the second portion 2602 is located on the transition region B2. The second portion 2602 at the bottom of the gate layer 270 covers the first doped region 230. The third portion 2603 is located on the main junction 250, and the thickness of the third portion 2603 is greater than the thickness of the first portion 2601.

[0036] In the direction from the first portion 2601 to the third portion 2603, the thickness of the second portion 2602 gradually changes from the thickness of the first portion 2601 to the thickness of the third portion 2603.

[0037] In this embodiment, the thickness variation region of the second portion 2602 causes high internal stress. Since the doping concentration of the first p-type doped region is lower than that of the p-type main junction, the quality of the second portion 2602 covering the first doped region 230 is improved, compensating for the impact of high internal stress on defects in the thickness variation region of the second portion 2602. Potential defects are less likely to form in the second portion 2602 during electrostatic discharge. In summary, the electrostatic discharge protection capability of the semiconductor structure is improved.

[0038] In this embodiment, the substrate layer 200 is silicon carbide (SiC) doped with N-type conductive ions.

[0039] In one embodiment, transition region B2 surrounds active region A, and terminal region B1 surrounds transition region B2.

[0040] The drift layer 210 has the same conductivity type as the substrate layer 200, and the doping concentration of the drift layer 210 is lower than that of the substrate layer 200. In one embodiment, the drift layer 210 is made of silicon carbide doped with N-type conductive ions. The N-type conductive ions can be phosphorus ions or nitrogen ions.

[0041] In one embodiment, the size of the first doped region 230 in the direction from the transition region B2 to the terminal region B1 is 5 micrometers to 30 micrometers, for example, 5 micrometers, 10 micrometers, 15 micrometers, 20 micrometers, 25 micrometers, or 30 micrometers. The first doped region 230 has sufficient size to be covered by the second portion 2602 in the direction from the transition region B2 to the terminal region B1.

[0042] If the doping concentration of the first doped region 230 is too low, it will be detrimental to improving the breakdown voltage of the semiconductor structure; if the doping concentration of the first doped region 230 is significantly higher than the doping concentration of the main junction 250, the improvement in the growth quality of the gate dielectric layer 260 covering the first doped region 230 will be relatively small. In one embodiment, the doping concentration of the first doped region 230 is 5E16 atom / cm². 3 -7E18atom / cm 3 The doping concentration of the main junction 250 is 1E19 atom / cm³. 3 -1E20atom / cm 3 .

[0043] In this embodiment, the semiconductor structure further includes a P-type second doped region 220, located between and adjacent to the first doped region 230, and the doping concentration of the second doped region 220 is greater than that of the first doped region 230. Preferably, the doping concentration of the second doped region 220 is 1E19 atom / cm³. 3 -1E20atom / cm 3 .

[0044] In one embodiment, the doping concentration of the second doped region 220 is equal to the doping concentration of the main junction 250. In other embodiments, the doping concentration of the second doped region 220 is greater than or less than the doping concentration of the main junction 250.

[0045] In the width direction of the gate layer 270, the size of the gate layer 270 is greater than, less than, or equal to the size of the first doped region 230. Preferably, in the width direction of the gate layer 270, the size of the first doped region 230 is greater than the size of the gate layer 270.

[0046] In this embodiment, the semiconductor structure further includes: a plurality of spaced-apart P-type well regions 280 located in the active region A, wherein the drift layer between adjacent well regions 280 is a JFET region 281; and an N-type source region (not shown) located in the well regions 280. The gate layer 270 on the active region A extends from the JFET region 281 to the source region. The doping concentration of the well regions 280 is less than the doping concentration of the second doped region 220 and less than the doping concentration of the main junction 250.

[0047] The doping concentration of the well region 280 can be greater than, equal to or less than the doping concentration of the first doping region 230.

[0048] Another embodiment of this application provides a method for fabricating a semiconductor structure, comprising: forming an N-type drift layer on one side of a substrate layer, the drift layer including an active region, a termination region, and a transition region located between the active region and the termination region; forming a P-type main junction in the termination region; forming a P-type first doped region in the transition region, the doping concentration of the first doped region being less than the doping concentration of the main junction; forming a gate structure on the side of the drift layer away from the substrate layer; wherein the gate structure includes: a gate dielectric layer and a gate layer located on the side of the gate dielectric layer away from the drift layer, the gate dielectric layer including a first portion, a second portion, and a third portion, the second portion being located between the first portion and the third portion in the direction from the active region to the termination region, the second portion connecting the first portion and the third portion respectively, the first portion extending from the active region to a portion of the transition region, the first portion being located on the active region, the second portion being located on the transition region, the second portion at the bottom of the gate layer covering the first doped region, the third portion being located on the main junction, and the thickness of the third portion being greater than the thickness of the first portion.

[0049] The description of the first doped region and the gate structure is the same as described in the foregoing embodiments.

[0050] In this embodiment, the method for fabricating the semiconductor structure further includes: forming a P-type second doped region, wherein the second doped region is located between and adjacent to the first doped region, and the doping concentration of the second doped region is greater than that of the first doped region. The description of the second doped region is the same as in the foregoing embodiment.

[0051] In this embodiment, the steps of forming the second doped region and the first doped region include: forming a P-type initial doped region in the transition region; implanting N-type ions into a portion of the initial doped region, wherein the region of the initial doped region implanted with N-type ions forms the first doped region, and the remaining region of the initial doped region forms the second doped region.

[0052] In one embodiment, the main junction is formed during the formation of the initial doped region, simplifying the process. In other embodiments, the main junction is formed after the initial doped region is formed, or the initial doped region is formed after the main junction is formed.

[0053] In this embodiment, the method for fabricating the semiconductor structure further includes: forming a plurality of spaced-apart P-type well regions in the active region, wherein the drift layer between adjacent well regions is a JFET region; forming an N-type source region in the well region; wherein the gate layer on the active region extends from the JFET region to the source region.

[0054] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A semiconductor structure, characterized in that, include: Substrate layer; An N-type drift layer, the drift layer comprising an active region, a terminal region, and a transition region located between the active region and the terminal region; The P-type main junction is located in the terminal region of the drift layer; The first doped region of the P-type located in the transition region has a doping concentration lower than that of the main junction; A gate structure is located on the side of the drift layer opposite to the substrate layer; wherein the gate structure includes: a gate dielectric layer and a gate layer located on the side of the gate dielectric layer opposite to the drift layer, the gate dielectric layer includes a first portion, a second portion and a third portion, the second portion is located between the first portion and the third portion in the direction from the active region to the terminal region, the second portion connects the first portion and the third portion respectively, the first portion is located on the active region, the second portion is located on the transition region, the second portion at the bottom of the gate layer covers the first doped region, the third portion is located on the main junction, and the thickness of the third portion is greater than the thickness of the first portion.

2. The semiconductor structure according to claim 1, characterized in that, The size of the first doped region in the direction from the transition region to the terminal region is 5 micrometers to 30 micrometers.

3. The semiconductor structure according to claim 1, characterized in that, The doping concentration of the first doped region is 5E16 atom / cm 3 -7E18atom / cm 3 The doping concentration of the main junction is 1E19 atom / cm³. 3 -1E20atom / cm 3 .

4. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes a P-type second doped region located between and adjacent to the first doped region, wherein the doping concentration of the second doped region is greater than that of the first doped region.

5. The semiconductor structure according to claim 4, characterized in that, The doping concentration of the second doped region is 1E19 atom / cm 3 -1E20atom / cm 3 .

6. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes: a plurality of spaced P-type well regions located in the active region, wherein the drift layer between adjacent well regions is a JFET region; and an N-type source region located in the well regions. The gate layer on the active region extends from the JFET region to the source region.

7. A method for fabricating a semiconductor structure, characterized in that, include: An N-type drift layer is formed on one side of the substrate layer, the drift layer including an active region, a terminal region and a transition region located between the active region and the terminal region; A P-type main junction is formed in the terminal region; A P-type first doped region is formed in the transition region, wherein the doping concentration of the first doped region is less than the doping concentration of the main junction; A gate structure is formed on the side of the drift layer away from the substrate layer; wherein the gate structure includes: a gate dielectric layer and a gate layer located on the side of the gate dielectric layer away from the drift layer, the gate dielectric layer includes a first portion, a second portion and a third portion, the second portion is located between the first portion and the third portion in the direction from the active region to the terminal region, the second portion connects the first portion and the third portion respectively, the first portion is located on the active region, the second portion is located on the transition region, the second portion at the bottom of the gate layer covers the first doped region, the third portion is located on the main junction, and the thickness of the third portion is greater than the thickness of the first portion.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, Also includes: A second P-type doped region is formed, which is located between and adjacent to the first doped region, and the doping concentration of the second doped region is greater than that of the first doped region.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, The steps of forming the second doped region and the first doped region include: forming a P-type initial doped region in the transition region; implanting N-type ions into a portion of the initial doped region, wherein the region of the initial doped region implanted with N-type ions forms the first doped region, and the remaining region of the initial doped region forms the second doped region.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that, The main junction is formed during the formation of the initial doped region.

11. The method for preparing a semiconductor structure according to claim 7, characterized in that, Also includes: Multiple P-type well regions are formed in the active region at intervals, and the drift layer between adjacent well regions is a JFET region; An N-type source region is formed in the well region; The gate layer on the active region extends from the JFET region to the source region.

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