A laser battery array chip

Abstract

The present invention discloses a laser battery array chip, which includes a substrate, and a laser battery array and an electrode connection part located on one side surface of the substrate; the laser battery array includes at least two battery units, and each battery unit includes a first junction sub-battery layer, a second junction sub-battery layer and a third junction sub-battery layer stacked in sequence from bottom to top; the working wavelength of the laser battery array chip is 850nm - 1200nm, and the first junction sub-battery layer, the second junction sub-battery layer and the third junction sub-battery layer all include a graded buffer layer, an optical spacer layer, a transparent layer, a base layer, an emission layer, a window layer, a contact layer and a gate stacked in sequence from bottom to top. With the above structure, compared with the two-junction sub-battery layer, the energy conversion efficiency and the output density of unit energy of the chip are improved, and the laser thermal effect of the chip is reduced.

Description

Technical Field

[0001] The present invention relates to the field of laser technology, and relates to a device for laser wireless energy transmission, and particularly relates to a laser battery array chip. Background Art

[0002] With the continuous expansion of the application scenarios of aerospace unmanned aerial vehicles and the rapid development of the aerospace industry, higher requirements are put forward for the endurance time and payload of aerospace unmanned aerial vehicles. At present, micro-aerospace unmanned aerial vehicles generally use on-board storage batteries for endurance. Because the energy density and power density of the storage batteries are relatively low, the payload, flight altitude and endurance time of the unmanned aerial vehicle are very limited. In order to enable micro-unmanned aerial vehicles to fly for a long time, carry a large load and fly at a high altitude, charging them by means of remote wireless charging is considered to be one of the most feasible future solutions. Lasers have the advantages of high power density, long transmission distance, strong anti-electromagnetic interference, good directivity, etc., and are considered to be the most promising wireless energy transmission carriers. The key to realizing high energy density laser wireless energy transmission per unit area is a miniaturized, high-voltage, light, efficient and high-temperature-resistant laser energy conversion battery. Therefore, developing a laser battery array chip with a large energy output per unit area, high voltage, small volume, light weight and laser resistance has important economic value.

[0003] The energy conversion layer in the existing laser battery array chips usually uses a two-junction sub-battery to achieve the energy conversion of the laser. However, using a two-junction sub-battery will result in a lower energy conversion efficiency, a lower output density per unit energy, and a higher temperature on the chip surface under laser radiation, making the performance of the final laser battery array chip poor and difficult to meet the actual performance requirements. Summary of the Invention

[0004] The present invention provides a laser battery array chip, which uses a three-junction sub-battery layer structure to greatly improve the energy conversion efficiency and output density per unit energy of the chip compared with a two-junction sub-battery under the same conditions, reduces the chip surface temperature under laser radiation, and has a smaller volume and a lighter weight, and is more suitable for applications in fields such as future unmanned aerial vehicle wireless charging.

[0005] The present invention provides a laser battery array chip, including a substrate and a laser battery array located on one side surface of the substrate;

[0006] The laser battery array includes at least two battery units, and each battery unit includes a first-junction sub-battery layer, a second-junction sub-battery layer and a third-junction sub-battery layer stacked in sequence from bottom to top;

[0007] The working wavelength of the laser battery array chip is 850nm - 1200nm. The first junction sub - battery layer, the second junction sub - battery layer, and the third junction sub - battery layer all include a graded buffer layer, an optical spacer layer, a transparent layer, a base layer, an emission layer, a window layer, a contact layer, and a gate, which are stacked in sequence from bottom to top.

[0008] Optionally, the thicknesses of the first junction sub - battery layer, the second junction sub - battery layer, and the third junction sub - battery layer decrease in sequence.

[0009] Optionally, the base layer includes a first base layer, a second base layer, and a third base layer stacked in sequence from bottom to top;

[0010] The graded buffer layer includes (Al 0.6 Ga) 0.55 ln 0.4 As, the optical spacer layer includes (Al 0.55 Ga) 0.65 ln 0.35 As, the transparent layer includes (Al 0.51 Ga) 0.7 ln 0.3 As, the first base layer includes p - Galn 0.3 As, the second base layer includes p - GalnAs, the third base layer includes i - GalnAs; the emission layer includes n - GalnAs; the window layer includes n - GalnP; the contact layer includes GalnAs; the gate includes Au.

[0011] Optionally, the thicknesses of the graded buffer layers in the first junction sub - battery layer, the second junction sub - battery layer, and the third junction sub - battery layer are the same; the thicknesses of the optical spacer layers in the first junction sub - battery layer, the second junction sub - battery layer, and the third junction sub - battery layer are the same; the thicknesses of the transparent layers in the first junction sub - battery layer, the second junction sub - battery layer, and the third junction sub - battery layer are the same; the thicknesses of the first base layers in the first junction sub - battery layer, the second junction sub - battery layer, and the third junction sub - battery layer decrease in sequence; the thicknesses of the second base layers in the first junction sub - battery layer, the second junction sub - battery layer, and the third junction sub - battery layer are the same; the thicknesses of the third base layers in the first junction sub - battery layer, the second junction sub - battery layer, and the third junction sub - battery layer are the same; the thicknesses of the emission layers in the first junction sub - battery layer, the second junction sub - battery layer, and the third junction sub - battery layer are the same; the thicknesses of the window layers in the first junction sub - battery layer, the second junction sub - battery layer, and the third junction sub - battery layer are the same.

[0012] Optionally, each battery unit further includes a first tunnel junction layer and a second tunnel junction layer. The first tunnel junction layer is disposed between the first junction sub - battery layer and the second junction sub - battery layer, and the second tunnel junction layer is disposed between the second junction sub - battery layer and the third junction sub - battery layer;

[0013] Both the first tunnel junction layer and the second tunnel junction layer include an n-GaAs-Te layer and a p-Al 0.3 GaAs-C layer that are stacked in sequence; the n-GaAs-Te layer and the p-Al 0.3 GaAs-C layers have the same thickness.

[0014] Optionally, the chip further includes an electrode connection part; the electrode connection part is located on the side of the substrate facing the laser battery array;

[0015] The electrode connection part includes an internal electrode connection structure, a first electrode, and a second electrode. One end of the internal electrode connection structure is connected above one battery unit, and the other end of the internal electrode connection structure is connected below another battery unit to serially connect the battery units in sequence; the first electrode is electrically connected to the first battery unit among the battery units connected in series in sequence, and the second electrode is electrically connected to the last battery unit among the battery units connected in series in sequence.

[0016] Optionally, the battery unit further includes a buffer layer, a gap layer, and an antireflection layer;

[0017] The buffer layer is disposed between the substrate and the first junction sub-battery layer, the gap layer is disposed between the third junction sub-battery layer and the antireflection layer, and the antireflection layer is located between the gap layer and the internal electrode connection structure.

[0018] Optionally, the laser battery array further includes an insulating passivation layer;

[0019] The insulating passivation layer is attached to the sidewall of the battery unit, and one end of the insulating passivation layer is embedded in the substrate.

[0020] Optionally, the internal electrode connection structure includes an internal first electrode, a sidewall electrode layer, and an internal second electrode;

[0021] The insulating passivation layer and the surface of the part of the battery unit away from the substrate are provided with the first electrode; one end of the sidewall electrode layer is connected to the internal first electrode and is attached to the surface of the insulating passivation layer; one end of the internal second electrode is connected to the other end of the sidewall electrode layer, and the other end is connected to the adjacent battery unit.

[0022] Optionally, the laser battery array further includes an isolation groove located between two adjacent battery units;

[0023] Part of the internal electrode connection structure is located in the isolation groove, and part of the internal electrode connection structure is located at the same-side ends of two adjacent battery units.

[0024] In the technical solution of the present invention, when the working wavelength of the laser battery array chip is 850 nm - 1200 nm, by arranging three successively stacked first junction sub-battery layers, second junction sub-battery layers and third junction sub-battery layers, when the laser is incident on each battery unit, the first junction sub-battery layer, the second junction sub-battery layer and the third junction sub-battery layer absorb photon energies of different wavelengths, and excite electron transitions to generate electron-hole pairs. The electron-hole pairs are separated under the action of the built-in electric field, the electrons flow to the negative electrode, and the holes flow to the positive electrode, thereby forming a current. With the above structure, the unit energy output density of the laser battery array chip is greatly improved, while the surface temperature is reduced, the energy conversion efficiency of the laser battery array chip is improved, and it has a smaller volume and a lighter weight, and is more suitable for applications in future fields such as wireless charging of unmanned aerial vehicles.

[0025] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0027] Figure 1 A front view schematic diagram of a laser battery array chip provided by an embodiment of the present invention;

[0028] Figure 2 A top view schematic diagram of a laser battery array chip provided by an embodiment of the present invention;

[0029] Figure 3 A schematic diagram of the structure of a battery unit provided by an embodiment of the present invention;

[0030] Figure 4 A schematic diagram of the structure of a second battery unit provided by an embodiment of the present invention;

[0031] Figure 5 A schematic diagram of the structure of a third battery unit provided by an embodiment of the present invention;

[0032] Figure 6 A schematic diagram of the structure of a fourth battery unit provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0033] To enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0034] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order different from those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0035] In one embodiment, Figure 1 is a front view schematic diagram of a laser battery array chip provided by an embodiment of the present invention, Figure 2 is a top view schematic diagram of a laser battery array chip provided by an embodiment of the present invention, Figure 3 is a structural schematic diagram of a battery unit provided by an embodiment of the present invention. This embodiment is applicable to the case of improving the laser energy conversion efficiency and unit energy output density of the laser battery array chip in the near-infrared band and reducing the laser thermal effect of the chip, such as Figures 1 to 3 As shown, the present invention provides a laser battery array chip, which includes a substrate 1, and a laser battery array 2 and an electrode connection part 3 located on one side surface of the substrate 1; the laser battery array 2 includes at least two battery units 21, and each battery unit 21 includes a first junction sub-battery layer 211, a second junction sub-battery layer 212, and a third junction sub-battery layer 213 stacked in sequence from bottom to top; the working wavelength of the laser battery array chip is 850 nm - 1200 nm, and the first junction sub-battery layer 211, the second junction sub-battery layer 212, and the third junction sub-battery layer 213 all include a graded buffer layer 209, an optical spacer layer 205, a transparent layer 206, a base layer 202, an emission layer 203, a window layer 204, a contact layer (not shown in the figure), and a gate 200 stacked in sequence.

[0036] Optionally, the chip further includes an electrode connection portion 3; the electrode connection portion 3 is located on the side of the substrate 1 facing the laser battery array 2; the electrode connection portion 3 includes an internal electrode connection structure 31, a first electrode 32, and a second electrode 33. One end of the internal electrode connection structure 31 is connected above one battery cell 21, and the other end of the internal electrode connection structure 31 is connected below another battery cell 21, so that the battery cells 21 are connected in series in sequence; the first electrode 32 is electrically connected to the first battery cell 21 among the battery cells 21 connected in series in sequence, and the second electrode 33 is electrically connected to the last battery cell 21 among the battery cells 21 connected in series in sequence.

[0037] Among them, the substrate 1 is the base of the laser battery array chip and is used to support the entire laser battery array. In this embodiment, the substrate 1 can be an insulating substrate or a semi-insulating substrate. The insulating substrate can be one of silicon oxide, sapphire substrate, polyimide substrate, and silicon carbide substrate. The laser battery array 2 is a device based on laser wireless energy transmission technology, and its core function is to convert the received laser energy into electrical energy. It usually includes multiple laser photoelectric conversion devices (battery cells), which are arranged in an array through a specific integration method to improve the energy conversion efficiency and output power. In this embodiment, the material of the laser battery array 2 can include, but is not limited to, gallium arsenide (GaAs) or perovskite stack. The laser battery array 2 includes at least two battery cells 21, and each battery cell 21 includes a first junction sub-battery layer 211, a second junction sub-battery layer 212, and a third junction sub-battery layer 213 stacked in sequence from bottom to top. The third junction sub-battery layer 213 refers to the first photoelectric conversion unit at the top layer of the multi-junction laser battery array 1, and is usually used to absorb photons with the highest energy (shortest wavelength), such as ultraviolet light and blue light. This layer of material generally uses a semiconductor material with a relatively wide bandgap to ensure that it can effectively absorb and convert high-energy photons into electrical energy and generate photo-generated carriers (electrons and holes). The second junction sub-battery layer 212 is the second photoelectric conversion unit, located below the third junction sub-battery layer 213, and is used to absorb photons with a medium-range wavelength, such as green light and yellow light. The material used in this layer has a bandgap width between that of the first junction sub-battery layer 211 and the third junction sub-battery layer 213, such as indium gallium phosphide (InGaP) or gallium arsenide (GaAs), to match the corresponding spectral absorption range and improve the overall energy conversion efficiency. The first junction sub-battery layer 211 is the third photoelectric conversion unit, located at the bottom layer of the multi-junction laser battery array 1, and is used to absorb photons with the lowest energy (longest wavelength), such as red light and near-infrared light. This layer usually uses a semiconductor material with a relatively narrow bandgap to more effectively capture the energy of this part of the spectrum and work together with the first two sub-battery layers to form a multi-junction stacked structure, increasing the output voltage and current and improving the overall performance. The internal electrode connection structure 31 is used to connect two adjacent battery cells 2 to ensure that each battery cell 2 is connected in series in sequence. The first electrode 32 and the second electrode 33 are two opposite electrodes of the laser battery array chip 2 and are used to connect to an external circuit or load. Among them, if the first electrode 32 is the positive electrode, then the second electrode 33 is the negative electrode; if the first electrode 32 is the negative electrode, then the second electrode 33 is the positive electrode, and no specific limitation is made here. The material of the electrode connection part 3 can include, but is not limited to, gold. In this embodiment, the working wavelength of the laser battery array chip is 850nm - 1200nm, that is, the near-infrared band.

[0038] Among them, the Gradual Buffer Layer (GB) 209 is a transition layer used between materials or structures, and the composition or structure of its material changes gradually in space. It is mainly used to alleviate the lattice mismatch and the difference in thermal expansion coefficient between different materials, thereby improving the structural stability and performance of the chip. The Optical Spacer Layer (OS) 205 is an intermediate layer used to adjust the optical path and optimize light propagation. It is used to reduce light reflection and loss by controlling the light propagation path and phase, thereby improving the light transmission efficiency and the overall performance of the chip. The Transparent Layer (TL) 206 is a material layer with high transmittance for light of a specific wavelength. It is mainly used to ensure that the optical signal can pass through the chip structure efficiently, while reducing light scattering and absorption, thereby improving the light transmission efficiency and the optical performance of the chip. The base layer 202 is the main light absorption layer of the battery cell 21, usually including P-type GaAs, which is responsible for absorbing most of the incident light and generating photo-generated carriers (electrons and holes). The emission layer 203 is located above the base layer 202 and is used to form a PN junction. Together with the base layer 202, it constitutes the core region for photoelectric conversion of the battery cell 21, and is responsible for separating and transporting the photo-generated carriers to the external circuit. The window layer 204 is located above the emission layer 203 and is used to reduce surface recombination, while allowing more light to enter the interior of the battery cell 21 to be absorbed, and can also protect the chip surface from the external environment. The contact layer is a structure provided between the battery cell and the electrode connection part. Its main function is to improve the contact condition by forming an ohmic contact with the electrode, thereby improving the performance of the laser battery array chip. The gate 200 is a structure formed on the electrode connection part through a photolithography process. It plays a role in controlling the current path and isolating adjacent sub-cells in the battery chip to increase the charge collection of photons and improve the energy conversion efficiency; during the manufacturing process, the formation of the gate 200 is usually achieved by opening a window in the metal electrode material covering the top surface of the contact layer. The material of the gate 200 is the same as that of the electrode connection part 3.

[0039] Specifically, when the laser irradiates the laser battery array 2, the laser will enter the first junction sub-battery layer 211, the second junction sub-battery layer 212, and the third junction sub-battery layer 213 on the battery cell 21. The first junction sub-battery layer 211, the second junction sub-battery layer 212, and the third junction sub-battery layer 213 will absorb photon energies of different wavelengths and excite electron transitions to generate electron-hole pairs. The electron-hole pairs are separated under the action of the built-in electric field, with electrons flowing to the negative electrode and holes flowing to the positive electrode, thus forming an electric current. By connecting multiple battery cells 21 in series, the output current of the laser battery array chip can be increased to achieve the conversion of laser light energy into electrical energy. In this embodiment, when the operating wavelength of the laser battery array chip is 850 nm - 1200 nm, by setting three successively stacked first junction sub-battery layers 211, second junction sub-battery layers 212, and third junction sub-battery layers 213, under the same laser conditions, the unit energy output density of the laser battery array chip can be increased by 1 to 1.5 times, and at the same time, the surface temperature of the laser battery array chip can be reduced by 1 time, so that the energy conversion efficiency is greatly improved.

[0040] In the technical solution of the embodiment of the present invention, when the operating wavelength of the laser battery array chip is 850 nm - 1200 nm, by setting three successively stacked first junction sub-battery layers, second junction sub-battery layers, and third junction sub-battery layers, when the laser enters each battery cell, the first junction sub-battery layer, the second junction sub-battery layer, and the third junction sub-battery layer absorb photon energies of different wavelengths and excite electron transitions to generate electron-hole pairs. The electron-hole pairs are separated under the action of the built-in electric field, with electrons flowing to the negative electrode and holes flowing to the positive electrode, thus forming an electric current. Using the above structure, the unit energy output density of the laser battery array chip is greatly increased, while the surface temperature is reduced, the energy conversion efficiency of the laser battery array chip is improved, and it has a smaller volume and a lighter weight, making it more suitable for applications in future fields such as wireless charging of drones.

[0041] In another specific embodiment, optionally, since the third junction sub-battery layer 213 closest to the laser incidence side absorbs the most photons when the laser is incident, and the first junction sub-battery layer 211 closest to the substrate 1 absorbs the fewest photons, when setting the thicknesses of the first junction sub-battery layer 211, the second junction sub-battery layer 212, and the third junction sub-battery layer 213, the thicknesses of the first junction sub-battery layer 211, the second junction sub-battery layer 212, and the third junction sub-battery layer 213 are set to decrease successively, that is, the thickness of the sub-battery layer farther away from the substrate 1 is smaller. In this way, it can be ensured that the output current of each junction sub-battery is the same, so as to optimize the energy conversion efficiency of the chip, improve the stability of the chip, and extend the service life of the chip.

[0042] In another specific embodiment, Figure 4Schematic diagram of the structure of the second battery cell provided by the embodiment of the present invention, refer to Figure 4 As shown, optionally, when the working wavelength of the laser battery array chip is 650nm - 850nm, the first junction sub-cell layer 211, the second junction sub-cell layer 212, and the third junction sub-cell layer 213 all include a back surface field layer 201, a base layer 202, an emitter layer 203, and a window layer 204 that are stacked in sequence from bottom to top.

[0043] Among them, the back surface field layer 201 is located at the bottom of each junction sub-cell layer and contacts the substrate 1, and is used to reduce the recombination of photo-generated carriers on the back surface of the chip, improve the collection efficiency of carriers, and thus improve the energy conversion efficiency of the chip. In addition, the meanings and functions of the base layer 202, the emitter layer 203, and the window layer 204 can refer to the previous embodiment and will not be elaborated here. In this embodiment, the back surface field layer 201 includes Al 0.3 GaAs, the base layer 202 and the emitter layer 203 both include GaAs, and the window layer 204 includes Alln 0.5 P.

[0044] Optionally, continue to refer to Figure 4 , the thicknesses of the back surface field layers 201 in the first junction sub-cell layer 211, the second junction sub-cell layer 212, and the third junction sub-cell layer 213 are all the same; the thicknesses of the base layers 202 in the first junction sub-cell layer 211, the second junction sub-cell layer 212, and the third junction sub-cell layer 213 decrease in sequence; the thicknesses of the emitter layers 203 in the first junction sub-cell layer 211, the second junction sub-cell layer 212, and the third junction sub-cell layer 213 are all the same; the thicknesses of the window layers 204 in the first junction sub-cell layer 211, the second junction sub-cell layer 212, and the third junction sub-cell layer 213 are all the same.

[0045] Specifically, when the working wavelength of the GaAs-based laser battery array chip is 650nm - 850nm, the substrate 1 can be an insulating sapphire substrate. At this time, the structures of each junction sub-cell layer all include a back surface field layer 201, a base layer 202, an emitter layer 203, and a window layer 204 that are arranged from bottom to top. Among them, the back surface field layer 201 is Al 0.3 GaAs, the base layer 202 is GaAs, the emitter layer 203 is GaAs, and the window layer 204 is Alln 0.5P; and in each battery cell 21, the thicknesses of the back field layers 201 in the first junction sub-battery layer 211, the second junction sub-battery layer 212, and the third junction sub-battery layer 213 are the same. In this embodiment, the thickness of the back field layer 201 is 60 nm. The thicknesses of the base layers 202 in the first junction sub-battery layer 211, the second junction sub-battery layer 212, and the third junction sub-battery layer 213 decrease in sequence. In this embodiment, the thickness of the first junction sub-battery layer 211 is 3000 nm, the thickness of the second junction sub-battery layer 212 is 2500 nm, and the thickness of the third junction sub-battery layer 211 is 2000 nm. The thicknesses of the emitter layers 203 in the first junction sub-battery layer 211, the second junction sub-battery layer 212, and the third junction sub-battery layer 213 are the same. In this embodiment, the thickness of the emitter layer 203 is 100 nm. The thicknesses of the window layers 204 in the first junction sub-battery layer 211, the second junction sub-battery layer 212, and the third junction sub-battery layer 213 are the same. In this embodiment, the thickness of the window layer 204 is 1000 nm.

[0046] In another specific embodiment, optionally, continue to refer to Figure 3 , the base layer 202 includes a first base layer 2021, a second base layer 2022, and a third base layer 2023 that are stacked in sequence from bottom to top; the graded buffer layer 209 includes (Al 0.6 Ga) 0.55 ln 0.4 As, the optical spacer layer 205 includes (Al 0.55 Ga) 0.65 ln 0.35 As, the transparent layer 206 includes (Al 0.51 Ga) 0.7 ln 0.3 As, the first base layer 2021 includes p-Galn 0.3 As, the second base layer 2022 includes p-GalnAs, the third base layer 2023 includes i-GalnAs; the emitter layer 203 includes n-GalnAs; the window layer 204 includes n-GalnP; the contact layer includes GalnAs; the gate includes Au.

[0047] Optionally, continue to refer to Figure 3, the thicknesses of the graded buffer layers 209 in the first sub-cell layer 211, the second sub-cell layer 212, and the third sub-cell layer 213 are all the same; the thicknesses of the optical spacer layers 205 in the first sub-cell layer 211, the second sub-cell layer 212, and the third sub-cell layer 213 are all the same; the thicknesses of the transparent layers 206 in the first sub-cell layer 211, the second sub-cell layer 212, and the third sub-cell layer 213 are all the same; the thicknesses of the first base layers 2021 in the first sub-cell layer 211, the second sub-cell layer 212, and the third sub-cell layer 213 decrease in sequence; the thicknesses of the second base layers 2022 in the first sub-cell layer 211, the second sub-cell layer 212, and the third sub-cell layer 213 are all the same; the thicknesses of the third base layers 2023 in the first sub-cell layer 211, the second sub-cell layer 212, and the third sub-cell layer 213 are all the same; the thicknesses of the emission layers 203 in the first sub-cell layer 211, the second sub-cell layer 212, and the third sub-cell layer 213 are all the same; the thicknesses of the window layers 204 in the first sub-cell layer 211, the second sub-cell layer 212, and the third sub-cell layer 213 are all the same.

[0048] Specifically, when the operating wavelength of the GaAs-based laser battery array chip is 850 nm - 1200 nm, the substrate 1 is an insulating sapphire substrate. At this time, the structure of each sub-cell layer includes a back field layer 101, an OS layer 205, a TL layer 206, a first base layer 2021, a second base layer 2022, a third base layer 2023, an emission layer 203, and a window layer 204 arranged from bottom to top. Among them, the graded buffer layer 209, that is, the GB layer is (Al 0.6 Ga) 0.55 ln 0.4 As, the optical spacer layer 205 is (Al 0.55 Ga) 0.65 ln 0.35 As, the transparent layer 206 is (Al 0.51 Ga) 0.7 ln 0.3 As, the first base layer 2021 is p-doped Galn 0.3As, the second base layer 2022 is p-doped GalnAs, the third base layer 2023 is undoped GalnAs; the emission layer 203 is n-doped GalnAs; the window layer 204 is n-doped GalnP. And in each cell unit 21, the thicknesses of the graded buffer layers 209 in the first sub-cell layer 211, the second sub-cell layer 212, and the third sub-cell layer 213 are the same. In this embodiment, the thickness of the graded buffer layer 209 can be 2000 nm. The thicknesses of the optical spacer layers 205 in the first sub-cell layer 211, the second sub-cell layer 212, and the third sub-cell layer 213 are the same. In this embodiment, the thickness of the optical spacer layer 205 can be 500 nm. The thicknesses of the transparent layers 206 in the first sub-cell layer 211, the second sub-cell layer 212, and the third sub-cell layer 213 are the same. In this embodiment, the thickness of the transparent layer 206 can be 300 nm. The thicknesses of the first base layers 2021 in the first sub-cell layer 211, the second sub-cell layer 212, and the third sub-cell layer 213 decrease in sequence. In this embodiment, the thickness of the first base layer 2021 in the first sub-cell layer 211 is 2300 nm, the thickness of the first base layer 2021 in the second sub-cell layer 212 is 2000 nm, and the thickness of the first base layer 2021 in the third sub-cell layer 211 is 1700 nm. The thicknesses of the second base layers 2022 in the first sub-cell layer 211, the second sub-cell layer 212, and the third sub-cell layer 213 are the same. In this embodiment, the thickness of the second base layer 2022 can be 300 nm. The thicknesses of the third base layers 2023 in the first sub-cell layer 211, the second sub-cell layer 212, and the third sub-cell layer 213 are the same. In this embodiment, the thickness of the third base layer 2023 can be 110 nm. The thicknesses of the emission layers 203 in the first sub-cell layer 211, the second sub-cell layer 212, and the third sub-cell layer 213 are the same. In this embodiment, the thickness of the emission layer 203 can be 220 nm. The thicknesses of the window layers 204 in the first sub-cell layer 211, the second sub-cell layer 212, and the third sub-cell layer 213 are the same. In this embodiment, the thickness of the window layer 204 can be 100 nm. Thus, the resistance in each cell unit 21 can be reduced, the current can be increased, and the photoelectric conversion efficiency of the chip can be enhanced.

[0049] Optionally, continue to refer to Figure 1 、 Figure 3 and Figure 4, each battery cell 21 further includes a first tunnel junction layer 214 and a second tunnel junction layer 215. The first tunnel junction layer 214 is disposed between the first sub-cell layer 211 and the second sub-cell layer 212, and the second tunnel junction layer 215 is disposed between the second sub-cell layer 212 and the third sub-cell layer 213. Both the first tunnel junction layer 214 and the second tunnel junction layer 215 include an n-GaAs-Te layer 207 and a p-Al 0.3 GaAs-C layer 208 stacked in sequence; the n-GaAs-Te layer 207 and the p-Al 0.3 GaAs-C layer 208 have the same thickness.

[0050] Among them, the first tunnel junction layer 214 is located between the first sub-cell layer 211 and the second sub-cell layer 212. It is a special semiconductor junction that includes highly doped p-type and n-type semiconductors, forming a very thin region that allows electrons to easily pass through this barrier through the quantum tunneling effect, that is, from the first sub-cell layer 211 to the second sub-cell layer 212, thereby reducing energy loss. The second tunnel junction layer 215 is located between the second sub-cell layer 212 and the third sub-cell layer 213, and its structure is similar to that of the first tunnel junction layer 214. Its function is to ensure that current can effectively be transmitted from the second sub-cell layer 212 to the third sub-cell layer 213, while minimizing energy loss and avoiding dislocation defects caused by lattice mismatch at the heterointerface. In this embodiment, both the first tunnel junction layer 214 and the second tunnel junction layer 215 include an n-doped GaAs-Te layer 207 and a p-doped Al 0.3 GaAs-C layer 208, and the GaAs-Te layer 207 and the Al 0.3 GaAs-C layer 208 have the same thickness. In this embodiment, the GaAs-Te layer 207 and the Al 0.3 GaAs-C layer 208 can both have a thickness of 20 nm or 30 nm, which can be specifically determined according to the working wavelength of the laser battery array chip. When the working wavelength is 650 nm - 850 nm, the thickness of the GaAs-Te layer 207 and the Al 0.3 GaAs-C layer 208 is 20 nm; when the working wavelength is 850 nm - 1200 nm, the thickness of the GaAs-Te layer 207 and the Al 0.3 GaAs-C layer 208 is 30 nm. This can reduce the overall resistance of the laser battery array chip and improve the photoelectric conversion efficiency of the chip.

[0051] Optionally, continue to refer to Figures 1 to 4, the battery cell 21 further includes a buffer layer 216, a spacer layer 217, and an antireflection layer 218; the buffer layer 216 is disposed between the substrate 1 and the first junction sub-cell layer 211, the spacer layer 217 is disposed between the third junction sub-cell layer 213 and the antireflection layer 218, and the antireflection layer 218 is located between the spacer layer 217 and the internal electrode connection structure 31.

[0052] Among them, the buffer layer 216 is used to provide an intermediate layer between the substrate 1 and the first junction sub-cell layer 211 to improve the interface characteristics between them, reduce defects, and improve the stability and performance of the overall structure. The spacer layer 217 generally refers to a structure used to isolate or separate different functional layers, which can be used to prevent direct contact between different functional layers, avoid short circuits or unnecessary electrical connections, reduce light reflection and scattering between different layers, improve the light transmission efficiency, and reduce the heat conduction between different functional layers to avoid the influence of heat on the chip performance. In this embodiment, the spacer layer 217 can be GaAs and / or GalnAs. The main function of the antireflection layer 218 is to reduce the reflection of laser light and improve the transmittance of laser light, thereby increasing the absorption of incident light. In this embodiment, the antireflection layer 218 can include, but is not limited to, a titanium oxide and / or silicon oxide antireflection film. In addition, the thicknesses of the spacer layers 217 in each battery cell 21 can be equal or unequal, and can be specifically determined according to actual situations, which are not limited herein. In this embodiment, the thicknesses of the spacer layers 217 in each battery cell 21 are equal. Exemplarily, the thickness of the spacer layer 217 is 400 nm. Similarly, the thicknesses of the buffer layers 216 in each battery cell 21 can be equal or unequal, and can be specifically determined according to actual situations, which are not limited herein. In this embodiment, the thicknesses of the buffer layers 216 in each battery cell 21 are equal. Exemplarily, the thickness of the buffer layer 216 is 1000 nm.

[0053] Optionally, continue to refer to Figure 1 , the laser battery array 1 further includes an insulating passivation layer 4; the insulating passivation layer 4 is attached to the side wall of the battery cell 21, and one end of the insulating passivation layer 4 is embedded in the substrate 1.

[0054] Among them, the insulating passivation layer 4 is an insulating material layer covering the side wall of the battery cell 21, which is usually used to protect the battery cell 21 and prevent the external environment from affecting the battery cell 21. In this embodiment, one end of the insulating passivation layer 4 is embedded in the substrate 1, which can effectively isolate the electrical connection between adjacent battery cells 21 and prevent the occurrence of leakage, thereby improving the electrical insulation effect of the chip.

[0055] Optionally, continue to refer to Figure 1, the internal electrode connection structure 31 includes an internal first electrode 311, a sidewall electrode layer 312, and an internal second electrode 313; an insulating passivation layer 4 and a part of the battery unit 21 are provided with the first electrode 311 on the surface away from the substrate 1; one end of the sidewall electrode layer 312 is connected to the internal first electrode 311 and is attached to the surface of the insulating passivation layer 4; one end of the internal second electrode 313 is connected to the other end of the sidewall electrode layer 312, and the other end is connected to the adjacent battery unit 21.

[0056] Among them, the internal first electrode 311, the sidewall electrode layer 312, and the internal second electrode 313 form a bridge electrode. The internal first electrode 311 is connected above one battery unit 21, the internal second electrode 313 is connected below another battery unit 21, the sidewall electrode layer 312 is attached to the surface of the insulating passivation layer 4, and connects the internal first electrode 311 and the internal second electrode 313, thereby realizing the series connection of each battery unit 21 in sequence.

[0057] Optionally, continue to refer to Figure 1 and Figure 2 , the laser battery array 1 further includes an isolation groove 5 located between adjacent two battery units; a part of the internal electrode connection structure 31 is located in the isolation groove 5, and a part of the internal electrode connection structure 31 is located at the same side end of adjacent two battery units 21.

[0058] Among them, the isolation groove 5 is a groove formed in the chip by an etching process, which is usually used for physically and electrically isolating different functional regions. In this embodiment, in the same row of battery units 21, a part of the internal electrode connection structure 31 for connecting adjacent two battery units 21 is located in the isolation groove 5 to realize the series connection of the battery units 21 in one row. In different rows, such as the upper and lower two battery units 21, a part of the internal electrode connection structure 31 for connecting the upper and lower two battery units 21 is located at the same side end of adjacent two battery units 21 to realize the series connection between the battery units 21 in different rows.

[0059] In a specific embodiment, Figure 5 is the structural schematic diagram of the third battery unit provided by the embodiment of the present invention. The structure of a GaAs-based laser battery array chip for the 650nm - 850nm band is as follows:

[0060] As Figure 5 shown, the triple-junction battery unit structure includes a buffer layer, a first-junction GaAs sub-battery layer 3-1, a first tunnel junction layer 3-2, a second-junction GaAs sub-battery layer 3-3, a second tunnel junction layer 3-4, a third-junction GaAs sub-battery layer 3-5, and a gap layer from bottom to top.

[0061] Among them, the first-junction GaAs sub-battery layer 3-1 includes, from bottom to top: Al 0.3GaAs back surface field layer 60 nm, GaAs base layer 3000 nm, GaAs emission layer 100 nm, and Alln 0.5 P window layer 1000 nm;

[0062] The second junction GaAs sub-cell layer 3-3 from bottom to top includes: Al 0.3 GaAs back surface field layer 60 nm, GaAs base layer 2500 nm, GaAs emission layer 100 nm, and Alln 0.5 P window layer 1000 nm;

[0063] The third junction GaAs sub-cell layer 3-5 from bottom to top includes, Al 0.3 GaAs back surface field layer 60 nm, GaAs base layer 200 nm, GaAs emission layer 100 nm, and Alln 0.5 P window layer 1000 nm;

[0064] The first tunneling junction layer 3-2 and the second tunneling junction layer 3-4 include: n-GaAs-Te 20 nm and p-Al 0.3 GaAs-C 20 nm;

[0065] The insulating substrate is a sapphire substrate;

[0066] The antireflection layer is a titanium oxide / silicon oxide antireflection film.

[0067] In another specific embodiment, Figure 6 This is the structural schematic diagram of the fourth battery cell provided by the embodiment of the present invention. The structure of a GaAs-based laser battery array chip for the 850 nm - 1200 nm band is as follows:

[0068] As Figure 6 shown, the triple-junction battery cell structure from bottom to top includes a buffer layer, a first junction GaAs sub-cell layer 3-1, a first tunnel junction layer 3-2, a second junction GaAs sub-cell layer 3-3, a second tunnel junction layer 3-4, a third junction GaAs sub-cell layer 3-5, and a gap layer.

[0069] Among them, the first junction GaAs sub-cell layer 3-1 from bottom to top includes: (Al 0.6 Ga) 0.55 ln 0.4 As GB layer 2000 nm, (Al 0.55 Ga) 0.65 ln 0.35 As OS layer 500 nm, (Al 0.51 Ga) 0.7 ln 0.3 As TL layer 300 nm, p-Galn 0.3As base layer 2300 nm, p-GalnAs base layer 300 nm, i-GalnAs base layer 110 nm, n-GalnAs emission layer 220 nm, and n-GalnP window layer 100 nm.

[0070] The second junction GaAs sub-cell layer 3-3 from bottom to top includes: (Al 0.6 Ga) 0.55 ln 0.4 As GB layer 2000 nm, (Al 0.55 Ga) 0.65 ln 0.35 As OS layer 500 nm, (Al 0.51 Ga) 0.7 ln 0.3 As TL layer 300 nm, p-Galn 0.3 As base layer 2000 nm, p-GalnAs base layer 300 nm, i-GalnAs base layer 110 nm, n-GalnAs emission layer 220 nm, and n-GalnP window layer 100 nm.

[0071] The third junction GaAs sub-cell layer 3-5 from bottom to top includes: (Al 0.6 Ga) 0.55 ln 0.4 As GB layer 2000 nm, (Al 0.55 Ga) 0.65 ln 0.35 As OS layer 500 nm, (Al 0.51 Ga) 0.7 ln 0.3 As TL layer 300 nm, p-Galn 0.3 As base layer 1700 nm, p-GalnAs base layer 300 nm, i-GalnAs base layer 110 nm, n-GalnAs emission layer 220 nm, and n-GalnP window layer 100 nm.

[0072] The first tunneling junction layer 3-2 and the second tunneling junction layer 3-4 include: n-GaAs-Te 15 nm and p-Al0.3GaAs-C 30 nm;

[0073] The insulating substrate is a sapphire substrate;

[0074] The antireflection layer is a titanium oxide / silicon oxide antireflection film.

[0075] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in the present invention can be executed in parallel, sequentially, or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and no limitation is made herein.

[0076] The above specific embodiments do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub - combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A laser battery array chip, characterized in that: It includes a substrate, and a laser cell array located on one side surface of the substrate; The laser battery array comprises at least two battery units, each of which comprises a first junction battery layer, a second junction battery layer and a third junction battery layer stacked sequentially from bottom to top; The working wavelength of the laser cell array chip is 850nm-1200nm, and the first junction cell layer, the second junction cell layer and the third junction cell layer all include a gradient buffer layer, an optical spacer layer, a transparent layer, a base layer, an emission layer, a window layer, a contact layer and a gate layer stacked in sequence from bottom to top; The base layer comprises a first base layer, a second base layer and a third base layer stacked in sequence from bottom to top; The gradient buffer layer comprises (Al 0.6 Ga) 0.55 ln 0.4 As, the optical spacing layer includes (Al 0.55 Ga) 0.65 ln 0.35 As, the transparent layer includes (Al 0.51 Ga) 0.7 ln 0.3 As, the first base layer includes p-Galn 0.3 As, the second base layer includes p-GalnAs, the third base layer includes i-GalnAs; the emission layer includes n-GalnAs; the window layer includes n-GalnP; the contact layer includes GalnAs; and the gate includes Au.

2. The laser cell array chip according to claim 1, characterized in that: The thicknesses of the first junction sub-battery layer, the second junction sub-battery layer and the third junction sub-battery layer decrease in sequence.

3. The laser cell array chip according to claim 1, characterized in that: The thickness of the gradient buffer layer in the first junction sub-battery layer, the second junction sub-battery layer and the third junction sub-battery layer is the same; the thickness of the optical spacer layer in the first junction sub-battery layer, the second junction sub-battery layer and the third junction sub-battery layer is the same; the thickness of the transparent layer in the first junction sub-battery layer, the second junction sub-battery layer and the third junction sub-battery layer is the same; the thickness of the first base layer in the first junction sub-battery layer, the second junction sub-battery layer and the third junction sub-battery layer decreases successively; the thickness of the second base layer in the first junction sub-battery layer, the second junction sub-battery layer and the third junction sub-battery layer is the same; the thickness of the third base layer in the first junction sub-battery layer, the second junction sub-battery layer and the third junction sub-battery layer is the same; the thickness of the emission layer in the first junction sub-battery layer, the second junction sub-battery layer and the third junction sub-battery layer is the same; the thickness of the window layer in the first junction sub-battery layer, the second junction sub-battery layer and the third junction sub-battery layer is the same.

4. The laser cell array chip according to claim 1, characterized in that: Each of the battery cells further includes a first tunnel junction layer and a second tunnel junction layer, wherein the first tunnel junction layer is disposed between the first junction sub-battery layer and the second junction sub-battery layer, and the second tunnel junction layer is disposed between the second junction sub-battery layer and the third junction sub-battery layer; The first tunnel junction layer and the second tunnel junction layer each include an n-GaAs-Te layer and a p-Al layer stacked in sequence. 0.3 GaAs-C layer; the n-GaAs-Te layer and the p-Al 0.3 The thickness of the GaAs-C layers is the same.

5. The laser cell array chip according to claim 1, characterized in that: It also includes an electrode connecting portion; the electrode connecting portion is located on a side of the substrate facing the laser cell array; The electrode connecting portion includes an internal electrode connecting structure, a first electrode and a second electrode, one end of the internal electrode connecting structure is connected to the top of one of the battery cells, and the other end of the internal electrode connecting structure is connected to the bottom of another battery cell, so that the battery cells are connected in series in sequence; the first electrode is electrically connected to the first battery cell among the battery cells connected in series in sequence, and the second electrode is electrically connected to the last battery cell among the battery cells connected in series in sequence.

6. The laser cell array chip according to claim 5, characterized in that: The battery cell also includes a buffer layer, a gap layer and an anti-reflection layer; The buffer layer is disposed between the substrate and the first junction sub-cell layer, the gap layer is disposed between the third junction sub-cell layer and the anti-reflection layer, and the anti-reflection layer is located between the gap layer and the internal electrode connection structure.

7. The laser cell array chip according to claim 6, characterized in that: The laser cell array also includes an insulating passivation layer; The insulating passivation layer is attached to the side wall of the battery unit, and one end of the insulating passivation layer is embedded in the substrate.

8. The laser cell array chip according to claim 7, characterized in that: The internal electrode connection structure includes an internal first electrode, a sidewall electrode layer and an internal second electrode; The first electrode is provided on the surface of the insulating passivation layer and part of the battery cells away from the substrate; one end of the sidewall electrode layer is connected to the internal first electrode and adheres to the surface of the insulating passivation layer; one end of the internal second electrode is connected to the other end of the sidewall electrode layer, and the other end is connected to the adjacent battery cell.

9. The laser cell array chip according to claim 5, characterized in that: The laser battery array further includes an isolation groove located between two adjacent battery units; Part of the internal electrode connection structure is located in the isolation groove, and part of the internal electrode connection structure is located at the ends of the same side of two adjacent battery cells.

Images