CIS pixel reading structure and manufacturing method

Abstract

According to the CIS pixel reading structure, an SF and an SG are of an asymmetric side wall structure, the distance from the lower end of a drain end metal plug of the SF to SF grid polycrystalline silicon can be reduced while the distance from the lower end of the drain end metal plug of the SF to SF grid polycrystalline silicon is not changed, and therefore the distance from a drain end connecting-out point of the SF to a source end connecting-out point of the SG is reduced; as the SG source end is not connected with the working voltage and is not influenced by electric leakage, the GIDL current can be kept, the parasitic resistance can be reduced, and the parasitic resistance effect can be reduced while the area of the SF and SG combined structure is reduced under the condition that the effective size of the SF and SG combined structure is not changed.

Description

Technical Field

[0001] The present invention relates to semiconductor manufacturing technology, and in particular to a CIS pixel readout structure and a manufacturing method. Background Art

[0002] CMOS image sensor (CIS) is composed of pixel unit circuit and CMOS circuit. Pixel unit circuit is located in pixel area, and CMOS circuit is logic circuit located in logic area. Compared with CCD image sensor, CMOS image sensor has better integration because it adopts CMOS standard manufacturing process. It can be integrated with other digital-analog operation and control circuits on the same chip, which is more adaptable to future development. According to the number of transistors contained in the pixel unit circuit of existing CMOS image sensor, it is mainly divided into 3T structure and 4T structure.

[0003] Figure 1 The figure shows an equivalent circuit diagram of a typical 3T-type CMOS image sensor pixel unit circuit, which includes a photodiode (PD) D1 and a CMOS pixel readout circuit. The CMOS pixel readout circuit is a 3T-type pixel circuit, including a reset tube M1, a source follower tube (SF) M2, and a select tube (SG) M3, all of which are NMOS tubes. The N-type region of the photodiode D1 is connected to the source of the reset tube M1. The gate of the reset tube M1 is connected to the reset signal Reset, which is a potential pulse. When the reset signal Reset is at a high level, the reset tube M1 is turned on and absorbs the electrons of the photodiode D1 into the power supply Vdd of the readout circuit to achieve reset. When light is irradiated, the photodiode D1 generates photogenerated electrons, the potential increases, and the electrical signal is transmitted through the amplifier circuit. The gate of the selector M3 is connected to the row selection signal Rs, which is used to select the amplified electrical signal to be output as the output signal Vout.

[0004] Figure 2 The equivalent circuit diagram of the pixel unit circuit of a typical 4T-type CMOS image sensor is shown in FIG. Figure 1 The difference between the structures shown is that Figure 2The structure shown has an additional transfer transistor or transmission tube M4, the source region of the transfer transistor M4 is an N-type region connected to the photodiode D1, the drain region of the transfer transistor M4 is a floating diffusion region (Floating Diffusion, FD), and the gate of the transfer transistor M4 is connected to the transmission control signal Tx. After the photodiode D1 generates photogenerated electrons, they are transferred to the floating diffusion region through the transfer transistor M4, and then connected to the gate of the source follower tube (SF) M2 through the floating diffusion region to achieve signal amplification.

[0005] As the pixel unit continues to shrink, the placement space for the source follower (SF) and selector (SG) combination structure is getting smaller and smaller. The smaller width of the source follower (SF) will lead to a decrease in transconductance (Gm), which will affect the noise of the CMOS image sensor. Even if the W / L ratio is reduced and the transconductance (Gm) remains unchanged, the 1 / f noise (noise) will increase due to the reduction in W*L size (size). As the node shrinks, the space for SF and SG to be reduced becomes smaller and smaller. When the pixel is reduced, every bit of space will be fully utilized to maintain the performance of the SF and SG combination structure.

[0006] The existing CIS pixel readout structure has a source follower tube (SF) and a selector tube (SG) combination structure as shown in FIG. Figure 3 The distance (pitch) between the drain terminal of SF and the source terminal of SG is large. Without changing its effective size (length and width of the device), it is difficult to reduce the area of ​​the combined structure of SF and SG while reducing the parasitic resistance effect. Summary of the invention

[0007] The technical problem to be solved by the present invention is to provide a CIS pixel readout structure and a manufacturing method, which can reduce the parasitic resistance effect while reducing the area of ​​the SF and SG combination structure without changing its effective size.

[0008] In order to solve the above technical problems, the present invention provides a CIS pixel readout structure, which has a P well 100 formed on the upper part of the semiconductor substrate;

[0009] SF gate polysilicon and SG gate polysilicon are formed on the P well 100;

[0010] The SG gate polysilicon is located on the left side of the SF gate polysilicon; there is a gap between the SG gate polysilicon and the SF gate polysilicon, and the left and right width L2 of the SF gate polysilicon is greater than the left and right width L1 of the SG gate polysilicon;

[0011] The gap is filled with silicon oxide;

[0012] The lateral thickness of the sidewall on the right side of the SF gate polysilicon is greater than the lateral thickness of the sidewall on the left side of the SG gate polysilicon;

[0013] A drain metal plug of SF is formed on the right side of the right sidewall of SF for externally connecting to the working voltage Vdd;

[0014] A gate metal plug of the SF connected to the SF gate polysilicon is formed above the SF gate polysilicon;

[0015] A source metal plug of SG is formed on the left side of the left side wall of SG, for outputting the CIS pixel readout voltage Vout;

[0016] A gate-terminal metal plug of SG connected to the SG gate polysilicon is formed above the SG gate polysilicon.

[0017] Preferably, a source terminal N+ region is formed on the P-well surface on the left side of the left side wall of the SG gate polysilicon;

[0018] The lower end of the source metal plug of SG is connected to the source N+ region;

[0019] A drain terminal N+ region is formed on the P-well surface on the right side of the right sidewall of the SF gate polysilicon;

[0020] The lower end of the drain metal plug of SF is connected to the drain N+ region.

[0021] Preferably, a distance CT1 from the lower end of the source metal plug of SG to the gate polysilicon of SG is smaller than a distance CT2 from the lower end of the drain metal plug of SF to the gate polysilicon of SF.

[0022] Preferably, the left sidewall of the SG gate polysilicon is a first sidewall SiN layer 152 laterally stacked with a first sidewall oxide layer 151;

[0023] The right sidewall of the SF gate polysilicon is formed by a second sidewall oxide layer 153 laterally stacked with a first sidewall SiN layer 152 and then laterally stacked with a first sidewall oxide layer 151;

[0024] The lateral thickness of the second sidewall oxide layer is

[0025] The gap between SG gate polysilicon and SF gate polysilicon is less than

[0026] In order to solve the above technical problems, the present invention provides a method for manufacturing a CIS pixel readout structure, which comprises the following steps:

[0027] S0. Performing a P-well (Well) process in a semiconductor substrate to form a P-well (Well) shared by a source follower tube (SF) and a select tube (SG);

[0028] S1. A gate oxide layer 110, a polysilicon layer 120 and a hard mask layer 130 are sequentially formed on a semiconductor substrate;

[0029] S2. Photolithography, etching, removing the polysilicon layer 120 around the SF gate region and the SG gate region to form a gate structure; the SG gate structure is located on the left side of the SF gate structure; there is a gap between the SG gate structure and the SF gate structure, and the left and right width L2 of the SF gate structure is greater than the left and right width L1 of the SG gate structure;

[0030] S3. Depositing a first sidewall oxide layer 151, the first sidewall oxide layer 151 fills the gap between the SG gate structure and the SF gate structure;

[0031] S4. Depositing a first sidewall SiN layer 152;

[0032] S5. Depositing a second sidewall oxide layer 153;

[0033] S6. Etching the second sidewall oxide layer 153, stopping at the first sidewall SiN layer 152, the second sidewall oxide layer 153 on the side of the gate structure is retained, and the second sidewall oxide layer 153 at other positions is removed;

[0034] S7. Photolithography, wet etching, using the first sidewall SiN layer 152 as a stop layer, removing the second sidewall oxide layer 153 on the side of the SG gate structure, retaining the second sidewall oxide layer 153 on the side of the SF gate structure, thereby forming an asymmetric structure;

[0035] S8. Etch the first sidewall SiN layer 152, the first sidewall SiN layer 152 on the side of the gate structure is retained, and the first sidewall SiN layer 152 at other positions is removed, forming an asymmetric sidewall structure on the left side of the SG gate structure and the right side of the SF gate structure, wherein the sidewall on the left side of the SG gate structure is the first sidewall SiN layer 152 laterally stacked with the first sidewall oxide layer 151, and the sidewall on the right side of the SF gate structure is the second sidewall oxide layer 153 laterally stacked with the first sidewall SiN layer 152 and then laterally stacked with the first sidewall oxide layer 151;

[0036] S9. Forming the drain metal plug and gate metal plug of SF and the source metal plug and gate metal plug of SG; the drain metal plug of SF is located on the right side of the right side wall of SF for externally connecting the working voltage Vdd;

[0037] The gate metal plug of SF is connected to the polysilicon layer 120 of SF;

[0038] The source metal plug of SG is located on the left side of the left side wall of SG and is used to output the CIS pixel readout voltage Vout;

[0039] The gate metal plug of SG is connected to the polysilicon layer 120 of SG;

[0040] S10. Perform subsequent process steps.

[0041] Preferably, a distance CT1 from the lower end of the source metal plug of SG to the polysilicon layer 120 of SG is smaller than a distance CT2 from the lower end of the drain metal plug of SF to the polysilicon layer 120 of SF.

[0042] Preferably, in step S1 , the hard mask layer 130 adopts a composite structure of a mask SiN layer 132 stacked on a mask oxide layer 131 .

[0043] Preferably, step S2 includes the following steps:

[0044] S21. Photolithography, etching the mask SiN layer 132, stopping at the mask oxide layer 131;

[0045] S22. Depositing a gap SiN layer 133;

[0046] S23. Etching the gap SiN layer 133, stopping at the mask oxide layer 131, thereby wrapping the gap SiN layer 133 around the mask SiN layer 132;

[0047] S24. Etching the mask oxide layer 131 and the polysilicon layer 120, stopping at the gate oxide layer 110, to form a gate structure.

[0048] Preferably, after step S24, the gate polysilicon (Poly) is first subjected to rapid thermal oxidation (RTO) treatment to form side protection for the gate polysilicon and repair etching damage to the gate polysilicon, and then step S3 is performed.

[0049] Preferably, the gap between the SG gate structure and the SF gate structure is less than

[0050] Preferably, the lateral thickness of the second sidewall oxide layer is

[0051] Preferably, after step S2, a self-aligned LDD implantation process is performed using the hard mask layer 130 to form the drain LDD of SF on the surface of the P well 100 at the right end of the SF gate structure and the source LDD of SG on the surface of the P well 100 at the left end of the SG gate structure; then step S3 is performed.

[0052] Preferably, after the LDD implantation is completed, SiN is removed by wet etching; and then step S3 is performed.

[0053] Preferably, step S9 includes the following steps:

[0054] S91. Perform N+ (N-type heavily doped) ion implantation in a self-aligned manner to form a drain N+ region of SF at the drain LDD surface of SF and a source N+ region of SG at the source LDD surface of SG; define different distances from the drain N+ region of SF and the source N+ region of SG to the channel by making the lateral thickness of the sidewall (spacer) on the right side of SF different from that on the left side of SG;

[0055] S92. A drain metal plug of the SF connected to the drain N+ region is formed on the right side of the right sidewall of the SF through an interlayer dielectric process and a contact hole process;

[0056] forming a gate-terminal metal plug of the SF connected to the SF gate polysilicon over the SF gate polysilicon;

[0057] A source metal plug of SG connected to the source N+ region is formed on the left side of the left side wall of SG;

[0058] A gate-terminal metal plug of SG connected to the SG gate polysilicon is formed over the SG gate polysilicon.

[0059] Preferably, in step S92, the interlayer dielectric process is to first deposit a silicide-blocked (SAB) oxide 162; then deposit an etch stop layer (CESL, Contact Etch Stop Layer) 161; and then deposit an ILD (interlayer dielectric) 163 and perform chemical mechanical polishing.

[0060] In the CIS pixel readout structure of the present invention, SG and SF adopt different sidewall lateral thicknesses, and the SG sidewall adopts a small lateral thickness, which is beneficial to reducing parasitic resistance, and the SF sidewall adopts a large lateral thickness, which is beneficial to reducing GIDL (gate-induced drain leakage) current. In the CIS pixel readout structure, SF and SG adopt an asymmetric sidewall (spacer) structure, which can reduce the distance CT1 from the lower end of the source metal plug of SG to the SG gate polysilicon while keeping the distance CT2 from the lower end of the drain metal plug of SF to the SF gate polysilicon unchanged, thereby reducing the distance (pitch) from the drain terminal contact point of SF to the source terminal contact point of SG. Since the SG source terminal will not be connected to the working voltage Vdd and will not be affected by leakage, it can maintain GIDL (gate-induced drain leakage) current and reduce parasitic resistance. Without changing its effective size (length and width of the device), the parasitic resistance effect can be reduced while reducing the area of ​​the combined structure of SF and SG, thereby effectively improving transconductance (Gm) and reducing imaging noise. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0062] Figure 1 It is the equivalent circuit diagram of the pixel unit circuit of a typical 3T-type CMOS image sensor;

[0063] Figure 2 It is the equivalent circuit diagram of the pixel unit circuit of a typical 4T-type CMOS image sensor;

[0064] Figure 3 It is a schematic diagram of the combined structure of a source follower tube (SF) and a selector tube (SG) of an existing CIS pixel readout structure;

[0065] Figures 4 to 21 1 is a schematic diagram of the steps of an embodiment of a method for manufacturing a CIS pixel readout structure of the present invention.

[0066] Description of reference numerals:

[0067] 100 P well; 110 gate oxide layer; 120 polysilicon layer; 130 hard mask layer; 131 mask oxide layer; 132 mask SiN layer; 133 gap SiN layer; 151 first sidewall oxide layer; 152 first sidewall SiN layer; 153 second sidewall oxide layer; 161 etch stop layer; 162 barrier oxide layer; 163 interlayer dielectric. DETAILED DESCRIPTION

[0068] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0069] The words "first", "second" and similar terms used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprises" and similar terms mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", "front", "back" and the like are only used to indicate relative position relationships. When the absolute position of the object being described changes, the relative position relationship may also change accordingly.

[0070] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0071] Embodiment 1

[0072] A CIS pixel readout structure, such as Fig.21 As shown, a P well 100 is formed on the upper part of the semiconductor substrate;

[0073] SF (source follower) gate polysilicon and SG (selection transistor) gate polysilicon are formed on the P well 100;

[0074] The SG gate polysilicon is located on the left side of the SF gate polysilicon; there is a gap between the SG gate polysilicon and the SF gate polysilicon, and the left and right width L2 of the SF gate polysilicon is greater than the left and right width L1 of the SG gate polysilicon;

[0075] The gap is filled with silicon oxide;

[0076] The lateral thickness of the sidewall on the right side of the SF gate polysilicon is greater than the lateral thickness of the sidewall on the left side of the SG gate polysilicon;

[0077] A drain metal plug of SF is formed on the right side of the right sidewall of SF for externally connecting to the working voltage Vdd;

[0078] A gate metal plug of the SF connected to the SF gate polysilicon is formed above the SF gate polysilicon;

[0079] A source metal plug of SG is formed on the left side of the left side wall of SG, for outputting the CIS pixel readout voltage Vout;

[0080] A gate-terminal metal plug of SG connected to the SG gate polysilicon is formed above the SG gate polysilicon.

[0081] In the CIS pixel readout structure of the first embodiment, SG and SF have different sidewall lateral thicknesses. The SG sidewall has a small lateral thickness, which is beneficial to reducing parasitic resistance, and the SF sidewall has a large lateral thickness, which is beneficial to reducing GIDL (gate-induced drain leakage) current.

[0082] In the CIS pixel readout structure of the first embodiment, SF and SG adopt an asymmetric spacer structure, which can reduce the distance CT1 from the lower end of the source metal plug of SG to the gate polysilicon of SG while keeping the distance CT2 from the lower end of the drain metal plug of SF to the gate polysilicon of SF unchanged, thereby reducing the distance (pitch) from the drain terminal contact point of SF to the source terminal contact point of SG. Since the source terminal of SG will not be connected to the working voltage Vdd and will not be affected by leakage, it can maintain the GIDL (gate-induced drain leakage) current and reduce the parasitic resistance. Without changing its effective size (length and width of the device), the parasitic resistance effect can be reduced while reducing the area of ​​the combined structure of SF and SG, thereby effectively improving the transconductance (Gm) and reducing the imaging noise.

[0083] Embodiment 2

[0084] Based on the CIS pixel readout structure of the first embodiment, an active end N+ (N-type heavily doped) region is formed on the P-well surface on the left side of the left sidewall of the SG gate polysilicon;

[0085] The lower end of the source metal plug of SG is connected to the source N+ region;

[0086] A drain terminal N+ region is formed on the P-well surface on the right side of the right sidewall of the SF gate polysilicon;

[0087] The lower end of the drain metal plug of SF is connected to the drain N+ region.

[0088] Preferably, the distance CT1 from the lower end of the source metal plug of SG to the gate polysilicon of SG is smaller than the distance CT2 from the lower end of the drain metal plug of SF to the gate polysilicon of SF. An asymmetric contact hole to polysilicon (CT to poly) distance design is adopted, and the contact hole to polysilicon (CT to poly) of SG and SF adopts different distances. Since the source end of SG will not be connected to the working voltage Vdd, there is no leakage effect. The distance from the source metal plug of SG to the gate polysilicon is small, which can reduce the parasitic resistance; the distance from the drain metal plug of SF to the gate polysilicon is large, which is conducive to reducing GIDL (gate-induced drain leakage) current.

[0089] Preferably, the gap between the SG gate polysilicon and the SF gate polysilicon is less than The gap between the SG gate polysilicon and the SF gate polysilicon is reduced, which can reduce the parasitic resistance of the shared active area (share AA).

[0090] Preferably, the left sidewall (spacer) of the SG gate polysilicon is a first sidewall SiN layer 152 laterally stacked with a first sidewall oxide layer 151;

[0091] The right sidewall of the SF gate polysilicon is formed by a second sidewall oxide layer 153 laterally stacked with a first sidewall SiN layer 152 and then with a first sidewall oxide layer 151 laterally stacked.

[0092] Preferably, the lateral thickness of the second sidewall oxide layer is

[0093] Embodiment 3

[0094] A method for manufacturing a CIS pixel readout structure comprises the following steps:

[0095] S0. Performing a P-well (Well) process in a semiconductor substrate to form a P-well (Well) shared by a source follower tube (SF) and a select tube (SG);

[0096] S1. A gate oxide layer 110, a polysilicon layer 120 and a hard mask layer 130 are sequentially formed on a semiconductor substrate, such as Figure 4 As shown;

[0097] S2. Photolithography, etching, removing the polysilicon layer 120 around the SF gate region and the SG gate region, forming a gate structure; the SG gate structure is located on the left side of the SF gate structure; there is a gap between the SG gate structure and the SF gate structure, and the left and right width L2 of the SF gate structure is greater than the left and right width L1 of the SG gate structure, such as Figure 5 , Figure 6 As shown;

[0098] S3. Depositing a first sidewall oxide layer 151, the first sidewall oxide layer 151 fills the gap between the SG gate structure and the SF gate structure, such as Fig.11 As shown;

[0099] S4. Depositing a first sidewall SiN layer 152;

[0100] S5. Deposit a second sidewall oxide layer 153 to form an oxide-nitride-oxide sidewall stack (ONO spacerfilm) structure, such as Fig.12 As shown;

[0101] S6. Etching the second sidewall oxide layer 153, stopping at the first sidewall SiN layer 152, the second sidewall oxide layer 153 on the side of the gate structure is retained, and the second sidewall oxide layer 153 at other locations is removed, such as Fig.13 As shown;

[0102] S7. Photolithography, wet etching, using the first sidewall SiN layer 152 as a stop layer, removing the second sidewall oxide layer 153 on the side of the SG gate structure, retaining the second sidewall oxide layer 153 on the side of the SF gate structure, thereby forming an asymmetric structure, such as Fig.14 , Fig.15 As shown;

[0103] S8. Etch the first sidewall SiN layer 152, the first sidewall SiN layer 152 on the side of the gate structure is retained, and the first sidewall SiN layer 152 at other positions is removed, forming an asymmetric sidewall structure on the left side of the SG gate structure and the right side of the SF gate structure, wherein the sidewall on the left side of the SG gate structure is the first sidewall SiN layer 152 laterally stacked with the first sidewall oxide layer 151, and the sidewall on the right side of the SF gate structure is the second sidewall oxide layer 153 laterally stacked with the first sidewall SiN layer 152 and then laterally stacked with the first sidewall oxide layer 151, as shown in FIG. Fig.16 As shown; the lateral thickness difference between the sidewalls of the SG gate structure and the SF gate structure is defined by the second sidewall oxide layer 153;

[0104] S9. Forming the drain metal plug and gate metal plug of SF and the source metal plug and gate metal plug of SG, such as Fig.21 As shown;

[0105] The drain metal plug of SF is located on the right side of the right side wall of SF and is used to connect to the external working voltage Vdd;

[0106] The gate metal plug of SF is connected to the polysilicon layer 120 of SF;

[0107] The source metal plug of SG is located on the left side of the left side wall of SG and is used to output the CIS pixel readout voltage Vout;

[0108] The gate metal plug of SG is connected to the polysilicon layer 120 of SG;

[0109] S10. Perform subsequent process steps, which are consistent with the standard logic process.

[0110] Preferably, the distance CT1 from the lower end of the source metal plug of SG to the polysilicon layer 120 of SG is smaller than the distance CT2 from the lower end of the drain metal plug of SF to the polysilicon layer 120 of SF. An asymmetric contact hole to polysilicon (CT to poly) distance design is adopted, and different distances are used for the contact holes to polysilicon (CT to poly) of SG and SF. Since the source end of SG will not be connected to the working voltage Vdd, there is no leakage effect.

[0111] In the CIS pixel readout structure manufactured by the manufacturing method of the CIS pixel readout structure of the third embodiment, SF and SG adopt an asymmetric spacer structure, which can reduce the distance CT1 from the lower end of the source metal plug of SG to the polysilicon layer 120 of SG while keeping the distance CT2 from the lower end of the drain metal plug of SF to the polysilicon layer 120 of SF unchanged, thereby reducing the distance (pitch) from the drain terminal contact point of SF to the source terminal contact point of SG. Since the source terminal of SG will not be connected to the working voltage Vdd and will not be affected by leakage, it can maintain the GIDL (gate-induced drain leakage) current and reduce the parasitic resistance. Without changing its effective size (length and width of the device), the parasitic resistance effect can be reduced while reducing the area of ​​the combined structure of SF and SG, thereby effectively improving the transconductance (Gm) and reducing the imaging noise.

[0112] Embodiment 4

[0113] Based on the manufacturing method of the CIS pixel readout structure of the third embodiment, in step S1, the hard mask layer 130 adopts a composite structure in which a mask SiN layer 132 is stacked on a mask oxide layer 131, such as Figure 4 shown.

[0114] Preferably, step S2 includes the following steps:

[0115] S21. Photolithography, etching the mask SiN layer 132, stopping at the mask oxide layer 131, such as Figure 5 , Figure 6 As shown;

[0116] S22. Depositing the gap SiN layer 133, such as Figure 7 As shown;

[0117] S23. Etching the gap SiN layer 133, stopping at the mask oxide layer 131, thereby wrapping the gap SiN layer 133 around the mask SiN layer 132;

[0118] S24. Etching the mask oxide layer 131 and the polysilicon layer 120, stopping at the gate oxide layer 110, forming a gate structure, such as Figure 8 shown.

[0119] This process can reduce the gap (Space) between the SG and SF gate polysilicon, reduce the parasitic resistance of the shared active area (share AA), and reduce the overall area of ​​the CIS pixel readout structure while keeping the effective sizes (L1 and L2) of SG and SF unchanged, while increasing the effective Gm of the SF and SG combination. The main purpose of this process step is to solve the problem of insufficient lithography resolution caused by insufficient process nodes when the distance between polysilicon and polysilicon (poly to poly) exceeds the lithography process capability of the current process technology node. This solution does not require mask and photoresist upgrades.

[0120] Preferably, after step S24, the gate polysilicon (Poly) is first subjected to rapid thermal oxidation (RTO) treatment to form side protection for the gate polysilicon and repair etching damage to the gate polysilicon, and then step S3 is performed.

[0121] Preferably, the gap between the SG gate structure and the SF gate structure is less than

[0122] Preferably, the lateral thickness of the second sidewall oxide layer is

[0123] Embodiment 5

[0124] Based on the CIS pixel readout structure manufacturing method of Example 3, after step S2, a self-aligned LDD injection process is performed using the hard mask layer 130 to form a drain terminal LDD of SF on the surface of the P well 100 at the right end of the SF gate structure, and a source terminal LDD of SG is formed on the surface of the P well 100 at the left end of the SG gate structure; then step S3 is performed.

[0125] After step S2, a self-aligned LDD implantation process is performed using the hard mask layer 130 to form the drain end LDD of SF on the surface of the P well 100 at the right end of the SF gate structure, and to form the source end LDD of SG on the surface of the P well 100 at the left end of the SG gate structure. Fig. 9 As shown; then proceed to step S3.

[0126] Preferably, after the LDD implantation is completed, SiN is removed by wet etching, such as Fig.10 As shown; then proceed to step S3.

[0127] Embodiment 6

[0128] Based on the CIS pixel readout structure manufacturing method of the fifth embodiment, step S9 includes the following steps:

[0129] Step S9 includes the following steps:

[0130] S91. Perform N+ (N-type heavily doped) ion implantation in a self-aligned manner to form a drain N+ region of SF at the drain LDD surface of SF and a source N+ region of SG at the source LDD surface of SG, such as Fig.17 As shown; the different distances from the drain end N+ region of SF and the source end N+ region of SG to the channel are defined by the difference in the lateral thickness of the sidewall (spacer) on the right side of SF and the lateral thickness of the sidewall (spacer) on the left side of SG;

[0131] S92. Through the interlayer dielectric process and the contact hole process, a drain metal plug of the SF connected to the drain N+ region is formed on the right side of the right side wall of the SF, such as Fig.21 As shown;

[0132] forming a gate-terminal metal plug of the SF connected to the SF gate polysilicon over the SF gate polysilicon;

[0133] A source metal plug of SG connected to the source N+ region is formed on the left side of the left side wall of SG;

[0134] A gate-terminal metal plug of SG connected to the SG gate polysilicon is formed over the SG gate polysilicon.

[0135] Preferably, in step S92, the interlayer dielectric process is to first deposit a blocking oxide layer (silicide-blocked (SAB) oxide) 162; then deposit an etch stop layer (CESL, Contact Etch Stop Layer) 161; and then deposit an ILD (interlayer dielectric) 163 and perform chemical mechanical polishing, such as Fig.18 , Fig.19 , Fig. 20 shown.

[0136] In the manufacturing method of the CIS pixel readout structure of the sixth embodiment, the distance of the corresponding N+ (N-type heavily doped) ion implantation to the channel is also achieved by an asymmetric sidewall (spacer), so that the distance CT1 from the lower end of the source metal plug of SG to the polysilicon layer 120 of SG can be reduced while the distance CT2 from the lower end of the drain metal plug of SF to the polysilicon layer 120 of SF remains unchanged, thereby reducing the distance (pitch) from the drain terminal contact point of SF to the source terminal contact point of SG. Since the source terminal of SG will not be connected to the operating voltage Vdd and will not be affected by leakage, it is possible to maintain the GIDL (gate-induced drain leakage) current and reduce the parasitic resistance.

[0137] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A CIS pixel readout structure, characterized in that: A P well is formed on the upper portion of the semiconductor substrate; SF gate polysilicon and SG gate polysilicon are formed on the P well; The SG gate polysilicon is located on the left side of the SF gate polysilicon; there is a gap between the SG gate polysilicon and the SF gate polysilicon, and the left and right widths of the SF gate polysilicon are greater than the left and right widths of the SG gate polysilicon; The gap is filled with silicon oxide; The lateral thickness of the sidewall on the right side of the SF gate polysilicon is greater than the lateral thickness of the sidewall on the left side of the SG gate polysilicon; A drain metal plug of SF is formed on the right side of the right side wall of SF for externally connecting the working voltage; A gate metal plug of the SF connected to the SF gate polysilicon is formed above the SF gate polysilicon; A source metal plug of the SG is formed on the left side of the left side wall of the SG, for outputting a CIS pixel readout voltage; A gate-terminal metal plug of SG connected to the SG gate polysilicon is formed above the SG gate polysilicon.

2. The CIS pixel readout structure according to claim 1, characterized in that: A source end N+ region is formed on the P-well surface on the left side of the left side wall of the SG gate polysilicon; The lower end of the source metal plug of SG is connected to the source N+ region; A drain terminal N+ region is formed on the P-well surface on the right side of the right sidewall of the SF gate polysilicon; The lower end of the drain metal plug of SF is connected to the drain N+ region.

3. The CIS pixel readout structure according to claim 1, characterized in that: The distance from the lower end of the source metal plug of SG to the SG gate polysilicon is smaller than the distance from the lower end of the drain metal plug of SF to the SF gate polysilicon.

4. The CIS pixel readout structure according to claim 1, characterized in that: The left sidewall of the SG gate polysilicon is a first sidewall SiN layer laterally stacked with a first sidewall oxide layer; The right sidewall of the SF gate polysilicon is composed of a second sidewall oxide layer laterally stacked with a first sidewall SiN layer and then laterally stacked with the first sidewall oxide layer; The lateral thickness of the second sidewall oxide layer is The gap between SG gate polysilicon and SF gate polysilicon is less than 5. A method for manufacturing a CIS pixel readout structure, characterized in that: The following steps are involved: S0. Performing a P-well process in a semiconductor substrate to form a P-well shared by SF and SG; S1. forming a gate oxide layer, a polysilicon layer and a hard mask layer on a semiconductor substrate in sequence; S2. Photolithography and etching are performed to remove the polysilicon layer around the SF gate region and the SG gate region to form a gate structure; the SG gate structure is located on the left side of the SF gate structure; there is a gap between the SG gate structure and the SF gate structure, and the left and right width of the SF gate structure is greater than the left and right width of the SG gate structure; S3. Depositing a first sidewall oxide layer, the first sidewall oxide layer fills the gap between the SG gate structure and the SF gate structure; S4. Depositing a first sidewall SiN layer; S5. Depositing a second sidewall oxide layer; S6. Etching the second sidewall oxide layer, stopping at the first sidewall SiN layer, the second sidewall oxide layer on the side of the gate structure is retained, and the second sidewall oxide layer at other positions is removed; S7. Photolithography, wet etching, using the first sidewall SiN layer as a stop layer, removing the second sidewall oxide layer on the side of the SG gate structure, retaining the second sidewall oxide layer on the side of the SF gate structure, thereby forming an asymmetric structure; S8. Etch the first sidewall SiN layer, the first sidewall SiN layer on the side of the gate structure is retained, and the first sidewall SiN layer at other positions is removed, forming an asymmetric sidewall structure on the left side of the SG gate structure and the right side of the SF gate structure, wherein the sidewall on the left side of the SG gate structure is the first sidewall SiN layer laterally stacked with the first sidewall oxide layer, and the sidewall on the right side of the SF gate structure is the second sidewall oxide layer laterally stacked with the first sidewall SiN layer and then laterally stacked with the first sidewall oxide layer; S9. Forming a drain metal plug, a gate metal plug of SF and a source metal plug, a gate metal plug of SG; The drain metal plug of SF is located on the right side of the right side wall of SF and is used to connect the external working voltage; The gate metal plug of SF is connected to the polysilicon layer of SF; The source metal plug of SG is located on the left side of the left side wall of SG and is used to output the CIS pixel readout voltage; The gate metal plug of SG is connected to the polysilicon layer of SG; S10. Perform subsequent process steps.

6. The method for manufacturing a CIS pixel readout structure according to claim 5, characterized in that: The distance between the lower end of the source metal plug of SG and the polysilicon layer of SG is smaller than the distance between the lower end of the drain metal plug of SF and the polysilicon layer of SF.

7. The method for manufacturing a CIS pixel readout structure according to claim 5, characterized in that: In step S1, the hard mask layer adopts a composite structure of a mask SiN layer stacked on a mask oxide layer.

8. The method for manufacturing a CIS pixel readout structure according to claim 5, characterized in that: Step S2 includes the following steps: S21. Photolithography, etching the mask SiN layer, and stopping at the mask oxide layer; S22. Depositing a gap SiN layer; S23. Etching the gap SiN layer, stopping at the mask oxide layer, thereby wrapping the gap SiN layer around the mask SiN layer; S24. Etch the mask oxide layer and the polysilicon layer, stop at the gate oxide layer, and form a gate structure.

9. The method for manufacturing a CIS pixel readout structure according to claim 8, characterized in that: After step S24, the gate polysilicon is first subjected to rapid thermal oxidation treatment to form side protection for the gate polysilicon and to repair etching damage to the gate polysilicon, and then step S3 is performed.

10. The method for manufacturing a CIS pixel readout structure according to claim 5, characterized in that: The gap between the SG gate structure and the SF gate structure is smaller than 11. The method for manufacturing a CIS pixel readout structure according to claim 5, characterized in that: The lateral thickness of the second sidewall oxide layer is 12. The method for manufacturing a CIS pixel readout structure according to claim 5, characterized in that: After step S2, a self-aligned LDD implantation process is performed using the hard mask layer 130 to form the drain LDD of SF on the P-well surface at the right end of the SF gate structure and the source LDD of SG on the P-well surface at the left end of the SG gate structure; then step S3 is performed.

13. The method for manufacturing a CIS pixel readout structure according to claim 12, wherein: After the LDD implantation is completed, SiN is removed by wet etching; then step S3 is performed.

14. The method for manufacturing a CIS pixel readout structure according to claim 12, wherein: Step S9 includes the following steps: S91. Perform N+ ion implantation in a self-aligned manner to form a drain N+ region of SF at the surface of the drain LDD of SF, and a source N+ region of SG at the surface of the source LDD of SG; define different distances from the drain N+ region of SF and the source N+ region of SG to the channel by different lateral thicknesses of the sidewalls on the right side of SF and on the left side of SG; S92. A drain metal plug of the SF connected to the drain N+ region is formed on the right side of the right sidewall of the SF through an interlayer dielectric process and a contact hole process; forming a gate-terminal metal plug of the SF connected to the SF gate polysilicon over the SF gate polysilicon; A source metal plug of SG connected to the source N+ region is formed on the left side of the left side wall of SG; A gate-terminal metal plug of SG connected to the SG gate polysilicon is formed over the SG gate polysilicon.

15. The method for manufacturing a CIS pixel readout structure according to claim 14, characterized in that: In step S92, the interlayer dielectric process is to first deposit a blocking oxide layer; then deposit an etch stop layer; and then deposit an ILD and perform chemical mechanical polishing.

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