High-mobility organic field effect transistor and preparation method thereof
By controlling the difference in hydrophilic and hydrophobic properties of the array silicon column template, an organic semiconductor single crystal array was grown on the silicon wafer, solving the problems of low crystallinity and disordered crystal orientation of organic field effect transistors in traditional technology, and achieving high mobility and low cost preparation effects.
Patent Information
- Application Number
- CN202510136721.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-07
- Publication Date
- 2025-05-13
AI Technical Summary
In the prior art, the organic field effect transistors prepared by the traditional solution processing method have low crystallinity and disordered crystal orientation, which limits their performance.
By controlling the difference in hydrophilic and hydrophobic performance between the side walls of the array silicon column template and the top of the array, an organic semiconductor single crystal array is grown on the silicon wafer to improve the carrier transmission capability.
The high mobility of organic field effect transistors is achieved, with a mobility of 6.57cm2/(V·S), and the preparation process is simplified and the cost is reduced.
Smart Images
Figure CN119997769A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a high-mobility organic field effect transistor and a preparation method thereof, belonging to the technical field of organic field effect transistors. Background Art
[0002] Organic field-effect transistors, as a transistor device that uses organic semiconductor materials as the active layer, have many unique advantages, such as compatibility with flexible substrates, low cost, biocompatibility, and greater environmental protection. They are widely used in many fields such as sensors, flexible electronics, panel displays, and solar cells.
[0003] In recent years, with the continuous development of my country's integrated circuit industry, the performance of organic field-effect transistors prepared by traditional solution processing methods can no longer meet people's growing needs. Although previous organic semiconductor solution patterning methods such as inkjet printing have achieved efficient and universal control of the position, arrangement and size of organic semiconductors, the resulting organic semiconductors have low crystallinity and disordered crystal orientation, which limits the performance of the organic field-effect transistors prepared by them. Summary of the invention
[0004] In view of the above-mentioned deficiencies in the prior art, the present invention proposes a high-mobility organic field-effect transistor and a method for preparing the same. By controlling the difference in hydrophilic and hydrophobic properties of the sidewalls and top of the array silicon pillar template, an organic semiconductor single crystal array can be grown on a silicon wafer, thereby effectively improving the carrier transmission capacity.
[0005] The first aspect of the present invention relates to a method for preparing a high-mobility organic field-effect transistor, comprising the following steps:
[0006] Modification steps: spin-coating a photoresist on a glass substrate with a smooth surface, and when the photoresist is not dried and solidified, pressing one side of the glass substrate on which the photoresist is spin-coated onto the hydrophilic top of the silicon column in the array silicon column template; then heating and heat preservation are performed to form a photoresist protective layer on the hydrophilic top of the silicon column to obtain a second state template; placing the second state template in a dryer with a hydrophobic modification reagent dripped on the side wall, evacuating until the hydrophobic modification reagent is vaporized, then placing it in an oven for heating and heat preservation, and then cooling and taking it out to obtain a third state template; finally, washing the third state template with ethanol, acetone, and isopropanol in sequence to remove the photoresist and obtain a fourth state template;
[0007] The steps of preparing the organic semiconductor array are as follows: dropping an organic semiconductor solution onto the fourth state template, covering the hydrophilic top of the silicon column with a silicon wafer, the silicon wafer including a dielectric layer, and the dielectric layer is in contact with the hydrophilic top of the silicon column; clamping the silicon wafer and the template in the height direction of the silicon column, and nucleating and growing on the silicon wafer above the hydrophilic top of the silicon column after a period of time to obtain the organic semiconductor array;
[0008] Electrode preparation steps: Fix a copper mesh mask on the top of the organic semiconductor array to evaporate metal to obtain source electrode and drain electrode.
[0009] For some specific embodiments, the array silicon pillar template in the modifying step is obtained by oxygen plasma treatment.
[0010] For some specific implementation schemes, the size parameters of the array silicon pillar template are that the silicon pillars are 2 to 5 μm wide and 10 to 20 μm high, and the spacing between the silicon pillars is 5 to 10 μm.
[0011] For some specific implementation schemes, the heating and heat preservation during the formation of the second state template is 95-105° C. for 3-5 hours.
[0012] For some specific implementation schemes, the heating and heat preservation during the formation of the third state template is carried out at 80-90° C. for 4-6 hours.
[0013] For some specific embodiments, the amount of the hydrophobic modification reagent added is 20-40 μL. By dripping the hydrophobic modification reagent on the side wall of the dryer, the hydrophobic modification reagent vaporized after vacuuming can be more evenly combined with the side wall surface of the silicon column.
[0014] For some specific implementation schemes, the solvent in the organic semiconductor solution is toluene and / or chlorobenzene, the solute is TIPS-Pentacene or C8-BTBT, the concentration is 1-5 mg / ml, and 10-15 μL is added dropwise with a pipette.
[0015] The second aspect of the present invention relates to a high-mobility organic field-effect transistor, which is manufactured by the above method and includes an organic semiconductor array with a single crystal structure, wherein the width of a single organic semiconductor in the array is 1 to 3 μm, the height is 100 to 500 nm, and the distance between two adjacent organic semiconductors is 7 to 14 μm.
[0016] Compared with the prior art, the present invention has the following technical effects:
[0017] 1) The present invention can grow an organic semiconductor single crystal array on a silicon wafer by controlling the difference in hydrophilic and hydrophobic properties between the sidewalls and top of the array silicon pillar template, effectively improving the carrier transmission capacity. The organic field effect transistor is as high as 6.57cm 2 / (V·S);
[0018] 2) It can be used in the field of flexible electronics, with a simple production process, low cost and large-scale preparation. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 This is the SEM image of the array silicon pillar template;
[0020] Figure 2 The difference diagram of contact angle between the top and side wall of array silicon pillar template;
[0021] Figure 3 is the morphology of the TIPS-Pentacene array;
[0022] Figure 4 This is a transmission electron microscopy image of the TIPS-Pentacene array;
[0023] Figure 5 It is a schematic structural diagram of the organic field effect transistor of the present invention;
[0024] Figure 6 It is the field effect transistor transfer curve diagram of TIPS-Pentacene;
[0025] In the figure: 1. source electrode; 2. drain electrode; 3. organic semiconductor array; 4. dielectric layer; 5. gate. DETAILED DESCRIPTION
[0026] The present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. The experimental methods without specific conditions in the examples are carried out according to conventional methods and conditions.
[0027] Example 1
[0028] The process of preparing a high-mobility organic field-effect transistor in this embodiment is as follows.
[0029] Creation of the first state template
[0030] 1) Design the mask using Klayout layout design software;
[0031] 2) According to the designed mask, polish the four-inch single-sided <100> The exposed N-type doped single crystal silicon wafer is photolithographically processed and etched to produce an array silicon pillar template, which is then cut into 1cm×1cm initial state templates by a dicing machine. The SEM image is shown below. Figure 1 As shown; in the initial state template, the silicon pillars are 2 μm wide and 20 μm high, and the interval between adjacent silicon pillars is 5 μm;
[0032] 3) The initial state template was treated with oxygen plasma using PSD Pro Series Digital UV from Novascan Company for 10 minutes to obtain a first state template.
[0033] Array silicon pillar template modification
[0034] 1) Spin-coat SU8 photoresist on a glass substrate with a smooth surface. When the photoresist is not dried and solidified, press the side of the glass substrate on which the photoresist is spun onto the top of the silicon column of the first state template, heat it to 98°C and keep it warm for 4 hours to obtain a second state template, in which a photoresist protective layer is formed on the top of the silicon column. Through this step, the photoresist protective layer can be formed only on the top of the silicon column, and the modification of the side wall of the silicon column will not be affected.
[0035] 2) The second state template is placed in a desiccator, and 30 μL of heptadecafluorodecyltrimethoxysilane is dripped on the side wall of the desiccator; vacuum is then applied until the heptadecafluorodecyltrimethoxysilane is vaporized, and then the template is placed in an oven, heated to 83°C and kept warm for 6 hours, and then cooled and taken out to obtain a third state template;
[0036] 3) Cleaning with ethanol, acetone, and isopropanol in sequence to remove the photoresist on the top of the silicon column in the third state template to obtain a fourth state template.
[0037] Figure 2 The difference diagram of the contact angle between the top and side wall of the silicon pillar in the fourth state template. Figure 2 It can be seen that after chemical modification, the contact angle of the side wall increases by about 100°, reaching a hydrophobic state, while the top is still in a hydrophilic state.
[0038] Organic semiconductor array preparation
[0039] 15 μL of TIPS-Pentacene solution is taken with a pipette and dropped onto the fourth state template; a 1.5 cm×1.5 cm silicon wafer is placed on the hydrophilic top of the silicon column, and the silicon wafer and the template are clamped in the height direction of the silicon column. After a period of time, nuclei are formed and grown on the silicon wafer above the hydrophilic top of the silicon column to obtain an organic semiconductor array 3;
[0040] The concentration of TIPS-Pentacene solution is 3 mg / mL, and the solvent is chlorobenzene. A 1.5 cm × 1.5 cm silicon wafer is cut into four-inch single-sided polished wafers by a dicing machine. <100> A P-type heavily doped silicon wafer (as gate 5) is obtained, and a SiO2 layer with a thickness of 300 nm is provided on one surface of the silicon wafer (as dielectric layer 4).
[0041] The process of forming the organic semiconductor array 3 is as follows: initially the liquid film is anchored at the top of the silicon pillar. As time goes by, it first shrinks along the direction of the silicon pillar array, then shrinks along the height direction of the silicon pillar, and finally nucleates and grows on the silicon wafer dielectric layer above the hydrophilic top of the silicon pillar to obtain an organic semiconductor array.
[0042] In this embodiment, the organic semiconductor array is a TIPS-Pentacene single crystal array;
[0043] like Figure 3The figure shows the morphology of the TIPS-Pentacene array observed under an optical microscope. It can be seen that the TIPS-Pentacene array has a complete morphology and is neatly arranged.
[0044] Figure 4 3 is a transmission electron microscope image of a TIPS-Pentacene array. From the regularly arranged diffraction points in the image, it can be seen that the TIPS-Pentacene array prepared in this embodiment is a single crystal array, not a polycrystalline array.
[0045] Electrode preparation
[0046] The copper mesh mask is fixed on the surface of the organic semiconductor array 3 by using a high temperature resistant tape, and a 10 nm thick Gr layer is first evaporated by an electron beam evaporation device, and then a 50 nm thick Au layer is evaporated on the Gr layer to obtain a source electrode 1 and a drain electrode 2, and finally the following is obtained: Figure 5 The organic field effect transistor shown.
[0047] The performance of the organic field effect transistor prepared in this embodiment was tested, and the testing process was as follows.
[0048] Using Keithley 4200 semiconductor tester and Lakeshore cryogenic vacuum probe station at room temperature, two probes were inserted into the source electrode and drain electrode of TIPS-Pentacene organic field effect transistor respectively. The gate of the organic field effect transistor was connected to the back electrode of the sample holder of Lakeshore cryogenic vacuum probe station. The gate was biased from 20V to -60V, V DS =-60V.
[0049] Mobility refers to the average drift velocity of carriers generated under unit electric field strength, and its unit is cm 2 / (V·S), represents the conductivity of the carrier; the mobility can be calculated from this formula: , where μ is the mobility, L is the channel length, and I DS is the source-drain current, V GS is the source-gate voltage, W is the channel width, C i is the specific capacitance of the dielectric layer;
[0050] Figure 6 The transfer curve of TIPS-Pentacene organic field-effect transistor. The slope of the gray line is 1.72×10 -4 , which is the calculation formula The value of this item; TIPS-Pentacene organic field effect transistor L is 5μm, channel width is 6μm, C i Take 0.75×10 -8 F / cm2 ;
[0051] Substituting the above parameters into the calculation, the mobility μ is 6.57 cm 2 / (V·S), it can be known that the organic field effect transistor prepared in this embodiment is a high-mobility organic field effect transistor.
[0052] It should be emphasized that the above are only preferred embodiments of the present invention and do not limit the present invention in any form. Any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention are still within the scope of the technical solution of the present invention.
Claims
1. A method for preparing a high-mobility organic field-effect transistor, characterized in that: The following steps are involved: Modification steps: spin-coating a photoresist on a glass substrate with a smooth surface, and when the photoresist is not dried and solidified, pressing one side of the glass substrate on which the photoresist is spin-coated onto the hydrophilic top of the silicon column in the array silicon column template; then heating and heat preservation are performed to form a photoresist protective layer on the hydrophilic top of the silicon column to obtain a second state template; placing the second state template in a dryer with a hydrophobic modification reagent dripped on the side wall, evacuating until the hydrophobic modification reagent is vaporized, then placing it in an oven for heating and heat preservation, and then cooling and taking it out to obtain a third state template; finally, washing the third state template with ethanol, acetone, and isopropanol in sequence to remove the photoresist and obtain a fourth state template; The steps of preparing the organic semiconductor array are as follows: dropping an organic semiconductor solution onto the fourth state template, covering the hydrophilic top of the silicon column with a silicon wafer, the silicon wafer including a dielectric layer, and the dielectric layer is in contact with the hydrophilic top of the silicon column; clamping the silicon wafer and the template in the height direction of the silicon column, and nucleating and growing on the silicon wafer above the hydrophilic top of the silicon column after a period of time to obtain the organic semiconductor array; Electrode preparation steps: Fix a copper mesh mask on the top of the organic semiconductor array to evaporate metal to obtain source electrode and drain electrode.
2. The preparation method according to claim 1, characterized in that: The array silicon column template is treated with oxygen plasma.
3. The preparation method according to claim 1 or 2, characterized in that: The size parameters of the array silicon column template are that the silicon column has a width of 2 to 5 μm, a height of 10 to 20 μm, and an interval of 5 to 10 μm between the silicon columns.
4. The preparation method according to claim 1, characterized in that: The heating and heat preservation process of forming the second state template is 95-105° C. for 3-5 hours.
5. The preparation method according to claim 1, characterized in that: The amount of the hydrophobic modification reagent added is 20 to 40 μL.
6. The preparation method according to claim 1, characterized in that: The heating and heat preservation during the formation of the third state template is carried out at 80-90° C. for 4-6 hours.
7. The preparation method according to claim 1, characterized in that: The solute in the organic semiconductor solution is TIPS-Pentacene or C8-BTBT, the concentration is 1-5 mg / ml, and 10-15 μL is added dropwise with a pipette.
8. The preparation method according to claim 1, characterized in that: The source electrode and the drain electrode are both composed of a stacked Gr layer and an Au layer, and the Gr layer is arranged on the organic semiconductor array.
9. The preparation method according to claim 8, characterized in that: The thickness of the Gr layer is 10 nm, and the thickness of the Au layer is 50 nm.
10. A high mobility organic field effect transistor, characterized in that: The organic semiconductor array is prepared by the preparation method according to any one of claims 1 to 9, and comprises a single crystal structure, wherein the width of a single organic semiconductor in the array is 1 to 3 μm, the height is 100 to 500 nm, and the distance between two adjacent organic semiconductors is 7 to 14 μm.