Conductive bridge memory and manufacturing method thereof

Abstract

The embodiment of the invention provides a conductive bridge memory and a manufacturing method thereof. The conductive bridge memory comprises a substrate layer, a first metal layer arranged on the substrate layer, a dielectric layer arranged on the first metal layer, and a second metal layer arranged on the dielectric layer, wherein a nanometer through hole is formed in the dielectric layer so as to connect the first metal layer and the second metal layer. According to the embodiment of the invention, the nano through hole for connecting the first metal layer and the second metal layer is formed in the dielectric layer, so that a prefabricated path is provided for the formation of the conductive filament, namely, the controllability of the conductive filament is realized. Therefore, the problem that a conductive bridge memory with a controllable conductive filament is needed in the prior art can be solved, and the effect of improving the performance of the conductive bridge memory is achieved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of memory devices, and in particular to a conductive bridge memory and a manufacturing method thereof. Background Art

[0002] Conductive Bridging Random Access Memory (CBRAM) based on non-volatile materials has a high switching speed and a large switching ratio. It integrates the switching speed of static random access memory (SRAM) and the high density characteristics of dynamic random access memory (DRAM), and has the non-volatile characteristics of flash memory. It is a new type of memory for future application scenarios such as 6G communications and the metaverse.

[0003] The migration of metal cations in common CBRAM uses random defects in the dielectric layer as a "stepping stone", so the formation and breaking of conductive filaments in three-dimensional space are highly random. This randomness reduces the performance consistency between devices and in different cycles of the same device. This poses a huge challenge to the application of CBRAM in in-memory computing, neural networks and other fields. Therefore, a CBRAM with controllable conductive filaments is needed to improve the performance consistency of devices. Summary of the invention

[0004] The embodiment of the present invention provides a conductive bridge memory and a manufacturing method thereof, so as to at least solve the problem in the related art that a conductive bridge memory with controllable conductive filaments is required.

[0005] According to one embodiment of the present invention, a conductive bridge memory is provided, comprising: a substrate layer, a first metal layer arranged above the substrate layer, a dielectric layer arranged above the first metal layer, and a second metal layer arranged above the dielectric layer; wherein nano-vias are opened in the dielectric layer to connect the first metal layer and the second metal layer.

[0006] According to another embodiment of the present invention, a method for manufacturing a conductive bridge memory is provided, comprising: depositing a first metal layer on top of a substrate by a deposition method; epitaxially growing a dielectric layer on top of the first metal layer by an epitaxial technology, and forming a mask layer on the dielectric layer; and opening nano-through holes in the dielectric layer at a preset angle according to the opening area marked by the mask layer; and depositing a second metal layer on top of the dielectric layer after the opening by the deposition method.

[0007] According to the above-mentioned embodiment of the present invention, since a nano-through hole connecting the first metal layer and the second metal layer is opened on the dielectric layer, a prefabricated path is provided for the formation of the conductive filament, that is, the controllability of the conductive filament is achieved. Therefore, the problem of requiring a conductive bridge memory with controllable conductive filaments in the related art can be solved, and the performance of the conductive bridge memory can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic structural diagram of a conductive bridge memory according to an embodiment of the present invention;

[0009] Figure 2 is a schematic structural diagram of a conductive bridge memory according to another embodiment of the present invention;

[0010] Figure 3 is a flow chart of a method for manufacturing a conductive bridge memory according to an embodiment of the present invention;

[0011] Figure 4 2 is a schematic diagram of the structure of a conductive bridge memory according to a third embodiment of the present invention;

[0012] Figure 5 1 is a schematic diagram of the structure of a conductive bridge memory according to a fourth embodiment of the present invention. DETAILED DESCRIPTION

[0013] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and in combination with the embodiments.

[0014] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0015] The era of 5G communication and artificial intelligence has arrived, and the storage, transmission and processing of big data face huge challenges. The memory in the classic von Neumann architecture faces the challenges of high power consumption and the "memory wall", while logic devices have reached the limit of Moore's Law. Computing solutions based on traditional architecture and hardware face three major challenges: high power consumption, the "memory wall" and Moore's Law, and new solutions are urgently needed. The in-memory computing architecture can complete calculations in situ in the memory, greatly reducing data migration and power consumption, and fundamentally improving the system energy efficiency of the hardware architecture. CBRAM has high switching speed and high density characteristics, and also has the non-volatile characteristics of flash memory. It is a new type of memory for future application scenarios such as 6G communication and the metaverse.

[0016] CBRAM is generally a "sandwich" structure of metal / dielectric / metal, and information is written and erased through the resistive effect of the dielectric layer, that is, the two metal layers serve as the active electrode and the inert electrode respectively. A positive bias is applied to the active electrode, causing an oxidation reaction in the active electrode, and the metal atoms become metal ions. The metal ions move through the dielectric layer to the inert electrode under the action of the electric field, and obtain electrons and are reduced to metal atoms. As more and more metal ions are reduced, a continuously extending metal atom pile is formed until the upper and lower electrode devices are connected. The metal atom pairs connecting the upper and lower motors are conductive filaments. When the conductive filaments connect the upper and lower electrode devices, the memory enters a low-resistance state; when a negative voltage is applied to the active electrode, the conductive filaments dissolve, and the memory returns to a high-resistance state. Among them, the dielectric layer in CBRAM is generally a polycrystalline solid electrolyte, metal oxide or low-dimensional nanomaterial.

[0017] Due to the high mobility of metal cations, CBRAM based on the metal cation migration mechanism has a high switching speed and a large switching ratio. However, the formation and breaking of the conductive filaments in common CBRAM in three-dimensional space are highly random. Therefore, in order to overcome the limitations of this randomness on the practical application of CBRAM, it is necessary to improve the performance consistency of CBRAM. At present, there are roughly three technical approaches to improve the performance consistency of CBRAM: introducing nanomaterials, forming cutting-edge electric fields, and designing multi-layer stacking structures.

[0018] Introducing nanomaterials such as quantum dots and nanoparticles on the surface or inside the dielectric layer can increase the probability of conductive filaments forming near the nanomaterials to a certain extent, but this method has very limited effects on improving device consistency and cannot be used in practice.

[0019] The formation of a tip electric field can also increase the probability of forming a conductive filament at the tip of the electrode to a certain extent, but this technical path requires a lot of etching work, which is relatively costly, and the extension path of the conductive filament formed at the tip of the electrode is still highly random.

[0020] Designing a multi-layer stacked structure can limit the generation of conductive filaments to a smaller range, but this method has more process steps, is more expensive, and is difficult to be compatible with CMOS technology.

[0021] The present invention provides a conductive bridge memory (CBRAM) with controllable conductive filaments, which has the characteristics of simple preparation process, high flexibility, high preparation precision, and is easy to be combined with traditional CMOS process. Figure 1 is a schematic diagram of a conductive bridge memory according to an embodiment of the present invention, Figure 1As shown, the conductive bridge memory includes: a substrate layer 10, a first metal layer 20 arranged above the substrate layer 10, a dielectric layer 30 arranged above the first metal layer 20, and a second metal layer 40 arranged above the dielectric layer; wherein a nano-via 50 is opened in the dielectric layer 30 to connect the first metal layer 20 and the second metal layer 40.

[0022] In this embodiment, nano-vias are used to connect the first metal layer and the second metal layer, providing a prefabricated path for the formation of conductive filaments, thereby essentially achieving controllability of the conductive filaments, thereby improving the performance consistency of the CBRAM.

[0023] In this embodiment, the material of the substrate layer 10 includes, but is not limited to: silicon (Si), silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), aluminum oxide (Al2O3), and diamond (C).

[0024] In this embodiment, the material of the first metal layer 20 is one or more combinations of single metal compounds such as platinum (Pt), gold (Au), titanium nitride (TiN), tantalum nitride (TaN), palladium (Pd), ruthenium (Ru), iridium (Ir), tungsten (W), aluminum (Al), hafnium (Hf), titanium (Ti), tantalum (Ta), vanadium (V), chromium (Cr), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), zinc (Zn), niobium (Nb), zirconium (Zr), etc., with a thickness of 100-1000 nanometers.

[0025] In this embodiment, the material of the dielectric layer 30 can be one or a combination of Nafion, SiN, SiO2, Al2O3, copper oxide (CuO), hafnium oxide (HfO2), titanium oxide (TiO2), nickel oxide (NiO), zirconium oxide (ZrO2), hexagonal boron nitride (hBN), molybdenum disulfide (MoS2), tungsten disulfide (WS2), molybdenum diselenide (MoSe2), tungsten diselenide (WSe2), etc., with a thickness of 1-1000 nanometers.

[0026] In this embodiment, the material of the second metal layer 40 can be one or more combinations of Pt, Au, TiN, TaN, Pd, Ru, Ir, W, Al, Hf, Ti, Ta, V, Cr, Fe, Co, Ni, Cu, Zn, Nb, Zr single substances and metal compounds, with a thickness of 100-1000 nanometers.

[0027] In this embodiment, the nano-via 50 is in a hollow state when there is no metal filling, and the diameter is 1-100 nanometers.

[0028] In this embodiment, the shape of the nano-through hole 50 includes but is not limited to: straight line, curve, broken line, and the cross-sectional shape of the hole includes but is not limited to circle, ellipse, rectangle, polygon.

[0029] The nano-hole forms a certain angle with the first metal layer, and the angle is 1° to 90°.

[0030] In one embodiment, there is an angle between the nano-via 50 and the first metal layer 20 , and the angle ranges from 1° to 90°.

[0031] In one embodiment, the diameter of the nano-via 50 is less than 10 nm.

[0032] In one embodiment, the top cross-sectional diameter of the nano-via 50 is larger than the bottom cross-sectional diameter of the nano-via 50 , the top is the end of the nano-via 50 connected to the second metal layer 40 , and the bottom is the end of the nano-via 50 connected to the first metal layer 20 .

[0033] In one embodiment, the top of the nano-through hole 50 is in a funnel shape 60. That is, when preparing the conductive bridge memory, the diameter of the top hole of the nano-through hole 50 is enlarged to form a funnel shape 60, such as Figure 2 As shown, at this time, the diameter of the top hole of the nano-through hole 50 is larger than the diameter of the bottom hole.

[0034] By depositing metal nanofunnel at the hole of the nanovia at the top (or upper surface) of the dielectric layer, this structure can be used to form a tip electric field to further increase the probability of forming conductive filaments at the mouth of the nanovia. Combined with the technical means of using nanovia as a prefabricated path for conductive filaments, the controllability of the conductive filaments and the performance consistency of CBRAM are further improved.

[0035] In one embodiment, the conductive bridge memory further includes: a metal nano funnel structure, wherein the metal nano funnel structure is formed by partially filling the funnel shape with metal of the second metal layer. At this time, except for the top portion of the nano via 50 which is filled with the second metal layer, the rest of the nano via 50 is in a hollow state and is not filled with metal.

[0036] In this embodiment, the metal nanofunnel structure is arranged at the interface between the dielectric layer 30 and the second metal layer 40, with a diameter of 1-100 nanometers and a height of 1-100 nanometers; the composition of the metal nanofunnel structure is consistent with that of the second metal layer 40, connecting the second metal layer 40 and the nano-via 50.

[0037] In one embodiment, there are multiple dielectric layers 30 , each dielectric layer 30 is provided with nano-through holes, and the nano-through holes of each dielectric layer 30 are interconnected.

[0038] In one embodiment, the angles between the nano-via 50 of each dielectric layer and the first metal layer 20 are different.

[0039] According to the above embodiment, since a nano-via connecting the first metal layer and the second metal layer is opened on the dielectric layer, a prefabricated path is provided for the formation of the conductive filament, that is, the controllability of the conductive filament is achieved. Therefore, the problem of requiring a conductive bridge memory with controllable conductive filaments in the related art can be solved, and the performance of the conductive bridge memory can be improved.

[0040] The embodiment of the present invention also provides a method for manufacturing a conductive bridge memory. Figure 3 is a flow chart of a method for manufacturing a conductive bridge memory according to an embodiment of the present invention. Figure 3 As shown, the method comprises the following steps:

[0041] Step S302, depositing a first metal layer on the substrate by a deposition method;

[0042] In this embodiment, the deposition method of the first metal layer includes but is not limited to: thermal evaporation, electron beam evaporation, magnetron sputtering, and ion beam sputtering.

[0043] Step S304, epitaxially growing a dielectric layer on the first metal layer by epitaxial technology, and forming a mask layer on the dielectric layer; and opening nano-vias in the dielectric layer at a preset angle according to the opening area marked by the mask layer;

[0044] In this embodiment, the epitaxial growth technology includes but is not limited to: PECVD (Plasma-Enhanced Chemical Vapor Deposition), PEALD (Plasma-Enhanced Atomic Layer Deposition), MOCVD (Metal-organic Chemical Vapor Deposition), PLD (Pulsed Laser Deposition), MBE (Molecular Beam Epitaxy), and magnetron sputtering.

[0045] In this embodiment, the material of the mask layer includes but is not limited to: photoresist, metal, nitride, and oxide.

[0046] In this embodiment, the process of forming the nano-through hole includes but is not limited to: ICP (Inductively Coupled Plasma), RIE (Reactive Ion Etching), high-energy laser irradiation, high-energy particle irradiation, and wet etching.

[0047] In step S304 of the present embodiment, a nano-through hole is opened in the dielectric layer at a preset angle according to the opening area marked by the mask layer, including: opening the nano-through hole in the dielectric layer at a preset angle according to the opening area marked by the first mask layer; forming a second mask layer multiple times at the nano-through hole in the dielectric layer, and expanding the area of ​​the top hole of the nano-through hole according to the opening area marked by the second mask layer until the top of the nano-through hole presents a preset funnel shape, wherein the top is an end of the nano-through hole connected to the second metal layer.

[0048] In step S304 of this embodiment, epitaxially growing a dielectric layer on the first metal layer by using the epitaxial technology includes: epitaxially growing a plurality of dielectric layers one by one on the first metal layer by using the epitaxial technology.

[0049] In step S304 of this embodiment, the nano-through holes are formed in the dielectric layer at a preset angle, including: forming nano-through holes in each of the plurality of dielectric layers at different preset angles, and the nano-through holes in each dielectric layer are interconnected.

[0050] In step S304 of this embodiment, after the nano-vias are opened in the dielectric layer at a preset angle, the method further includes: performing oxygen and post-metal annealing treatment on the dielectric layer.

[0051] Step S306 , depositing a second metal layer on the dielectric layer after the holes are opened by the deposition method.

[0052] In this embodiment, the deposition method of the second metal layer includes but is not limited to: thermal evaporation, electron beam evaporation, magnetron sputtering, and ion beam sputtering.

[0053] In step S306 of this embodiment, it includes: filling part of the metal of the second metal layer into the funnel shape to form a metal nano-funnel structure.

[0054] The CBRAM of the embodiment of the present invention can control the density of the conductive filaments by controlling the density of the nano-vias, that is, the thickness of the conductive filaments can be controlled by controlling the thickness of the nano-vias; by controlling the etching angle, the angle between the nano-holes and the substrate layer can be controlled, thereby controlling the length of the conductive filaments. By controlling factors such as the nano-hole diameter, the etching time, and the etching intensity, the diameter and size of the metal nano-funnel can be controlled, thereby controlling the intensity of the tip electric field. The above technical means can all improve the controllability of the conductive filaments.

[0055] To facilitate the understanding of the technical solution provided by the present invention, a detailed description will be given below in conjunction with embodiments of specific scenarios.

[0056] Scenario Example 1

[0057] In this embodiment, the following steps are performed based on the substrate 10 made of Si to obtain a conductive bridge memory. The structure of the conductive bridge memory obtained can be referred to as follows: Figure 2 :

[0058] Step S402, depositing and growing a first metal layer 20 on the substrate 10 by electron beam evaporation, wherein the material of the first metal layer 20 is Cu, and the thickness is 500 nanometers;

[0059] Step S404, epitaxially growing a dielectric layer 30 on the first metal layer 20 by PEALD technology, wherein the dielectric layer 30 is made of SiO2 and has a thickness of 50 nanometers;

[0060] Step S406, forming a mask layer on the dielectric layer 30 and marking the opening area, wherein the opening diameter is 10 nanometers and the mask layer material is photoresist;

[0061] Step S408 , performing ICP etching at an etching angle of 80° on the opening area on the dielectric layer 30 until the nano-via 50 extends to the first metal layer 20 .

[0062] Step S410, forming a mask layer again on the dielectric layer 30 and marking the opening area to enlarge the top diameter of the nano-via 50;

[0063] Step S412 , performing short-time high-intensity ICP etching again on the dielectric layer 30 at an etching angle of 80° until a funnel shape is formed at the top of the nano-via 50 , wherein the opening diameter of the enlarged portion is 30 nanometers.

[0064] Step S414, after washing away the mask layer on the dielectric layer 30, the second metal layer 40 is evaporated by electron beam, wherein the second metal layer 40 is Al, and has a thickness of 500 nanometers.

[0065] In this embodiment, part of the metal of the second metal layer 40 is filled into the funnel shape formed in step S412 to obtain a metal nano-funnel structure 60 .

[0066] Scenario Example 2

[0067] In the present embodiment of the scenario, compared with the above-mentioned first embodiment of the scenario, the dielectric layer material, the method of forming the nanopores and the nanofunnel in the present embodiment of the scenario are different, and the rest of the manufacturing methods are the same.

[0068] Based on the substrate 10 made of Si, the following steps are performed to obtain a conductive bridge memory (the memory structure can be referred to as Figure 2 ):

[0069] Step S502, depositing and growing a first metal layer 20 on the substrate 10 by electron beam evaporation, wherein the material of the first metal layer 20 is Cu, and the thickness is 500 nanometers;

[0070] Step S504, epitaxially growing a dielectric layer 30 on the first metal layer 20 by spin coating and then drying technology, wherein the dielectric layer 30 is made of Nafion and has a thickness of 500 nanometers;

[0071] Step S506, forming a mask layer on the dielectric layer 30 and marking the opening area, wherein the opening diameter is 10 nanometers and the mask layer material is Ni;

[0072] Step S508 , performing high-energy laser etching at an etching angle of 80° on the opening area on the dielectric layer 30 until the nano-via 50 extends to the first metal layer 20 .

[0073] Step S510, forming a mask layer again on the dielectric layer 30 and marking the opening area to enlarge the top diameter of the nano-via 50;

[0074] Step S512, wet etching the top of the nano-hole again at an etching angle of 80° on the dielectric layer 30 by using a chemical solution until the top of the nano-through hole 50 forms a funnel shape, wherein the opening diameter of the enlarged part is 30 nanometers and the height is 30 nanometers, and the chemical solution is a hydrogen peroxide solution;

[0075] Step S514, after washing away the mask layer on the dielectric layer 30, a second metal layer 40 is deposited by electron beam evaporation, wherein the second metal layer 40 is Al and has a thickness of 500 nanometers.

[0076] In this embodiment, part of the metal of the second metal layer 40 is filled into the funnel shape formed in step S512 to obtain a metal nano-funnel structure 60 .

[0077] Scenario Example 3

[0078] Figure 4 1 is a schematic diagram of the structure of a conductive bridge memory according to the third embodiment of the present invention. Compared with the first embodiment of the above-mentioned scenario, the dielectric layer structure and the method of forming nanopores in this embodiment of the scenario are different, and the rest of the manufacturing methods are the same. Specifically, it includes:

[0079] The conductive bridge memory is obtained by performing the following steps based on the substrate 10 made of Si:

[0080] Step S602, depositing and growing a first metal layer 20 on the substrate 10 by electron beam evaporation, wherein the material of the first metal layer 20 is Cu, and the thickness is 500 nanometers;

[0081] Step S604, epitaxially growing a first dielectric layer 30 on the first metal layer 20 by magnetron sputtering technology, wherein the dielectric layer 30 is made of CuO and has a thickness of 50 nanometers;

[0082] Step S606, epitaxially growing a second dielectric layer 31 on the first dielectric layer 30 by PLD technology, wherein the material of the second dielectric layer is Al2O3 and the thickness is 50 nanometers;

[0083] Step S608, epitaxially growing a third dielectric layer 32 on the second dielectric layer 31 by PECVD technology, wherein the material of the third dielectric layer 32 is SiO2, and the thickness is 30 nanometers;

[0084] In this embodiment, each dielectric layer may be grown using the same epitaxial technology and material, or may be grown using different epitaxial technologies and materials.

[0085] Step S610, forming a mask layer on the third dielectric layer 32 and marking a first irradiation area, wherein the irradiation diameter is 5 nanometers and the mask layer material is Ni;

[0086] Step S612, high-energy particle irradiation is performed on the first irradiation area on the third dielectric layer 32 at an irradiation angle of 80° until the nano-through hole 50; wherein the high-energy particles are Cu ions;

[0087] Step S614, forming a mask layer again on the third dielectric layer 32 and marking a second irradiation area to enlarge the top diameter of the nano-via 50;

[0088] Step S616, wet-etching the second irradiated area on the third dielectric layer 32 with a chemical solution until a funnel shape is formed on the surface thereof, wherein the opening diameter of the enlarged portion is 30 nanometers and the height is 30 nanometers, and the chemical solution is a hydrofluoric acid solution;

[0089] Step S618, after washing away the mask layer on the third dielectric layer 32, a second metal layer 40 is deposited by electron beam evaporation, wherein the second metal layer 40 is Al and has a thickness of 500 nanometers.

[0090] In this embodiment, part of the metal of the second metal layer 40 is filled into the funnel shape formed in step S616 to obtain a metal nano-funnel structure 60 .

[0091] Scenario Example 4

[0092] Figure 5 1 is a schematic diagram of the structure of a conductive bridge memory according to the fourth embodiment of the present invention. Compared with the first embodiment of the present invention, the dielectric layer structure and the extended shape of the nano-holes in the present embodiment of the present invention are different, and the rest of the manufacturing methods are the same. Specifically, it includes:

[0093] The conductive bridge memory is obtained by performing the following steps based on the substrate 10 made of Si:

[0094] Step S702, depositing and growing a first metal layer 20 on the substrate 10 by electron beam evaporation, wherein the material of the first metal layer 20 is Cu, and the thickness is 500 nanometers;

[0095] Step S704, epitaxially growing a first dielectric layer 30 on the first metal layer 20 by PEALD technology, wherein the dielectric layer 30 is made of SiO2 and has a thickness of 200 nanometers;

[0096] Step S706, forming a mask layer on the first dielectric layer 30 and marking an opening area, wherein the opening diameter of the opening area is 50 nanometers, and the mask layer material is photoresist;

[0097] Step S708, the opening area on the first dielectric layer 30 is formed at 60° (i.e. Figure 5 ICP etching is performed at an etching angle of θ1) in the figure until the first nano-via 51 extends to the first metal layer 20;

[0098] Step S710, epitaxially growing a second dielectric layer 31 on the first dielectric layer 30 by PEALD technology, wherein the material of the second dielectric layer 31 is SiO2, and the thickness is 200 nanometers;

[0099] Step S712, forming a mask layer on the second dielectric layer 31 and marking an opening area, wherein the opening diameter of the opening area is 30 nanometers, and the mask layer material is photoresist;

[0100] Step S714, the opening area of ​​the second dielectric layer 31 is cut at 70° (i.e. Figure 5 ICP etching is performed at an etching angle of θ2) in the figure until the second nano-via 52 extends to the first dielectric layer 30;

[0101] Step S716, epitaxially growing a third dielectric layer 32 on the second dielectric layer 31 by PEALD technology, wherein the material of the third dielectric layer 32 is SiO2, and the thickness is 200 nanometers;

[0102] Step S718, forming a mask layer on the third dielectric layer 32 and marking an opening area, wherein the opening diameter of the opening area is 10 nanometers, and the mask layer material is photoresist;

[0103] Step S720, the opening area on the third dielectric layer 32 is cut at 80° (i.e. Figure 5 ICP etching is performed at an etching angle of θ3) in the middle until the third nano-via 53 extends to the second dielectric layer 31;

[0104] Step S722, forming a mask layer again on the third dielectric layer 32 and marking the opening area to enlarge the top diameter of the third dielectric layer 32, wherein the top diameter is 30 nanometers;

[0105] Step S724, wet-etching the opening area on the third dielectric layer 32 with a chemical solution until a funnel shape is formed on the surface thereof, wherein the diameter of the top of the funnel shape is 30 nanometers and the height is 30 nanometers, and the chemical solution is a hydrofluoric acid solution;

[0106] Step S726 , after washing away the mask layer on the third dielectric layer 32 , a second metal layer 40 is deposited by electron beam evaporation, wherein the material of the second metal layer 40 is Al, and the thickness is 500 nanometers.

[0107] In this embodiment, part of the metal of the second metal layer 40 is filled into the funnel shape formed in step S724 to obtain a metal nano-funnel structure 60 .

[0108] Through the above-mentioned preparation method of the conductive filament controllable CBRAM, the tip electric field of the metal nanofunnel structure can be formed by prefabricating the path for the conductive filament. The preparation process is simple, flexible and accurate, and it is also easy to combine with the traditional CMOS process.

[0109] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present invention shall be included in the protection scope of the present invention.

Claims

1. A conductive bridge memory, characterized in that: include: A substrate layer, a first metal layer disposed above the substrate layer, a dielectric layer disposed above the first metal layer, and a second metal layer disposed above the dielectric layer; Wherein, a nano-through hole is opened in the dielectric layer to connect the first metal layer and the second metal layer.

2. The conductive bridge memory according to claim 1, characterized in that: in, An angle is formed between the nano-via and the first metal layer.

3. The conductive bridge memory according to claim 1, characterized in that: in, The top cross-sectional diameter of the nano-via is larger than the bottom cross-sectional diameter of the nano-via, the top is the end of the nano-via connected to the second metal layer, and the bottom is the end of the nano-via connected to the first metal layer.

4. The conductive bridge memory according to claim 1, characterized in that: in, The top of the nano-through hole is in a funnel shape.

5. The conductive bridge memory according to claim 4, characterized in that: Also includes: The metal nano funnel structure is formed by partially filling the funnel shape with the metal of the second metal layer.

6. The conductive bridge memory according to claim 1, characterized in that: in, There are multiple dielectric layers, each of which is provided with nano-through holes, and the nano-through holes in each dielectric layer are interconnected.

7. The conductive bridge memory according to claim 6, characterized in that: in, The angles between the nano-via holes in each dielectric layer and the first metal layer are different.

8. A method for manufacturing a conductive bridge memory, characterized in that: include: Depositing a first metal layer on the substrate by a deposition method; epitaxially grow a dielectric layer on the first metal layer by using an epitaxial technology, and form a mask layer on the dielectric layer; and opening a nano-through hole in the dielectric layer at a preset angle according to the opening area marked by the mask layer; The second metal layer is deposited on the dielectric layer after the holes are opened by the deposition method.

9. The method according to claim 8, characterized in that According to the opening area marked by the mask layer, a nano-through hole is opened in the dielectric layer at a preset angle, comprising: According to the opening area marked by the first mask layer, opening the nano-through hole in the dielectric layer at a preset angle; A second mask layer is formed multiple times at the nano-through hole of the dielectric layer, and the area of ​​the top hole of the nano-through hole is expanded according to the opening area marked by the second mask layer, until the top of the nano-through hole presents a preset funnel shape, wherein the top is one end of the nano-through hole connected to the second metal layer.

10. The method according to claim 9, characterized in that Depositing a second metal layer on the dielectric layer after the opening by the deposition method includes: Part of the metal of the second metal layer is filled into the funnel shape to form a metal nano funnel structure.

11. The method according to claim 8, characterized in that: Epitaxially growing a dielectric layer on the first metal layer by using an epitaxial growth technology, including: A plurality of dielectric layers are epitaxially grown one by one on the first metal layer by using the epitaxial growth technology.

12. The method according to claim 11, characterized in that Opening a nano-through hole in the dielectric layer at a preset angle comprises: A nano-through hole is opened in each of the plurality of dielectric layers at different preset angles, and the nano-through holes in each dielectric layer are interconnected.

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