Monolithic stacked field effect transistor (SFET) with dual intermediate dielectric isolation (MDI) separation

Abstract

Embodiments of the invention relate to monolithic stacked field effect transistor (SFET) processing methods and resulting structures with dual intermediate dielectric isolation (MDI) separation. In a non-limiting embodiment of the invention, a first nanosheet is formed, and a second nanosheet is vertically stacked over the first nanosheet. A gate is formed around the channel region of the first nanosheet and the channel region of the second nanosheet, and an intermediate dielectric isolation structure is formed between the first nanosheet and the second nanosheet. The intermediate dielectric isolation structure includes a first intermediate dielectric isolation layer and a second intermediate dielectric isolation layer vertically stacked over the first intermediate dielectric isolation layer. A portion of the gate extends between the first intermediate dielectric isolation layer and the second intermediate dielectric isolation layer in the intermediate dielectric isolation structure.

Description

Background Art

[0001] The present invention generally relates to methods of fabricating semiconductor devices and the resulting structures, and more particularly, to methods of processing monolithically stacked field effect transistors (SFETs) with dual inter-dielectric isolation (MDI) separation and the resulting structures.

[0002] Known metal oxide semiconductor field effect transistor (MOSFET) manufacturing technology includes a process flow for building a planar field effect transistor (FET). A planar FET includes a substrate (also called a silicon slab); a gate formed above the substrate; source and drain regions formed on opposite sides of the gate; and a channel region below the gate near the surface of the substrate. The channel region electrically connects the source and drain, while the gate controls the current in the channel. The gate voltage controls whether the path from the drain to the source is an open circuit ("off") or a resistive path ("on").

[0003] In recent years, research has been devoted to developing non-planar transistor architectures. For example, GAA transistors (also known as nanosheet FETs or nanowire FETs) include non-planar architectures that provide improved device density and a degree of enhanced performance relative to lateral devices. Unlike traditional planar FETs, in nanosheet FETs, the channel is implemented as multiple stacked and spaced nanosheets. The gate stack surrounds the entire periphery of each nanosheet, achieving more adequate depletion of the channel region and reducing short channel effects due to steeper subthreshold swings (SS) and smaller drain-induced barrier lowering (DIBL). As MOSFET manufacturing continues to develop, stacked FET architectures are being studied to meet aggressive gate length (Lg) scaling requirements and current drive capabilities. In a stacked FET, two (or more) FETs are stacked vertically above a substrate to reduce the overall device footprint. Summary of the invention

[0004] Embodiments of the present invention relate to methods for forming a stacked semiconductor device with dual intermediate dielectric isolation (MDI) separation. A non-limiting example of the method includes forming a first nanosheet and vertically stacking a second nanosheet above the first nanosheet. A gate is formed around a channel region of the first nanosheet and a channel region of the second nanosheet, and an intermediate dielectric isolation structure is formed between the first nanosheet and the second nanosheet. The intermediate dielectric isolation structure includes a first intermediate dielectric isolation layer and a second intermediate dielectric isolation layer vertically stacked above the first intermediate dielectric isolation layer. A portion of the gate extends between the first intermediate dielectric isolation layer and the second intermediate dielectric isolation layer in the intermediate dielectric isolation structure.

[0005] In some embodiments, the method further includes forming a first nanosheet stack including the first nanosheet and one or more additional nanosheets, and a second nanosheet stack including the second nanosheet and one or more additional nanosheets, such that the stacked transistor architecture has an arbitrary number of channels.

[0006] In some embodiments, the semiconductor device is a stacked field effect transistor having a reduced footprint compared to a non-stacked architecture. In some embodiments, the gate is a common gate of the stacked field effect transistor. In some embodiments, the gate includes a first portion (i.e., a first gate) and a second portion (i.e., a second gate) electrically isolated from the first portion. In some embodiments, the first portion serves as a gate for the first nanosheet, and the second portion serves as a separate gate for the second nanosheet.

[0007] In some embodiments, the stacked field effect transistor includes a stacked pFET and an nFET to implement a complementary stacked field effect transistor structure. In some embodiments, the first nanosheet stack defines a portion of one of the nFET and the pFET, and the second nanosheet stack defines a portion of the other of the nFET and the pFET.

[0008] In some embodiments, the method further includes forming a first source or drain region in direct contact with the sidewall of the first nanosheet, and forming a second source or drain region in direct contact with the sidewall of the second nanosheet. In some embodiments, an intermediate interlayer dielectric is formed between the first source or drain region and the second source or drain region. The intermediate interlayer dielectric can be in direct contact with the sidewall of the first intermediate dielectric isolation layer and the sidewall of the second intermediate dielectric isolation layer, ensuring isolation between stacked FETs in the final device. In some embodiments, the first source or drain region includes a first doping type (e.g., n-type or p-type), and the second source or drain region includes a second doping type (e.g., p-type or n-type) opposite to the first doping type, allowing a complementary transistor architecture (e.g., CMOS).

[0009] In some embodiments, the thickness of the first intermediate dielectric spacer layer and the thickness of the second intermediate dielectric spacer layer are less than or equal to 10 nanometers. Advantageously, limiting the thickness of each intermediate dielectric spacer layer according to one or more embodiments avoids defects related to epitaxy and improves the performance and reliability of the final device.

[0010] Embodiments of the present invention relate to semiconductor structures. A non-limiting example of the semiconductor structure includes a first nanosheet and a second nanosheet vertically stacked above the first nanosheet. A gate is formed around a channel region of the first nanosheet and a channel region of the second nanosheet. An intermediate dielectric isolation structure is formed between the first nanosheet and the second nanosheet. The intermediate dielectric isolation structure includes a first intermediate dielectric isolation layer and a second intermediate dielectric isolation layer vertically stacked above the first intermediate dielectric isolation layer. A portion of the gate extends between the first intermediate dielectric isolation layer and the second intermediate dielectric isolation layer in the intermediate dielectric isolation structure.

[0011] Additional technical features and advantages are achieved through the technology of the present invention. Various embodiments and aspects of the present invention are described in detail herein and are considered part of the claimed subject matter. For a better understanding, reference is made to the detailed description and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The specific content of the exclusive rights described herein is specifically pointed out and clearly required in the claims at the end of the specification. The foregoing and other features and advantages of various embodiments of the present invention will become more apparent from the following detailed description in conjunction with the accompanying drawings, in which:

[0013] Figure 1A depicts a first cross-sectional view (across a gate in a channel region) of a semiconductor wafer after an initial set of processing operations in accordance with one or more embodiments of the present invention;

[0014] Figure 1B Depicts a process that follows an initial set of processing operations according to one or more embodiments of the present invention. Figure 1A a second cross-sectional view of the semiconductor wafer in FIG. 1 (along the gate in the channel region);

[0015] Figure 2A depicts a cross-sectional view across a gate of a semiconductor wafer after processing operations in accordance with one or more embodiments of the present invention;

[0016] Figure 2B Depicts a process after processing operations according to one or more embodiments of the present invention. Figure 2A A cross-sectional view of a semiconductor wafer along a gate electrode;

[0017] Figure 3A depicts a cross-sectional view across a gate of a semiconductor wafer after processing operations in accordance with one or more embodiments of the present invention;

[0018] Figure 3B Depicts a process after processing operations according to one or more embodiments of the present invention. Figure 3AA cross-sectional view of a semiconductor wafer along a gate electrode;

[0019] Figure 4A depicts a cross-sectional view across a gate of a semiconductor wafer after processing operations in accordance with one or more embodiments of the present invention;

[0020] Figure 4B Depicts a process after processing operations according to one or more embodiments of the present invention. Figure 4A A cross-sectional view of a semiconductor wafer along a gate electrode;

[0021] Figure 5A depicts a cross-sectional view across a gate of a semiconductor wafer after processing operations in accordance with one or more embodiments of the present invention;

[0022] Figure 5B Depicts a process after processing operations according to one or more embodiments of the present invention. Figure 5A A cross-sectional view of a semiconductor wafer along a gate electrode;

[0023] Fig. 6A depicts a cross-sectional view across a gate of a semiconductor wafer after processing operations in accordance with one or more embodiments of the present invention;

[0024] Figure 6B Depicts a process after processing operations according to one or more embodiments of the present invention. Fig. 6A A cross-sectional view of a semiconductor wafer along a gate electrode;

[0025] Fig. 7A depicts a cross-sectional view across a gate of a semiconductor wafer after processing operations in accordance with one or more embodiments of the present invention;

[0026] Figure 7B Depicts a process after processing operations according to one or more embodiments of the present invention. Fig. 7A A cross-sectional view of a semiconductor wafer along a gate electrode;

[0027] Fig. 8A depicts a cross-sectional view across a gate of a semiconductor wafer after processing operations in accordance with one or more embodiments of the present invention;

[0028] Figure 8B Depicts a process after processing operations according to one or more embodiments of the present invention. Fig. 8A A cross-sectional view of a semiconductor wafer along a gate electrode;

[0029] Fig.9A depicts a cross-sectional view across a gate of a semiconductor wafer after processing operations in accordance with one or more embodiments of the present invention;

[0030] Fig. 9B Depicts a process after processing operations according to one or more embodiments of the present invention. Fig.9A A cross-sectional view of a semiconductor wafer along a gate electrode;

[0031] Fig. 10A depicts a cross-sectional view across a gate of a semiconductor wafer after processing operations in accordance with one or more embodiments of the present invention;

[0032] Fig. 10B Depicts a process after processing operations according to one or more embodiments of the present invention. Fig. 10A A cross-sectional view of a semiconductor wafer along a gate electrode;

[0033] Fig.11A depicts a cross-sectional view across a gate of a semiconductor wafer after processing operations in accordance with one or more embodiments of the present invention;

[0034] Fig. 11B Depicts a process after processing operations according to one or more embodiments of the present invention. Fig.11A A cross-sectional view of a semiconductor wafer along a gate electrode;

[0035] Fig. 12A depicts a cross-sectional view across a gate of a semiconductor wafer after processing operations in accordance with one or more embodiments of the present invention;

[0036] Fig. 12B Depicts a process after processing operations according to one or more embodiments of the present invention. Fig. 12A A cross-sectional view of a semiconductor wafer along a gate electrode;

[0037] Fig.13 A flow chart illustrating a method according to one or more embodiments of the invention is depicted.

[0038] The diagrams described herein are illustrative. There may be many variations of the diagrams or the operations described therein without departing from the spirit of the present invention. For example, the actions may be performed in a different order, or may be added, deleted, or modified.

[0039] In the accompanying drawings and the following detailed description of the described embodiments of the present invention, each element illustrated in the drawings is provided with two or three reference numerals. With few exceptions, the (multiple) leftmost digits of each reference numeral correspond to the figure in which the element is first illustrated. DETAILED DESCRIPTION

[0040] It is understood in advance that although exemplary embodiments of the present invention are described in association with specific transistor architectures, the embodiments of the present invention are not limited to the specific transistor architectures or materials described in this specification. Instead, the embodiments of the present invention can be implemented in combination with any other type of transistor architecture or material now known or subsequently developed.

[0041] For the sake of brevity, conventional techniques related to semiconductor device and integrated circuit (IC) fabrication may or may not be described in detail herein. In addition, various tasks and processing steps described herein may be included in more comprehensive procedures or processes having additional steps and functions not described in detail herein. In particular, various steps in the fabrication of semiconductor devices and semiconductor-based ICs are well known, and therefore, for the sake of brevity, many conventional steps will only be briefly mentioned herein or will be omitted entirely without providing well-known process details.

[0042] Turning now to an overview of the technology more specifically related to aspects of the present invention, ICs are manufactured in a series of stages, including front-end-of-line (FEOL) stages, middle-of-line (MOL) stages, and back-end-of-line (BEOL) stages. The process flow for manufacturing modern ICs is typically identified based on whether the process flow belongs to the FEOL stage, the MOL stage, or the BEOL stage. In general, the FEOL stage is the stage where device elements (e.g., transistors, capacitors, resistors, etc.) are patterned on a semiconductor substrate / wafer. The FEOL stage processes include wafer preparation, isolation, gate patterning, and the formation of wells, source / drain (S / D) regions, extension junctions, silicide regions, and liners. The MOL stage typically includes process flows for forming contacts (e.g., CAs) and other structures that are communicatively coupled to the active regions (e.g., gates, sources, and drains) of the device elements. For example, silicidation of the source / drain regions and deposition of metal contacts can occur during the MOL stage to connect the elements patterned during the FEOL stage. During the BEOL phase, interconnect layers (e.g., metallization layers) are formed on top of these logic and functional layers to complete the IC. Most ICs require more than one layer of wires to form all the necessary connections, and as many as 5-12 layers are added during the BEOL process. The various BEOL layers are interconnected by vias that couple from one layer to another. Insulating dielectric materials are used in the layers of an IC to perform a variety of functions, including stabilizing the IC structure and providing electrical isolation of IC components. For example, metal interconnect wires in the BEOL region of an IC are isolated by dielectric layers to prevent shorts between the wires and other metal layers.

[0043] There are several non-planar transistor architectures for scaling transistors below the 7nm node, but each is currently limited due to various factors. One such architecture is the so-called stacked field effect transistor (FET). In order to increase the available computing power per unit area, a stacked FET device (or SFET) vertically stacks two (or more) FETs above a shared substrate footprint. The resulting stacked transistor architecture provides several improvements over planar and fin-type devices, such as the ability to build complementary devices (e.g., CMOS) with a smaller footprint. However, the manufacture of SFETs is challenging, and efforts are still underway to design SFET manufacturing schemes and structures suitable for mass production.

[0044] Monolithic SFET formation, for example, builds two (or more) FETs monolithically, i.e., continuously builds two (or more) FETs from a common stack of semiconductors and sacrificial layers. This is different from other SFET formation techniques, in which two wafers are processed separately (i.e., a semiconductor stack is built on each wafer) and later combined by a wafer bonding process. For monolithic SFET formation, one of the key challenges is to provide a wider separation between the top FET and the bottom FET. Without sufficient separation, top to bottom source / drain epitaxial shorts, work function metal (WFM) patterning undercuts, and other structural problems may occur. The top FET and the bottom FET are electrically isolated from each other by an intermediate dielectric isolation (MDI) layer. The thickness of this layer corresponds to the thickness of the intermediate sacrificial layer in the common stack. Unfortunately, directly increasing the thickness of the intermediate sacrificial layer (exceeding, for example, about 10 nanometers) leads to inner spacer shape and uniformity problems and epitaxial defects.

[0045] Turning now to an overview of aspects of the present invention, one or more embodiments of the present invention address the above-mentioned shortcomings by providing a monolithic SFET fabrication method and a resulting structure having a dual intermediate dielectric isolation (MDI) layer (also referred to as a dual-layer MDI separation. Advantageously, each MDI layer can be formed to a thickness of less than 10 nanometers while still providing an overall separation between the top FET and the bottom FET greater than 10 nanometers.

[0046] The monolithic SFET manufactured according to one or more embodiments largely avoids the manufacturing and structural problems associated with thicker (e.g., greater than about 10 nanometers) intermediate sacrificial layers. In some embodiments, an intermediate interlayer dielectric (ILD) is located between the top and bottom source / drain epitaxies adjacent to the MDI layer. The intermediate ILD supports the MDI layer to prevent the top to bottom source / drain epitaxies from shorting. In addition, although for convenience, various aspects of the present invention are discussed primarily with respect to double-layer MDI separations, the number of MDI layers need not be so limited. In some embodiments, any number of MDI layers can collectively define a multilayer MDI separation with an arbitrary total height thickness while ensuring that all component MDI layers have a defined thickness, such as, for example, a thickness of less than 10 nanometers.

[0047] Turning now to a more detailed description of manufacturing operations and resulting structures according to aspects of the present invention, Figure 1A Depicted is a first cross-sectional view (gate across the channel region) of a semiconductor wafer 100 after an initial set of fabrication operations have been applied as part of a method of manufacturing a final semiconductor device in accordance with one or more embodiments of the present invention. Figure 1B Depicted Figure 1A FIG. 1 is a second cross-sectional view of the semiconductor wafer 100 (the gate along the channel region).

[0048] like Figure 1A As shown, the first nanosheet stack 102 is formed above the second nanosheet stack 104. The first nanosheet stack 102 and the second nanosheet stack 104 are formed together on a substrate 106. In some embodiments, the first nanosheet stack 102 and the second nanosheet stack 104 each include one or more nanosheets 108 alternating with two or more sacrificial layers 110. In some embodiments, the nanosheets 108 and the sacrificial layers 110 are epitaxially grown layers. For ease of discussion, reference is made to a substrate having three sacrificial layers (e.g., Figure 1A The three sacrificial layers 110 of the first nanosheet stack 102 and the second nanosheet stack 104 shown in FIG. 1 are respectively alternately two nanosheets (eg, Figure 1A108 in the first nanosheet stack 102 and the second nanosheet stack 104, respectively. However, it will be appreciated that the first nanosheet stack 102 and the second nanosheet stack 104 may include any number of nanosheets alternating with a corresponding number of sacrificial layers. For example, the nanosheet stacks 102, 104 may include two nanosheets, five nanosheets, eight nanosheets, thirty nanosheets (e.g., 3D NAND), or any number of nanosheets, and a corresponding number of sacrificial layers (i.e., appropriately formed nanosheet stacks having a topmost sacrificial layer, a bottommost sacrificial layer, and a sacrificial layer between each pair of adjacent nanosheets). Furthermore, the number of nanosheets 108 in the first nanosheet stack 102 and the second nanosheet stack 104 need not be the same, and other configurations having any nanosheet distribution are also within the scope of the present disclosure.

[0049] The nanosheets 108 and the substrate 106 may be made of any suitable semiconductor material, such as, for example, single crystal silicon (Si), silicon germanium (SiGe), III-V compound semiconductors, II-VI compound semiconductors, or silicon on insulator (SOI). Group III-V compound semiconductors include, for example, materials containing at least one Group III element and at least one Group V element, such as aluminum gallium arsenide (AlGaAs), aluminum gallium nitride (AlGaN), aluminum arsenide (AlAs), aluminum indium arsenide (AlInAs), aluminum nitride (AlN), gallium antimonide (GaSb), gallium antimonide aluminum (GaAlSb), gallium arsenide (GaAs), gallium arsenide antimonide (GaAsSb), gallium nitride (GaN), indium antimonide (InSb), indium arsenide (InAs), indium gallium arsenide (InGaAs), indium gallium arsenide phosphide (InGaAsP), indium gallium nitride (InGaN), indium nitride (InN), indium phosphide (InP), and one or more of an alloy combination including at least one of the above materials. Alloy combinations may include binary alloys (two elements, e.g., gallium (III) arsenide (GaAs)), ternary alloys (three elements, e.g., InGaAs), and quaternary alloys (four elements, e.g., aluminum gallium indium phosphide (AlInGaP)). The nanosheets 108 and substrate 106 may be made of the same or different semiconductor materials. In some embodiments, the nanosheets 108 have a thickness of about 5 nm to about 15 nm (e.g., 10 nanometers), although other thicknesses are also within the contemplated scope of the present disclosure.

[0050] In some embodiments, the substrate 106 is constructed as a silicon-on-insulator (SOI) substrate having a buried oxide layer 112. The buried oxide layer 112 may be made of any suitable material, such as, for example, silicon oxide (SiO 2) or silicon germanium. In some embodiments, the buried oxide layer 112 is formed to a thickness of about 10-200 nm, although other thicknesses are also within the contemplated scope of the present disclosure.

[0051] Depending on the material of the nanosheet 108, the sacrificial layer 110 can be made of silicon, silicon germanium, or other semiconductor materials to meet the etching selectivity requirements. For example, in an embodiment where the nanosheet 108 is a silicon nanosheet, the sacrificial layer 110 can be a silicon germanium layer. In an embodiment where the nanosheet 108 is a silicon germanium nanosheet, the sacrificial layer 110 can be a silicon layer or a silicon germanium layer having a higher germanium concentration than the germanium concentration in the nanosheet 108. For example, if the nanosheet 108 is a silicon germanium with a germanium concentration of 5 percent (sometimes referred to as SiGe5), the sacrificial layer 110 can be a silicon germanium layer with a germanium concentration of 25 percent (SiGe25), although other germanium concentrations are also within the scope of the present disclosure. In some embodiments, the sacrificial layer 110 has a thickness of about 5 nm to about 12 nm (e.g., 10 nm), although other thicknesses are also within the scope of the present disclosure.

[0052] In some embodiments, the first nanosheet stack 102 and the second nanosheet stack 104 are separated by an isolation structure 114. The isolation structure 114 may include a top sacrificial layer 116, a bottom sacrificial layer 118, and an intermediate sacrificial layer 120 located between the top sacrificial layer 116 and the bottom sacrificial layer 118. In some embodiments, the intermediate sacrificial layer 120 uses the same material as the sacrificial layer 110, although other materials may also be used.

[0053] The materials of the top sacrificial layer 116 and the bottom sacrificial layer 118 are selected to ensure etching selectivity with respect to the nanosheet 108, the sacrificial layer 110, and the intermediate sacrificial layer 120. For example, in an embodiment where the nanosheet 108 is a silicon nanosheet and the sacrificial layers 110, 120 are SiGe30 layers, the top sacrificial layer 116 and the bottom sacrificial layer 118 can be SiGe55 layers, although other germanium concentrations are also within the scope of the present disclosure. In some embodiments, the top sacrificial layer 116 and the bottom sacrificial layer 118 are formed to a thickness of no more than 10 nanometers, although other thicknesses are also within the scope of the present disclosure.

[0054] like Figure 1B 1 , the first nanosheet stack 102 and the second nanosheet stack 104 can be patterned in a process known as nanosheet patterning. In some embodiments, portions of the first nanosheet stack 102 and the second nanosheet stack 104 are removed to expose the surface of the substrate 106, which is then recessed to define a cavity (not separately shown). A shallow trench isolation (STI) region 122 can be formed by refilling the cavity with a dielectric.

[0055] Figure 2Aand Figure 2B 1 and 2 respectively depict cross-sectional views of a semiconductor wafer 100 across and along the gate after processing operations according to one or more embodiments. Figure 2A and Figure 2B , a sacrificial gate 202 (sometimes referred to as a dummy gate) is formed and patterned over the channel region of the first nanosheet stack 102 and the second nanosheet stack 104. As used herein, "channel region" refers to the portion of the nanosheet on which a conductive gate (described in further detail below) is formed, and through which current flows from the source to the drain in the final device. The sacrificial gate 202 can be made of any suitable material, such as, for example, amorphous silicon or polycrystalline silicon. Any known method for patterning a sacrificial gate can be used, such as, for example, wet etching, dry etching, or a combination of a series of wet and / or dry etching. In some embodiments, a hard mask 204 is formed on the sacrificial gate 202. The hard mask 204 can be made of any suitable material, such as, for example, silicon nitride.

[0056] Figure 3A and Figure 3B 1 and 2 respectively depict cross-sectional views of a semiconductor wafer 100 across and along the gate after processing operations according to one or more embodiments. Figure 3A and Figure 3B 3, the top sacrificial layer 116 and the bottom sacrificial layer 118 are removed to define the cavity 302. The top sacrificial layer 116 and the bottom sacrificial layer 118 can be removed using, for example, wet etching, dry etching, or a combination of a series of wet and / or dry etching. In some embodiments, the top sacrificial layer 116 and the bottom sacrificial layer 118 are removed selectively to the nanosheet 108, the sacrificial layer 110, and the intermediate sacrificial layer 120.

[0057] Figure 4A and Figure 4B 1 and 2 respectively depict cross-sectional views of a semiconductor wafer 100 across and along the gate after processing operations according to one or more embodiments. Figure 4A , gate spacers 402 are formed on the sidewalls of sacrificial gate 202. This process may be referred to as a gate spacer module. Gate spacers 402 may be made of any suitable dielectric material, such as, for example, silicon oxide, silicon nitride, silicon carbide, hydrogenated silicon carbonitrides, silicon oxynitrides, and silicon borocarbonitrides, although other dielectrics are also within the scope of the present disclosure. In some embodiments, the spacer material is deposited over semiconductor wafer 100 and patterned using anisotropic etching, such as reactive ion etching (RIE).

[0058] like Figure 4A and Figure 4B , during the gate spacer module, the cavity 302 is filled with a dielectric, defining a top MDI layer 404 and a bottom MDI layer 406. The top MDI layer 404 and the bottom MDI layer 406 together define a double-layer MDI partition between the first nanosheet stack 102 and the second nanosheet stack 104.

[0059] Figure 5A and Figure 5B 1 and 2 respectively depict cross-sectional views of a semiconductor wafer 100 across and along the gate after processing operations according to one or more embodiments. Figure 5A As shown, a FEOL fabrication process is used to form inner spacers 502 , top source / drain regions 504 , bottom source / drain regions 506 , and an intermediate ILD 508 located between the top source / drain regions 504 and the bottom source / drain regions 506 .

[0060] In some embodiments, the first nanosheet stack 102 and the second nanosheet stack 104 are recessed, the sacrificial layers 110 and 120 are recessed, and the inner spacer 502 is formed in the recesses. In some embodiments, the sacrificial layers 110 and 120 are recessed selectively to the nanosheet 108 .

[0061] In some embodiments, the bottom source / drain region 506 is epitaxially grown or otherwise formed on the exposed surface of the substrate 106 after recessing the first nanosheet stack 102 and the second nanosheet stack 104. Additionally or alternatively, the bottom source / drain region 506 may also be epitaxially grown from the exposed sidewalls of the nanosheet 108.

[0062] In some embodiments, an intermediate ILD 508 is deposited or otherwise formed on the bottom source / drain regions 506. The intermediate ILD 508 may be made of any suitable dielectric material, such as, for example, oxide, low-k dielectric, nitride, silicon nitride, silicon oxide, SiON, SiC, SiOCN, and SiBCN.

[0063] In some embodiments, the top source / drain region 504 is formed on the surface of the middle ILD 508. In some embodiments, the top source / drain region 504 can be epitaxially grown from the exposed sidewalls of the nanosheet 108.

[0064] Advantageously, due to the dual-layer MDI separation constructed according to one or more embodiments, a middle ILD 508 height H (i.e., the distance between the top source / drain region 504 and the bottom source / drain region 506) greater than 10 nanometers is easily achieved, allowing variations in epitaxial growth thickness and ILD etch-back rate without causing structural or electrical defects.

[0065] Fig. 6A and Figure 6B 1 and 2 respectively depict cross-sectional views of a semiconductor wafer 100 across and along the gate after processing operations according to one or more embodiments. Fig. 6A As shown, ILD 602 ​​is formed by deposition or otherwise over top source / drain regions 504. ILD 602 ​​may be made of any suitable dielectric material, such as, for example, oxide, low-k dielectric, nitride, silicon nitride, silicon oxide, SiON, SiC, SiOCN, and SiBCN.

[0066] like Fig. 6A and Figure 6B As shown, the semiconductor wafer 100 may be polished (planarized) to remove the hard mask 204. The semiconductor wafer 100 may be polished using any suitable method, such as, for example, chemical mechanical planarization (CMP). In some embodiments, the semiconductor wafer 100 may be polished to the surface of the sacrificial gate 202.

[0067] Fig. 7A and Figure 7B 1 and 2 depict cross-sectional views of the semiconductor wafer 100 across and along the gate, respectively, after processing operations according to one or more embodiments. Fig. 7A As shown, the sacrificial gate 202 and sacrificial layers 110, 120 are removed to release the nanosheets 108. The sacrificial gate 202 may be removed using a wet etch, a dry etch, or a combination of a series of wet and / or dry etches.

[0068] The sacrificial layers 110, 120 can be selectively removed with respect to the nanosheets 108. For example, when the nanosheets 108 are composed of silicon and the sacrificial layers 110, 120 are composed of silicon germanium, hydrogen chloride (HCl) gas or an aqueous solution containing a mixture of ammonia and hydrogen peroxide can be used to selectively remove silicon germanium relative to silicon. In another example, when the nanosheets 108 are composed of silicon germanium and the sacrificial layers 110, 120 are composed of silicon, water-soluble hydroxide chemicals including ammonium hydroxide and potassium hydroxide can be used to selectively remove silicon relative to silicon germanium.

[0069] Fig. 8A and Figure 8B1 and 2 respectively depict cross-sectional views of a semiconductor wafer 100 across and along the gate after processing operations according to one or more embodiments. Fig. 8A and Figure 8B As shown, the removed sacrificial gate 202 ( Fig. 7A ) can be replaced by a conductive gate 802.

[0070] The conductive gate 802 may be a high-k metal gate (HKMG) formed over the channel regions of the first nanosheet stack 102 and the second nanosheet stack 104 using a known replacement metal gate (RMG) process or a so-called gate-last process. In some embodiments, the conductive gate 802 may include a gate dielectric and a work function metal stack (not shown separately). Although only a single gate (i.e., a common gate stack) is shown for ease of illustration and discussion, it should be understood that the conductive gate 802 may include separate gate portions of the first nanosheet stack 102 and the second nanosheet stack 104. That is, in some embodiments, each gate portion may be electrically isolated from each other using, for example, one or more interlayer dielectric layers (not shown separately).

[0071] In some embodiments, the gate dielectric is a high-k dielectric film formed on the surface (sidewall) of the nanosheet 108. The high-k dielectric film can be made of, for example, silicon oxide, silicon nitride, silicon oxynitride, boron nitride, high-k materials, or any combination of these materials. Examples of high-k materials include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The high-k material may also include dopants such as lanthanum and aluminum. In some embodiments of the present invention, the high-k dielectric film may have a thickness of about 0.5 nm to about 4 nm. In some embodiments of the present invention, the high-k dielectric film includes hafnium oxide and has a thickness of about 1 nm, although other thicknesses are also within the scope of the present disclosure.

[0072] If present, the work function metal stack may include one or more work function layers, which are located between the high-k dielectric film and the bulk gate material. In some embodiments, the conductive gate 802 includes one or more work function layers, but does not include the main gate material. The work function layer can be made of, for example, aluminum, lanthanum oxide, magnesium oxide, strontium titanate, strontium oxide, titanium nitride, tantalum nitride, hafnium nitride, tungsten nitride, molybdenum nitride, niobium nitride, hafnium silicon nitride, titanium aluminum nitride, tantalum silicon nitride, titanium aluminum carbide, tantalum carbide and combinations thereof. The work function layer can be used to adjust the work function of the conductive gate 802 and achieve the adjustment of the device threshold voltage. The work function layer can be formed to a thickness of about 0.5 to 6nm, although other thicknesses are also within the scope of the present disclosure. In some embodiments, each work function layer can be formed to a different thickness.

[0073] In some embodiments, the conductive gate 802 includes a body formed of a main conductive gate material deposited over the work function layer and / or the gate dielectric. The bulk gate material may include any suitable conductive material, such as, for example, a metal (e.g., tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminum, lead, platinum, tin, silver, gold), a conductive metal compound material (e.g., tantalum nitride, titanium nitride, tantalum carbide, titanium carbide, titanium aluminum carbide, tungsten silicide, tungsten nitride, ruthenium oxide, cobalt silicide, nickel silicide), conductive carbon, graphene, or any suitable combination of these materials. The conductive gate material may also include dopants that are included during or after the deposition process.

[0074] Fig.9A and Fig. 9B 1 and 2 respectively depict cross-sectional views of a semiconductor wafer 100 across and along the gate after processing operations according to one or more embodiments. Fig.9A and Fig. 9B 1 and 2, using known FEOL and MOL manufacturing operations, the ILD 602 ​​is extended using the same or different dielectric materials and contacts are formed with various device substructures (e.g., contact 902 (sometimes referred to as top epitaxial contact or shallow contact), contact 904 (sometimes referred to as common epitaxial contact or deep contact), and gate contact 906). Fig.9A and Fig. 9B As further shown, known BEOL manufacturing operations are used to form BEOL interconnects 908 over the semiconductor wafer 100 , and a carrier wafer 910 is bonded to the semiconductor wafer 100 .

[0075] Fig. 10A and Fig. 10B 1 and 2 respectively depict cross-sectional views of a semiconductor wafer 100 across and along the gate after processing operations according to one or more embodiments. Fig. 10A and Fig. 10BAs shown, semiconductor wafer 100 can be flipped for backside processing. In some embodiments, a portion of substrate 106 is removed to expose buried oxide layer (BOX) 112. In some embodiments, substrate 106 is recessed using a selective process that stops on buried oxide layer 112.

[0076] Fig.11A and Fig. 11B 1 and 2 respectively depict cross-sectional views of a semiconductor wafer 100 across and along the gate after processing operations according to one or more embodiments. Fig.11A and Fig. 11B As shown, the remaining portion of the buried oxide layer 112 and the substrate 106 are removed to expose the underlying structures (e.g., the bottom source / drain region 506, the conductive gate 802, the STI region 122, etc.). The remaining portion of the buried oxide layer 112 and the substrate 106 can be removed using a wet etch, a dry etch, or a combination of a series of wet and / or dry etches.

[0077] Fig. 12A and Fig. 12B 1 and 2 respectively depict cross-sectional views of a semiconductor wafer 100 across and along the gate after processing operations according to one or more embodiments. Fig. 12A and Fig. 12B 5 , a backside interlayer dielectric (BILD) 1202 is shown formed on the semiconductor wafer 100. The BILD 1202 can be formed of a dielectric material similar to the middle ILD 508 discussed previously with respect to FIG. 5 and in a similar manner. In some embodiments, a backside contact 1204 (sometimes referred to as a bottom epitaxial contact) is formed or embedded within the BILD 1202 to land on or within the bottom source / drain region 506.

[0078] like Fig. 12A and Fig. 12B Further shown, backside interconnect 1206 is formed over BILD 1202 and backside contact 1204. Backside interconnect 1206 may be formed using various BEOL processes, using similar methods as interconnect 908 previously discussed in connection with FIG.

[0079] After backside processing is complete, additional BEOL processing may be performed using known processes (e.g., including incorporation of additional M x The semiconductor wafer 100 is finally processed by metallization layers, far back end of line (FBEOL) processing, packaging modules, etc. to define the final device.

[0080] Fig.13A flow chart illustrating a method 1300 for providing a monolithic SFET with dual MDI separation according to one or more embodiments of the present invention is depicted. As shown at block 1302, a first nanosheet is formed. At block 1304, a second nanosheet is vertically stacked above the first nanosheet. In some embodiments, the semiconductor device is a stacked field effect transistor.

[0081] In some embodiments, the method includes forming a first nanosheet stack including a first nanosheet and one or more additional nanosheets, and forming a second nanosheet stack including a second nanosheet and one or more additional nanosheets. In some embodiments, the stacked field effect transistor is a complementary stacked field effect transistor including an nFET and a pFET. In some embodiments, the first nanosheet stack defines a portion of one of the nFET and the pFET, and the second nanosheet stack defines a portion of the other of the nFET and the pFET.

[0082] At block 1306, a gate is formed around the channel region of the first nanosheet and the channel region of the second nanosheet. In some embodiments, the gate is a common gate of the stacked field effect transistor. In some embodiments, the gate includes a first portion (i.e., the first gate) and a second portion (i.e., the second gate) electrically isolated from the first portion. In some embodiments, the first portion serves as a gate for the first nanosheet and the second portion serves as a separate gate for the second nanosheet.

[0083] In block 1308, an intermediate dielectric isolation structure is formed between the first nanosheet and the second nanosheet. The intermediate dielectric isolation structure includes at least a first intermediate dielectric isolation layer and a second intermediate dielectric isolation layer vertically stacked above the first intermediate dielectric isolation layer. In some embodiments, a portion of the gate extends between the first intermediate dielectric isolation layer and the second intermediate dielectric isolation layer in the intermediate dielectric isolation structure. In some embodiments, a thickness of the first intermediate dielectric isolation layer and a thickness of the second intermediate dielectric isolation layer are less than or equal to 10 nanometers.

[0084] The method may also include forming a first source or drain region in direct contact with a sidewall of the first nanosheet, and forming a second source or drain region in direct contact with a sidewall of the second nanosheet. In some embodiments, an intermediate interlayer dielectric is formed between the first source or drain region and the second source or drain region. In some embodiments, the intermediate interlayer dielectric is in direct contact with a sidewall of the first intermediate dielectric isolation layer and a sidewall of the second intermediate dielectric isolation layer. In some embodiments, the first source or drain region includes a first doping type, and the second source or drain region includes a second doping type opposite to the first doping type.

[0085] The methods and structures described herein can be used in the manufacture of IC chips. The IC chips produced can be distributed by the manufacturer in raw wafer form (i.e., a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single-chip package (e.g., a plastic carrier with pins fixed to a motherboard or other higher-level carrier) or in a multi-chip package (e.g., a ceramic carrier with either surface interconnects, buried interconnects, or both). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product containing an IC chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0086] The various embodiments of the present invention are described herein with reference to the relevant drawings. Alternative embodiments may be designed without departing from the scope of the present invention. Although various connections and positional relationships (e.g., above, below, adjacent, etc.) between elements are specified in the following description and drawings, those skilled in the art will recognize that when the described functions remain unchanged, even if the direction changes, many positional relationships described herein remain independent in direction. These connections and / or positional relationships, unless otherwise specified, may be direct or indirect, and the present invention is not intended to be limited in this respect. Similarly, the term "coupling" and its variants describe that there is a communication path between two elements, and do not mean that there is no direct connection between the elements / connections in the middle. All of these variants are considered part of this specification. Accordingly, the coupling between entities may refer to direct coupling or indirect coupling, and the positional relationship between entities may be a direct or indirect positional relationship. As an example of an indirect positional relationship, in this description, as long as the intermediary layer does not substantially change the relevant characteristics and functions of layer "A" and layer "B", the reference to forming layer "A" on layer "B" includes the case where there are one or more intermediate layers (e.g., layer "C") between layer "A" and layer "B".

[0087] The following definitions and abbreviations are used to interpret the claims and specification. As used herein, the terms "comprises," "including," "having," or "containing," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that includes a set of elements is not necessarily limited to those elements but may also include other elements not expressly listed or inherent to the composition, mixture, process, method, article, or apparatus.

[0088] In addition, the term "exemplary" is used herein to mean "serving as an example, instance, or demonstration". Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" are understood to include any integer greater than or equal to one, i.e., one, two, three, four, etc. The term "plurality" is understood to include any integer greater than or equal to two, i.e., two, three, four, five, etc. The term "connected" may include indirect "connected" and direct "connected".

[0089] The phrases "one embodiment", "an embodiment", "an exemplary embodiment", etc. mentioned in the specification indicate that the described embodiment may include specific features, structures or characteristics, but each embodiment may or may not include the specific features, structures or characteristics. In addition, these phrases do not necessarily refer to the same embodiment. In addition, when a specific feature, structure or characteristic is described in association with an embodiment, it is deemed that it is within the knowledge of those skilled in the art to implement such feature, structure or characteristic in other embodiments, whether or not explicitly described.

[0090] For the purposes of description herein, the terms "upper", "lower", "right", "left", "vertical", "horizontal", "top", "bottom" and their derivatives are to be understood relative to the orientation of the structures and methods described in the accompanying drawings. The terms "overlying", "located above", "on top of", "placed on", or "placed on" indicate that a first element (e.g., a first structure) is located above a second element (e.g., a second structure), wherein there may be an intervening element such as an interface structure between the first and second elements. The term "direct contact" means that a first element (e.g., a first structure) is connected to a second element (e.g., a second structure) at the interface of the two elements without any intervening conductive, insulating, or semiconducting layers.

[0091] Spatially relative terms (e.g., "below," "lower," "above," "upper," etc.) are used herein to describe the relationship of one element or feature relative to another (or multiple) element or feature for ease of description. It will be understood that the spatially relative terms are intended to cover different orientations that the device may have during use or operation in addition to the orientation described in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, an element or feature described as "below" or "below" will become "above." Therefore, the term "below" can cover both the above and below directions. The device can be oriented in other orientations (e.g., rotated 90 degrees or other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0092] The terms "about," "substantially," "approximately," and variations thereof are intended to encompass the degree of error associated with measurement of a particular quantity based on equipment available at the time the application is filed. For example, "about" may include a range of ±8%, ±5%, or ±2% relative to a given value.

[0093] The phrase "selectively toward," for example, say, "a first element selectively toward a second element," means that the first element may be etched and the second element may act as an etch stop (ie, the second element remains).

[0094] The term "conformal" (eg, conformal layer or conformal deposition) means that the thickness of the layer is substantially the same on all surfaces, or that the thickness varies by less than 15% of the nominal thickness of the layer.

[0095] The terms "epitaxial growth and / or deposition" and "epitaxial formation and / or growth" refer to the growth of a semiconductor material (crystalline material) on a deposition surface of another semiconductor material (crystalline material), wherein the grown semiconductor material (crystalline cover) has substantially the same crystal properties as the semiconductor material (seed material) on the deposition surface. During epitaxial deposition, the chemical reactants provided by the source gases can be controlled, and the system parameters can be set, so that the deposited atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move on the surface, thereby adjusting the deposited atoms to the crystal arrangement of the atoms on the deposition surface. The epitaxially grown semiconductor material can have substantially the same crystal properties as the deposition surface on which the epitaxially grown material is formed. For example, a semiconductor material deposited on <100> Epitaxial growth of semiconductor materials onto a crystal surface can be achieved using <100> Orientation. In certain embodiments of the present invention, epitaxial growth and / or deposition processes may be selectively directed toward formation on semiconductor surfaces, and may or may not deposit material on other exposed surfaces such as, for example, silicon dioxide or silicon nitride surfaces.

[0096] As used herein, the term "p-type" refers to the addition of impurities to an intrinsic semiconductor, thereby creating a deficiency of valence electrons. In silicon-containing substrates, examples of p-type dopants (ie, impurities) include, but are not limited to, boron, aluminum, gallium, and indium.

[0097] As used herein, the term "n-type" refers to the addition of impurities to provide free electrons to an intrinsic semiconductor. In silicon-containing substrates, examples of n-type dopants (ie, impurities) include, but are not limited to, antimony, arsenic, and phosphorus.

[0098] As described earlier in this document, for the sake of brevity, conventional techniques related to the manufacture of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. However, as background, a more general description of a semiconductor device manufacturing process that may be employed to implement one or more embodiments of the present invention will now be provided. Although the specific manufacturing operations used in implementing one or more embodiments of the present invention may be individually known, the combination of operations described in the present invention and / or the resulting structure is unique. Therefore, the unique combination of operations described in connection with the manufacture of semiconductor devices according to the present invention employs a variety of known physical and chemical processes performed on semiconductor (e.g., silicon) substrates, some of which will be described in the following recent paragraphs.

[0099] In general, the various processes used to form the microchips that will be packaged into ICs are divided into four general categories, namely, thin film deposition, removal / etching, semiconductor doping and patterning / lithography. Deposition is any process that grows, coats or otherwise transfers a material to a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and atomic layer deposition (ALD) in recent years. Removal / etching is any process that removes material from a wafer. Examples include etching processes (wet or dry) and chemical mechanical planarization (CMP). For example, reactive ion etching (RIE) is a dry etching process that uses chemically reactive plasma to remove materials such as mask patterns of semiconductor materials by exposing the material to ion bombardment that dislocates part of the material from the exposed surface. Plasma is usually generated by electromagnetic fields at low pressure (vacuum). Semiconductor doping is a change in electrical properties by doping (usually by diffusion and / or ion implantation) such as the source and drain of a transistor. These doping processes are accompanied by furnace annealing or rapid thermal annealing (RTA). Annealing is used to activate the implanted dopants. Thin films of both conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. Selective doping of various areas of the semiconductor substrate allows the conductivity of the substrate to vary with the applied voltage. By creating structures of these different components, millions of transistors can be built and wired together to form the complex circuits of modern microelectronic devices. Semiconductor lithography is the formation of a three-dimensional relief image or pattern on a semiconductor substrate for subsequent transfer of the pattern to the substrate. In semiconductor lithography, the pattern is formed by a photosensitive polymer called a photoresist. In order to build the complex structure that makes up the transistors and the many wires that connect the millions of transistors of the circuit, the lithography and etching pattern transfer steps are repeated many times. Each pattern printed on the wafer is aligned with the previously formed pattern, and the conductors, insulators, and selectively doped areas are slowly built to form the final device.

[0100] The flowcharts and block diagrams in the accompanying drawings illustrate possible implementations of manufacturing and / or operating methods according to various embodiments of the present invention. The various functions / operations of the method are represented by the blocks in the block diagram. In some alternative embodiments, the functions indicated in the blocks may occur outside the order indicated in the figure. For example, in practice, two consecutively displayed blocks may be executed substantially simultaneously, or the blocks may sometimes be executed in reverse order, depending on the functions involved.

[0101] The description of the various embodiments of the present invention is presented for illustrative purposes only, but is not intended to be exhaustive or limited to the described embodiments. Many modifications and variations are apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications or technical improvements in the technology on the market, or to enable other persons of ordinary skill in the art to understand the embodiments described herein.

Claims

1. A method for forming a semiconductor device, the method comprising: forming a first nanosheet; forming a second nanosheet vertically stacked above the first nanosheet; forming a gate around the channel region of the first nanosheet and the channel region of the second nanosheet; as well as An intermediate dielectric isolation structure is formed between the first nanosheet and the second nanosheet, wherein the intermediate dielectric isolation structure comprises: a first interlayer dielectric isolation layer; and a second intermediate dielectric isolation layer vertically stacked above the first intermediate dielectric isolation layer; Part of the gate extends between the first intermediate dielectric isolation layer and the second intermediate dielectric isolation layer in the intermediate dielectric isolation structure.

2. The method according to claim 1, further comprising: forming a first nanosheet stack, the first nanosheet stack comprising the first nanosheet and one or more additional nanosheets; as well as A second nanosheet stack is formed, the second nanosheet stack comprising the second nanosheet and one or more additional nanosheets. The method of claim 2 , wherein the semiconductor device comprises a stacked field effect transistor. The method of claim 3 , wherein the gate comprises a common gate of the stacked field effect transistors. 5 . The method of claim 4 , wherein the stacked field effect transistor comprises a complementary stacked field effect transistor comprising an nFET and a pFET. 6 . The method of claim 5 , wherein the first nanosheet stack defines a portion of one of the nFET and the pFET, and the second nanosheet stack defines a portion of the other of the nFET and the pFET.

7. The method according to claim 1, further comprising: forming a first source or drain region in direct contact with a sidewall of the first nanosheet; as well as A second source or drain region is formed in direct contact with the sidewall of the second nanosheet.

8. The method according to claim 7 further includes forming an intermediate interlayer dielectric between the first source or drain region and the second source or drain region, wherein the intermediate interlayer dielectric is in direct contact with the sidewalls of the first intermediate dielectric isolation layer and the sidewalls of the second intermediate dielectric isolation layer. 9 . The method of claim 7 , wherein the first source or drain region comprises a first doping type and the second source or drain region comprises a second doping type opposite to the first doping type.

10. The method according to claim 1, wherein a thickness of the first intermediate dielectric isolation layer and a thickness of the second intermediate dielectric isolation layer are less than or equal to 10 nanometers.

11. A semiconductor device comprising: The first nanosheet; a second nanosheet stacked vertically above the first nanosheet; forming a gate around the channel region of the first nanosheet and the channel region of the second nanosheet; as well as An intermediate dielectric isolation structure between the first nanosheet and the second nanosheet, the intermediate dielectric isolation structure comprising: a first interlayer dielectric isolation layer; and a second intermediate dielectric isolation layer vertically stacked above the first intermediate dielectric isolation layer; Wherein, a portion of the gate extends between the first intermediate dielectric isolation layer and the second intermediate dielectric isolation layer in the intermediate dielectric isolation structure.

12. The semiconductor device according to claim 11, further comprising: a first nanosheet stack, the first nanosheet stack comprising the first nanosheet and one or more additional nanosheets; as well as A second nanosheet stack includes the second nanosheet and one or more additional nanosheets. 13 . The semiconductor device of claim 12 , wherein the semiconductor device comprises stacked field effect transistors. The semiconductor device according to claim 13 , wherein the gate comprises a common gate of stacked field effect transistors. 15 . The semiconductor device of claim 14 , wherein the stacked field effect transistor comprises a complementary stacked field effect transistor comprising an nFET and a pFET. 16 . The semiconductor device of claim 15 , wherein the first nanosheet stack defines a portion of one of the nFET and the pFET, and the second nanosheet stack defines a portion of the other of the nFET and the pFET.

17. The semiconductor device according to claim 11, further comprising: a first source or drain region directly contacting a sidewall of the first nanosheet; as well as A second source or drain region is in direct contact with a sidewall of the second nanosheet.

18. The semiconductor device according to claim 17, further comprising an intermediate interlayer dielectric between the first source or drain region and the second source or drain region, the intermediate interlayer dielectric directly contacting the sidewalls of the first intermediate dielectric isolation layer and the sidewalls of the second intermediate dielectric isolation layer. 19 . The semiconductor device of claim 17 , wherein the first source or drain region comprises a first doping type, and the second source or drain region comprises a second doping type opposite to the first doping type. 20 . The semiconductor device according to claim 11 , wherein a thickness of the first intermediate dielectric isolation layer and a thickness of the second intermediate dielectric isolation layer are less than or equal to 10 nanometers.

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