Method and device for managing and controlling CPU (Central Processing Unit) power consumption

Abstract

The invention discloses a CPU power consumption management and control method and device, the method is applied to a management and control device, the management and control device comprises a decision unit, and the method comprises the steps that the decision unit judges whether a target period meets a preset enabling low-power-consumption execution condition or not; if the enabling low-power-consumption execution condition is met, the decision-making unit generates a first enabling instruction, and the first enabling instruction is used for controlling the CPU module to start the WFI to automatically enter a low-power-consumption mode in a target period; if the enabling low-power-consumption execution condition is not met, the decision-making unit generates a second enabling instruction, and the second enabling instruction is used for controlling the CPU module to close the WFI in the target period to automatically enter the low-power-consumption mode. Therefore, the comprehensiveness and rationality of the CPU power consumption mode management and control mode can be improved, the management and control accuracy and reliability of the CPU power consumption mode are improved, the management and control efficiency, convenience and timeliness of the CPU power consumption mode are improved, and the CPU power consumption is reduced on the premise that the performance is not affected.

Description

Technical Field

[0001] The present invention relates to the technical field of CPU power consumption control, and in particular to a method and device for controlling CPU power consumption. Background Art

[0002] With the rapid development of information technology, CPU, as the core component of computers and smart devices, its performance and power consumption management have become key areas of research and development. The power consumption of CPU is not only directly related to the device's battery life, heat dissipation requirements and overall energy efficiency, but also significantly affects the stability and service life of the device.

[0003] However, in actual applications, the existing CPU power consumption control methods are mostly implemented through cpufreq technology or cpuidle technology. Among them, cpufreq technology cannot reduce the CPU to an extremely low frequency for system performance and response speed. Because cpuidle technology involves the power switch, its wake-up delay is usually large and the usage scenarios are limited, and the control accuracy and efficiency of CPU power consumption are low. It can be seen that it is particularly important to provide a CPU power consumption control method that can improve the control accuracy and efficiency of CPU power consumption. Summary of the invention

[0004] The present invention provides a method and device for controlling CPU power consumption, which can improve the control accuracy and control efficiency of CPU power consumption and reduce CPU power consumption without affecting performance.

[0005] In order to solve the above technical problems, the first aspect of the present invention discloses a method for controlling CPU power consumption, which is applied to a control device, wherein the control device includes a decision unit, and the method includes:

[0006] The decision unit determines whether the target cycle meets a preset low power consumption execution enabling condition;

[0007] When it is determined that the target cycle satisfies the low power consumption execution enabling condition, the decision unit generates a first enabling instruction, wherein the first enabling instruction is used to control the CPU module to turn on WFI in the target cycle and automatically enter the low power consumption mode;

[0008] When it is determined that the target cycle does not meet the low power execution enabling condition, the decision unit generates a second enabling instruction, where the second enabling instruction is used to control the CPU module to turn off WFI in the target cycle and automatically enter the low power mode.

[0009] As an optional implementation manner, in a first aspect of the present invention, a method for controlling CPU power consumption is provided, characterized in that the method is applied to a control device, wherein the control device includes a decision unit, and the method includes:

[0010] The decision unit determines whether the target cycle meets a preset low power consumption execution enabling condition;

[0011] When it is determined that the target cycle satisfies the low power consumption execution enabling condition, the decision unit generates a first enabling instruction, wherein the first enabling instruction is used to control the CPU module to turn on WFI in the target cycle and automatically enter the low power consumption mode;

[0012] When it is determined that the target cycle does not meet the low power execution enabling condition, the decision unit generates a second enabling instruction, where the second enabling instruction is used to control the CPU module to turn off WFI in the target cycle and automatically enter the low power mode.

[0013] As an optional embodiment, in the first aspect of the present invention, the method further comprises:

[0014] When there is an interrupt request signal input through the second external device, the wake-up logic module performs a latch operation on the interrupt request signal and reflects its current state through a low-level wake-up signal;

[0015] The signal phase AND module performs corresponding signal phase AND analysis operations on the high-level waiting interrupt signal and the low-level wake-up signal to obtain a second enable signal;

[0016] The gating enable module performs a corresponding failure operation according to the second enable signal, so that the CPU clock signal input by the first external device can be transmitted to the CPU module;

[0017] The CPU module executes the corresponding WFI low power state mode exit operation according to the CPU clock signal and the low level wake-up signal, and reflects its current state through a low level wait interrupt signal.

[0018] As an optional embodiment, in the first aspect of the present invention, the method further comprises:

[0019] The gating enabling module performs a corresponding continuous failure operation according to the low-level waiting interrupt signal, so that the CPU clock signal input by the first external device can be continuously transmitted to the CPU module;

[0020] The CPU module performs a corresponding normal operating mode switching operation according to the CPU clock signal, so that the CPU module is in a normal operating state;

[0021] And, the method further comprises:

[0022] When the CPU module is in the normal operating state, the CPU module performs a corresponding signal response operation on an interrupt request signal received and inputted through the second external device;

[0023] The wake-up logic module performs a corresponding signal clearing operation and reflects its current state through a high-level wake-up signal.

[0024] As an optional implementation, in the first aspect of the present invention, the execution unit further includes an enabling switch control module, and the method further includes:

[0025] The enabling switch control module determines whether the enabling control mode of the target cycle meets the preset enabling control matching condition according to the WFI automatic entry and exit low power consumption state control requirement for the CPU module;

[0026] When it is determined that the enabling control mode does not satisfy the enabling control matching condition, a corresponding enabling control mode switching operation is performed.

[0027] As an optional implementation manner, in the first aspect of the present invention, the decision unit determines whether the target cycle meets the preset low power execution enabling condition, including:

[0028] The decision unit determines the number of historical interruptions in each past window according to the determined CPU historical interruption frequency information, and determines the expected number of interruptions in the target cycle according to all the historical interruption numbers and the determined interruption statistics window information;

[0029] Determine, based on the determined CPU expected frequency information, acceptable extension information corresponding to the target cycle and the CPU entering and exiting the low power consumption state operation;

[0030] Determining an expected performance impact threshold of the target period according to the determined expected performance impact information;

[0031] Determining whether the target period meets preset function and performance impact conditions according to the interruption statistics window information, the expected number of interruptions, the acceptable extension information and the expected performance impact threshold;

[0032] When it is determined that the target cycle satisfies the function and performance impact condition, determining that the target cycle satisfies a preset low power consumption enabling execution condition;

[0033] When it is determined that the target cycle does not satisfy the function and performance impact condition, it is determined that the target cycle does not satisfy a preset low power execution enabling condition.

[0034] As an optional implementation, in the first aspect of the present invention, the decision unit determines whether the target period meets the preset function and performance impact conditions according to the interruption statistical window information, the expected number of interruptions, the acceptable extension information and the expected performance impact threshold, including:

[0035] Determine a first calculation result according to the expected performance impact threshold, the interruption statistical window information and the acceptable extension information;

[0036] Determining whether the first calculation result is greater than or equal to the expected number of interruptions;

[0037] When it is determined that the first calculation result is greater than or equal to the expected number of interruptions, determining that the target period meets a preset function and performance impact condition;

[0038] When it is determined that the first calculation result is less than the expected number of interruptions, determining that the target period does not meet the preset function and performance impact condition;

[0039] And, the first calculation result is greater than or equal to the expected number of interruptions, which is reflected by the following formula:

[0040]

[0041] Among them, N corresponds to the expected number of interruptions, H corresponds to the expected performance impact threshold, T corresponds to the interruption statistical window information, and D corresponds to the acceptable delay information.

[0042] A second aspect of the present invention discloses a control device for CPU power consumption, the control device comprising a decision unit, wherein the decision unit comprises a judgment module and an instruction generation module, wherein:

[0043] The judging module is used to judge whether the target cycle satisfies the preset low power consumption execution enabling condition;

[0044] The instruction generation module is used for the decision unit to generate a first enabling instruction when the judgment module judges that the target cycle meets the low power execution enabling condition, and the first enabling instruction is used to control the CPU module to turn on WFI in the target cycle to automatically enter the low power mode;

[0045] The instruction generation module is also used for the decision unit to generate a second enabling instruction when the judgment module determines that the target cycle does not meet the enabling low power execution condition, and the second enabling instruction is used to control the CPU module to turn off WFI in the target cycle and automatically enter the low power mode.

[0046] As an optional implementation, in the second aspect of the present invention, the control device further includes an execution unit, wherein the execution unit includes the CPU module, the gating enable module, the wake-up logic module, and the signal phase and module, wherein:

[0047] The CPU module is used to reflect its current state through a high-level waiting interrupt signal when the CPU module turns on the WFI to automatically enter the low power consumption mode and the CPU module is in the WFI state;

[0048] The wake-up logic module is used to reflect its current state through a high-level wake-up signal;

[0049] The signal phase AND module is used to perform corresponding signal phase AND analysis operations on the high-level waiting interrupt signal and the high-level wake-up signal to obtain a first enable signal;

[0050] The gating enable module is used to perform a corresponding signal blocking operation on the CPU clock signal input by the first external device according to the first enable signal;

[0051] The CPU module is further used to execute a corresponding clockless WFI low power consumption state mode switching operation to put the CPU module in a clockless WFI low power consumption state.

[0052] As an optional implementation, in the second aspect of the present invention, the wake-up logic module is further used to perform a latch operation on the interrupt request signal when there is an interrupt request signal input through the second external device, and reflect its current state through a low-level wake-up signal;

[0053] The signal phase AND module is further used to perform a corresponding signal phase AND analysis operation on the high-level waiting interrupt signal and the low-level wake-up signal to obtain a second enable signal;

[0054] The gating enable module is further used to perform a corresponding failure operation according to the second enable signal, so that the CPU clock signal input by the first external device can be transmitted to the CPU module;

[0055] The CPU module is also used to execute the corresponding WFI low power state mode exit operation according to the CPU clock signal and the low level wake-up signal, and reflect its current state through a low level wait interrupt signal.

[0056] As an optional implementation, in the second aspect of the present invention, the gating enabling module is further used to perform a corresponding continuous failure operation according to the low-level waiting interrupt signal, so that the CPU clock signal input by the first external device can be continuously transmitted to the CPU module;

[0057] The CPU module is further used to perform a corresponding normal operating mode switching operation according to the CPU clock signal, so that the CPU module is in a normal operating state;

[0058] And, the CPU module is further used to perform a corresponding signal response operation on an interrupt request signal received and inputted through the second external device when in the normal operation state;

[0059] The wake-up logic module is also used to perform corresponding signal clearing operations and reflect its current state through a high-level wake-up signal.

[0060] As an optional implementation, in the second aspect of the present invention, the execution unit further includes an enabling switch control module, wherein:

[0061] The enable switch control module is used to determine whether the enable control mode of the target cycle meets the preset enable control matching condition according to the WFI automatic entry and exit low power consumption state control requirement of the CPU module; when it is determined that the enable control mode does not meet the enable control matching condition, perform the corresponding enable control mode switching operation.

[0062] As an optional implementation, in the second aspect of the present invention, the manner in which the judgment module judges whether the target cycle satisfies the preset low power consumption execution enabling condition specifically includes:

[0063] Determine the number of historical interruptions in each past window according to the determined CPU historical interruption frequency information, and determine the expected number of interruptions in the target cycle according to all the historical interruption numbers and the determined interruption statistics window information;

[0064] Determine, based on the determined CPU expected frequency information, acceptable extension information corresponding to the target cycle and the CPU entering and exiting the low power consumption state operation;

[0065] Determining an expected performance impact threshold of the target period according to the determined expected performance impact information;

[0066] Determining whether the target period meets preset function and performance impact conditions according to the interruption statistics window information, the expected number of interruptions, the acceptable extension information and the expected performance impact threshold;

[0067] When it is determined that the target cycle satisfies the function and performance impact condition, determining that the target cycle satisfies a preset low power consumption enabling execution condition;

[0068] When it is determined that the target cycle does not satisfy the function and performance impact condition, it is determined that the target cycle does not satisfy a preset low power execution enabling condition.

[0069] As an optional implementation, in the second aspect of the present invention, the judgment module judges whether the target period meets the preset function and performance impact conditions according to the interruption statistical window information, the expected number of interruptions, the acceptable extension information and the expected performance impact threshold, specifically including:

[0070] Determine a first calculation result according to the expected performance impact threshold, the interruption statistical window information and the acceptable extension information;

[0071] Determining whether the first calculation result is greater than or equal to the expected number of interruptions;

[0072] When it is determined that the first calculation result is greater than or equal to the expected number of interruptions, determining that the target period meets a preset function and performance impact condition;

[0073] When it is determined that the first calculation result is less than the expected number of interruptions, determining that the target period does not meet the preset function and performance impact condition;

[0074] And, the first calculation result is greater than or equal to the expected number of interruptions, which is reflected by the following formula:

[0075]

[0076] Among them, N corresponds to the expected number of interruptions, H corresponds to the expected performance impact threshold, T corresponds to the interruption statistical window information, and D corresponds to the acceptable delay information.

[0077] A third aspect of the present invention discloses another CPU power consumption control device, the control device comprising:

[0078] A memory storing executable program code;

[0079] a processor coupled to the memory;

[0080] The processor calls the executable program code stored in the memory to execute a method for controlling CPU power consumption disclosed in the first aspect of the present invention.

[0081] A fourth aspect of the present invention discloses a computer storage medium, wherein the computer storage medium stores computer instructions, and when the computer instructions are called, they are used to execute a CPU power consumption control method disclosed in the first aspect of the present invention.

[0082] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0083] In an embodiment of the present invention, it is applied to a control device, and the control device includes a decision unit; in addition, the decision unit determines whether the target cycle meets the preset low-power execution condition; when it is determined that the target cycle meets the low-power execution condition, the decision unit generates a first enabling instruction, and the first enabling instruction is used to control the CPU module to turn on WFI and automatically enter the low-power mode in the target cycle; when it is determined that the target cycle does not meet the low-power execution condition, the decision unit generates a second enabling instruction, and the second enabling instruction is used to control the CPU module to turn off WFI and automatically enter the low-power mode in the target cycle. It can be seen that the present invention can determine whether the target cycle meets the low-power execution condition through the decision unit, and generate matching enabling instructions according to the result of meeting the low-power execution condition, so as to control the CPU module to turn on / off WFI and automatically enter the low-power mode in the target cycle, which is conducive to improving the comprehensiveness and rationality of the CPU power mode control method, and then it is conducive to improving the accuracy and reliability of the control of the CPU power mode, and it is conducive to improving the efficiency, convenience and timeliness of the control of the CPU power mode, so as to reduce the CPU power consumption without affecting the performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0084] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0085] Figure 1 It is a flowchart of a method for controlling CPU power consumption disclosed in an embodiment of the present invention;

[0086] Figure 2 It is a flowchart of another method for controlling CPU power consumption disclosed in an embodiment of the present invention;

[0087] Figure 3 It is a structural schematic diagram of a CPU power consumption control device disclosed in an embodiment of the present invention;

[0088] Figure 4 It is a structural schematic diagram of another CPU power consumption control device disclosed in an embodiment of the present invention;

[0089] Figure 5 It is a structural schematic diagram of another CPU power consumption control device disclosed in an embodiment of the present invention;

[0090] Figure 6 It is a structural schematic diagram of another CPU power consumption control device disclosed in an embodiment of the present invention;

[0091] Figure 7 It is a logical schematic diagram of an execution unit disclosed in an embodiment of the present invention. DETAILED DESCRIPTION

[0092] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0093] The terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish different objects rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, device, product or end including a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units inherent to these processes, methods, products or ends.

[0094] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0095] The present invention discloses a method and device for controlling CPU power consumption, which can judge whether a target cycle satisfies a condition for enabling low power consumption execution through a decision unit, and respectively generate matching enabling instructions according to the result of enabling low power consumption execution condition satisfaction, so as to control the CPU module to turn on / off WFI in the target cycle to automatically enter a low power consumption mode, which is conducive to improving the comprehensiveness and rationality of the CPU power consumption mode control method, and thus is conducive to improving the control accuracy and reliability of the CPU power consumption mode, and is conducive to improving the control efficiency, convenience, and timeliness of the CPU power consumption mode, so as to achieve the reduction of CPU power consumption without affecting performance. The following are detailed descriptions.

[0096] Embodiment 1

[0097] See also Figure 1 , Figure 11 is a flow chart of a method for controlling CPU power consumption disclosed in an embodiment of the present invention. Figure 1 The described method may be applied to a control device, wherein the control device includes a decision-making unit, which is not limited in the embodiment of the present invention. Figure 1 As shown, the CPU power consumption control method includes the following operations:

[0098] 101. A decision unit determines whether a target cycle satisfies a preset low power consumption enabling execution condition. When the determination result is yes, step 102 is executed; when the determination result is no, step 103 is executed.

[0099] Optionally, the target period may be the current period, the next period, or other periods determined according to actual needs, which is not limited in the embodiment of the present invention.

[0100] Optionally, whether the above-mentioned conditions for enabling low-power execution are met can be understood as a decision on whether to enable the CPU low-power standby function; further, a decision on whether to enable the CPU low-power standby function is made based on the CPU's past interrupt frequency, the CPU's delay in entering and exiting the low-power state, and the target system's acceptance threshold of the impact on performance, which is not limited in the embodiments of the present invention.

[0101] 102. The decision unit generates a first enabling instruction, where the first enabling instruction is used to control the CPU module to turn on WFI in a target cycle to automatically enter a low power consumption mode.

[0102] 103. The decision unit generates a second enabling instruction, where the second enabling instruction is used to control the CPU module to turn off WFI in a target cycle and automatically enter a low power consumption mode.

[0103] Optionally, this solution provides a method for implementing low-power consumption in CPU idle state with low latency and wide coverage of scenarios, which makes up for the shortcomings of cpuidle technology in application scenarios (such as high-frequency wake-up related scenarios caused by high-frequency interruptions, where the use of cpuidle technology may result in a loss in power consumption), further reduces CPU idle state power consumption, and reduces CPU power consumption without affecting performance, which is not limited to the embodiments of the present invention.

[0104] It can be seen that the implementation of a CPU power consumption control method described in an embodiment of the present invention can determine whether the target cycle meets the low power consumption execution enabling conditions through a decision unit, and generate matching enabling instructions according to the results of meeting the low power consumption execution enabling conditions, so as to control the CPU module to turn on / off WFI to automatically enter the low power consumption mode during the target cycle, which is beneficial to improving the comprehensiveness and rationality of the CPU power consumption mode control method, and further beneficial to improving the accuracy and reliability of the CPU power consumption mode control, as well as the efficiency, convenience and timeliness of the CPU power consumption mode control, thereby facilitating reducing the CPU power consumption without affecting performance.

[0105] In an optional embodiment, the control device further includes an execution unit, and further, the execution unit includes a CPU module, a gating enable module, a wake-up logic module, and a signal phase and module;

[0106] And, the method may also include the following operations:

[0107] When the CPU module turns on WFI to automatically enter low power consumption mode and the CPU module is in WFI state, the CPU module reflects its current state through a high-level waiting interrupt signal, and the wake-up logic module reflects its current state through a high-level wake-up signal;

[0108] The signal phase AND module performs corresponding signal phase AND analysis operations on the high-level waiting interrupt signal and the high-level wake-up signal to obtain a first enable signal;

[0109] The gating enabling module performs a corresponding signal blocking operation on the CPU clock signal input from the first external device according to the first enabling signal;

[0110] The CPU module executes the corresponding clockless WFI low power state mode switching operation to put the CPU module in the clockless WFI low power state.

[0111] Optionally, the decision unit is responsible for deciding when to enable the low-power standby function, and the execution unit is used to implement the low-power standby function of the CPU; further, the interaction relationship between the decision unit and the execution unit can refer to but is not limited to the attached specification. Figure 6 The embodiments of the present invention are not limited thereto.

[0112] Optional, such as Figure 7 As shown, the gate enable module may correspond to gate, the wake-up logic module may correspond to wake uplogic, the CPU clock signal may correspond to cpu_clk, and the interrupt request signal may correspond to irq, which is not limited in the embodiment of the present invention.

[0113] Optionally, the CPU module reflects its current state through a high-level waiting interrupt signal, which can be understood as the WFI signal corresponding to the CPU module outputting a high level (see Figure 7 The signal ①) in the embodiment of the present invention is not limited.

[0114] Optionally, the above wake-up logic module reflects its current state through a high-level wake-up signal, which can be understood as the wakeup signal corresponding to the wake-up logic module outputs a high level by default (see Figure 7 The signal ②) in the embodiment of the present invention is not limited.

[0115] Optionally, the signal phase and analysis module performs a corresponding signal phase and analysis operation on the high-level waiting interrupt signal and the high-level wake-up signal to obtain a first enable signal; the gated enable module performs a corresponding signal blocking operation on the CPU clock signal input by the first external device according to the first enable signal. For example: the high-level waiting interrupt signal and the high-level wake-up signal are phased and the first enable signal is generated (see Figure 7 The gated enable module gates off the CPU clock signal based on the first enable signal (see Figure 7 Signal ④) in the CPU enters a clock-free WFI low power consumption state, which is not limited in the embodiment of the present invention.

[0116] Optionally, after the CPU enters the WFI state, its clock input is automatically gated, thereby reducing the CPU dynamic power consumption to zero, which is not limited in the embodiment of the present invention.

[0117] It can be seen that this optional embodiment can control the CPU module to be in a clock-free WFI low-power state through a series of operations among the CPU module, the gating enable module, the wake-up logic module, and the signal phase and module in the execution unit, which is beneficial to improving the comprehensiveness and rationality of the control method of the clock-free WFI low-power state of the CPU module, and further beneficial to improving the execution accuracy and reliability of the CPU module entering the clock-free WFI low-power state, thereby helping to reduce the CPU idle power consumption.

[0118] In another optional embodiment, the method may further include the following operations:

[0119] When there is an interrupt request signal input through the second external device, the wake-up logic module performs a latch operation on the interrupt request signal and reflects its current state through a low-level wake-up signal;

[0120] The signal phase AND module performs corresponding signal phase AND analysis operations on the high-level waiting interrupt signal and the low-level wake-up signal to obtain a second enable signal;

[0121] The gating enable module performs a corresponding failure operation according to the second enable signal, so that the CPU clock signal input by the first external device can be transmitted to the CPU module;

[0122] The CPU module executes the corresponding WFI low-power state mode exit operation according to the CPU clock signal and the low-level wake-up signal, and reflects its current state through the low-level wait interrupt signal.

[0123] Optionally, when there is an interrupt request signal input through the second external device, the wake-up logic module performs a latch operation on the interrupt request signal and reflects its current state through a low-level wake-up signal. For example: Figure 7 As shown, after the interrupt request signal irq signal (see signal ⑥ in the figure) arrives, the wake-up signal (see signal ② in the figure) is latched by the wake-up logic module and outputs a low level signal (i.e. corresponding to the low level wake-up signal), which is not limited in the embodiment of the present invention.

[0124] Optionally, the signal phase and module performs corresponding signal phase and analysis operations on the high-level waiting interrupt signal and the low-level wake-up signal to obtain the second enable signal. For example: Figure 7 As shown, the signal AND module generates a second enable signal (see signal ③ in the figure) according to a high-level wait interrupt signal (see signal ① in the figure) and a low-level wake-up signal (see signal ② in the figure), which is not limited in the embodiment of the present invention.

[0125] Optionally, the gating enable module performs a corresponding failure operation according to the second enable signal, so that the CPU clock signal input by the first external device can be transmitted to the CPU module. For example: Figure 7 As shown, the gate enabling module fails the gate circuit according to the second enabling signal (see signal ③ in the figure), and the CPU clock signal (see signal ④ in the figure) is output to the CPU module, which is not limited in the embodiment of the present invention.

[0126] Optionally, the CPU module executes the corresponding WFI low power state mode exit operation according to the CPU clock signal and the low level wake-up signal, and reflects its current state through the low level wait interrupt signal. For example: Figure 7 As shown, the CPU module exits the WFI low power state after receiving a low-level wake-up signal (see signal ② in the figure), and the WFI signal outputs a low level (see signal ① in the figure, that is, a low-level wait interrupt signal), which is not limited in the embodiment of the present invention.

[0127] Optionally, after the wake-up signal arrives, the gating enable module for CPU clock gating is automatically turned off, and the CPU exits the WFI state and restarts, which is not limited in the embodiment of the present invention.

[0128] It can be seen that this optional embodiment can control the CPU module to exit the WFI low power state through a series of operations between the wake-up logic module, the signal AND module, the gating enable module and the CPU module, which is beneficial to improving the comprehensiveness and integrity of the CPU power consumption control method, and is beneficial to improving the comprehensiveness and rationality of the CPU's WFI low power state exit method, and further helps to improve the switching accuracy and reliability of the CPU's WFI low power state.

[0129] In yet another optional embodiment, the method may further include the following operations:

[0130] The gated enabling module performs a corresponding continuous failure operation according to the low-level waiting interrupt signal, so that the CPU clock signal input by the first external device can be continuously transmitted to the CPU module;

[0131] The CPU module executes the corresponding normal operating mode switching operation according to the CPU clock signal to put the CPU module in a normal operating state.

[0132] Optionally, the gated enable module executes a corresponding continuous failure operation according to the low-level waiting interrupt signal. For example: Figure 7 As shown, the WFI signal outputs a low level (see signal ① in the figure, that is, a low-level waiting interrupt signal) to ensure that the gate logic of the gating enable module fails, that is, the WFI signal outputs a low level so that the signal phase module continues to output the second enable signal to ensure that the gating enable module continues to fail, and the CPU clock signal (see signal ④ in the figure) is normally input into the CPU module, which is not limited in the embodiment of the present invention.

[0133] Optionally, the CPU module performs a corresponding normal operating mode switching operation according to the CPU clock signal, which can be understood as: the CPU clock signal is normally input into the CPU, and the CPU returns to a normal operating state, which is not limited in the embodiment of the present invention.

[0134] It can be seen that this optional embodiment can control the CPU to switch to the normal operating mode through a series of operations between the gating enable module and the CPU module, which is beneficial to improving the comprehensiveness and integrity of the CPU power consumption control method, and is beneficial to improving the comprehensiveness and rationality of the CPU's normal operating mode switching method, and thus is beneficial to improving the accuracy and reliability of the CPU's normal operating state switching.

[0135] In yet another optional embodiment, the method may further include the following operations:

[0136] When the CPU module is in a normal operating state, the CPU module performs a corresponding signal response operation on an interrupt request signal received through the second external device;

[0137] The wake-up logic module performs the corresponding signal clearing operation and reflects its current state through a high-level wake-up signal.

[0138] Optionally, for example: after the CPU module returns to normal operating state, it responds to the irq interrupt (i.e., interrupt request signal), clears the wake-up logic interrupt pending signal, and the wake up signal is restored to the high-level default state (i.e., high-level wake-up signal), which is not limited in the embodiment of the present invention.

[0139] It can be seen that this optional embodiment can trigger and execute the signal clearing operation through a series of operations between the CPU module and the wake-up logic module, which is beneficial to improving the comprehensiveness and integrity of the CPU power consumption control method, and is beneficial to improving the accuracy, efficiency and timeliness of signal data clearing, and thus is beneficial to optimizing memory consumption.

[0140] In yet another optional embodiment, the execution unit further includes an enabling switch control module, and the method may further include the following operations:

[0141] The enabling switch control module automatically enters and exits the low power consumption state control requirement according to the WFI of the CPU module, and determines whether the enabling control mode of the target cycle meets the preset enabling control matching condition;

[0142] When it is determined that the enabling control mode does not satisfy the enabling control matching condition, a corresponding enabling control mode switching operation is performed.

[0143] Further optionally, the enabling switch control module determines whether the enabling control mode of the target period meets the preset enabling control matching condition according to the WFI automatic entry and exit low power consumption state control requirement for the CPU module, which may include:

[0144] The switch control module is enabled to automatically enter and exit the low power consumption state control demand according to the WFI for the CPU module, determine the current demand switch mode, and determine the current actual switch module;

[0145] Determine whether the current required switching mode matches the current actual switching mode;

[0146] When it is determined that the current demand switching mode matches the current actual switching mode, determining that the enabling control mode of the target cycle satisfies a preset enabling control matching condition;

[0147] When it is determined that the current required switching mode does not match the current actual switching mode, it is determined that the enabling control mode of the target period does not satisfy a preset enabling control matching condition.

[0148] Optional, such as Figure 7As shown, the enable switch control module can refer to signal ⑤ in the figure, that is, the enable switch control module is used to control whether the CPU clock signal passes through the gating enable module to enter the CPU module, that is, to control whether the entire set of CPU automatic entry and exit low power state logic of this solution is effective, which is not limited in the embodiment of the present invention.

[0149] It can be seen that this optional embodiment can realize the enabling control mode switching function by enabling the switch control module, which is beneficial to improving the comprehensiveness and rationality of the enabling control mode switching method, and then beneficial to improving the switching accuracy and reliability of the enabling control mode, as well as beneficial to improving the switching efficiency, convenience and timeliness of the enabling control mode, thereby facilitating improving the regulation accuracy and effectiveness of the CPU power consumption switching scheme.

[0150] Embodiment 2

[0151] See also Figure 2 , Figure 2 1 is a flow chart of another method for controlling CPU power consumption disclosed in an embodiment of the present invention. Figure 2 The described method may be applied to a control device, wherein the control device includes a decision-making unit, which is not limited in the embodiment of the present invention. Figure 2 As shown, the CPU power consumption control method includes the following operations:

[0152] 201. The decision unit determines the number of historical interruptions in each past window according to the determined CPU historical interruption frequency information, and determines the expected number of interruptions in the target cycle according to all historical interruption numbers and the determined interruption statistics window information.

[0153] Optionally, the above method determines the expected number of interruptions in the target cycle based on all historical interruption times and the determined interruption statistics window information. For example, the historical interruption frequency of the CPU is counted to predict the interruption frequency of the CPU in the target cycle (such as the next cycle), and then the expected number of interruptions is obtained; further, assuming that the interruption statistics window is T, the interruption times of the past M windows are N0, N1, ...N respectively. M-1 , a variety of algorithms can be used to predict the number of interruptions N in the next window, as follows:

[0154] (1) Mean method: average the number of historical interruptions and use the mean as the number of interruptions in the next window:

[0155]

[0156] (2) Weight decay method: the closest data (such as N0) has the largest weight, and the value N after weight decay is used as the number of interruptions in the next window:

[0157]

[0158] (3) Other algorithms, such as AI intelligent prediction, are not limited in the embodiments of the present invention.

[0159] 202. The decision unit determines, based on the determined CPU expected frequency information, acceptable extension information corresponding to the target cycle and the CPU entering and exiting the low power consumption state operation.

[0160] Optionally, the delay for entering and exiting the low power state is different at different CPU clock frequencies, and the acceptable extension information is determined based on actual needs; further, this scheme can take the longest delay for the CPU to enter and exit the low power state at the lowest frequency as the acceptable extension information, which is not limited in the embodiments of the present invention.

[0161] 203. The decision unit determines an expected performance impact threshold of the target period according to the determined expected performance impact information.

[0162] Optionally, the expected performance impact threshold of the target period can be set to different values ​​according to actual needs, and the expected performance impact threshold is a number less than 1, such as 1%, etc., which is not limited in the embodiment of the present invention.

[0163] 204. The decision unit determines whether the target period meets the preset function and performance impact conditions based on the interruption statistical window information, the expected number of interruptions, the acceptable extension information and the expected performance impact threshold. When the judgment result is yes, execute step 205; when the judgment result is no, execute step 206.

[0164] Optionally, for example: based on the predicted interrupt frequency, the delay required to enter and exit the WFI state, and the performance impact control threshold, dynamically switch to enter the WFI low frequency function to achieve the best fit between performance and power consumption, decide whether to turn on the WFI low frequency function in the target period, provided that the impact of this function on the performance is limited to the expected performance impact threshold, which is not limited in the embodiments of the present invention.

[0165] 205. The decision unit generates a first enabling instruction, where the first enabling instruction is used to control the CPU module to turn on WFI in a target cycle to automatically enter a low power consumption mode.

[0166] 206. The decision unit generates a second enabling instruction, where the second enabling instruction is used to control the CPU module to turn off WFI in a target cycle and automatically enter a low power consumption mode.

[0167] In the embodiment of the present invention, for other descriptions of step 201 to step 206, please refer to the detailed description of step 101 to step 103 in the first embodiment, and the embodiment of the present invention will not be repeated.

[0168] It can be seen that the embodiment of the present invention can determine whether the target cycle satisfies the low power consumption execution enabling condition through the decision unit, and generate matching enabling instructions according to the result of satisfying the low power consumption execution enabling condition, so as to control the CPU module to turn on / off WFI to automatically enter the low power consumption mode in the target cycle, which is conducive to improving the comprehensiveness and rationality of the CPU power consumption mode control method, and thus is conducive to improving the accuracy and reliability of the CPU power consumption mode control, and is conducive to improving the efficiency, convenience and timeliness of the CPU power consumption mode control, so as to achieve the reduction of CPU power consumption without affecting the performance; and, it can also determine the result of satisfying the function and performance impact condition according to the determined interrupt statistical window information, the expected number of interrupts, the acceptable extension information and the expected performance impact threshold, and then determine the result of satisfying the low power consumption execution enabling condition, which is conducive to improving the comprehensiveness and rationality of the method for determining the result of satisfying the low power consumption execution enabling condition, and thus is conducive to improving the accuracy and reliability of the determined result of satisfying the low power consumption execution enabling condition, so as to improve the accuracy and reliability of the enabling instruction generated based on the result of satisfying the low power consumption execution enabling condition, and improve the control accuracy, reliability and timeliness of turning on / off WFI of the CPU to automatically enter the low power consumption mode.

[0169] In an optional embodiment, the decision unit determines whether the target period meets the preset function and performance impact conditions according to the interruption statistical window information, the expected number of interruptions, the acceptable extension information and the expected performance impact threshold, including:

[0170] Determine a first calculation result according to the expected performance impact threshold, the interruption statistical window information, and the acceptable extension information;

[0171] Determining whether the first calculation result is greater than or equal to the expected number of interruptions;

[0172] When it is determined that the first calculation result is greater than or equal to the expected number of interruptions, determining that the target period meets the preset function and performance impact conditions;

[0173] When it is determined that the first calculation result is less than the expected number of interruptions, it is determined that the target period does not satisfy the preset function and performance impact condition.

[0174] It can be seen that this optional embodiment can determine the first calculation result based on the expected performance impact threshold, interruption statistical window information and acceptable extension information, and then determine the function and performance impact condition satisfaction result based on the comparison between the first calculation result and the expected number of interruptions, which is beneficial to improving the comprehensiveness and rationality of the method for determining the function and performance impact condition satisfaction result, and further helps to improve the accuracy and reliability of the determined function and performance impact condition satisfaction result.

[0175] In another optional embodiment, the first calculation result is greater than or equal to the expected number of interruptions, which is reflected by the following formula:

[0176]

[0177] Among them, N corresponds to the expected number of interruptions, H corresponds to the expected performance impact threshold, T corresponds to the interruption statistics window information, and D corresponds to the acceptable delay information.

[0178] It can be seen that this optional embodiment can reflect the situation that the first calculation result is greater than or equal to the expected number of interruptions through the formula, and determine the first calculation result through the formula, which is conducive to improving the scientificity, rationality, accuracy, and pertinence of the method for determining the first calculation result, and thus is conducive to improving the accuracy and reliability of the comparison between the determined first calculation result and the expected number of interruptions.

[0179] Embodiment 3

[0180] See also Figure 3 , Figure 3 Schematic diagram of a CPU power consumption control device disclosed in an embodiment of the present invention. Figure 3 The described control device includes a decision unit, wherein the decision unit includes a judgment module 301 and an instruction generation module 302, wherein:

[0181] The judgment module 301 is used to judge whether the target cycle meets the preset low power execution enabling condition.

[0182] The instruction generation module 302 is used for the decision unit to generate a first enabling instruction when the judging module 301 judges that the target cycle meets the low power execution enabling condition. The first enabling instruction is used to control the CPU module to turn on WFI in the target cycle to automatically enter the low power mode.

[0183] The instruction generation module 302 is also used for the decision unit to generate a second enabling instruction when the judging module 301 judges that the target cycle does not meet the low power execution enabling condition. The second enabling instruction is used to control the CPU module to turn off WFI in the target cycle and automatically enter the low power mode.

[0184] It can be seen that the implementation Figure 3The described CPU power consumption control device can determine whether a target cycle satisfies the low power consumption execution enabling condition through a decision unit, and generate matching enabling instructions according to the result of satisfying the low power consumption execution enabling condition, so as to control the CPU module to turn on / off WFI to automatically enter the low power consumption mode in the target cycle, which is beneficial to improving the comprehensiveness and rationality of the CPU power consumption mode control method, and further beneficial to improving the accuracy and reliability of the CPU power consumption mode control, as well as the efficiency, convenience and timeliness of the CPU power consumption mode control, so as to achieve the reduction of CPU power consumption without affecting performance.

[0185] In an alternative embodiment, Figure 4 The described CPU power consumption control device may further include an execution unit, wherein the execution unit may include a CPU module 303, a gating enable module 304, a wake-up logic module 305, and a signal phase and module 306, wherein:

[0186] The CPU module 303 is used to reflect its current state through a high-level waiting interrupt signal when the CPU module turns on WFI to automatically enter the low power consumption mode and the CPU module is in the WFI state.

[0187] The wake-up logic module 305 is used to reflect its current state through a high-level wake-up signal.

[0188] The signal phase AND module 306 is used to perform corresponding signal phase AND analysis operations on the high-level waiting interrupt signal and the high-level wake-up signal to obtain a first enable signal.

[0189] The gated enabling module 304 is used to perform a corresponding signal blocking operation on the CPU clock signal input from the first external device according to the first enabling signal.

[0190] The CPU module 303 is further configured to execute a corresponding clockless WFI low power consumption state mode switching operation to put the CPU module in a clockless WFI low power consumption state.

[0191] It can be seen that the implementation Figure 4 The described CPU power consumption control device can control the CPU module to be in a clockless WFI low power consumption state through a series of operations among the CPU module, the gating enable module, the wake-up logic module, and the signal phase and module in the execution unit, which is beneficial to improving the comprehensiveness and rationality of the control method of the clockless WFI low power consumption state of the CPU module, and further beneficial to improving the execution accuracy and reliability of the CPU module entering the clockless WFI low power consumption state, thereby helping to reduce the CPU idle power consumption.

[0192] In another optional embodiment, the wake-up logic module 305 is further configured to, when there is an interrupt request signal input through the second external device, perform a latch operation on the interrupt request signal and reflect its current state through a low-level wake-up signal.

[0193] The signal AND module 306 is further used to perform corresponding signal AND analysis operations on the high-level waiting interrupt signal and the low-level wake-up signal to obtain a second enable signal.

[0194] The gated enabling module 304 is further configured to execute a corresponding disabled operation according to the second enabling signal, so that the CPU clock signal inputted from the first external device can be transmitted to the CPU module.

[0195] The CPU module 303 is also used to execute the corresponding WFI low power state mode exit operation according to the CPU clock signal and the low level wake-up signal, and reflect its current state through the low level wait interrupt signal.

[0196] It can be seen that the implementation Figure 4 The described CPU power consumption control device can also control the CPU module to exit the WFI low power consumption state through a series of operations between the wake-up logic module, the signal phase and module, the gate enable module and the CPU module, which is beneficial to improving the comprehensiveness and integrity of the CPU power consumption control method, and is beneficial to improving the comprehensiveness and rationality of the CPU's WFI low power consumption state exit method, and further beneficial to improving the switching accuracy and reliability of the CPU's WFI low power consumption state.

[0197] In yet another optional embodiment, the gated enabling module 304 is further configured to execute a corresponding continuous disabled operation according to the low-level wait interrupt signal, so that the CPU clock signal input by the first external device can be continuously transmitted to the CPU module.

[0198] The CPU module 303 is also used to execute a corresponding normal operating mode switching operation according to the CPU clock signal, so that the CPU module is in a normal operating state.

[0199] It can be seen that the implementation Figure 4 The described CPU power consumption control device can also control the CPU to switch to a normal operating mode through a series of operations between a gated enable module and a CPU module, which is beneficial to improving the comprehensiveness and integrity of the CPU power consumption control method, and is beneficial to improving the comprehensiveness and rationality of the CPU's normal operating mode switching method, thereby helping to improve the accuracy and reliability of the CPU's normal operating state switching.

[0200] In yet another optional embodiment, the CPU module 303 is further configured to, when in a normal operating state, perform a corresponding signal response operation on an interrupt request signal received via a second external device.

[0201] The wake-up logic module 305 is also used to perform corresponding signal clearing operations and reflect its current state through a high-level wake-up signal.

[0202] It can be seen that the implementation Figure 4 The described CPU power consumption control device can also trigger and execute signal clearing operations through a series of operations between the CPU module and the wake-up logic module, which is beneficial to improving the comprehensiveness and integrity of the CPU power consumption control method, and is beneficial to improving the accuracy, efficiency and timeliness of signal data clearing, thereby helping to optimize memory consumption.

[0203] In yet another optional embodiment, Figure 4 As shown, the execution unit further includes an enabling switch control module 307, wherein:

[0204] The enable switch control module 307 is used to determine whether the enable control mode of the target cycle meets the preset enable control matching condition according to the WFI automatic entry and exit low power consumption state control requirement of the CPU module 303; when it is determined that the enable control mode does not meet the enable control matching condition, the corresponding enable control mode switching operation is performed.

[0205] It can be seen that the implementation Figure 4 The described CPU power consumption control device can also realize the enabling control mode switching function through the enabling switch control module, which is conducive to improving the comprehensiveness and rationality of the enabling control mode switching method, and then is conducive to improving the switching accuracy and reliability of the enabling control mode, as well as the switching efficiency, convenience and timeliness of the enabling control mode, thereby facilitating improving the regulation accuracy and effectiveness of the CPU power consumption switching scheme.

[0206] In another optional embodiment, the method in which the determination module 301 determines whether the target cycle satisfies the preset low power consumption execution enabling condition specifically includes:

[0207] According to the determined CPU historical interrupt frequency information, the number of historical interrupts in each past window is determined, and according to all historical interrupt times and the determined interrupt statistical window information, the expected number of interrupts in the target cycle is determined;

[0208] Determine, based on the determined CPU expected frequency information, acceptable extension information corresponding to the CPU entering and exiting the low power consumption state operation based on the target cycle;

[0209] Determine an expected performance impact threshold of a target period according to the determined expected performance impact information;

[0210] According to the interruption statistics window information, expected interruption times, acceptable extension information and expected performance impact threshold, determine whether the target cycle meets the preset function and performance impact conditions;

[0211] When it is determined that the target cycle satisfies the function and performance impact conditions, determining that the target cycle satisfies a preset low power execution enabling condition;

[0212] When it is determined that the target cycle does not satisfy the function and performance impact condition, it is determined that the target cycle does not satisfy the preset low power consumption enabling execution condition.

[0213] It can be seen that the implementation Figure 4 The described CPU power consumption control device can also determine the results of satisfying the function and performance impact conditions based on the determined interrupt statistical window information, expected number of interrupts, acceptable extension information and expected performance impact threshold, and then determine the results of satisfying the enabling low power execution conditions, which is beneficial to improving the comprehensiveness and rationality of the method for determining the results of satisfying the enabling low power execution conditions, and further beneficial to improving the accuracy and reliability of the determined results of satisfying the enabling low power execution conditions, thereby facilitating improving the accuracy and reliability of the enabling instructions generated based on the results of satisfying the enabling low power execution conditions, and improving the control accuracy, reliability and timeliness of turning on / off WFI of the CPU to automatically enter the low power mode.

[0214] In another optional embodiment, the judgment module 301 judges whether the target period meets the preset function and performance impact conditions according to the interruption statistical window information, the expected number of interruptions, the acceptable extension information and the expected performance impact threshold value, specifically including:

[0215] Determine a first calculation result according to the expected performance impact threshold, the interruption statistical window information, and the acceptable extension information;

[0216] Determining whether the first calculation result is greater than or equal to the expected number of interruptions;

[0217] When it is determined that the first calculation result is greater than or equal to the expected number of interruptions, determining that the target period meets the preset function and performance impact conditions;

[0218] When it is determined that the first calculation result is less than the expected number of interruptions, it is determined that the target period does not satisfy the preset function and performance impact condition.

[0219] It can be seen that the implementation Figure 4The described CPU power consumption control device can also determine a first calculation result based on the expected performance impact threshold, interruption statistical window information and acceptable extension information, and then determine the function and performance impact condition satisfaction result based on the comparison between the first calculation result and the expected number of interruptions, which is beneficial to improving the comprehensiveness and rationality of the method for determining the function and performance impact condition satisfaction result, and further beneficial to improving the accuracy and reliability of the determined function and performance impact condition satisfaction result.

[0220] In yet another optional embodiment, the first calculation result being greater than or equal to the expected number of interruptions is reflected by the following formula:

[0221]

[0222] Among them, N corresponds to the expected number of interruptions, H corresponds to the expected performance impact threshold, T corresponds to the interruption statistics window information, and D corresponds to the acceptable delay information.

[0223] It can be seen that the implementation Figure 4 The described CPU power consumption control device can also reflect the situation that the first calculation result is greater than or equal to the expected number of interruptions through a formula, and determine the first calculation result through a formula, which is conducive to improving the scientificity, rationality, accuracy and pertinence of the method for determining the first calculation result, and thus is conducive to improving the accuracy and reliability of the comparison between the determined first calculation result and the expected number of interruptions.

[0224] Embodiment 4

[0225] See also Figure 5 , Figure 5 is a schematic diagram of the structure of another CPU power consumption control device disclosed in an embodiment of the present invention. Figure 5 The described device may include a server, wherein the server includes a local server or a cloud server, which is not limited in the embodiment of the present invention. Figure 5 As shown, the device may include:

[0226] A memory 401 storing executable program codes;

[0227] a processor 402 coupled to the memory 401;

[0228] Furthermore, it may also include an input interface 403 and an output interface 404 coupled to the processor 402;

[0229] The processor 402 calls the executable program code stored in the memory 401 to execute the steps in the method for controlling CPU power consumption described in the first or second embodiment.

[0230] Embodiment 5

[0231] An embodiment of the present invention discloses a computer storage medium storing a computer program for electronic data exchange, wherein the computer program enables a computer to execute the steps of a method for controlling CPU power consumption described in Embodiment 1 or Embodiment 2.

[0232] Embodiment 6

[0233] An embodiment of the present invention discloses a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to enable a computer to execute the steps in a method for controlling CPU power consumption described in Embodiment 1 or Embodiment 2.

[0234] The device embodiments described above are only illustrative, wherein the modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, they may be located in one place, or they may be distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Those of ordinary skill in the art may understand and implement it without creative work.

[0235] Through the specific description of the above embodiments, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on such an understanding, the above technical solution can be essentially or partly contributed to the prior art in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, and the storage medium includes a read-only memory (ROM), a random access memory (RAM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), a one-time programmable read-only memory (OTPROM), an electronically erasable rewritable read-only memory (EEPROM), a compact disc (CD-ROM) or other optical disc storage, a magnetic disk storage, a magnetic tape storage, or any other computer-readable medium that can be used to carry or store data.

[0236] Finally, it should be noted that the method and device for controlling CPU power consumption disclosed in the embodiment of the present invention disclose only the preferred embodiments of the present invention, which are only used to illustrate the technical solution of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments can still be modified, or some of the technical features can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for controlling CPU power consumption, characterized in that: The method is applied in a control device, wherein the control device includes a decision-making unit, and the method includes: The decision unit determines whether the target cycle meets a preset low power consumption execution enabling condition; When it is determined that the target cycle satisfies the low power consumption execution enabling condition, the decision unit generates a first enabling instruction, wherein the first enabling instruction is used to control the CPU module to turn on WFI in the target cycle and automatically enter the low power consumption mode; When it is determined that the target cycle does not meet the low power execution enabling condition, the decision unit generates a second enabling instruction, where the second enabling instruction is used to control the CPU module to turn off WFI in the target cycle and automatically enter the low power mode.

2. A method for controlling CPU power consumption according to claim 1, characterized in that: The control device further includes an execution unit, wherein the execution unit includes the CPU module, the gating enable module, the wake-up logic module, and the signal phase and module; And, the method further comprises: When the CPU module turns on the WFI to automatically enter the low power consumption mode and the CPU module is in the WFI state, the CPU module reflects its current state through a high-level waiting interrupt signal, and the wake-up logic module reflects its current state through a high-level wake-up signal; The signal phase AND module performs a corresponding signal phase AND analysis operation on the high-level waiting interrupt signal and the high-level wake-up signal to obtain a first enable signal; The gating enabling module performs a corresponding signal blocking operation on the CPU clock signal input from the first external device according to the first enabling signal; The CPU module performs a corresponding clockless WFI low power state mode switching operation to put the CPU module in a clockless WFI low power state.

3. A method for controlling CPU power consumption according to claim 2, characterized in that: The method further comprises: When there is an interrupt request signal input through the second external device, the wake-up logic module performs a latch operation on the interrupt request signal and reflects its current state through a low-level wake-up signal; The signal phase AND module performs corresponding signal phase AND analysis operations on the high-level waiting interrupt signal and the low-level wake-up signal to obtain a second enable signal; The gating enable module performs a corresponding failure operation according to the second enable signal, so that the CPU clock signal input by the first external device can be transmitted to the CPU module; The CPU module executes the corresponding WFI low power state mode exit operation according to the CPU clock signal and the low level wake-up signal, and reflects its current state through a low level wait interrupt signal.

4. A method for controlling CPU power consumption according to claim 3, characterized in that: The method further comprises: The gating enabling module performs a corresponding continuous failure operation according to the low-level waiting interrupt signal, so that the CPU clock signal input by the first external device can be continuously transmitted to the CPU module; The CPU module performs a corresponding normal operating mode switching operation according to the CPU clock signal, so that the CPU module is in a normal operating state; And, the method further comprises: When the CPU module is in the normal operating state, the CPU module performs a corresponding signal response operation on an interrupt request signal received and inputted through the second external device; The wake-up logic module performs a corresponding signal clearing operation and reflects its current state through a high-level wake-up signal.

5. A method for controlling CPU power consumption according to any one of claims 2 to 4, characterized in that: The execution unit further includes an enabling switch control module, and the method further includes: The enabling switch control module determines whether the enabling control mode of the target cycle meets the preset enabling control matching condition according to the WFI automatic entry and exit low power consumption state control requirement for the CPU module; When it is determined that the enabling control mode does not satisfy the enabling control matching condition, a corresponding enabling control mode switching operation is performed.

6. A method for controlling CPU power consumption according to claim 1, characterized in that: The decision unit determines whether the target cycle meets the preset low power consumption execution enabling condition, including: The decision unit determines the number of historical interruptions in each past window according to the determined CPU historical interruption frequency information, and determines the expected number of interruptions in the target cycle according to all the historical interruption numbers and the determined interruption statistics window information; Determine, based on the determined CPU expected frequency information, acceptable extension information corresponding to the target cycle and the CPU entering and exiting the low power consumption state operation; Determining an expected performance impact threshold of the target period according to the determined expected performance impact information; Determining whether the target period meets preset function and performance impact conditions according to the interruption statistics window information, the expected number of interruptions, the acceptable extension information and the expected performance impact threshold; When it is determined that the target cycle satisfies the function and performance impact condition, determining that the target cycle satisfies a preset low power consumption enabling execution condition; When it is determined that the target cycle does not satisfy the function and performance impact condition, it is determined that the target cycle does not satisfy a preset low power consumption enabling execution condition.

7. A method for controlling CPU power consumption according to claim 6, characterized in that: The decision unit determines whether the target period meets the preset function and performance impact conditions according to the interruption statistical window information, the expected number of interruptions, the acceptable extension information and the expected performance impact threshold, including: Determine a first calculation result according to the expected performance impact threshold, the interruption statistical window information and the acceptable extension information; Determining whether the first calculation result is greater than or equal to the expected number of interruptions; When it is determined that the first calculation result is greater than or equal to the expected number of interruptions, determining that the target period meets a preset function and performance impact condition; When it is determined that the first calculation result is less than the expected number of interruptions, determining that the target period does not meet the preset function and performance impact condition; And, the first calculation result is greater than or equal to the expected number of interruptions, which is reflected by the following formula: Among them, N corresponds to the expected number of interruptions, H corresponds to the expected performance impact threshold, T corresponds to the interruption statistical window information, and D corresponds to the acceptable delay information.

8. A CPU power consumption control device, characterized in that: The control device includes a decision unit, wherein the decision unit includes a judgment module and an instruction generation module, wherein: The judging module is used to judge whether the target cycle satisfies the preset low power consumption execution enabling condition; The instruction generation module is used for the decision unit to generate a first enabling instruction when the judging module judges that the target cycle meets the enabling low power execution condition, and the first enabling instruction is used to control the CPU module to turn on WFI in the target cycle to automatically enter the low power mode; The instruction generation module is also used for the decision unit to generate a second enabling instruction when the judgment module determines that the target cycle does not meet the low power execution enabling condition, and the second enabling instruction is used to control the CPU module to turn off WFI in the target cycle and automatically enter the low power mode.

9. A CPU power consumption control device, characterized in that: The control device comprises: A memory storing executable program code; a processor coupled to the memory; The processor calls the executable program code stored in the memory to execute a method for controlling CPU power consumption as described in any one of claims 1 to 7.

10. A computer storage medium, characterized in that: The computer storage medium stores computer instructions, and when the computer instructions are called, they are used to execute a CPU power consumption control method as described in any one of claims 1-7.

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