Apparatus with multi-mode register read and write commands

Abstract

The invention relates to a device with multi-mode register read and write commands. This disclosure provides methods, apparatuses, and systems related to operations for performing mode register full read and mode register full write commands. The memory device may perform mode register full read or mode register full write commands using unit intervals of one or more DQs. One or more command address pins may be specified to store a group of mode registers. The memory device may read or write mode register information associated with the group of mode registers through a predefined number of DQs, a burst length, and a die configuration.

Description

Technical Field

[0001] The disclosed embodiments relate to devices, and in particular to semiconductor memory devices having mode register read and write commands. Background Art

[0002] An apparatus (e.g., a data processing device, a memory device, a memory system, or a combination thereof) may include one or more semiconductor circuits configured to store and / or process information. For example, the apparatus may include a memory device, such as a volatile memory device, a nonvolatile memory device, or a combination device. Memory devices (e.g., flash memory and dynamic random access memory (DRAM)) may utilize electrical energy to store and access data.

[0003] With the increase of technological advancement and application in various fields, the market is constantly seeking faster, more efficient and smaller devices. In order to meet market demand, semiconductor devices are being pushed to the limit. However, attempts to increase operating speed and / or reduce circuit size often produce other problems, such as signal quality degradation, increased noise and increased processing errors. In view of the increasing commercial competitive pressures together with the growing consumer expectations and the desire to differentiate products on the market, it is increasingly expected to find answers to these problems. In addition, semiconductor devices must perform read and write operations at high speeds, which may cause errors. In addition, the need to reduce costs, improve efficiency and performance, and cope with competitive pressures adds even greater pressure to find answers to these problems. Summary of the invention

[0004] One aspect of the present disclosure relates to a device, comprising: an input / output circuit configured to communicate with an external controller, wherein the input / output circuit includes a command / address (CA) interface and a data (DQ) interface; and a mode register circuit coupled to the input / output circuit and configured to: decode a command from the external controller on the CA interface, wherein the command includes a mode register read-all (MRR-ALL) command or a mode register write-all (MRW-ALL) command; determine a die configuration and a burst length for executing the MRR-ALL command or the MRW-ALL command; and determine at least one mode register group identified in the MRR-ALL command or the MRW-ALL command, wherein the input / output circuit is configured to: send mode register information associated with the at least one mode register group identified in the MRR-ALL command to the external controller through the DQ interface.

[0005] Another aspect of the present disclosure relates to a memory system, comprising: a memory controller; and a memory array, which is operably coupled to the memory controller and configured to: decode a command from the memory controller, wherein the command comprises a mode register read-all (MRR-ALL) command or a mode register write-all (MRW-ALL) command; determine a die configuration and a burst length for executing the MRR-ALL command or the MRW-ALL command; determine at least one mode register group identified in the MRR-ALL command or the MRW-ALL command; and send mode register information associated with the at least one mode register group identified in the MRR-ALL command to the memory controller.

[0006] Yet another aspect of the present disclosure relates to a method for operating a device, the method comprising: decoding a command from an external controller, wherein the command comprises a mode register read-all (MRR-ALL) command or a mode register write-all (MRW-ALL) command; determining a die configuration and a burst length for executing the MRR-ALL command or the MRW-ALL command; determining at least one mode register group identified in the MRR-ALL command or the MRW-ALL command; and sending mode register information associated with the at least one mode register group identified in the MRR-ALL command to the external controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A is a block diagram of an example environment in which devices may operate in accordance with embodiments of the present technology.

[0008] Figure 1B is a block diagram of a device according to an embodiment of the present technology.

[0009] Figures 2A to 2E is a diagram illustrating the assignment of mode registers to data input / output (DQ) pins of a memory device in different die configurations and for different burst length configurations for mode register full read and / or mode register full write commands in accordance with an embodiment of the present technology.

[0010] Figure 3A is a flow chart illustrating an example method of operating an apparatus for a mode register full read command in accordance with an embodiment of the present technology.

[0011] Figure 3B is a diagram illustrating a command truth table of a mode register full read command according to an embodiment of the present technology.

[0012] Figure 4A is a flow chart illustrating an example method of operating an apparatus for a mode register full write command in accordance with an embodiment of the present technology.

[0013] Figure 4B is a diagram illustrating a command truth table of a mode register full write command according to an embodiment of the present technology.

[0014] Figure 4C is a timing diagram illustrating the timing of a mode register full write command according to an embodiment of the present technology.

[0015] Figure 4D is a timing diagram illustrating a back-to-back mode register full write command according to an embodiment of the present technology.

[0016] Figure 5 is a schematic diagram of a system including devices according to embodiments of the present technology. DETAILED DESCRIPTION

[0017] As described in more detail below, the technology disclosed herein relates to an apparatus for managing memory internal operations, such as a memory system, a system having one or more memory devices, related methods, etc. In particular, the disclosed technology relates to improved transfer of data to and from a mode register of one or more memory devices.

[0018] Currently, due to the high operating speeds, memory systems require various training processes before initiating normal data transfer operations. The training process may require components of the memory system (e.g., a memory controller and / or a host) to write data to and / or read data from one or more mode registers of a memory device of the memory system. In addition, after training, the system may need to continue to read and / or write mode register information periodically or irregularly. The memory system may support a mode register read (MRR) command (by which the host can read data from a mode register of a memory device) and a mode register write (MRW) command (by which the host can write data to a mode register of a memory device). In some memory systems (e.g., memory systems that comply with certain versions of the double data rate (DDR) synchronous DRAM (SDRAM) standard (e.g., DDR5)), each MRR and / or MRW command addresses a single mode register. For example, an MRR command issued by a host may specify a single mode register (e.g., as part of the command), and the memory device may send data from that mode register on all data pins (DQ) of the memory device via a burst of multiple UIs. As a further example, an MRW command issued by a host may specify a single mode register (e.g., as part of the command) and data to be written to that mode register (e.g., as another part of the command). For example, the host may indicate the mode register to be read or written using one or more command address (CA) signals received by a memory device. In such a memory system (where each MRR and / or MRW command issued by the host provides access to a single mode register), the host must issue multiple MRR and / or MRW commands to access multiple mode registers. Because in such a memory system, multiple commands are required to access various mode registers (e.g., a host that needs to write to 15 different mode registers will need to issue 15 corresponding MRW commands), writing or reading mode register bits from various mode registers may cause latency in the system, which degrades performance. Therefore, there is a need for a memory system with commands to read and write multiple mode registers at once ("a memory system with multiple mode register read and write commands") to support efficient transfer of mode register related data between a memory device and a host.

[0019] Therefore, an embodiment of a memory system with multi-mode register read and write commands provides a command to read data from a multi-mode register (MRR-ALL command) and / or a command to write data to a multi-mode register (MRW-ALL command). As described herein, the MRR-ALL and / or MRW-ALL commands may be configured to transfer data of different mode registers through multiple UIs of a burst using one or more DQs of a memory device. Although referred to herein as MRR-ALL and MRW-ALL commands, in some embodiments, each issued command is capable of accessing multiple mode registers of a memory device, but not all mode registers of the memory device. As described herein, in an embodiment of a memory system with multi-mode register read and write commands, the mode registers (or a subset of the mode registers) of the memory device are divided into one or more mode register groups, and each issued MRR-ALL and / or MRW-ALL command may access all mode registers belonging to the group identified by the issued command. The MRR-ALL and / or MRW-ALL commands may be used in low frequency operations before the device completes training and / or in high frequency operations after the device completes training (eg, write / read training).

[0020] In some embodiments of the MRR-ALL command, one or more CA signals between the host and the memory device are used to indicate the group. Each group may be associated with one or more mode registers (e.g., group A may be associated with mode registers 0 to 3, group B may be associated with mode registers 4 to 7, etc.), and the contents of different mode registers associated with the indicated group may be read in response to the MRR-ALL command. As described herein, the contents of each mode register belonging to the indicated group (e.g., OP0 to OP7 of each mode register) may be transmitted between the memory device and the host via DQs during the UIs that make up the burst. The DQs used to transmit the contents of a particular mode register in the group and the UIs during which those mode register contents are to be transmitted may be predefined. In some embodiments, the number of groups and CA pins may be predefined. When the host sends the MRR-ALL command to the memory device, the memory device retrieves the mode register information of the mode registers belonging to the group specified by the MRR-ALL command. Since information from different mode registers is sent via several DQs, the host may receive mode register information for multiple mode registers in response to a single command (e.g., MRR-ALL). To receive mode register information from a designated group, the host may mark the associated CA pin as "high" when issuing the MRR-ALL command. Upon receiving the MRR-ALL command, the memory device will respond with mode register information from the designated mode register group.

[0021] In some embodiments of the MRW-ALL command, one or more CA signals between the host and the memory device are used to indicate the group. As described above, each group may be associated with one or more mode registers, and different mode registers associated with the indicated group may be written based on the MRW-ALL command. As described herein, the content to be written to each mode register belonging to the indicated group (e.g., OP0 to OP7 of each mode register) may be transmitted between the host and the memory device via DQ during the UI that constitutes the burst. The DQ used to transmit the content of the specific mode register to be written to the group and the UI during which those mode register contents will be transmitted may be predefined. In some embodiments, the number of groups and CA pins may be predefined. When the host sends the MRW-ALL command to the memory device, the memory device stores the mode register information in the mode register belonging to the group specified by the MRW-ALL command. Since the information to be written to different mode registers is transmitted via several DQs, the host may send the mode register information of multiple mode registers as part of a single command (e.g., MRW-ALL). To store mode register information to a specific group, the host may mark the associated CA pin as "high" when issuing the MRW-ALL command. Upon receiving the MRW-ALL command, the memory device stores the mode register information to the mode register belonging to the specific group.

[0022] As described in more detail below, grouping the mode registers of the memory devices into groups may depend on the configuration of the memory devices. For example, the memory devices may have different die configurations associated with the number of DQ pins of the memory devices. That is, some memory devices may have 4 DQ pins (referred to as x4 devices, with DQ0 to DQ3), some memory devices may have 8 DQ pins (referred to as x8 devices, with DQ0 to DQ7), some memory devices may have 16 DQ pins (referred to as x16 devices, with DQ0 to DQ15), etc. As a further example, the memory devices may be configured with different burst lengths (e.g., the amount of data transmitted through the DQ pins after a command). That is, some memory devices may have a burst length of 16 (referred to as BL16, where data is transmitted through the DQ within 16 UI), some memory devices may have a burst length of 32 (referred to as BL32, where data is transmitted through the DQ within 32 UI, etc.). Based on the die configuration of the memory device (e.g., how many DQ pins the memory device has) and / or the burst length configuration of the memory device (e.g., how many UIs of data can be transmitted through each DQ), the total amount of data that can be transmitted through the memory device DQ pins in association with the MRR-ALL or MRW-ALL command changes, and the number of mode registers that can be assigned to a group (and the group composition) changes accordingly. For example, a x16 memory device configured as BL16 can transmit 256 data bits through the DQ pins as part of the MRR-ALL or MRW-ALL command (e.g., 16 DQ pins multiplied by 16 UIs per DQ). In an embodiment where each mode register has 8 bits of information (e.g., OP0-OP7), the x16 / BL16 memory device can therefore transmit the contents corresponding to 32 mode registers through the DQs in response to the MRR-ALL or MRW-ALL command (e.g., 256 data bits through the DQs divided by 8 data bits per mode register). As a further example, a x4 memory device configured as BL16 may transmit the contents of 8 mode registers per MRR-ALL or MRW-ALL command, provided that there are 8 bits of information per mode register. Thus, the size of a group (e.g., the number of mode registers assigned to a group) may vary depending on the memory device configuration, such that data associated with all mode registers in a group may be transmitted as part of an MRR-ALL or MRW-ALL command issued to that memory device. For example, a x16 / BL16 memory device may have a group size of 32, while a x4 / BL16 memory device may have a group size of 8. Similarly, mode registers within a group may be assigned to a DQ of the memory device, depending on the memory device configuration.Therefore, and as described in more detail herein, components of a memory system (e.g., a host, a memory controller, and / or a memory device) having multi-mode register read and write commands may associate different mode registers with groups corresponding to different group sizes that are transmitted through different DQs at different UIs depending on the configuration of the memory devices within the memory system.

[0023] As described in detail below, embodiments of the present technology may provide technical advantages over conventional techniques. For example, by grouping multiple mode registers into groups (where each group is sized so that information corresponding to all mode registers within the group can be transmitted during a burst), a memory system with multiple mode register read and write commands may provide information associated with additional (e.g., 8*X number of mode registers) mode registers in the same amount of time as conventional techniques provide information associated with a single mode register. The mode registers forming the group for the MRW-ALL command may be different from or the same as the mode registers forming the group for the MRR-ALL command.

[0024] Figure 1A 1 is a block diagram of an example environment 101 in which apparatus 100 may operate according to embodiments of the present technology. Example environment 101 may correspond to a computing device or system. As described in detail below, apparatus 100 may include a memory device or system, such as volatile memory, non-volatile memory, or a combination device / system. For example, apparatus 100 may include DRAM.

[0025] The device 100 may be electrically coupled to a device controller 102 (e.g., a memory controller, a buffer, a repeater device such as an RCD, etc.) and a host 103 (e.g., one or more processors). Some example operating environments may include a computing system having a central processing unit (CPU) as the host 103, which interacts with the device controller 102 to write data to the DRAM (device 100) and read data from it. The host 103 may operate according to an operating system and send operation communications (e.g., read / write commands, MRR-ALL commands, MRW-ALL commands, write data, addresses, etc.) to the device controller 102. The device 100 may also send read data back to the device controller 102 as an operation communication. The device controller 102 may manage the flow of data to or from the device 100 according to addresses and / or operations.

[0026] Figure 1B 1 is a block diagram of an apparatus 100 (e.g., a semiconductor die assembly, including a 3DI device or a die-stacked package) according to an embodiment of the present technology. For example, the apparatus 100 may include a DRAM (e.g., a DDR DRAM, such as a DDR4 or DDR5 DRAM, an LP DRAM, an HBM DRAM, etc.) or a portion thereof.

[0027] The apparatus 100 may include an array of memory cells, such as the memory array 150. The memory array 150 may include a plurality of banks (e.g., banks 0 to 15), and each bank may include a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells arranged at the intersections of the word lines and the bit lines. The memory cells may include any of a number of different memory media types, including capacitive, magnetoresistive, ferroelectric, phase change, or the like. The selection of the word lines (WL) may be performed by a row decoder 140, and the selection of the bit lines BL may be performed by a column decoder 145. A sense amplifier (SAMP) may be provided for the corresponding bit lines BL and connected to at least one corresponding local I / O line pair (LIOT / B), which in turn may be coupled to at least one corresponding main I / O line pair (MIOT / B) via a transfer gate (TG), which may act as a switch. The memory array 150 may also include plate lines and corresponding circuitry for managing their operation.

[0028] The device 100 may employ a plurality of external terminals including command and address terminals coupled to a command bus and an address bus to receive a command signal (CMD) and an address signal (ADDR), respectively. The device 100 may further include a chip select terminal for receiving a chip select signal (CS), a clock terminal for receiving clock signals CK and CKF, a data clock terminal for receiving data clock signals WCK and WCKF, data terminals DQ, RDQS, DBI and DMI, power supply terminals VDD, VSS and VDDQ.

[0029] Address signals and bank address signals can be supplied to the command terminal and address terminal from the outside ( Figure 1B 140). The address signal supplied to the address terminal and the memory bank address signal may be transmitted to the address decoder 110 via the command / address input circuit 105. The address decoder 110 may receive the address signal and supply the decoded row address signal (XADD) to the row decoder 140, and supply the decoded column address signal (YADD) to the column decoder 145. The address decoder 110 may also receive the memory bank address signal and supply the memory bank address signal to both the row decoder 140 and the column decoder 145.

[0030] can be obtained from a memory controller (e.g., Figure 1A , 2AThe device controller 102 of the memory controller 100 and 3A supplies a command signal (CMD), an address signal (ADDR) and a chip select signal (CS) to the command and address terminals. The command signal may represent various memory commands (e.g., including access commands, which may include read commands and write commands) from the memory controller. The chip select signal may be used to select the device 100 to respond to the command and address provided to the command and address terminals. When the active chip select signal is provided to the device 100, the command and address may be decoded and the memory operation may be performed. The command signal may be provided to the command decoder 115 as an internal command signal ICMD via the command / address input circuit 105. The command decoder 115 may include a circuit for decoding the internal command signal ICMD to generate various internal signals and commands for performing memory operations (e.g., a row command signal for selecting a word line and a column command signal for selecting a bit line). The command decoder 115 may further include one or more registers for tracking various counts or values ​​(e.g., a refresh command received by the device 100 or a count of a self-refresh operation performed by the device 100).

[0031] Read data may be read from a memory cell specified by a row address (e.g., an address provided with an active command) and a column address (e.g., an address provided with a read) in the memory array 150. The read command may be received by the command decoder 115, which may provide an internal command to the input / output circuit 160, so that the read data may be output from the data terminals DQ, RDQS, DBI, and DMI via the read / write amplifier 155 and the input / output circuit 160 according to the RDQS clock signal. The read data may be provided at a time defined by the read latency information RL, which may be programmed in the device 100, for example, in a mode register ( Figure 1B The read latency information RL may be defined according to a clock cycle of the CK clock signal. For example, when providing associated read data, the read latency information RL may be the number of clock cycles of the CK signal after the read command is received by the device 100.

[0032] The write data may be supplied to the data terminals DQ, DBI, and DMI according to the WCK and WCKF clock signals. The write command may be received by the command decoder 115, which may provide an internal command to the input / output circuit 160, so that the write data may be received by the data receiver in the input / output circuit 160 and supplied to the memory array 150 via the input / output circuit 160 and the read / write amplifier 155. The write data may be written into the memory cell specified by the row address and the column address. The write data may be provided to the data terminal at a time defined by the write delay WL information. The write delay WL information may be programmed in the device 100, for example, in the mode register ( Figure 1BThe write latency information WL may be defined according to the clock cycle of the CK clock signal. For example, when the associated write data is received, the write latency information WL may be the number of clock cycles of the CK signal after the write command is received by the device 100.

[0033] The power supply terminal may be supplied with power supply potentials VDD and VSS for power supply. These power supply potentials VDD and VSS may be supplied to the internal voltage generator circuit 170. The internal voltage generator circuit 170 may generate various internal potentials VPP, VOD, VARY, VPERI, and the like based on the power supply potentials VDD and VSS. The internal potential VPP may be used in the row decoder 140, the internal potentials VOD and VARY may be used in the sense amplifiers included in the memory array 150, and the internal potential VPERI may be used in many other circuit blocks.

[0034] The power supply terminal may also be supplied with a power supply potential VDDQ. The power supply potential VDDQ may be supplied to the input / output circuit 160 together with the power supply potential VSS. In an embodiment of the present technology, the power supply potential VDDQ may be the same potential as the power supply potential VDD. In another embodiment of the present technology, the power supply potential VDDQ may be a different potential from the power supply potential VDD. However, a dedicated power supply potential VDDQ may be used for the input / output circuit 160 so that the power supply noise generated by the input / output circuit 160 does not propagate to other circuit blocks.

[0035] The clock terminal and the data clock terminal may be supplied with an external clock signal and a complementary external clock signal. The external clock signals CK, CKF, WCK, and WCKF may be supplied to the clock input circuit 120. The CK and CKF signals may be complementary, and the WCK and WCKF signals may also be complementary. The complementary clock signals may have opposite clock levels and simultaneously transition between opposite clock levels. For example, when the clock signal is at a low clock level, the complementary clock signal is at a high level, and when the clock signal is at a high clock level, the complementary clock signal is at a low clock level. In addition, when the clock signal transitions from a low clock level to a high clock level, the complementary clock signal transitions from a high clock level to a low clock level, and when the clock signal transitions from a high clock level to a low clock level, the complementary clock signal transitions from a low clock level to a high clock level.

[0036] The input buffer included in the clock input circuit 120 may receive an external clock signal. For example, the input buffer may receive a clock / enable signal when enabled by a clock / enable signal from the command decoder 115. The clock input circuit 120 may receive an external clock signal to generate an internal clock signal ICLK. The internal clock signal ICLK may be supplied to the internal clock circuit 130. The internal clock circuit 130 may generate an internal clock signal ICLK based on the received internal clock signal ICLK and the clock enable ( Figure 1B For example, the internal clock circuit 130 may include a clock path (not shown) that receives the internal clock signal ICLK and provides various clock signals to the command decoder 115. Figure 1B 100). The internal clock circuit 130 may further provide an input / output (IO) clock signal. The IO clock signal may be supplied to the input / output circuit 160 and may be used as a timing signal for determining the output timing of read data and the input timing of write data. The IO clock signal may be provided at multiple clock frequencies so that data may be output from and input to the device 100 at different data rates. When high memory speed is desired, a higher clock frequency may be desired. When lower power consumption is desired, a lower clock frequency may be desired. The internal clock signal ICLK may also be supplied to a timing generator and various internal clock signals may be generated accordingly.

[0037] The apparatus 100 may be connected to any of a number of electronic devices or components thereof that are capable of utilizing memory to temporarily or permanently store information. For example, the host device and the apparatus 100 may be included in a computing device such as a desktop or portable computer, a server, a handheld device (e.g., a mobile phone, a tablet computer, a digital reader, a digital media player), or a component thereof (e.g., a central processing unit, a coprocessor, a dedicated memory controller, etc.).

[0038] Device 100 may include MRR / MRW circuit 180. MRR / MRW circuit 180 may be included in or coupled to a circuit that receives a signal from an external source. For example, MRR / MRW circuit 180 may be included in or coupled to command / address input circuit 105, clock input circuit 120, and / or IO circuit 160. MRR / MRW circuit 180 may be configured to receive a signal from an external source (e.g., Figure 1AThe device controller 102 of the MRR / MRW circuit 180 receives the MRR-ALL command and / or the MRW-ALL command. The MRR / MRW circuit 180 may store mode register information to or retrieve mode register information from one or more mode registers 182. The mode registers 182 may be organized into one or more groups. Each group is associated with a specific mode register from the mode registers 182 to which information is stored during a write operation (e.g., in response to a MRW-ALL command) or from which information is read during a read operation (e.g., in response to a MRR-ALL command). The group to be read and / or written may be indicated by one or more of the command and / or address signals. In some embodiments, one or more individual bits of the command and / or address signals may be associated with individual groups, and the asserted bit selects the corresponding group (e.g., one bit may be used to select group A, another bit may be used to select group B, and another bit may be used to select group C). In some embodiments, one or more bits of the command and / or address signals are used to encode a group identifier (e.g., three command / address signals may be used to encode an identifier of one of groups A to H). The MRR / MRW circuit 180 may determine which mode registers from the mode registers 182 belong to the selected group based on the configuration of the device 100 (e.g., based on the number of DQs, the burst length, and / or the die configuration). During a burst, the device 100 may send or receive information of different mode registers (e.g., OP0 to OP7) via the DQs at a particular UI, as determined by the MRR / MRW circuit 180 and / or the command decoder 115. For example, in response to the MRR-ALL command, the device 100 may transmit the contents of a first mode register via DQ0 during UI0 to UI7, and transmit the contents of a second mode register via DQ0 during UI8 ​​to UI15. The contents of other mode registers may be transmitted via other DQs (e.g., DQ1 to DQ15) and / or within other UIs (e.g., UI16 to UI31), where the mode register from which information is read is based on the selected group, depending on the configuration of the device 100. Similarly, during a MRW-ALL command, the device 100 may receive information to be written to different mode registers within a selected group via DQ at different UIs within a burst. The command decoder 115 (or MRR / MRW circuit 180) may send / receive signals to one or more mode registers in the mode registers 182 to store or retrieve data based on the group selection indicated by the command and address pins.The signals may include a mode register selection (e.g., which mode registers are being read or written), operand data from CA (e.g., data to be written to a mode register provided over a command / address bus, e.g., for a conventional MRW command), operand data from DQ (e.g., data to be written to a mode register provided over a data bus, e.g., for a MRW-ALL command), an MRR command control enable signal (e.g., when the device receives a conventional MRR command), an MRW command control enable signal (e.g., when the device receives a conventional MRW command), an MRR-ALL command control enable signal (e.g., when the device receives an MRR-ALL command), and / or an MRW-ALL command control enable signal (e.g., when the device receives a MRW-ALL command). In a MRW-ALL command, data (e.g., write-leveling data) is received through the DQs of the IO circuit 160 and sent to the selected mode register 182.

[0039] Figure 2A 200 is a diagram illustrating the assignment of mode registers to DQ pins for an x4 memory device configured as BL16 in accordance with an embodiment of the present technology. As illustrated by MRR / MRW-ALL assignment logic 205, the mode register associated with a given DQ may be based on a mode register group (e.g., as indicated by an MRR-ALL and / or MRW-ALL command), a DQ identifier (e.g., which of DQ0 through DQ3), a UI identifier (e.g., a location within a burst), a die configuration of the memory device (e.g., how many DQ pins), and / or a burst length. For example, in an x4 memory device configured as BL16, if the MRR-ALL and / or MRW-ALL commands select mode register group A, then DQ0 will be used for data of a designated mode register during UI[0:7] of the burst (as illustrated by decode 210), and for a different designated mode register during UI[8:15] of the burst. Table 215 illustrates an example assignment of a single group (e.g., Group A) of an x4 memory device configured as BL16. As shown in FIG. Figure 2A As illustrated in Table 215, in example assignment 200, Group A consists of mode registers MR#1 to MR#8. As reflected in Table 215, in example assignment 200, the contents of MR#1, MR#3, MR#5, and MR#7 are transferred through DQ0 to DQ3 during the first half of the burst (e.g., UI0 to UI7), and the contents of MR#2, MR#4, MR#6, and MR#8 are transferred through DQ0 to DQ3 during the second half of the burst (e.g., UI8 to UI15). That is, Figure 2A, in an embodiment where each mode register contains 8 bits of information (e.g., OP0-OP7), then when used with a x4 memory device configured as BL16, the MRR-ALL and / or MRW-ALL commands enable the transfer of the contents of a total of 8 mode registers. It will be appreciated that in some embodiments, other mode registers may be associated with a particular mode register group.

[0040] Figure 2B 2 is a diagram illustrating the assignment of mode registers to DQ pins for a x4 memory device configured as BL32 according to an embodiment of the present technology. Table 225 illustrates an example assignment for a single group (e.g., Group A) of a x4 memory device configured as BL32. Figure 2B 2, in example assignment 220, group A consists of mode registers MR#1 through MR#16. As reflected in table 225, in example assignment 220, the contents of a first set of mode registers within a group are transferred within a first portion of a burst (e.g., UI0 through UI7), the contents of a second set of mode registers within a group are transferred within a second portion of a burst (e.g., UI8 through UI15), etc. For example, in an embodiment, the contents of MR#2 are transferred using DQ0 during UI8 ​​through UI15 of a burst (as illustrated by decode 230).

[0041] Figure 2C and 2D Mode register assignments for other configurations of memory devices are described. For example, Figure 2C illustrates the assignment 235 of mode registers to DQ pins for a x8 memory device configured as BL 32, and Figure 2D The assignment of mode registers to DQ pins for a x16 memory device configured as BL32 is illustrated 240. Figure 2C and 2D As described in , the number of mode registers whose contents can be transferred over DQ during a burst (e.g., from a memory device during MRR-ALL or to a memory device during MRW-ALL) can increase as the number of DQ pins of a memory device increases.

[0042] Figure 2E 2 is a diagram illustrating an assignment 245 for a x4 memory device configured for BL32 according to an embodiment of the present technology. As illustrated in the assignment 245, each bit of the mode register information is transmitted within two UIs, thus providing additional timing margin (e.g., with Figure 2A 200 as described in ). For example, Figure 2EAs illustrated in FIG. 245 , the contents of MR#1 may be transmitted in UI0 to UI15, wherein half of the contents of the mode register (OP0 to OP3) are transmitted in UI0 to UI7, and the other half of the contents of the mode register (OP4 to OP7) are transmitted in UI8 to UI15. That is, in assignment 245, fewer contents of the mode register may be transmitted during a burst, but a larger timing margin is provided for transmitting each bit of the mode register. Although Figure 2E Assignment 245 illustrates a representative group (e.g., "Group A") on a x4 memory device with a burst length of 32, but assignments in which each bit of mode register data is transmitted within two UIs may include assignments of other groups and / or other memory device configurations. Although assignment 245 illustrates one OP bit spanning two UIs, the present technique may be applied to one OP bit spanning any number of unit intervals. For example, each OP bit of the mode register may be transmitted within four UIs for further improving timing margins. In some embodiments, different commands and / or configuration settings may be used to indicate how many UIs each OP bit of the mode register will be transmitted within.

[0043] although Figures 2A to 2E The assignment of a single group (e.g., Group A) is illustrated, but it should be understood that the techniques described herein can be applied to support other groups (e.g., Group B, Group C, etc.). Figures 2A to 2E The representation of certain mode registers (e.g., MR#1, MR#2, MR#3, etc.) in the WO 200800004 10 ...

[0044] Figure 3A is a device (e.g., Figure 1A1B and / or the apparatus illustrated in 1B). The example method 300 may correspond to the operation of a computing device or system, such as including an apparatus 100 (e.g., a DRAM) electrically coupled to an apparatus controller 102 (e.g., a memory controller). The apparatus controller 102 and the apparatus 100 may interact with each other in real time, such as during system initialization and / or actual use by an end user, to perform an MRR-ALL operation. The apparatus controller 102 and the apparatus 100 may use the MRR-ALL operation to transfer the contents of a multi-mode register of the apparatus (e.g., from the apparatus 100 to the apparatus controller 102). As described herein, a mode register may contain data characterizing a configuration of the apparatus 100, operating parameters of the apparatus, a state of the apparatus, etc.

[0045] At block 302, the device controller 102 may send an MRR-ALL command to the device 100. The device controller 102 may be configured to send the MRR-ALL command during operation of the corresponding system / environment. For example, the device controller 102 may be configured to read one or more mode registers of the device 100 at system power-up or corresponding system initialization to train the interface (e.g., CA / CS / CK) of the device. The MRR-ALL command sent by the device controller 102 may indicate the mode register group from which the mode register information is read. For example, one or more bits (e.g., CA bits) used to send the MRR-ALL command may be used to encode a group identifier and / or individual bits may be used to specify a particular group. In an embodiment in which the device 100 is coupled to a 14-bit CA interface (e.g., CA[13:0]), CA[13:11] may be used to indicate the group.

[0046] At block 304, the device 100 may determine the device configuration of the device in response to receiving the MRR-ALL command from the device controller 102. For example, the device may activate Figure 1B The device 100 may determine one or more aspects of the device configuration that are associated with how much data the device may send in response to the MRR-ALL command. For example, the device 100 may determine the die configuration of the device (e.g., how many DQs couple the device to the device controller 102) and the burst length of the device.

[0047] At block 306, the apparatus 100 may identify, based on the device configuration of the apparatus, a mode register belonging to the group indicated by the MRR-ALL command. For example, during the sending of the MRR-ALL command, one or more CA pins (e.g., Figure 3BCA11, CA12, and CA13 described in ) may be used to indicate a mode register group requested by the device controller 102. Each group defines one or more mode registers that are read in response to the MRR-ALL command. As described herein, the composition of each group (e.g., the number of mode registers associated with the group, and which mode registers are associated with the group) may depend on one or more aspects of the device configuration of the device 100 (e.g., the number of DQs and the burst length). In addition, how to transmit information from the mode register associated with the indicated group may depend on one or more aspects of the device configuration of the device 100. For example, which DQ to use to transmit the information of the mode register and during which UIs within the burst to transmit the information of the mode register may be determined by the device 100. The device 100 may determine which mode registers belong to a given group and how to transmit the information of the mode register based on the device configuration using one or more of dedicated logic, configurable logic, a lookup table, etc. For example, the apparatus 100 may include a lookup table configured to receive as input a group identifier and aspects of the device configuration, and provide as output the mode registers belonging to that group and how (e.g., during which UIs and over which DQs) the mode register information will be transmitted. Although described in the context of the apparatus 100, the apparatus controller 102 may include similar functionality (e.g., to determine which group requests to receive information from a desired mode register and / or to determine when mode register information is expected to be transmitted over a DQ). In an embodiment, not all mode registers of the apparatus 100 are associated with a group and / or some mode registers of the apparatus may be associated with more than one group. For example, in an apparatus 100 having 256 mode registers, only 64 mode registers (e.g., mode registers storing information used during training operations) may be associated with one or more groups that may be selected by the MRR-ALL command. During a training operation, a subset of the mode registers may be read instead of all mode registers.

[0048] At block 308, the device 100 may send mode register contents of one or more mode registers (e.g., OP0 to OP7) to the device controller 102 in response to the MRR-ALL command. As described herein, the device 100 may send the contents of one or more mode registers on the DQs within one or more UIs in a burst. For example, the device 100 may send the contents of a first mode register via DQ0 and the contents of a second mode register via DQ1 during a first UI (e.g., UI0 to UI7) of a burst, and then send the contents of a third mode register via DQ0 and the contents of a fourth mode register via DQ1 during a second UI (e.g., UI8 to UI15) of the burst. The mode registers to be read may be based on the group indication of the MRR-ALL command, based on which the device 100 may determine which mode registers belong to the group and how the mode register contents should be transferred (e.g., via which DQ and during which UIs) according to, for example, block 306. Since the mode register content is sent through several DQs, the device controller 102 can simultaneously receive mode register information of multiple mode registers in response to the MRR-ALL command.

[0049] At block 310, device controller 102 may determine a configuration setting and / or state of device 100 based on the mode register information received in response to the MRR-ALL command. For example, device controller 102 may determine a state of device 100 related to training.

[0050] At block 312, the device controller 102, the device 100, or a combination thereof may perform one or more operations based on the determined configuration settings and / or states. For example, the device controller 102 and / or the device 100 may adjust settings used during training.

[0051] although Figure 3A An embodiment of method 300 is described in which device 100 and / or device controller 102 uses mode register information read via the MRR-ALL command to perform training, but information read from the mode register may be used for other purposes of the memory system.

[0052] Figure 3Bis a diagram illustrating a command truth table 320 for an MRR-ALL command according to an embodiment of the present technology. The command truth table 320 illustrates that during a first cycle of the MRR-ALL command (e.g., when CS_n is L), CA5 to CA12 may be used to encode addresses of individual mode registers (MRA0 to MRA7). As described below, the individual mode register addresses may be used to identify the individual mode registers that are read when the MRR-ALL command is decoded as an MRR command. The command truth table 320 further illustrates that during a second cycle of the MRR-ALL command (e.g., when CS_n is H), CA11, CA12, and CA13 are used to indicate a group. Figure 3B In the embodiment illustrated in , each of CA11, CA12, and CA13 indicates an individual group, e.g., CA11 indicates Group A, CA12 indicates Group B, and CA13 indicates Group C. In embodiments where each CA pin indicates an individual group, zero or one pin may be asserted as a valid MRR-ALL command (e.g., multiple pins cannot be asserted to indicate multiple groups). In an embodiment (not shown), CA11 to CA13 may be used to store encoded group identifiers. Although only three CA pins associated with three mode register groups are shown for illustrative purposes, the current technology may include any number of mode register groups and be indicated by an encoded or decoded (e.g., zero-hot or one-hot) form. In an embodiment, if the MRR-ALL command indicates a valid group identifier during the second cycle (e.g., on CA11 to CA13), the mode register addresses (MRA0 to MRA7) of the first cycle are ignored. For example, if at the next stage (when CS_n goes H), the remainder of the decode indicates an MRR-ALL instruction rather than an MRR instruction (e.g., based on the presence of the GA, GB, and GC bits), then the MRA0 to MRA7 bits become "don't cares." In an embodiment, if the MRR-ALL command does not include a group identifier during the second cycle, then the command causes a read from the mode register associated with the mode register address information of the first cycle (e.g., as a regular MRR command).

[0053] Figure 4A is a device (eg, Figure 1A1B and / or the device illustrated in 1B). The example method 400 may correspond to the operation of a computing device or system, such as a device 100 (e.g., a DRAM) electrically coupled to a device controller 102 (e.g., a memory controller). The device controller 102 and the device 100 may interact with each other in real time, such as during system initialization and / or actual use by an end user, to perform MRW-ALL operations. The device controller 102 and the device 100 may use the MRW-ALL operations to store data in a multi-mode register of the device. As described herein, the mode register may contain data characterizing the configuration of the device 100, operating parameters of the device, the state of the device, etc.

[0054] At block 402, the device controller 102 may send a MRW-ALL command to the device 100. The device controller 102 may be configured to send the MRW-ALL command during operation of the corresponding system / environment. For example, the device controller 102 may be configured to write data into one or more mode registers of the device 100 to train the interface (e.g., CA / CS / CK) of the device at system power-on or corresponding system initialization. The MRW-ALL command sent by the device controller 102 may indicate a mode register group to which the mode register information is written. For example, one or more bits (e.g., CA bits) used to send the MRW-ALL command may be used to encode a group identifier and / or individual bits may be used to specify a specific group. In an embodiment in which the device 100 is coupled to a 14-bit CA interface (e.g., CA[13:0]), CA[13:11] may be used to indicate the group.

[0055] At block 404, the device 100 may determine the device configuration of the device in response to receiving the MRW-ALL command from the device controller 102. For example, the device may activate Figure 1B The device 100 may determine one or more aspects of the device configuration that are associated with how much data the device can write in response to the MRW-ALL command. For example, the device 100 may determine the die configuration of the device (e.g., how many DQs couple the device to the device controller 102) and the burst length of the device.

[0056] At block 406, the apparatus 100 may identify the mode registers belonging to the group indicated by the MRW-ALL command based on the device configuration of the apparatus. For example, during the sending of the MRW-ALL command, one or more CA pins (e.g., Figure 4BCA11, CA12, and CA13 described in ) may be used to indicate a mode register group indicated by the device controller 102. Each group defines one or more mode registers used to store data in response to the MRW-ALL command. As described herein, the composition of each group (e.g., the number of mode registers associated with the group, and which mode registers are associated with the group) may depend on one or more aspects of the device configuration of the device 100 (e.g., the number of DQs and the burst length). In addition, how information is stored on the mode register associated with the indicated group may depend on one or more aspects of the device configuration of the device 100. For example, which DQ is used to write information about the mode register and which UIs within the burst during which the information about the mode register is written may be determined by the device 100. The device 100 may determine which mode registers belong to a given group and how to store information about the mode registers based on the device configuration using one or more of dedicated logic, configurable logic, a lookup table, etc. For example, the apparatus 100 may include a lookup table configured to receive as input a group identifier and aspects of the device configuration, and provide as output the mode registers belonging to that group and how the mode register information will be stored (e.g., through which DQs during which UIs). Although described in the context of the apparatus 100, the apparatus controller 102 may include similar functionality (e.g., to determine which group requests that information be written to a desired mode register and / or to determine when mode register information is expected to be stored through a DQ). In an embodiment, not all mode registers of the apparatus 100 are associated with a group and / or some mode registers of the apparatus may be associated with more than one group. For example, in an apparatus 100 having 256 mode registers, only 64 mode registers (e.g., mode registers that store information used during training operations) may be associated with one or more groups that may be selected by the MRR-ALL command. During a training operation, a subset of the mode registers may be written instead of all mode registers.

[0057] At block 408, the device controller 102 may send information to be written to the mode registers via the DQs. As described above, the device controller 102 and / or the device 100 may determine (e.g., at block 406) which DQ will be used to transmit write data for each mode register in the indicated group, and at which UIs within the burst the write data will be transmitted via the DQs.

[0058] At block 410, the device 100 may write the mode register contents (e.g., OP0 to OP7) to one or more mode registers in response to the MRW-ALL command. As described herein, the device 100 may store data to the one or more mode registers on the DQs at one or more UIs in a burst. For example, the device 100 may write data to a first mode register via DQ0 during a first UI (e.g., UI0 to UI7) of a burst, and to a second mode register via DQ1, and then write data to a third mode register via DQ0 during a second UI (e.g., UI8 to UI15) of the burst, and to a fourth mode register via DQ1. The device 100 may write data to the mode registers based on the group indication of the MRW-ALL command, based on which the device 100 may determine which mode registers belong to a group and how (e.g., via which DQ and during which UIs) to store the data to the mode registers according to, for example, block 404. Since the mode registers are received via several DQs, the device 100 may store the mode register information from each DQ simultaneously. To store the mode register information in the designated group, the device controller 102 may mark the associated CA pin as "high" when the MRW-ALL command is issued.

[0059] At block 412 , the device 100 may send a confirmation message to the device controller 102 to confirm that the MRW-ALL command was executed and the associated mode register information was stored.

[0060] At block 414, the device controller 102 may determine a configuration setting and / or state of the device 100 based on the mode register information stored in response to the MRW-ALL command. For example, the device controller 102 may determine a state of the device 100 related to training.

[0061] At block 416, the device controller 102, the device 100, or a combination thereof may perform one or more operations based on the determined configuration settings and / or states. For example, the device controller 102 and / or the device 100 may adjust settings used during training. After executing the MRW-ALL command, the device controller 102, the device 100, or a combination thereof may perform high-speed operations before or after completing training (e.g., CA / CS / CK training, write leveling, write training, etc.) since the MRW-ALL command used DQ operations.

[0062] although Figure 4A An embodiment of method 400 is described in which device 100 and / or device controller 102 performs training using mode register information written via the MRW-ALL command, but information written to the mode register may be used for other purposes of the memory system.

[0063] Figure 4B is a diagram illustrating an instruction truth table 420 for an MRW-ALL instruction according to an embodiment of the present technology. The command truth table 420 illustrates that during the first cycle of the MRW-ALL command (e.g., when CS_n is L), CA5 to CA12 may be used to encode the addresses of individual mode registers (MRA0 to MRA7). As described below, the individual mode register addresses may be used to identify the individual mode registers that are read when the MRW-ALL command is decoded as a MRW command. The command truth table 420 further illustrates that during the second cycle of the MRW-ALL command (e.g., when CS_n is H), CA11, CA12, and CA13 are used to indicate a group. Figure 4B In the embodiment illustrated in , each of CA11, CA12, and CA13 indicates an individual group, e.g., CA11 indicates Group A, CA12 indicates Group B, and CA13 indicates Group C. In embodiments where each CA pin indicates an individual group, zero or one pin may be asserted as a valid MRW-ALL command (e.g., multiple pins cannot be asserted to indicate multiple groups). In an embodiment (not shown), CA11 to CA13 may be used to store encoded group identifiers. Although only three CA pins associated with three mode register groups are shown for illustrative purposes, the current technology may include any number of mode register groups and be indicated by an encoded or decoded (e.g., zero-hot or one-hot) form. In an embodiment, if the MRW-ALL command does not include a group identifier during the second cycle, then in response to the command, the device 100 may write the data provided on CA0 to CA7 during the second cycle (OP0 to OP7) of the command to the specific mode register identified on CA5 to CA13 during the first cycle (MRA0 to MRA7) of the command; that is, the device may treat the command as a regular MRW command. In an embodiment, if the MRW-ALL command indicates a valid group identifier during the second cycle (e.g., the command will be treated as MRW-ALL), then OP0 to OP7 and MRA0 to MRA7 on the corresponding CA bits may be ignored and the write data of the mode register is transmitted over the DQ instead as described herein. For example, if at the next stage (when CS_n becomes H), the remainder of the decode indicates a MRW-ALL instruction instead of a MRW instruction (e.g., based on the presence of the GA, GB, and GC bits), then the MRA0 to MRA7 bits become "don't care".

[0064] Figure 4C4 is a timing diagram 440 illustrating the timing of the MRW-ALL instruction according to an embodiment of the present technology. The timing diagram 440 illustrates that for the MRW-ALL command, the host can use different DQs during multiple UIs of a burst to transmit data being written to multiple mode registers. For example, DQ0 is used to send data within a burst of 16 UIs (8 UIs for mode register A and 8 UIs for mode register B), DQ1 is used to send data within a burst of 16 UIs (8 UIs for mode register C and 8 UIs for mode register D), DQ2 is used to send data within a burst of 16 UIs (8 UIs for mode register E and 8 UIs for mode register F), and DQ3 is used to send data within a burst of 16 UIs (8 UIs for mode register G and 8 UIs for mode register H).

[0065] Figure 4D 4 is a timing diagram 450 illustrating back-to-back mode register write all commands according to an embodiment of the present technology. The timing diagram 450 illustrates an example of back-to-back timing of two MRW-ALL commands. The timing gap between the MRW-ALL commands is equal to half the burst length multiplied by the clock period (e.g., tCK). In a first example, for a burst length of 32, the timing gap between the MRW-ALL commands is 16*tCK. In a second example, for a burst length of 16, the timing gap between the MRW-ALL commands is 8*tCK.

[0066] Figure 5 is a schematic diagram of a system including an apparatus according to an embodiment of the present technology. Figures 1A to 4D Any of the foregoing apparatus (eg, memory devices) described may be incorporated into any of a myriad of larger and / or more complex systems, a representative example of which is Figure 5 580 is schematically shown in FIG. 580. The system 580 may include a memory device 500, a power supply 582, a driver 584, a processor 586, and / or other subsystems or components 588. The memory device 500 may include the same Figures 1A to 4D The features of the described apparatus are generally similar features, and thus may include various features for performing direct read requests from a host device. The resulting system 580 may perform any of a variety of functions, such as memory storage, data processing, and / or other suitable functions. Thus, representative systems 580 may include, but are not limited to, handheld devices (e.g., mobile phones, tablet computers, digital readers, and digital audio players), computers, vehicles, appliances, and other products. The components of system 580 may be housed in a single unit or distributed over multiple interconnected units (e.g., via a communication network). Components of system 580 may also include any of a variety of remote devices and computer-readable media.

[0067] It will be appreciated from the foregoing that specific embodiments of the present technology have been described herein for illustrative purposes, but various modifications may be made without departing from the present disclosure. Additionally, certain aspects of the new technology described in the context of a particular embodiment may also be combined or eliminated in other embodiments. Furthermore, although the advantages associated with certain embodiments of the new technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages and not all embodiments necessarily exhibit such advantages to fall within the scope of the present technology. Therefore, the present disclosure and associated technology may encompass other embodiments not explicitly shown or described herein.

[0068] In the illustrated embodiments above, the apparatus has been described in the context of a DRAM device. However, in addition to or in lieu of a DRAM device, an apparatus configured according to other embodiments of the present technology may also include other types of suitable storage media, such as devices incorporating NAND-based or NOR-based non-volatile storage media (e.g., NAND flash memory), magnetic storage media, phase-change storage media, ferroelectric storage media, etc.

[0069] As used herein, the term "processing" includes manipulating signals and data, such as writing or programming, reading, erasing, refreshing, adjusting or changing values, calculating results, executing instructions, assembling, transmitting and / or manipulating data structures. The term "data structure" includes information arranged as bits, words or codewords, blocks, files, input data, system-generated data (e.g., calculated or generated data), and program data. In addition, the term "dynamic" as used herein describes a process, function, action, or implementation that occurs during operation, use, or deployment of a corresponding device, system, or embodiment and after or while running manufacturer or third-party firmware. A process, function, action, or implementation that occurs dynamically may occur after design, manufacturing, and initial testing, setup, or configuration.

[0070] The above embodiments are described in sufficient detail to enable those skilled in the art to make and use the embodiments. However, those skilled in the relevant art will appreciate that the present technology may have additional embodiments and may be used without the above reference. Figures 1A to 5 The present technology is practiced without the use of several details of the described embodiments.

Claims

1. A device comprising: an input / output circuit configured to communicate with an external controller, wherein the input / output circuit includes a command / address CA interface and a data DQ interface; and a mode register circuit coupled to the input / output circuit and configured to: Decoding a command from the external controller on the CA interface, wherein the command includes a mode register read all (MRR-ALL) command or a mode register write all (MRW-ALL) command; Determining a die configuration and a burst length for executing the MRR-ALL command or the MRW-ALL command; and determining at least one mode register group identified in the MRR-ALL command or the MRW-ALL command, wherein the input / output circuit is configured to: Mode register information associated with the at least one mode register group identified in the MRR-ALL command is sent to the external controller through the DQ interface.

2. The apparatus of claim 1, wherein the DQ interface comprises at least four DQs, and wherein sending the mode register information through the DQ interface comprises sending information of at least four mode registers through the at least four DQs.

3. The apparatus of claim 1, wherein the at least one mode register group includes a number of mode registers based on the determined die configuration and the burst length. 4 . The apparatus of claim 1 , wherein the determination of the at least one mode register group is based on at least one group identifier received in association with the MRR-ALL command or the MRW-ALL command through the CA interface.

5. The apparatus of claim 1, wherein the DQ interface comprises a plurality of DQs, and wherein each of the plurality of DQs sends different mode register information according to the burst length.

6. The apparatus of claim 1, wherein the DQ interface comprises a number of DQs, and wherein each of the DQs has a double unit interval of a burst length comprising 16.

7. The device of claim 1, wherein the device is a dynamic random access memory (DRAM) coupled to the external controller.

8. A memory system comprising: Memory controller; and a memory array operably coupled to the memory controller and configured to: Decoding a command from the memory controller, wherein the command includes a mode register read all (MRR-ALL) command or a mode register write all (MRW-ALL) command; Determining a die configuration and a burst length for executing the MRR-ALL command or the MRW-ALL command; determining at least one mode register group identified in the MRR-ALL command or the MRW-ALL command; and Mode register information associated with the at least one mode register group identified in the MRR-ALL command is sent to the memory controller.

9. The memory system of claim 8, wherein the memory array comprises at least four DQs, and wherein sending the mode register information comprises sending information of at least four mode registers through the at least four DQs.

10. The memory system of claim 8, wherein the at least one mode register group includes a number of mode registers based on the determined die configuration and the burst length.

11. The memory system of claim 8, wherein the determination of the at least one mode register group is based on at least one group identifier received in association with the MRR-ALL command or the MRW-ALL command.

12. The memory system of claim 8, wherein the memory array comprises a plurality of DQs, and wherein each of the plurality of DQs sends different mode register information according to the burst length.

13. The memory system of claim 8, wherein the memory array comprises a number of DQs, and wherein each of the DQs has a double unit interval of a burst length comprising 16.

14. The memory system of claim 8, wherein the memory array is a dynamic random access memory (DRAM).

15. A method of operating a device, the method comprising: Decoding a command from an external controller, wherein the command includes a mode register read all (MRR-ALL) command or a mode register write all (MRW-ALL) command; Determining a die configuration and a burst length for executing the MRR-ALL command or the MRW-ALL command; determining at least one mode register group identified in the MRR-ALL command or the MRW-ALL command; and Mode register information associated with the at least one mode register group identified in the MRR-ALL command is sent to the external controller. 16 . The method of claim 15 , wherein the device comprises at least four DQs, and wherein sending the mode register information comprises sending information of at least four mode registers through the at least four DQs.

17. The method of claim 15, wherein the at least one mode register group includes a number of mode registers based on the determined die configuration and the burst length.

18. The method of claim 15, wherein the determination of the at least one mode register group is based on at least one group identifier received in association with the MRR-ALL command or the MRW-ALL command.

19. The method of claim 15, wherein the device comprises a plurality of DQs, and wherein each of the plurality of DQs sends different mode register information according to the burst length.

20. The method of claim 15, wherein the apparatus comprises a number of DQs, and wherein each of the DQs has a double unit interval of a burst length comprising 16.

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