Data processing method and device, storage equipment and medium

Abstract

The invention relates to the technical field of storage devices, in particular to a data processing method and device, a storage device and a medium. The method comprises the steps of querying a first logic physical address mapping table based on an access command for a target logic address to obtain a first physical block mapped by the target logic address; wherein the first logic physical address mapping table is cached in a memory in a first time period; the first time period is from a first time point to a second time point; the first time point is when the first physical block is returned to an idle pool after being subjected to data recovery; the second time point is after the first physical block is redistributed in the idle pool and before the stored first data is erased; and reading the first data from the first physical block. Therefore, the problem of poor performance of the storage device due to the fact that the logic physical address mapping table is stored in the flash memory by the existing storage device can be effectively solved.

Description

Technical Field

[0001] The present application relates to the technical field of storage devices, and in particular to a data processing method, apparatus, storage device and medium. Background Art

[0002] Storage device management needs to manage the mapping relationship between the logical address (Logical Block Addressing, abbreviated as LBA) and the physical address (Physical Block Addressing, abbreviated as PBA) of its internal NAND (non-volatile memory). The mapping relationship between an LBA address and a PBA address occupies 4 bytes of memory. Due to the limited memory space of the storage device, only part of the mapping table (logical-physical address mapping table) can be stored in the memory, and the rest of the mapping table can only be stored in the NAND. Among them, the mapping Table (logical-physical address mapping table) is a data structure used to store the correspondence between logical addresses and physical addresses. However, it takes a long time to access the mapping table to the NAND, resulting in poor performance of the storage device and slow data processing. Summary of the invention

[0003] In view of this, the embodiments of the present application provide a data processing method, apparatus, storage device and medium, which can effectively solve the problem of poor storage device performance caused by storing the logical-physical address mapping table in flash memory in existing storage devices.

[0004] In a first aspect, an embodiment of the present application provides a data processing method, including:

[0005] Based on the access command to the target logical address, query the first logical-physical address mapping table to obtain the first physical block mapped to the target logical address;

[0006] The first logical-physical address mapping table is cached in the memory in a first time period; the first time period is from a first time point to a second time point; the first time point is when the first physical block is returned to the free pool after data is recycled; the second time point is when the first physical block is reallocated in the free pool again and before the first data stored therein is erased;

[0007] The first data is read from the first physical block.

[0008] In some embodiments, the method further comprises:

[0009] After the first physical block is reallocated from the free pool, in response to erasing the first data in the first physical block, the first mapping information in the first logical-physical address mapping table is deleted; the first mapping information is the address mapping relationship between the target logical address and the first physical block.

[0010] In some embodiments, the method further comprises:

[0011] After the first data stored in the first physical block is recovered to the second physical block, second mapping information is added to the first logical-physical address mapping table in the memory; the second mapping information is the address mapping relationship between the target logical address and the second physical block.

[0012] In some embodiments, the method further comprises:

[0013] After the first mapping information is deleted, determining the second mapping information based on the target logical address;

[0014] A second physical block mapped to the target logical address is determined according to the second mapping information to read the first data from the second physical block.

[0015] In some embodiments, a second logical-physical address mapping table is stored in the flash memory;

[0016] The method further includes: storing the address mapping information in the first logical-physical address mapping table into the second logical-physical address mapping table according to a scheduled task and / or before power-off.

[0017] In some embodiments, the method further comprises:

[0018] If the first physical block is not determined in the first logical-physical address mapping table stored in the memory according to the target logical address based on the access command, the second logical-physical address mapping table in the flash memory is queried to determine the physical block mapped by the target logical address.

[0019] In some embodiments, the method further includes: when the length of the continuous logical address corresponding to the data to be written in the access command exceeds a preset threshold, storing the first address of the continuous logical address and the length of the continuous logical address in the first logical-physical address mapping table.

[0020] In a second aspect, an embodiment of the present application provides a data processing device, which is applicable to a storage device, wherein the storage device includes a control unit, a memory, and a flash memory, and the device includes:

[0021] A physical block determination module, configured to query a first logical-physical address mapping table based on an access command to a target logical address, and obtain a first physical block mapped to the target logical address;

[0022] The first logical-physical address mapping table is cached in the memory in a first time period; the first time period is from a first time point to a second time point; the first time point is when the first physical block is returned to the free pool after data is recycled; the second time point is when the first physical block is reallocated in the free pool again and before the first data stored therein is erased;

[0023] A data reading module is used to read the first data from the first physical block.

[0024] In a third aspect, an embodiment of the present application provides a storage device, the storage device comprising a control unit, a memory and a flash memory;

[0025] The control unit is used to implement a data processing method provided in the first aspect of the present application.

[0026] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium storing a computer program. When the computer program is executed on a processor, it implements a data processing method provided according to the first aspect of the present application.

[0027] The embodiments of the present application have the following beneficial effects:

[0028] The present application determines a first physical block in a first logical-physical address mapping table stored in the memory according to the target logical address, based on an access command to the target logical address within a first time period; wherein the first time period is from the time when the first physical block mapped by the target logical address is data-reclaimed, so that the first physical block returns to a free pool, to the time when the first physical block is allocated again to erase the first data stored therein; and reads the first data in the first physical block. In the prior art, the address mapping information between the target logical address and the first physical block is deleted when data is recycled, resulting in the inability to continue to use it subsequently, and the address mapping information after the data is moved must be read from the flash memory. The present application reduces the number of times the address mapping information is read from the flash memory. Therefore. The present application can effectively solve the problem of poor performance of existing storage devices due to storing the logical-physical address mapping table in the flash memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0030] Figure 1 A structural block diagram of a storage device according to an embodiment of the present application is shown;

[0031] Figure 2 A flow chart showing a data processing method according to an embodiment of the present application is shown;

[0032] Figure 3 Another flow chart of the data processing method according to the embodiment of the present application is shown;

[0033] Figure 4 A structural schematic diagram of a data processing device according to an embodiment of the present application is shown.

[0034] Description of main component symbols:

[0035] 100 - storage device; 110 - control unit; 120 - memory; 130 - flash memory; 410 - physical block determination module; 420 - data reading module. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0037] The components of the embodiments of the present application generally described and shown in the drawings herein may be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0038] Hereinafter, the terms "including", "having" and their cognates that can be used in various embodiments of the present application are intended only to indicate specific features, numbers, steps, operations, elements, components or a combination of the foregoing items, and should not be understood as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or a combination of the foregoing items or increasing the possibility of one or more features, numbers, steps, operations, elements, components or a combination of the foregoing items. In addition, the terms "first", "second", "third" and the like are only used to distinguish descriptions and cannot be understood as indicating or implying relative importance.

[0039] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meanings as those generally understood by those skilled in the art to which the various embodiments of the present application belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meanings as the contextual meanings in the relevant technical field and will not be interpreted as having idealized meanings or overly formal meanings unless clearly defined in the various embodiments of the present application.

[0040] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0041] In disk storage, in order to improve data read and write efficiency and facilitate management, the disk is divided into multiple fixed-size areas, each of which is called a "physical block". The size of a physical block is usually predefined, such as 512 bytes, 1KB, 4KB, etc.

[0042] Each physical block has its own unique physical address, which is relative to the entire disk and is used to identify the location of the block on the disk, that is, the physical address refers to the exact location of each block on the disk. For example, for traditional disk storage, the physical address can be determined by the cylinder number (Cylinder), head number (Head) and sector number (Sector), that is, the CHS addressing mode. Modern hard disks use more logical block addressing (LBA, Logical Block Addressing) to indicate the location of each block by a global number. In order to facilitate the management of each physical block, it is necessary to periodically recover the data in the physical block and move it to other free physical blocks.

[0043] In the prior art, when the storage device needs to recycle data, the data corresponding to LBA1 is moved from the physical block A pointed to by the old physical address PBA1 to the physical block B corresponding to the new physical address PBA2, and the mapping relationship of LBA1=>PBA1 (logical address 1 points to physical address 2) in the logical-physical address mapping table is deleted. In other words, the mapping relationship in the mapping table is deleted when the data is recycled. After the data is recycled, the physical block A corresponding to PBA1 returns to the free block pool and waits to be allocated and used again. Among them, the free block pool refers to a collection of unused storage space that can be used for allocation in the storage device. This mechanism is mainly used to manage storage resources and ensure that data is efficiently allocated to available storage space.

[0044] However, currently in the art, when applying for a new free block (free physical block) from the free block pool, the data in the free block will be erased when starting to write data to the free block. The inventor has found through research that the original data in the physical block A is still valid from the time the physical block A returns to the free block pool to the time it is erased before data is written after being allocated again. The original data in the physical block A is not fully utilized. If the mapping (the mapping relationship from the logical address to the physical address) is stored in the physical block A, the validity time of the mapping is short.

[0045] Therefore, the present application provides a data processing method, apparatus, storage device and medium to extend the effective time of mapping in the storage device memory, reduce the read interaction with NAND, and reduce the time spent on retrieving mapping, thereby effectively solving the problem of poor storage device performance caused by storing the logical-physical address mapping table in NAND in existing storage devices.

[0046] In the prior art, when searching for a mapping, the mapping table part stored in the memory is first retrieved. If the mapping cannot be retrieved in the memory, the mapping table part on the NAND is retrieved. If the mapping on the memory is pointed to as invalid, the mapping cannot be read from the memory and can only be read from the NAND. This application extends the validity period of the mapping in the memory of the storage device, and the mapping can still be read from the memory, thereby reducing the read interaction with the NAND.

[0047] Figure 1 A structural block diagram of a storage device of an embodiment of the present application is shown. Exemplarily, the storage device 100 includes: a control unit 110, a memory 120 and a flash memory 130. The memory is used to cache data of the storage device. The storage device 100 may include a main control unit and a storage chip. The storage chip includes a memory and a flash memory (NAND).

[0048] Exemplarily, the program corresponding to the data processing method of the embodiment of the present application is stored in a storage component outside the storage device, and the program is loaded into the control unit 110 before reading and writing data to the storage device 100 or after the storage device 100 is started.

[0049] The control unit 110 is used to implement the data processing method of the embodiment of the present application. The data processing method is described below in conjunction with some specific embodiments.

[0050] Figure 2 A flow chart of a data processing method according to an embodiment of the present application is shown. Exemplarily, the data processing method includes the following steps:

[0051] S110, based on an access command to a target logical address, query a first logical-physical address mapping table to obtain a first physical block mapped to the target logical address.

[0052] Among them, the first logical-physical address mapping table is cached in the memory during a first time period; the first time period is from a first time point to a second time point; the first time point is when the first physical block is returned to the free pool after data is recycled; the second time point is after the first physical block is reallocated in the free pool and before the stored first data is erased.

[0053] Exemplarily, after the data in the first physical block is recycled to other physical blocks, the first physical block returns to the free pool to wait to be allocated to other logical addresses for use again.

[0054] Furthermore, the method further comprises:

[0055] After the first physical block is reallocated from the free pool, in response to erasing the first data in the first physical block, the first mapping information in the first logical-physical address mapping table is deleted; the first mapping information is the address mapping relationship between the target logical address and the first physical block.

[0056] After the first physical block is allocated to other logical addresses, before writing data to the first physical block, the first data stored in the first physical block needs to be erased. Therefore, from the time of being in the free pool to before being erased, the first data stored in the first physical block is still valid.

[0057] The first logical-physical address mapping table stores address mapping relationships between respective logical addresses and respectively mapped physical blocks.

[0058] The method further includes: before the first time period, when the first physical block is assigned to the target logical address, adding first mapping information to the first logical-physical address mapping table. The first mapping information is the address mapping relationship between the target logical address and the first physical block. The first mapping information is retained when the first physical block is erased.

[0059] S120, reading first data from the first physical block to reduce the number of times address mapping information is read from the flash memory.

[0060] It is understandable that after the first data stored in the first physical block is recycled to the second physical block, the second mapping information needs to be added to the first logical-physical address mapping table in the memory 120 to ensure that the target logical address can be accessed subsequently to obtain the first data. The second mapping information is the address mapping relationship between the target logical address and the second physical block.

[0061] Furthermore, the method further comprises:

[0062] After the first mapping information is deleted, determining second mapping information based on the target logical address;

[0063] A second physical block mapped to the target logical address is determined according to the second mapping information to read the first data from the second physical block.

[0064] Furthermore, a second logical-physical address mapping table is stored in the flash memory 130. The second logical-physical address mapping table also stores the address mapping relationship between each logical address and the respectively mapped physical block.

[0065] The method further includes: storing the address mapping information in the first logical-physical address mapping table into the second logical-physical address mapping table according to a scheduled task or before power-off.

[0066] Generally, the size of the memory 120 of the storage device 100 is only a few KB, and the mapping table (logical-physical address mapping table) part is only cached in the memory 120 and saved when there is power. After power failure, the mapping table part in the memory 120 will be lost, so it is necessary to store the mapping table part in the memory 120 into the flash memory 130 regularly and before powering off.

[0067] For example, a mapping (address mapping relationship) of an LBA address => PBA address occupies 4 bytes of memory. Due to the limited memory space of the storage device, only part of the mapping table (logical-physical address mapping table) can be stored in the memory 120, and the rest of the logical-physical address mapping table is stored in the nand.

[0068] Therefore, in the embodiment of the present application, the duration of the address mapping information in the logical-physical address mapping table is extended to ensure that the first logical-physical address mapping table stored in the memory 120 determines the first physical block of the target logical address mapping, thereby avoiding the burden of querying the second logical-physical address mapping table in the flash memory 130.

[0069] In one embodiment, because the first mapping information is stored in the first logical-physical address mapping table in the memory 120, after the first data stored in the first physical block is recovered to the second physical block, the second mapping information is directly added to the second logical-physical address mapping table in the flash memory 130 to reduce the occupancy of the memory 120.

[0070] It can be understood that if the first physical block is not determined in the first logical-physical address mapping table stored in the memory 120 according to the target logical address based on the access command, the second logical-physical address mapping table in the flash memory 130 is queried to determine the physical block mapped by the target logical address.

[0071] Furthermore, in order to reduce the storage amount of address mapping information, the method further includes: when the length of the continuous logical address corresponding to the data to be written in the access command exceeds a preset threshold, storing the first address of the continuous logical address and the length of the continuous logical address in the first logical-physical address mapping table. <ex>When LBA1024~LBA2047, the address mapping information in the memory 120 only records the first logical address: LBA1024, and the logical address length: 1024, a total of 4 bytes + 4 bytes.

[0072] The data processing method of the present application is introduced below with an example. Figure 3 As shown, the following steps are included:

[0073] S210, allocate a first physical block from the free pool for the target logical address to store the first data. Record the first mapping information in the first logical-physical address mapping table in the memory 120. The first mapping information is the address mapping relationship between the target logical address and the first physical block. For example, if the target logical address is LBA 0x00000400, the first physical block is blockA corresponding to PBA10x00001000, and the first mapping information is <ex>LBA=>PBA1LBA 0x00000400=>PBA10x00001000.

[0074] S220, when the storage device 100 performs data recycling, the first data corresponding to LBA 0x00000400 is moved from block A corresponding to the old address PBA1 0x00001000 to the second physical block block B corresponding to PBA2 0x10001000. The first physical block block A returns to the free pool to wait for re-allocation. At this time, the first mapping information LBA=>PBA1 recorded in the first logical-physical address mapping table is not deleted.

[0075] S230, record the second mapping information in the first logical-physical address mapping table in the memory 120, the second mapping information is <ex>LBA=>PBA2 LBA 0x00000400=>PBA20x10001000.

[0076] S240, applying for a free first physical block blockA from the free pool. Before writing data to the free first physical block blockA, it is necessary to erase the first data in the first physical block blockA. At the same time, the first mapping information recorded in the first logical-physical address mapping table is deleted. If the first mapping information is written to the flash memory 130, the first mapping information in the flash memory 130 is deleted.

[0077] S250, during the time period from when the first physical block blockA returns to the free pool to when the first data is erased, if an access command to access the target logical address is received, the first mapping information is recorded in the first logical-physical address mapping table, the first physical block blockA mapped to the target logical address is determined, and the first data is read from the first physical block blockA.

[0078] After data recovery, although LBA 0x00000400 has changed from block A corresponding to the old address PBA10x00001000 to block B corresponding to PBA2 0x10001000, this transfer is not caused by the host writing new data, but by the storage recovering data, so the data on the old address PBA 0x00001000 and the new address PBA 0x10001000 are exactly the same, both are the first data.

[0079] It can be seen that the memory 120 stores the first mapping information <ex>LBA=>PBA1 LBA 0x00000400=>PBA10x00001000 can still read the first data. After block A returns to the free pool, it can be allocated. Generally, block A may stay in the free pool for a period of time before being allocated. Therefore, the validity of the mapping is extended.

[0080] The changes in the physical blocks mapped to the target logical address, the data stored in the physical blocks, and the changes in the mapping table are shown in Tables 1 and 2.

[0081] Table 1 Target logical address and mapped physical block

[0082]

[0083] Table 2 mapping table information

[0084]

[0085] S260 , if the first physical block blockA of the target logical address mapping is not found in the first logical-physical address mapping table, the second physical block block B of the target logical address mapping is found in the flash memory 130 to read the first data from the second physical block block B.

[0086] The present application does not delete the mapping relationship between the physical block and the logical address when recovering data. When erasing the data of the physical block, the mapping relationship is deleted, thereby extending the validity of the mapping table in the memory 120, thereby reducing the number of times the mapping table is accessed from the NAND, thereby improving the performance of the storage device 100.

[0087] Figure 4 A schematic diagram of the structure of a data processing device according to an embodiment of the present application is shown. Exemplarily, the data processing device includes: a physical block determination module 410 and a data reading module 420.

[0088] The physical block determination module 410 is used to query the first logical-physical address mapping table based on an access command to the target logical address, and obtain the first physical block mapped to the target logical address.

[0089] Among them, the first logical-physical address mapping table is cached in the memory during a first time period; the first time period is from a first time point to a second time point; the first time point is when the first physical block is returned to the free pool after data is recycled; the second time point is after the first physical block is reallocated in the free pool and before the stored first data is erased.

[0090] The data reading module 420 is used to read the first data from the first physical block to reduce the number of times of reading the address mapping information from the flash memory.

[0091] It can be understood that the device of this embodiment corresponds to the data processing method of the above embodiment, and the options in the above embodiment are also applicable to this embodiment, so they will not be described repeatedly here.

[0092] The present application also provides a terminal device. Exemplarily, the terminal device includes a processor and a memory, wherein the memory stores a computer program, and the processor runs the computer program, thereby enabling the terminal device to execute the functions of each module in the above-mentioned data processing method or the above-mentioned data processing device.

[0093] Among them, the processor can be an integrated circuit chip with signal processing capabilities. The processor can be a general-purpose processor, including a central processing unit (CPU), a graphics processing unit (GPU) and a network processor (NP), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or at least one of other programmable logic devices, discrete gates or transistor logic devices, and discrete hardware components. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc., which can implement or execute the disclosed methods, steps and logic block diagrams in the embodiments of the present application.

[0094] The memory may be, but is not limited to, a random access memory (RAM), a read only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc. Among them, the memory is used to store a computer program, and the processor can execute the computer program accordingly after receiving an execution instruction.

[0095] The present application also provides a computer-readable storage medium for storing a computer program used in the above-mentioned terminal device. For example, the computer-readable storage medium may include, but is not limited to, various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0096] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and structure diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in an alternative implementation, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the structure diagram and / or the flow diagram, and the combination of boxes in the structure diagram and / or the flow diagram, can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0097] In addition, the functional modules or units in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0098] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a smart phone, a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the various embodiments of the present application.

[0099] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.< / ex> < / ex> < / ex> < / ex>

Claims

1. A data processing method, characterized in that: include: Based on the access command to the target logical address, query the first logical-physical address mapping table to obtain the first physical block mapped to the target logical address; The first logical-physical address mapping table is cached in the memory in a first time period; the first time period is from a first time point to a second time point; the first time point is when the first physical block is returned to the free pool after data is recycled; the second time point is when the first physical block is reallocated in the free pool again and before the first data stored therein is erased; The first data is read from the first physical block.

2. The data processing method according to claim 1, characterized in that: The method further comprises: After the first physical block is reallocated from the free pool, in response to erasing the first data in the first physical block, the first mapping information in the first logical-physical address mapping table is deleted; the first mapping information is the address mapping relationship between the target logical address and the first physical block.

3. The data processing method according to claim 2, characterized in that: The method further comprises: After the first data stored in the first physical block is recovered to the second physical block, second mapping information is added to the first logical-physical address mapping table in the memory; the second mapping information is the address mapping relationship between the target logical address and the second physical block.

4. The data processing method according to claim 3, characterized in that: The method further comprises: After the first mapping information is deleted, determining the second mapping information based on the target logical address; A second physical block mapped to the target logical address is determined according to the second mapping information to read the first data from the second physical block.

5. The data processing method according to claim 1, characterized in that: A second logical-physical address mapping table is stored in the flash memory; the method further includes: According to a scheduled task and / or before power-off, the address mapping information in the first logical-physical address mapping table is stored in the second logical-physical address mapping table.

6. The data processing method according to claim 5, characterized in that: The method further comprises: If the first physical block is not determined in the first logical-physical address mapping table stored in the memory according to the target logical address based on the access command, the second logical-physical address mapping table in the flash memory is queried to determine the physical block mapped by the target logical address.

7. The data processing method according to claims 1 to 6, characterized in that: The method further comprises: When the length of the continuous logical address corresponding to the data to be written in the access command exceeds a preset threshold, the first address of the continuous logical address and the length of the continuous logical address are stored in the first logical-physical address mapping table.

8. A data processing device, characterized in that: Applicable to a storage device, the storage device includes a control unit, a memory and a flash memory, and the device includes: A physical block determination module, configured to query a first logical-physical address mapping table based on an access command to a target logical address, and obtain a first physical block mapped to the target logical address; The first logical-physical address mapping table is cached in the memory in a first time period; the first time period is from a first time point to a second time point; the first time point is when the first physical block is returned to the free pool after data is recycled; the second time point is when the first physical block is reallocated in the free pool again and before the first data stored therein is erased; A data reading module is used to read the first data from the first physical block.

9. A storage device, characterized in that: The storage device includes a control unit, a memory and a flash memory; the control unit is used to implement the data processing method described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that: The computer program stores a computer program, which, when executed on a processor, implements the data processing method according to any one of claims 1 to 7.

Images