Data reading method and memory controller

Abstract

The invention provides a data reading method and a memory controller thereof, which are suitable for a storage device with a rewritable nonvolatile memory module. The method comprises the following steps: executing a reading operation on a target physical page to obtain target data containing multiple pieces of bit page data; when the error bit number of the target bit page data exceeds a preset threshold value, obtaining a target voltage gear table corresponding to the bit page type, and selecting a current gear sequence number according to the sequence of the gear sequence numbers in the table to execute iterative rereading; and if the error bit number after rereading does not exceed the preset threshold value, acquiring original data and updating the target voltage gear table based on the current gear sequence number. According to the method, the sequence of the voltage gear table is maintained, and the voltage gear group with high rereading success rate is preferentially used, so that the trying times of rereading operation can be effectively reduced, and the rereading efficiency of the flash memory is improved.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a data reading method and a memory controller thereof for improving the rereading efficiency of a rewritable non-volatile memory (Non-volatile Memory). Background Art

[0002] NAND flash memory is a non-volatile memory that can retain data after power failure. It has the advantages of data non-volatility, power saving, small size and no mechanical structure, and is widely used in various electronic devices.

[0003] Due to the inherent characteristics of NAND flash memory, each page of data is usually divided into multiple Error Correction Code (ECC) blocks. When writing, each ECC block performs error detection and correction coding so that the corresponding ECC decoding can be performed when reading to ensure the integrity of the data.

[0004] As NAND flash memory is used, the storage cells will gradually wear out, resulting in an increase in the number of error bits. To ensure data reliability, user data must be protected by ECC so that even if some bits are wrong, they can be corrected by ECC. However, the error correction capability of ECC is limited, and when the error exceeds its error correction range, a reread (Read Retry) operation is required. The reread operation rereads the data by adjusting the read voltage and uses ECC for error correction. If the parameter adjustment is unreasonable, it will lead to multiple reads and verifications, increase the burden on the NAND controller, and affect the read speed and overall performance. Summary of the invention

[0005] The object of the present invention is to provide a method for improving the reread efficiency of flash memory and its memory controller, which helps to reduce the number of reread readings by maintaining a sorting table about a voltage adjustment table, thereby improving the reread efficiency after an error occurs in reading data from a NAND flash memory.

[0006] One or more embodiments of the present invention provide a data reading method for a memory controller of a storage device configured with a rewritable non-volatile memory module. The method comprises: performing a read operation on a target physical page of the rewritable non-volatile memory module to obtain target data including a plurality of bit page data corresponding to a plurality of bit page types and a number of error bits corresponding to each bit page data, wherein each storage unit of the target physical page can store a plurality of bits corresponding to the plurality of bit page types respectively; if the target number of error bits of the target bit page data in the plurality of bit page data exceeds a preset error bit number threshold value: obtaining a target voltage gear table of the target bit page type corresponding to the target bit page data; selecting a gear number as a current gear number according to the order of a plurality of gear numbers in the target voltage gear table, so as to perform an iterative reread operation on the target physical page through the current gear number, thereby obtaining reread target data including a plurality of reread bit page data corresponding to the plurality of bit page types and a number of reread error bits corresponding to each reread bit page data; and if the number of reread error bits of each reread bit page data does not exceed the preset error bit number threshold value, determining that the original data stored in the target physical page is successfully obtained, terminating the iterative reread operation, and updating the target voltage gear table based on the current gear number.

[0007] In one or more embodiments of the present invention, after obtaining the reread target data and the error correction status corresponding to each reread bit page data, the method further includes: if the error correction status corresponding to each reread bit page data is characterized as unsuccessful error correction, then sequentially selecting the next gear sequence number as the new current gear sequence number to perform the iterative reread operation, and repeating this cycle until a gear sequence number appears that causes the error correction status of each reread bit page data to be characterized as successful error correction.

[0008] In one or more embodiments of the present invention, the iterative reread operation includes: determining the corresponding target voltage adjustment gear in the target voltage gear table according to the current gear sequence number; adjusting the target read reference voltage corresponding to the target bit page type in the reference voltage group based on the target voltage adjustment gear; and re-reading the target physical page using the adjusted reference voltage group to obtain reread target data including multiple reread bit page data corresponding to the multiple bit page types and error correction status corresponding to each reread bit page data.

[0009] In one or more embodiments of the present invention, the method further includes: establishing a sorting table according to the target voltage gear table, wherein the sorting table prioritizes each gear number according to the sorting information of each gear number; the step of sequentially selecting a gear number as the current gear number according to the order of multiple gear numbers in the target voltage gear table includes: obtaining the sorting table, and sequentially selecting a gear number as the current gear number according to the priority of each gear number in the sorting table. The step of updating the sorting information corresponding to the current gear number includes: updating the sorting information of the current gear number, and adjusting the priority of the current gear number in the sorting table according to the updated sorting information.

[0010] In one or more embodiments of the present invention, the method further includes: if the original data is successfully obtained after performing the iterative reread operation on the target physical page through the current gear sequence number, accumulating the number of successful rereads corresponding to the current gear sequence number, wherein the step of updating the sorting information corresponding to the current gear sequence number includes: after updating the number of successful rereads of the current gear sequence number, sorting the multiple gear sequence numbers in descending order according to the size of the number of successful rereads of each of the multiple gear sequence numbers to obtain the updated target voltage gear table, wherein the gear sequence number with the largest number of successful rereads will be selected first to perform the iterative reread operation.

[0011] In one or more embodiments of the present invention, the method further includes: if the original data is successfully obtained after the iterative reread operation is performed on the target physical page through the current gear number, the number of successful rereads corresponding to the current gear number is accumulated, and the number of programming and erasing cycles of the target physical page is obtained, and the target programming and erasing cycle interval is determined according to the number of programming and erasing cycles; and according to the target bit page type and the target programming and erasing cycle interval, the target voltage gear table corresponding to the target bit page type and the target programming and erasing cycle interval is obtained, wherein the step of updating the sorting information corresponding to the current gear number includes: after updating the number of successful rereads of the current gear number, the multiple gear numbers are sorted in descending order according to the size of the number of successful rereads of each of the multiple gear numbers to obtain the updated target voltage gear table, wherein the gear number with the largest number of successful rereads will be selected first to perform the iterative reread operation.

[0012] In one or more embodiments of the present invention, the step of obtaining the target voltage level table corresponding to the target bit page type includes: obtaining the number of program-erase cycles of the target physical page;

[0013] Determine a target programming and erasing cycle interval according to the number of programming and erasing cycles; and obtain the target voltage level table corresponding to the target programming and erasing cycle interval from a plurality of voltage level tables corresponding to the target bit page type according to the target bit page type and the target programming and erasing cycle interval.

[0014] In one or more embodiments of the present invention, the method further includes: when it is necessary to establish a new voltage level table corresponding to a new programming and erasing cycle interval, if one or more adjacent voltage level tables corresponding to one or more adjacent programming and erasing cycle intervals adjacent to the new programming and erasing cycle interval have been established, copying one of the one or more adjacent voltage level tables as the initial content of the new voltage level table.

[0015] In one or more embodiments of the present invention, the method further includes: obtaining an original voltage gear table; dividing the original voltage gear table according to multiple gear data corresponding to the multiple bit page types in the original voltage gear table to obtain multiple voltage gear tables corresponding to the multiple bit page types respectively, wherein each voltage gear table has gear data of the corresponding bit page type, and the target voltage gear table is one or more of the multiple voltage gear tables.

[0016] In one or more embodiments of the present invention, the method further includes: after acquiring the multiple voltage gear tables, performing deduplication processing on the multiple gear sub-data of the gear data of each voltage gear table, including: acquiring multiple target gear sub-data with the same content from the multiple gear sub-data, wherein each gear sub-data corresponds to a different original gear serial number of the original voltage gear table; and retaining only one target gear sub-data from the multiple target gear sub-data; and after completing the deduplication processing, assigning multiple gear serial numbers to the multiple remaining gear sub-data respectively, so as to obtain the multiple voltage gear tables corresponding to the multiple bit page types respectively.

[0017] One or more embodiments of the present invention provide a memory controller for controlling a storage device configured with a rewritable non-volatile memory module. The memory controller includes: a memory interface control circuit for electrically connecting to the rewritable non-volatile memory module; and a processor electrically connected to the memory interface control circuit, wherein the processor is configured to: perform a read operation on a target physical page of the rewritable non-volatile memory module to obtain target data including a plurality of bit page data corresponding to a plurality of bit page types and an error correction status corresponding to each bit page data, wherein each storage unit of the target physical page can store a plurality of bits corresponding to the plurality of bit page types respectively; if the error correction status of the target bit page data in the plurality of bit page data is characterized as unsuccessful error correction: obtain the error correction status of the target bit page data; A target voltage gear table of a target bit page type corresponding to the target bit page data; according to the order of multiple gear numbers in the target voltage gear table, one gear number is selected in sequence as the current gear number, so as to perform an iterative reread operation on the target physical page through the voltage regulation gear corresponding to the current gear number, so as to obtain reread target data including multiple reread bit page data corresponding to the multiple bit page types and the error correction status of each reread bit page data; and if the error correction status of each reread bit page data is characterized as successful error correction, it is determined that the original data stored in the target physical page is successfully obtained, and the sorting information corresponding to the current gear number is updated.

[0018] Based on the above, the data reading method and memory controller provided by the embodiment of the present invention perform a read operation on the target physical page of the rewritable non-volatile memory module to obtain target data including multiple bit page data corresponding to multiple bit page types and the error correction bit number status corresponding to each bit page data. If the error correction status of the target bit page data in the multiple bit page data is characterized as unsuccessful error correction, the gear sequence number is selected according to the order of multiple gear sequence numbers in the target voltage gear table to perform an iterative reread operation. By giving priority to the gear sequence numbers that have been successfully reread, the number of invalid reread attempts is reduced, thereby improving the rereading efficiency. At the same time, by maintaining the voltage gear table for different bit page types, the system can more accurately select the appropriate voltage adjustment gear, effectively reducing the processing burden of the memory controller while improving the reliability of data reading. In addition, the present invention implements an adaptive voltage adjustment strategy by statistically analyzing and dynamically sorting the gear sequence numbers that have been successfully reread, which not only improves the accuracy of the reread operation, but also extends the service life of the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0020] Figure 1 is a block diagram of a host system and a storage device according to an embodiment of the present invention;

[0021] Figure 2 A schematic diagram of threshold voltage distributions and corresponding bit values ​​of QLC corresponding to different bit page types according to an embodiment of the present invention;

[0022] Figure 3 A schematic diagram of an original voltage gear table according to an embodiment of the present invention;

[0023] Figure 4 It is a schematic diagram of dividing the original voltage gear table based on the bit page type according to an embodiment of the present invention;

[0024] Figure 5 A schematic diagram of generating a voltage level table corresponding to different bit page types through a segmentation operation and a deduplication operation according to an embodiment of the present invention;

[0025] Figure 6 A schematic diagram of adjusting the priority of the current gear sequence number in the sorting table according to updated sorting information according to an embodiment of the present invention;

[0026] Figure 7 It is a schematic diagram showing updating the voltage gear table after successfully acquiring the original data through a reread operation according to an embodiment of the present invention;

[0027] Figure 8 A schematic diagram of a voltage level table corresponding to different programming and erasing cycle intervals belonging to the same bit page type according to an embodiment of the present invention;

[0028] Fig. 9 FIG. 4 is a flow chart of a data reading method according to an embodiment of the present invention.

[0029] Description of Figure Numbers

[0030] 10: Host system

[0031] 20: Storage device

[0032] 211: First processor

[0033] 110: Second processor

[0034] 120: Host memory

[0035] 130: Data transmission interface circuit

[0036] 210: Memory Controller

[0037] 212: Data management circuit

[0038] 213: Memory interface control circuit

[0039] 214: Buffer memory

[0040] 220: Rewritable non-volatile memory module

[0041] 230: Connecting interface circuit

[0042] BP1: First bit page type

[0043] BP2: Second bit page type

[0044] BP3: The third bit page type

[0045] BP4: The fourth bit page type

[0046] RV1-RV15: Read reference voltage

[0047] RVG: Reference Voltage Group

[0048] TB0, TB40, TB50: Original voltage range table

[0049] TB41-TB44, TB51-TB54, TB55-TB58, TB81-TB83: Voltage range table

[0050] TB71: Target voltage range table

[0051] TB72: Updated target voltage range table

[0052] A41-A44, A51-A54: Arrow (split operation)

[0053] A55-A58: Arrow (deduplication operation)

[0054] A61-A63: Arrow (update operation)

[0055] A71-A72: Arrow (update operation)

[0056] S910-S940: Process steps of data reading method DETAILED DESCRIPTION

[0057] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0058] Figure 1 FIG. 1 is a block diagram of a host system and a storage device according to an embodiment of the present invention. Figure 1, the host system 10 is, for example, a personal computer, a notebook computer, or a server. The host system 10 includes a processor 110 (also referred to as a second processor), a host memory 120, and a data transfer interface circuit 130. In the present embodiment, the processor 110 is coupled (also referred to as electrically connected) to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 are electrically connected to each other using a system bus. In the present embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 may be disposed on a motherboard of the host system 10.

[0059] The storage device 20 includes a storage controller 210, a rewritable non-volatile memory module 220, and a connection interface circuit 230. The storage controller 210 includes a processor 211 (also called a first processor), a data management circuit 212, and a memory interface control circuit 213.

[0060] In this embodiment, the host system 10 is electrically connected to the storage device 20 through the data transmission interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform data access operations. For example, the host system 10 can store data to the storage device 20 or read data from the storage device 20 via the data transmission interface circuit 130.

[0061] In this embodiment, the number of the data transmission interface circuit 130 can be one or more. Through the data transmission interface circuit 130, the motherboard can be electrically connected to the storage device 20 via a wired or wireless manner. The storage device 20 can be, for example, a USB flash drive, a memory card, a solid state drive (SSD) or a wireless memory storage device. The wireless memory storage device can be, for example, a near field communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth memory storage device or a low power consumption Bluetooth memory storage device (e.g., iBeacon) and other memory storage devices based on various wireless communication technologies. In addition, the motherboard can also be electrically connected to various I / O devices such as a global positioning system (GPS) module, a network interface card, a wireless transmission device, a keyboard, a screen, a speaker, etc. through a system bus.

[0062] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the high-speed peripheral component interconnect interface (Peripheral Component Interconnect Express, PCI Express) standard. In addition, the data transmission interface circuit 130 and the connection interface circuit 230 use the fast non-volatile memory interface standard (Non-Volatile Memory express, NVMe) communication protocol to transmit data.

[0063] Furthermore, in another embodiment, the connection interface circuit 230 and the memory controller 210 may be packaged in one chip, or the connection interface circuit 230 may be disposed outside a chip including the memory controller 210 .

[0064] In the present embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. For example, in the present embodiment, the host memory 120 may be a dynamic random access memory (DRAM), a static random access memory (SRAM), etc. However, it should be understood that the present invention is not limited thereto, and the host memory 120 may also be other suitable memories.

[0065] The memory controller 210 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 220 according to instructions of the host system 10 .

[0066] In more detail, the processor 211 in the memory controller 210 is hardware with computing capabilities, which is used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed by a plurality of control instructions / program codes, and when the storage device 20 operates, these control instructions / program codes are executed to perform operations such as writing, reading and erasing data. In addition, in this embodiment, the control instructions / program codes can be further executed to perform data reading operations to implement the data reading method provided by the present invention. The control instructions / program codes corresponding to the data reading method can be further implemented as a circuit unit in the form of hardware to implement the data reading method provided by the present invention.

[0067] It is worth mentioning that in the present embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor, or other programmable processing units (Microprocessor), a digital signal processor (DSP), a programmable controller, an application specific integrated circuit (ASIC), a programmable logic device (PLD) or other similar circuit components, but the present invention is not limited thereto.

[0068] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by the various components of the memory controller 210 can also be regarded as the operations performed by the memory controller 210.

[0069] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213 and the connection interface circuit 230. The data management circuit 212 is used to receive instructions from the processor 211 to transmit data. For example, data is read from the host system 10 (e.g., the host memory 120) via the connection interface circuit 230, and the read data is written to the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (e.g., the write operation is performed according to the write instruction from the host system 10). For another example, data is read from one or more physical units (also called physical blocks) of the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (data can be read from multiple storage units in one or more physical units), and the read data is written to the host system 10 (e.g., the host memory 120) via the connection interface circuit 230 (e.g., the read operation is performed according to the read instruction from the host system 10). In another embodiment, the data management circuit 212 can also be integrated into the processor 211.

[0070] The memory interface control circuit 213 is used to receive instructions from the processor 211 and cooperate with the data management circuit 212 to perform a write (also called programming) operation, a read operation or an erase operation on the rewritable non-volatile memory module 220 .

[0071] In addition, the data to be written to the rewritable non-volatile memory module 220 will be converted into a format acceptable to the rewritable non-volatile memory module 220 via the memory interface control circuit 213. Specifically, if the processor 211 wants to access the rewritable non-volatile memory module 220, the processor 211 will transmit a corresponding instruction sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform a corresponding operation. For example, these instruction sequences may include a write instruction sequence indicating writing data, a read instruction sequence indicating reading data, an erase instruction sequence indicating erasing data, and corresponding instruction sequences for indicating various memory operations. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, in the read instruction sequence, information such as the read identification code, memory address, and physical address will be included.

[0072] In addition, the memory controller 210 establishes a logical to physical address mapping table (Logical To Physical address mapping table) and a physical to logical address mapping table (Physical To Logical address mapping table) to record the mapping relationship between the logical address of the logical unit (e.g., logical block, logical page) configured for the rewritable non-volatile memory module 220 and the physical address (physical address) of the physical unit (e.g., physical erase unit / physical block, physical page). In other words, the memory controller 210 can search for the physical unit mapped by a logical unit (e.g., search for the physical page mapped by a logical page; search for the physical address mapped by a logical address) through the logical to physical address mapping table (also called the logical to physical mapping table), and the memory controller 210 can search for the logical unit mapped by a physical unit (e.g., search for the logical page mapped by a physical page; search for the logical address mapped by a physical address) through the physical to logical address mapping table (also called the physical to logical mapping table).

[0073] In one embodiment, the memory controller 210 further includes a buffer memory 214. The buffer memory is electrically connected to the processor 211 and is used to temporarily store data and instructions from the host system 10, data from the rewritable non-volatile memory module 220, or other system data for managing the storage device 20 (e.g., various voltage level tables, various mapping tables, and programming and erasing cycle tables), so that the processor 211 can quickly access the data, instructions, or system data from the buffer memory 216. In one embodiment, the memory controller 210 can establish one or more write mapping tables in the buffer memory 214 to indicate the target physical address for writing valid data. It should be noted that in other embodiments, the buffer memory 214 can also be configured outside the memory controller 210. Alternatively, the buffer memory 214 can be configured inside and outside the memory controller 210.

[0074] The rewritable non-volatile memory module 220 is electrically connected to the memory controller 210 (memory interface control circuit 213 ) and is used to store user data sent by the host system 10 .

[0075] In the present embodiment, each memory grain (chip) of the multiple memory grains of the rewritable non-volatile memory module 220 has multiple planes (Plane), and each plane has multiple physical blocks. Each physical block includes multiple physical programming units (also called physical pages). Each physical page has multiple storage groups (also called physical bytes or bytes), and each storage group corresponds to a physical address. The physical address is used to record the physical location of the data stored in the storage group. It should be noted that the present invention is not limited to the size of each physical page and logical page. Each storage group has multiple storage cells (also called storage cells, Memory Cell).

[0076] In one embodiment, the memory controller 210 uses error checking and correction (ECC) technology to identify and repair error bits in the data. More specifically, when the memory controller 210 needs to read the original data TD stored in the target physical page of the rewritable non-volatile memory module to respond to the host system 10, the memory controller 210 first performs a read operation on the target physical page to obtain target data including multiple bit page data corresponding to multiple bit page types and its ECC check bits, wherein each storage unit of the target physical page can store multiple bits corresponding to the multiple bit page types respectively.

[0077] Then, the memory controller 210 uses a decoder of a specific algorithm to obtain the error correction status of the target data, and determines whether the error correction is successful according to the error correction status. The error correction status of the target bit page data among the plurality of bit pages data is characterized as unsuccessful error correction, and an iterative reread operation is prepared.

[0078] It should be noted that the target bit page data refers to data stored in the same bit page type.

[0079] In one embodiment, after obtaining the reread target data and the error correction status of each reread bit page data, the memory controller 211 first checks the error correction status of each reread bit page data. If the memory controller 211 finds that the error correction status of any reread bit page data is still characterized as unsuccessful error correction, it continues to perform the iterative reread operation.

[0080] Specifically, the memory controller 211 selects the gear number with the second highest priority from the current sorting table or the voltage gear table as the new current gear number. For example, assuming that the memory controller 211 uses the gear number A with the highest priority to perform an iterative reread operation, and finds that the error correction status of the reread bit page data corresponding to the second bit page type BP2 is still characterized as unsuccessful error correction, the memory controller 211 selects the gear number B with the second highest priority as the new current gear number, and performs a new round of iterative reread operations.

[0081] The memory controller 211 will continue this cyclic operation, that is, whenever it is detected that the error correction status of any re-read bit page data is characterized as unsuccessful error correction, the next gear sequence number with a higher priority will be selected to perform an iterative re-read operation. This process will continue until a gear sequence number appears that makes the error correction status of all re-read bit page data characterized as successful error correction, or all available gear sequence numbers have been tried.

[0082] In one embodiment, the specific execution process of the iterative re-read operation is described in detail. The iterative re-read operation executed by the memory controller 211 includes a series of specific steps.

[0083] First, the memory controller 211 determines the corresponding target voltage adjustment gear from the target voltage gear table according to the current gear sequence number. For example, assuming that the target bit page type is the first bit page type BP1 and the current gear sequence number is 2, the memory controller 211 obtains four target voltage adjustment gears corresponding to the gear sequence number from the target voltage gear table. For example, these voltage adjustment gears are used to adjust the read reference voltages RV1, RV4, RV6 and RV11, respectively.

[0084] Next, the memory controller 211 adjusts the target read reference voltage corresponding to the target bit page type in the reference voltage group based on these target voltage adjustment levels. For example, if a target voltage adjustment level is 0x06, the memory controller 211 will increase the corresponding read reference voltage by 0.12 volts (0.02 volts × 6); if the target voltage adjustment level is 0xF9, the read reference voltage will be lowered by 0.14 volts (0.02 volts × [249-256]). It should be noted that when adjusting these target read reference voltages, the read reference voltages corresponding to other bit page types in the reference voltage group remain unchanged.

[0085] Finally, the memory controller 211 performs a re-read operation on the target physical page using the adjusted complete reference voltage group. This re-read operation obtains the complete re-read target data including all bit page type data, even if only the read reference voltage of a specific bit page type is adjusted. The memory controller 211 then processes the re-read data through a decoder to obtain the error correction status corresponding to each re-read bit page data, which is used to determine whether this iterative re-read operation is successful.

[0086] In one embodiment, for example, the memory controller 210 uses a low density parity check (LDPC) decoder to calculate the relationship between the check bit and the data bit through a check matrix, and counts the number of error bits corresponding to each bit page data. If the target error bit number of the target bit page data in the multiple bit page data exceeds the preset error bit number threshold (e.g., the error correction status of the target bit page data in the multiple bit page data is characterized as unsuccessful error correction), the memory controller 210 will mark the target bit page type of the target physical page to wait for an iterative reread operation. Conversely, if the error bit number of the read target data does not exceed the preset error bit number threshold, the memory controller 210 determines that the original data stored in the target physical page is successfully acquired, and the original data TD can be transmitted to the host system 10.

[0087] In order to better understand the storage characteristics of the target physical page described in the present invention, a QLC type storage unit is taken as an example for description.

[0088] Figure 2 FIG. 4 is a schematic diagram of threshold voltage distributions and corresponding bit values ​​of a QLC corresponding to different bit page types according to an embodiment of the present invention.

[0089] In one embodiment, please refer to Figure 2 , Figure 2 Where RVG represents a reference voltage group for a read operation. Figure 2 The vertical axis in the diagram represents the critical voltage distribution, and the horizontal axis represents the reference voltage. The "1" or "0" marked in the peak region represents the bit value stored in the memory cell within the critical voltage range under the corresponding bit page type.

[0090] like Figure 2As shown, a QLC type storage cell can store 4 bits of data through different critical voltage values. Accordingly, the QLC type storage cell corresponds to four bit page types, including a first bit page type BP1, a second bit page type BP2, a third bit page type BP3 and a fourth bit page type BP4. This means that each storage cell of the target physical page described in the present invention can store multiple bits corresponding to the multiple bit page types respectively. Specifically, each storage cell can simultaneously store a first bit corresponding to the first bit page type BP1, a second bit corresponding to the second bit page type BP2, a third bit corresponding to the third bit page type BP3, and a fourth bit corresponding to the fourth bit page type BP4.

[0091] During a read operation, different read reference voltages RV1 to RV15 in the reference voltage group RVG need to be applied to obtain the bit value stored in the memory cell. Figure 2 As shown, the QLC type memory cell can obtain the bit value stored in the memory cell by applying different read reference voltages RV1 to RV15. Specifically, reference voltages RV1, RV4, RV6 and RV11 are used to control the data reading corresponding to the first bit page type BP1 (also called, Lower page); reference voltages RV3, RV7, RV9 and RV13 are used to control the data reading corresponding to the second bit page type BP2 (also called, Middle page); reference voltages RV2, RV8, RV14 are used to control the data reading corresponding to the third bit page type BP3 (also called, Upper page); reference voltages RV5, RV10, RV12 and RV15 are used to control the data reading corresponding to the fourth bit page type BP4 (also called, eXtra page). By applying these read reference voltages, the bit values ​​stored in the memory cell under different bit page types can be obtained.

[0092] More specifically, in one embodiment, by applying an appropriate read reference voltage to the memory cell, the data stored therein can be determined according to the conduction status of the memory cell. Taking the first bit page type BP1 (Lower page) as an example, when the reference voltage RV8 is applied, if the critical voltage of the memory cell is lower than RV8, it means that the bit value stored in the first bit page type BP1 of the memory cell is "1", and conversely, if the critical voltage of the memory cell is higher than RV8, it means that the stored bit value is "0". The reading operation of other bit page types also follows a similar principle. For example, for the second bit page type BP2 (Middle page), by applying reference voltages RV4, RV5, RV6 and RV12 in sequence, and determining the conduction status of the memory cell under these reference voltages, the bit value stored in the second bit page type BP2 of the memory cell can be determined. In this way, the bit values ​​corresponding to different bit page types can be read from the same memory cell.

[0093] However, as the storage unit is used over time, Figure 1 As shown, the critical voltage of the storage unit is prone to deviation. If the original reading reference voltage is still used for reading, the target error bit number of the target bit page data may exceed the preset error bit number threshold (i.e., exceed the error correction capability of the error detection and correction coding), thereby failing to obtain the original data stored in the target physical page.

[0094] Based on this, the manufacturer of the rewritable non-volatile memory module 220 will formulate a target voltage level table. When the target error bit number exceeds the preset error bit number threshold, the memory controller 211 can select a level number as the current level number according to the order of multiple level numbers in the target voltage level table, so as to perform an iterative reread operation on the target physical page through the current level number. Specifically, the target voltage level table may include 256 level numbers, which are represented as 0x00-0xFF in hexadecimal, where 0x01-0x7F is a positive offset (right offset) voltage level, and 0x80-0xFF is a negative offset (left offset) voltage level. The voltage adjustment amplitude corresponding to each level number can be set to the same value, such as 0.02 volts. Therefore, when the current level number corresponding to a certain read reference voltage is 0x03, the new read reference voltage value used in the iterative reread operation will be the initial value of the read reference voltage plus 0.02 volts multiplied by 3.

[0095] Figure 3 Schematic diagram of an original voltage level table according to an embodiment of the present invention.

[0096] In one embodiment, if Figure 3As shown, the original voltage level table TB0 includes voltage adjustment levels of multiple read reference voltages for different bit page types. Specifically, the original voltage level table TB0 records the voltage adjustment levels of multiple read reference voltages corresponding to the first bit page type BP1 (Lower), the second bit page type BP2 (Middle), the third bit page type BP3 (Upper), and the fourth bit page type BP4 (eXtra).

[0097] In this embodiment, the original voltage level table TB0 includes multiple groups of voltage adjustment levels, each of which is numbered with a preset number (for the convenience of explanation, only 8 preset levels are used, such as 0 to 8, and the present invention is not limited to the total number of voltage adjustment levels). It should be noted that level number 0 is a preset level number, which is used to indicate that the existing read voltage is maintained without adjustment.

[0098] The read reference voltages RV1, RV4, RV6 and RV11 corresponding to the first bit page type BP1, their voltage adjustment gears are recorded in the Lower-R1, Lower-R4, Lower-R6 and Lower-R11 columns respectively; the read reference voltages RV3, RV7, RV9 and RV13 corresponding to the second bit page type BP2, their voltage adjustment gears are recorded in the Middle-R3, Middle-R7, Middle-R9 and Middle-R13 columns respectively; the read reference voltages RV2, RV8, RV14 corresponding to the third bit page type BP3, their voltage adjustment gears are recorded in the Upper-R2, Upper-R8, Upper-R14 columns respectively (Upper-NU is a null value); the read reference voltages RV5, RV10, RV12 and RV15 corresponding to the fourth bit page type BP4, their voltage adjustment gears are recorded in the eXtra-R5, eXtra-R10, eXtra-R12 and eXtra-R15 columns respectively.

[0099] For example, when the voltage adjustment level group corresponding to the preset sequence number 1 is selected, the voltage adjustment level of the read reference voltage RV1 corresponding to the first bit page type BP1 is 0x06, and the voltage adjustment level of RV4 is 0x04; the voltage adjustment level of the read reference voltage RV3 corresponding to the second bit page type BP2 is 0x05, and the voltage adjustment level of RV7 is 0x02; the voltage adjustment level of the read reference voltage RV2 corresponding to the third bit page type BP3 is 0x06, and the voltage adjustment level of RV8 is 0x01; the voltage adjustment level of the read reference voltage RV5 corresponding to the fourth bit page type BP4 is 0x04, and the voltage adjustment level of RV15 is 0x00, and so on. The memory controller 211 can adjust the corresponding read reference voltage values ​​according to these voltage adjustment levels to perform an iterative reread operation.

[0100] In one embodiment, when performing an iterative reread operation, the memory controller 211 determines the corresponding target voltage adjustment level according to the current level sequence number, and adjusts the target read reference voltage corresponding to the target bit page type in the reference voltage group based on the target voltage adjustment level. For example, assuming that the memory controller 211 needs to adjust the read reference voltage RV1 for reading the first bit page type BP1 data, and the voltage adjustment level corresponding to the current level sequence number is 0x06 (hexadecimal), since the voltage adjustment level belongs to the positive offset range (0x01-0x7F), the memory controller 211 will increase the voltage value of RV1 by 0.12 volts (0.02 volts × 6). In contrast, if the voltage adjustment level is 0xF9 (hexadecimal, i.e., 249 in decimal), since the value belongs to the negative offset range (0x80-0xFF), the memory controller 211 will lower the target read reference voltage by 1.4 volts (0.02 volts × [249-256]).

[0101] The memory controller 211 then uses the adjusted reference voltage group to re-read the target physical page to obtain reread target data including a plurality of reread bit page data corresponding to the plurality of bit page types and a reread error bit number (e.g., error correction status) corresponding to each reread bit page data. If the reread error bit number still exceeds the preset error bit number threshold (e.g., when the error correction status is characterized as unsuccessful error correction), the memory controller 211 selects the next gear sequence number as the new current gear sequence number to perform another round of iterative reread operations until the original data stored in the target physical page is successfully obtained or all available gear sequence numbers are exhausted.

[0102] In one embodiment, in addition to maintaining the voltage level table, the memory controller 211 may also establish a corresponding sorting table. The sorting table is used to record the priority information of each level number, where the priority information may be determined based on various factors, such as the number of successful rereads, etc. By maintaining this independent sorting table, the order of use of the level numbers may be dynamically adjusted while maintaining the stability of the original voltage level table.

[0103] Specifically, when the memory controller 211 needs to perform an iterative reread operation, it will first query the sorting table to obtain the gear number with the highest priority, and then obtain the voltage adjustment gear information corresponding to the gear number from the voltage gear table. This separate design allows the system to flexibly adjust the reread strategy without affecting the basic voltage gear data.

[0104] After the reread operation is successful, the memory controller 211 will update the priority information of the gear sequence number in the sorting table. For example, the number of successful rereads can be increased, and the priorities of the gear sequence numbers can be rearranged according to the updated number of successful rereads, or the priority of the gear sequence number that has been successfully reread can be directly adjusted to the highest level to update the sorting table. This dynamic update mechanism ensures that the gear sequence number with a higher success rate can be used preferentially in subsequent reread operations.

[0105] In one embodiment, the memory controller 211 implements a sorting table-based gear number management mechanism that optimizes the selection order of the gear numbers in the iterative re-read operation by maintaining an independent sorting table while maintaining the stability of the original voltage gear table.

[0106] Specifically, the memory controller 211 first establishes a corresponding sorting table according to the target voltage gear table. The sorting table records the sorting information of each gear number and prioritizes the gear numbers based on the sorting information. For example, if the target voltage gear table includes gear numbers 0 to 7, the sorting table may arrange them into a priority sequence according to the historical performance of each gear number: 3, 1, 4, 2, 6, 5, 7, 0 (e.g., gear number 3 has the highest priority).

[0107] When performing an iterative reread operation, the memory controller 211 does not directly use the gear sequence number sequence in the target voltage gear table, but obtains the sorting table and selects the gear sequence number according to the priority order recorded therein. For example, when starting a new iterative reread operation, the memory controller 211 first selects the gear sequence number 3 with the highest priority in the sorting table as the current gear sequence number; if the reread operation using the gear sequence number 3 fails, the gear sequence number 1 with the second highest priority is selected, and so on.

[0108] More importantly, after each iterative reread operation, the memory controller 211 dynamically updates the sorting information. Specifically, after performing an iterative reread operation using a current gear number, the memory controller 211 updates the sorting information of the gear number according to the reread result. For example, if the reread operation is successful, the success count of the gear number may be increased; conversely, if the reread fails, its priority may be lowered. Subsequently, the memory controller 211 adjusts the priority ranking of the current gear number in the sorting table according to the updated sorting information.

[0109] Through this dynamic management mechanism, the sorting table can continuously optimize the order of the gear numbers according to actual operating experience, while the original voltage gear table remains unchanged and continues to provide basic voltage adjustment gear information. This separate design not only improves the efficiency of the re-reading operation, but also enhances the maintainability of the system.

[0110] Figure 6 It is a schematic diagram showing how to adjust the priority of the current gear sequence number in the sorting table according to updated sorting information according to an embodiment of the present invention.

[0111] In one embodiment, Figure 6 The figure shows in detail how the memory controller 211 dynamically manages the priority of the gear sequence number through the sorting table, and maintains the number of successful rereads of each gear sequence number. The figure shows a complete priority update process.

[0112] Specifically, Figure 6 The upper area of ​​TB51 shows a voltage level table (labeled as B61), which contains multiple voltage adjustment levels for the first bit page type (Lower page). The table records the level numbers 0 to 8 (level number 0 is the preset level), and each level number corresponds to four voltage adjustment level values, which are used to adjust the read reference voltages RV1, RV4, RV6, and RV11.

[0113] As shown by arrow A61, the memory controller 211 establishes a sorting table based on the voltage level table TB51. The sorting table performs priority sorting according to the number of successful rereads (e.g., sorting information) of each level number, wherein: the number of successful rereads of level number 1 is "11", with the highest priority; the number of successful rereads of level number 2 is "10", with the second highest priority; the number of successful rereads of level number 3 is "9". And so on, a priority sorting from high to low is formed.

[0114] In actual operation, the memory controller 211 selects gear number 6 to perform an iterative reread operation, and after adjusting the reference voltage group using the voltage adjustment gear corresponding to gear number 6 (Lower-R1: 0x05, Lower-R4: 0xFA, Lower-R6: 0xFB, Lower-R11: 0xF0), the original data in the target physical page is successfully obtained.

[0115] As shown by arrow A62, after this successful re-read operation, the memory controller 211 increases the number of successful re-reads of gear number 6 by 1, updating it from "6" to "7" (the sorting information is updated). This update triggers the re-sorting of the priorities in the sorting table.

[0116] Finally, as shown by arrow A63, due to the increase in the number of successful rereads of gear number 6, its position in the new sorting table TB52 rises and is located between the gear numbers with successful rereads of "8" and "6". This dynamic adjustment ensures that in subsequent reread operations, the gear number with a higher success rate can be selected first.

[0117] In the above embodiment, the memory controller 211 manages the priority of the gear sequence number by maintaining an independent sorting table. However, in another embodiment, the memory controller 211 can also directly record and update the successful reread times information in the voltage gear table, thereby optimizing the reread operation. This method directly associates the voltage adjustment gear information with its use effect by adding a successful reread times field in the voltage gear table, and then reorders the gear sequence number according to actual operation experience.

[0118] Furthermore, since the data in the target physical page to be read will be stored in different bit page types of the storage unit, a sorting table for different bit page types can be established, such as establishing corresponding sorting tables for the first bit page type (Lowerpage), the second bit page type (Middle page), the third bit page type (Upper page) and the fourth bit page type (eXtra page). When the target bit page data is reread, the corresponding sorting table can be adjusted according to the bit page type to which the target bit page data belongs.

[0119] The following embodiments will explain in detail the implementation method of directly recording the number of successful rereads in the voltage level table.

[0120] Figure 7 It is a schematic diagram showing updating the voltage range table after original data is successfully acquired through a re-read operation according to an embodiment of the present invention.

[0121] In one embodiment, if Figure 7 As shown, the target voltage level table TB71 corresponding to the first bit page type BP1 (also called Lower page) includes multiple groups of voltage adjustment levels, each group of voltage adjustment levels includes voltage adjustment level values ​​for adjusting the read reference voltages RV1, RV4, RV6, and RV11, and each group of voltage adjustment levels corresponds to a level sequence number (e.g., 0 to 8). The memory controller 211 also records the number of successful rereads corresponding to each level sequence number to indicate the number of times the original data is successfully obtained by performing an iterative reread operation using the level sequence number.

[0122] For example, when the memory controller 211 performs a read operation on the target physical page, if it is found that the target error bit number of the target bit page data corresponding to the first bit page type BP1 exceeds the preset error bit number threshold, the memory controller 211 will obtain the target voltage level table TB71 corresponding to the first bit page type BP1. Then, the memory controller 211 will select the level number from the target voltage level table TB71 according to the descending order of the number of successful rereads. Figure 7As shown, since the number of successful rereads corresponding to the gear sequence number 1 is "11", which is the highest among all the gear sequence numbers, the memory controller 211 first selects the gear sequence number 1 as the current gear sequence number.

[0123] The memory controller 211 then obtains the corresponding target voltage adjustment level according to the current level sequence number 1, namely, the voltage adjustment level 0x06 of RV1, the voltage adjustment level 0x04 of RV4, the voltage adjustment level 0x00 of RV6, and the voltage adjustment level 0xF9 of RV11. Based on these voltage adjustment levels, the memory controller 211 adjusts the voltage values ​​of the read reference voltages RV1, RV4, RV6, and RV11 corresponding to the first bit page type BP1 in the reference voltage group (the read voltages corresponding to other bit page types remain unchanged), and uses the adjusted reference voltage group to re-read the target physical page to obtain the re-read target data and the corresponding number of re-read error bits.

[0124] If the number of reread error bits of the reread bit page data corresponding to the first bit page type BP1 (target bit page type) still exceeds the preset error bit number threshold, the memory controller 211 will select the gear number 2 with the second highest number of successful rereads as the new current gear number, and use the corresponding voltage adjustment gear (RV1: 0x00, RV4: 0x04, RV6: 0xFE, RV11: 0xFA) to perform another round of iterative reread operations. This process will continue until the number of reread error bits of all reread bit page data does not exceed the preset error bit number threshold (e.g., the number of reread error bits of the reread bit page data of the first bit page type BP1 (target bit page type) does not exceed the preset error bit number threshold), or all gear numbers in the target voltage gear table TB71 are tried.

[0125] When the iterative reread operation successfully obtains the original data stored in the target physical page, the memory controller 211 will update the number of successful rereads of the current gear number that has been successfully used, and re-sort the gear numbers in the target voltage gear table TB71 in descending order based on the updated number of successful rereads, so that the gear numbers with higher successful reread times will be preferentially selected for subsequent iterative reread operations.

[0126] Figure 4 It is a schematic diagram of dividing the original voltage level table based on the bit page type according to an embodiment of the present invention.

[0127] In one embodiment, if Figure 4As shown, the memory controller 211 can obtain the original voltage gear table TB40, which includes multiple gear data corresponding to multiple bit page types. In order to improve the reading speed of the target voltage adjustment gear, the memory controller 211 can divide the original voltage gear table TB40 into multiple voltage gear tables according to the multiple gear data corresponding to the multiple bit page types in the original voltage gear table TB40.

[0128] Specifically, if Figure 4 As shown by arrows A41, A42, A43 and A44, the memory controller 211 saves the multiple gear data in the original voltage gear table TB40 into voltage gear tables corresponding to different bit page types.

[0129] For example, the gear position data corresponding to arrow A41 includes the voltage regulation gear positions for adjusting the read reference voltages RV1, RV4, RV6 and RV11 of the first bit page type BP1, and is saved in the voltage gear position table TB41 corresponding to the first bit page type BP1; the gear position data corresponding to arrow A42 includes the voltage regulation gear positions for adjusting the read reference voltages RV3, RV7, RV9 and RV13 of the second bit page type BP2, and is saved in the voltage gear position table TB42 corresponding to the second bit page type BP2; the gear position data corresponding to arrow A43 includes the voltage regulation gear positions for adjusting the read reference voltages RV2, RV8 and RV14 of the third bit page type BP3, and is saved in the voltage gear position table TB43 corresponding to the third bit page type BP3; the gear position data corresponding to arrow A44 includes the voltage regulation gear positions for adjusting the read reference voltages RV5, RV10, RV12 and RV15 of the fourth bit page type BP4, and is saved in the voltage gear position table TB44 corresponding to the fourth bit page type BP4.

[0130] In this way, when the memory controller 211 needs to perform an iterative reread operation on the target bit page data in the target physical page, it only needs to read the gear data in the voltage gear table corresponding to the target bit page type, without having to read the complete original voltage gear table TB40 as in the traditional way. For example, when the target bit page type is the first bit page type BP1, the memory controller 211 only needs to read the gear data in the voltage gear table TB41 to adjust the read voltage corresponding to the first bit page type BP1, thereby reducing the amount of read data and improving the speed of obtaining the target voltage adjustment gear.

[0131] Figure 5 It is a schematic diagram showing a voltage level table corresponding to different bit page types generated through a segmentation operation and a deduplication operation according to an embodiment of the present invention.

[0132] In one embodiment, if Figure 5As shown, the memory controller 211 can not only divide the original voltage level table TB50 into multiple voltage level tables, but also perform deduplication processing on these voltage level tables to improve the efficiency of the re-read operation.

[0133] Specifically, as shown by arrow A51, the memory controller 211 first extracts the gear data corresponding to the first bit page type BP1 in the original voltage gear table TB50 into the voltage gear table TB51. Similarly, as shown by arrows A52, A53 and A54, the memory controller 211 also extracts the gear data corresponding to the second bit page type BP2, the third bit page type BP3 and the fourth bit page type BP4 into the voltage gear tables TB52, TB53 and TB54 respectively.

[0134] After acquiring these voltage gear tables, the memory controller 211 performs deduplication processing on the gear data in each voltage gear table. Taking the voltage gear table TB51 as an example, the memory controller 211 detects that the gear sub-data corresponding to the gear sequence number 1 and the gear sequence number 6 are exactly the same, that is, Lower-R1 is 0x06, Lower-R4 is 0x04, Lower-R6 is 0x00, and Lower-R11 is 0xF9. Since the contents of these two groups of gear sub-data are the same, when performing deduplication processing, the memory controller 211 only retains one group of gear sub-data (in this example, the gear sub-data corresponding to the gear sequence number 1 is retained).

[0135] As shown by arrow A55, after the deduplication process is completed, the memory controller 211 renumbers the remaining gear sub-data in the voltage gear table TB51 to generate the deduplicated voltage gear table TB55. Similarly, as shown by arrow A56, the memory controller 211 also performs deduplication process on the gear sub-data (such as gear sequence number 3 and gear sequence number 8) with the same content in the voltage gear table TB52, and renumbers the remaining gear sub-data to generate the deduplicated voltage gear table TB56.

[0136] For the voltage level table TB53, as shown by arrow A57, the memory controller 211 does not recognize the level sub-data with the same content, renumbers all the level sub-data, and generates the voltage level table TB57. Finally, as shown by arrow A58, the memory controller 211 also performs the same deduplication processing on the voltage level table TB54 to generate the deduplication-free voltage level table TB58.

[0137] As a result, the memory controller 211 also completes the initialization operation of multiple voltage level tables corresponding to different bit page types.

[0138] Through this segmentation and deduplication processing, the memory controller 211 not only reduces the amount of data when reading the voltage level table, but also avoids repeated attempts using the level sub-data with the same content in the iterative reread operation, thereby improving the efficiency of the reread operation. For example, when the target bit page data corresponding to the first bit page type BP1 needs to perform an iterative reread operation, the memory controller 211 only needs to use the level sub-data in the voltage level table TB55 after deduplication to adjust the read reference voltage, without repeatedly trying the level combination with the same content.

[0139] Figure 7 It is a schematic diagram showing updating the voltage range table after original data is successfully acquired through a re-read operation according to an embodiment of the present invention.

[0140] In one embodiment, for example, Figure 7 As shown, when the memory controller 211 performs a read operation on the target physical page, if it is found that the target error bit number of the target bit page data corresponding to the first bit page type BP1 exceeds the preset error bit number threshold, the memory controller 211 will obtain the target voltage level table TB71 corresponding to the first bit page type BP1.

[0141] In this embodiment, the target voltage level table TB71 records the number of successful rereads corresponding to each level sequence number. For example, the number of successful rereads of level sequence number 1 is "11", the number of successful rereads of level sequence number 2 is "10", and so on. The number of successful rereads of each level sequence number will be accumulated and updated after the corresponding reread operation is successful. For example, if the original data is successfully obtained after the iterative reread operation is performed on the target physical page through the current level sequence number, the memory controller 211 accumulates the number of successful rereads corresponding to the current level sequence number.

[0142] According to the number of successful rereads, the memory controller 211 sorts all the gear numbers in the target voltage gear table TB71 in descending order. The gear number at the front reflects the highest success rate of its reread operation. Therefore, in this embodiment, the memory controller 211 will first select the first gear number (e.g., gear number 1) as the current gear number to perform an iterative reread operation according to the arrangement order.

[0143] Assume that after trying several gear sequence numbers, the memory controller 211 performs an iterative reread operation on the target physical page through gear sequence number 6 (the corresponding voltage adjustment gears are Lower-R1: 0x05, Lower-R4: 0xFA, Lower-R6: 0xFB, Lower-R11: 0xF0) and successfully obtains the original data stored in the target physical page. At this time, the memory controller 211 will accumulate the number of successful rereads of gear sequence number 6 from "6" to "7".

[0144] As shown by arrow A71, after the number of successful rereads of gear number 6 is updated, the memory controller 211 updates the target voltage gear table according to the number of successful rereads of each gear number, and generates an updated target voltage gear table TB72. As shown by arrow A72, since the number of successful rereads of gear number 6 ("7") is now greater than the number of successful rereads of gear number 5 ("6"), in the updated target voltage gear table TB72, gear number 6 is adjusted before gear number 5. Such an order ensures that in subsequent iterative reread operations, the gear number with a higher number of successful rereads will be selected first, thereby improving the success rate of the reread operation.

[0145] Figure 8 It is a schematic diagram of a voltage level table corresponding to different programming and erasing cycle intervals belonging to the same bit page type according to an embodiment of the present invention.

[0146] In one embodiment, if Figure 8 As shown, the memory controller 211 can establish corresponding voltage level tables for different programming and erasing cycle intervals. Taking the first bit page type BP1 as an example, the voltage level table TB81 corresponds to the interval of programming and erasing cycle times from 0 to 500 times, the voltage level table TB82 corresponds to the interval of programming and erasing cycle times from 501 to 1000 times, the voltage level table TB83 corresponds to the interval of programming and erasing cycle times from 1001 to 1500 times, and so on.

[0147] It can be seen from the contents of these voltage level tables that as the number of programming and erasing cycles increases, the value of the voltage adjustment level also shows an increasing trend. For example, for the read reference voltage RV1 (Lower-R1), the voltage adjustment level range in the voltage level table TB81 is 0x02 to 0x06, the voltage adjustment level range in the voltage level table TB82 is 0x04 to 0x08, and the voltage adjustment level range in the voltage level table TB83 is 0x06 to 0x0E, which reflects the characteristic that the storage unit requires a larger voltage adjustment range as the number of uses increases.

[0148] In the process of establishing these voltage level tables, the memory controller 211 may perform the following steps:

[0149] First, determine the division method of the programming and erasing cycle intervals, such as every 500 times as one interval;

[0150] Establish an initial voltage range table for each interval, and use the preset voltage adjustment range;

[0151] In actual use, the voltage level table of each interval is updated by iteratively rereading the results of the operation, and the number of successful rereads of each level sequence number is maintained;

[0152] Regularly sort the gear numbers in the voltage gear table of each interval in descending order according to the number of successful rereads.

[0153] When the memory controller 211 needs to perform a read operation on the target physical page, and finds that the target number of error bits of the target bit page data exceeds the preset error bit number threshold, the memory controller 211 will first obtain the number of programming and erasing cycles of the target physical page. For example, if the number of programming and erasing cycles obtained is 750 times, the memory controller 211 will determine that the target programming and erasing cycle interval is 501 to 1000 times. Subsequently, the memory controller 211 obtains the voltage level table TB82 as the target voltage level table from the multiple voltage level tables corresponding to the first bit page type BP1 according to the target bit page type (such as the first bit page type BP1) and the target programming and erasing cycle interval (501 to 1000 times), and uses the voltage adjustment level in the target voltage level table to perform an iterative reread operation.

[0154] In one embodiment, the memory controller 211 needs to dynamically establish voltage level tables corresponding to different programming and erasing cycle intervals according to the number of programming and erasing cycles of the target physical page during actual use. When a new voltage level table corresponding to a new programming and erasing cycle interval needs to be established, the memory controller 211 can refer to the voltage level table established in the adjacent interval to improve the initial availability of the new voltage level table.

[0155] For example, it is assumed that the memory controller 211 has established and maintained the voltage level table TB81 for the program-erase cycle interval of 0 to 500. When the memory controller 211 needs to perform a reread operation on the target physical page with the program-erase cycle number of 501 to 1000, it is found that the voltage level table for this interval has not been established.

[0156] In this case, since the program-erase cycle interval with a program-erase cycle number of 501 to 1000 is adjacent to the program-erase cycle interval with a program-erase cycle number of 0 to 500, the memory controller 211 can select the voltage level table of the program-erase cycle interval with a program-erase cycle number of 0 to 500 as the initial content of the newly created voltage level table. For example, the memory controller 211 can choose to copy the content of the voltage level table TB81 as the initial content of the voltage level table TB82 of the program-erase cycle interval with a program-erase cycle number of 501 to 1000.

[0157] Subsequently, in the process of performing a reread operation on the target physical page in the programming and erasing cycle interval with a programming and erasing cycle number of 501 to 1000 times, the memory controller 211 will accumulate the number of successful rereads of the gear sequence number that is successfully used according to the actual reread result, and sort the gear sequence numbers in the voltage gear table TB82 in descending order, thereby gradually optimizing the voltage gear table of the programming and erasing cycle interval. In this way, the memory controller 211 does not need to establish a new voltage gear table from scratch, but can use the voltage gear table that has been optimized in the adjacent programming and erasing cycle interval as a basis to quickly establish a voltage gear table suitable for the new programming and erasing cycle interval, thereby improving the adaptability and efficiency of the system. It should be noted that, in another embodiment, the memory controller 211 will also copy the number of successful rereads corresponding to all the gear numbers of the voltage gear table in the programming and erasing cycle interval from 0 to 500 times to record the initial successful reread number of all the gear numbers of the voltage gear table in the programming and erasing cycle interval from 501 to 1000 times as the initial value. By inheriting these statistical data, the newly created voltage gear table can have a relatively reasonable gear number sorting in the initial stage, thereby improving the success rate of the early reread operation.

[0158] In one embodiment, when the memory controller 211 successfully obtains the original data after performing an iterative reread operation on the target physical page through the current gear sequence number, the memory controller 211 will not only accumulate the number of successful rereads of the current gear sequence number, but also obtain the number of programming and erasing cycles of the target physical page. For example, it is assumed that the memory controller 211 successfully performs an iterative reread operation using the voltage adjustment gear (Lower-R1: 0x05, Lower-R4: 0x03, Lower-R6: 0xFE, Lower-R11: 0xFC) corresponding to the gear sequence number 2 in the voltage gear table TB82, and the number of programming and erasing cycles of the target physical page obtained is 750 times.

[0159] At this time, the memory controller 211 determines the target programming and erasing cycle interval (501 to 1000 times) according to the acquired programming and erasing cycle number (750 times), and confirms that the voltage level table TB82 is the target voltage level table that needs to be updated according to the target bit page type (such as the first bit page type BP1) and the target programming and erasing cycle interval. Then, after accumulating the number of successful rereads of the level number 2, the memory controller 211 will sort these level numbers in descending order according to the number of successful rereads of each level number in the target voltage level table TB82 to obtain the updated target voltage level table TB82. In this way, it is ensured that when the iterative reread operation is performed on the target physical page with a programming and erasing cycle number of 501 to 1000 times, the level number with a higher number of successful rereads can be preferentially selected.

[0160] This method of updating the voltage level table based on the program-erase cycle interval enables the memory controller 211 to maintain the optimal voltage adjustment level sequence for each storage unit with different usage levels, thereby improving the efficiency of the reread operation. For example, compared with the interval with a lower number of program-erase cycles (such as 0 to 500 times), the interval with a higher number of program-erase cycles (such as 1001 to 1500 times) may require a larger voltage adjustment range. By maintaining the voltage level tables of these intervals respectively, the appropriate voltage adjustment level can be selected more accurately for the storage units with different usage levels.

[0161] In various embodiments, in addition to maintaining the voltage level table based on the number of program-erase cycles, the memory controller 211 may also consider other factors that affect the critical voltage distribution of the memory cells and establish a more detailed voltage level table grouping for each bit page type.

[0162] For example, in one embodiment, since the critical voltage distribution of the memory cell may shift as the operating temperature changes, the memory controller 211 may maintain the voltage level table according to the temperature range (such as 0-25°C, 26-50°C, 51-75°C, etc.). When the number of error bits of the target bit page data is detected to exceed the preset error bit number threshold within a certain temperature range (such as 40°C), the memory controller 211 will preferentially select the voltage level table corresponding to the temperature range (26-50°C) to perform the iterative reread operation.

[0163] In addition, in another embodiment, considering that the data retention time will affect the critical voltage distribution of the storage unit, the memory controller 211 can record the data write timestamp of each physical page and select the corresponding voltage level table according to the data storage time (such as 0-30 days, 31-90 days, 91-180 days, etc.). For example, for data with a storage time of more than 90 days, a larger voltage adjustment range may be required to compensate for the natural drift of the critical voltage.

[0164] In another embodiment, since the memory cells at different positions in the same memory chip may have performance differences, the memory controller 211 may also maintain different voltage level tables according to the positions of the physical blocks in the chip. For example, for the memory cells at the edge of the chip, it may be necessary to adopt a different voltage adjustment strategy than the memory cells in the center area.

[0165] In another embodiment, the memory controller 211 may also maintain a dedicated voltage level table for different data writing modes. For example, a continuously written data block may present a critical voltage distribution characteristic different from a randomly written data block, and therefore a different voltage adjustment level combination may be used to perform a reread operation.

[0166] In order to implement these grouping methods, the memory controller 211 needs to record and maintain the corresponding attribute information. For example, the temperature range identifier, data write timestamp, physical location information, write mode identifier, etc. can be recorded in the management information of the target physical page. When a reread operation needs to be performed on the target physical page, the memory controller 211 can select the most matching voltage level table according to these attribute information, thereby improving the accuracy and efficiency of the reread operation.

[0167] Fig. 9 FIG. 4 is a flow chart of a data reading method according to an embodiment of the present invention.

[0168] In one embodiment, if Fig. 9 As shown, the data reading method of the present invention comprises the following steps:

[0169] First, in step S910, the memory controller 211 performs a read operation on the target physical page of the rewritable non-volatile memory module 220 to obtain target data including multiple bit page data corresponding to multiple bit page types and the number of error bits corresponding to each bit page data. For example, if the target physical page uses a QLC type storage unit, the memory controller 211 can read the bit page data corresponding to the first bit page type BP1 to the fourth bit page type BP4, and calculate the number of error bits of each bit page data through error detection and correction coding. This enables the memory controller 211 to promptly discover the target bit page data that needs to be reread.

[0170] Next, in step S920, if the target error bit number of the target bit page data in the multiple bit page data exceeds the preset error bit number threshold, the target voltage level table of the target bit page type corresponding to the target bit page data is obtained. For example, if it is found that the error bit number of the bit page data corresponding to the first bit page type BP1 exceeds the preset error bit number threshold, and the number of programming and erasing cycles of the target physical page is 750 times, the memory controller 211 will obtain the voltage level table TB82 corresponding to the programming and erasing cycle interval 501 to 1000 times as the target voltage level table. This method of selecting the voltage level table based on the bit page type and the programming and erasing cycle interval can more accurately select the appropriate voltage adjustment level for storage cells with different usage levels.

[0171] Then, in step S930, a gear sequence number is selected as the current gear sequence number according to the order of the multiple gear sequence numbers in the target voltage gear table, so as to perform an iterative reread operation on the target physical page through the current gear sequence number. For example, the memory controller 211 will preferentially select the gear sequence number with the highest number of successful rereads in the voltage gear table TB82, and use the voltage adjustment gear corresponding to the gear sequence number (such as Lower-R1: 0x04, Lower-R4: 0x02, Lower-R6: 0x00, Lower-R11: 0xFD) to adjust the read reference voltages RV1, RV4, RV6 and RV11 to perform an iterative reread operation. This method of selecting the gear sequence number based on the number of successful rereads can improve the success rate of the reread operation.

[0172] Finally, in step S940, if the number of reread error bits of each reread bit page data does not exceed the preset error bit number threshold, it is determined that the original data stored in the target physical page is successfully acquired, the iterative reread operation is terminated, and the target voltage gear table is updated based on the current gear sequence number. For example, when the original data is successfully acquired using gear sequence number 2, the memory controller 211 will increase the number of successful rereads of the gear sequence number by 1, and reorder the gear sequence numbers in the voltage gear table TB82 according to the updated number of successful rereads. This dynamic update mechanism enables the voltage gear table to be continuously optimized to adapt to the usage characteristics of the storage unit.

[0173] However, Fig. 9 The steps in the above are described in detail, so I will not repeat them here. It is worth noting that Fig. 9 Each step in the above-mentioned embodiment can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Fig. 9 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention is not limited thereto.

[0174] This embodiment also provides a computer program product, including a computer readable code, or a non-volatile computer readable storage medium carrying the computer readable code, when the computer readable code is executed in the processor of the host system, the processor executes the steps of the above data reading method. The computer program product can be implemented in hardware, firmware, software or a combination thereof. In an optional embodiment, the computer program product is specifically embodied as a computer storage medium, and in another optional embodiment, the computer program product is specifically embodied as a software product, such as a software development kit (Software Development Kit, SDK) and the like.

[0175] It can be seen from the above embodiments that the data reading method and the memory controller provided by the present invention mainly have the following technical effects:

[0176] First, the present invention maintains voltage level tables for different bit page types respectively, so that the memory controller can select the most suitable voltage adjustment level for each bit page type to perform a reread operation. For example, when it is detected that the number of error bits of the target bit page data corresponding to the first bit page type BP1 exceeds the preset error bit number threshold, the voltage level table corresponding to the first bit page type BP1 can be directly obtained without considering the voltage adjustment levels of other bit page types, thereby improving the accuracy of the reread operation.

[0177] Secondly, the present invention establishes an adaptive voltage adjustment mechanism by recording the number of successful rereads of each gear sequence number and sorting the gear sequence numbers in descending order based on the number of successful rereads. When the voltage adjustment gear corresponding to a gear sequence number is successfully used for a reread operation, the priority of the gear sequence number will be increased accordingly, ensuring that the voltage adjustment gear that is more likely to succeed is used first in subsequent reread operations, which significantly reduces the number of attempts for the reread operation.

[0178] Furthermore, the present invention takes into account that the usage level of the storage unit will affect its voltage adjustment requirements, and therefore maintains independent voltage level tables for different programming and erasing cycle intervals. This fine-grained management method enables the memory controller to select an appropriate voltage level table based on the actual usage level of the target physical page, thereby improving the accuracy of the reread operation. For example, for storage cells with a high number of programming and erasing cycles, a larger voltage adjustment range can be used; while for storage cells with a low usage level, a relatively mild voltage adjustment strategy can be adopted.

[0179] In addition, the present invention not only reduces the amount of data when reading the voltage level table by segmenting and deduplicating the voltage level table, but also avoids repeated attempts of the same voltage adjustment level combination in the reread operation. This optimization significantly improves the speed at which the memory controller acquires the target voltage adjustment level.

[0180] In summary, the present invention improves the rereading efficiency and enhances the data reading reliability of the storage device through a refined voltage level table management mechanism combined with dynamic update and optimization strategies. The realization of these technical effects not only reduces the processing burden of the memory controller, but also prolongs the service life of the storage device.

[0181] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data reading method, applicable to a memory controller of a storage device equipped with a rewritable non-volatile memory module, characterized in that: The method comprises: Performing a read operation on a target physical page of the rewritable non-volatile memory module to obtain target data including a plurality of bit page data corresponding to a plurality of bit page types and an error correction status corresponding to each bit page data, wherein each storage unit of the target physical page can store a plurality of bits corresponding to the plurality of bit page types respectively; If the error correction status of the target bit page data among the plurality of bit pages data is characterized as unsuccessful error correction: Acquire a target voltage level table corresponding to a target bit page type of the target bit page data; According to the order of the multiple gear numbers in the target voltage gear table, one gear number is selected in sequence as the current gear number, so as to perform an iterative reread operation on the target physical page through the voltage adjustment gear corresponding to the current gear number, thereby obtaining reread target data including multiple reread bit page data corresponding to the multiple bit page types and error correction status corresponding to each reread bit page data; and If the error correction status of each re-read bit page data is characterized as successful error correction, it is determined that the original data stored in the target physical page is successfully acquired, and the sorting information corresponding to the current gear sequence number is updated.

2. The data reading method according to claim 1, characterized in that: After obtaining the reread target data and the error correction status corresponding to each reread bit page data, the method further includes: If the error correction status corresponding to each reread bit page data is characterized as unsuccessful error correction, the next gear sequence number is selected in sequence as the new current gear sequence number to perform the iterative reread operation, and this cycle is repeated until a gear sequence number appears that makes the error correction status of each reread bit page data characterized as successful error correction.

3. The data reading method according to claim 1, characterized in that: The iterative rereading operation includes: Determine the corresponding target voltage adjustment gear in the target voltage gear table according to the current gear sequence number; Based on the target voltage adjustment level, adjusting a target read reference voltage in the reference voltage group corresponding to the target bit page type; and The target physical page is re-read using the adjusted reference voltage group to obtain re-read target data including a plurality of re-read bit page data corresponding to the plurality of bit page types and an error correction status corresponding to each re-read bit page data.

4. The data reading method according to claim 1, characterized in that: Also includes: Establishing a sorting table according to the target voltage gear table, wherein the sorting table prioritizes each gear sequence number according to the sorting information of each gear sequence number; The step of selecting a gear number as the current gear number in sequence according to the order of the multiple gear numbers in the target voltage gear table comprises: Obtaining the sorting table, and selecting a gear number in order according to the priority of each gear number in the sorting table as the current gear number; The step of updating the sorting information corresponding to the current gear sequence number includes: The sorting information of the current gear sequence number is updated, and the priority of the current gear sequence number in the sorting table is adjusted according to the updated sorting information.

5. The data reading method according to claim 1, characterized in that: The method further comprises: If the original data is successfully obtained after the iterative reread operation is performed on the target physical page through the current gear sequence number, the number of successful rereads corresponding to the current gear sequence number is accumulated, The step of updating the sorting information corresponding to the current gear sequence number includes: After updating the number of successful rereads of the current gear sequence number, the multiple gear sequence numbers are sorted in descending order according to the number of successful rereads of each of the multiple gear sequence numbers to obtain the updated target voltage gear table, The gear sequence number with the largest number of successful re-read times will be selected first to perform the iterative re-read operation.

6. The data reading method according to claim 1, characterized in that: The method further comprises: If the original data is successfully obtained after the iterative reread operation is performed on the target physical page through the current gear sequence number, the number of successful rereads corresponding to the current gear sequence number is accumulated, and the number of program-erase cycles of the target physical page is obtained, Determining a target program-erase cycle interval according to the program-erase cycle number; and According to the target bit page type and the target programming and erasing cycle interval, the target voltage level table corresponding to the target bit page type and the target programming and erasing cycle interval is obtained, The step of updating the sorting information corresponding to the current gear sequence number includes: After updating the number of successful rereads of the current gear sequence number, the multiple gear sequence numbers are sorted in descending order according to the number of successful rereads of each of the multiple gear sequence numbers to obtain the updated target voltage gear table, The gear sequence number with the largest number of successful re-read times will be selected first to perform the iterative re-read operation.

7. The data reading method according to claim 1, characterized in that: The step of obtaining the target voltage level table corresponding to the target bit page type includes: Obtaining the number of program-erase cycles of the target physical page; Determining a target program-erase cycle interval according to the program-erase cycle number; and According to the target bit page type and the target programming-erasing cycle interval, the target voltage level table corresponding to the target programming-erasing cycle interval is acquired from a plurality of voltage level tables corresponding to the target bit page type.

8. The data reading method according to claim 7, characterized in that: The method further comprises: When it is necessary to establish a new voltage level table corresponding to a new programming-erasing cycle interval, if one or more adjacent voltage level tables corresponding to one or more adjacent programming-erasing cycle intervals adjacent to the new programming-erasing cycle interval have been established, copy one of the one or more adjacent voltage level tables as the initial content of the new voltage level table.

9. The data reading method according to claim 1, characterized in that: The method further comprises: Get the original voltage range table; According to the multiple gear data corresponding to the multiple bit page types in the original voltage gear table, the original voltage gear table is divided to obtain multiple voltage gear tables corresponding to the multiple bit page types respectively, wherein each voltage gear table has the gear data of the corresponding bit page type, and the target voltage gear table is one or more of the multiple voltage gear tables.

10. The data reading method according to claim 1, characterized in that: The method further comprises: After acquiring the plurality of voltage gear tables, deduplication processing is performed on the plurality of gear sub-data of the gear data of each voltage gear table, including: Acquire a plurality of target gear sub-data having the same content from the plurality of gear sub-data, wherein each gear sub-data corresponds to a different original gear sequence number of the original voltage gear table; and retaining only one target gear position sub-data among the plurality of target gear position sub-data; and After the deduplication process is completed, a plurality of remaining gear sub-data are respectively assigned a plurality of gear sequence numbers to obtain the plurality of voltage gear tables corresponding to the plurality of bit page types respectively.

11. A memory controller for controlling a storage device equipped with a rewritable non-volatile memory module, characterized in that: The memory controller comprises: A memory interface control circuit, for electrically connecting to the rewritable non-volatile memory module; and a processor electrically connected to the memory interface control circuit, wherein the processor is configured to: Performing a read operation on a target physical page of the rewritable non-volatile memory module to obtain target data including a plurality of bit page data corresponding to a plurality of bit page types and an error correction status corresponding to each bit page data, wherein each storage unit of the target physical page can store a plurality of bits corresponding to the plurality of bit page types respectively; If the error correction status of the target bit page data among the plurality of bit pages data is characterized as unsuccessful error correction: Acquire a target voltage level table corresponding to a target bit page type of the target bit page data; According to the order of the multiple gear numbers in the target voltage gear table, one gear number is selected in sequence as the current gear number, so as to perform an iterative reread operation on the target physical page through the voltage adjustment gear corresponding to the current gear number, thereby obtaining reread target data including multiple reread bit page data corresponding to the multiple bit page types and error correction status corresponding to each reread bit page data; and If the error correction status of each re-read bit page data is characterized as successful error correction, it is determined that the original data stored in the target physical page is successfully acquired, and the sorting information corresponding to the current gear sequence number is updated.

12. The memory controller according to claim 11, wherein: The processor is also configured to: If the error correction status corresponding to each reread bit page data is characterized as unsuccessful error correction, the next gear sequence number is selected in sequence as the new current gear sequence number to perform the iterative reread operation, and this cycle is repeated until a gear sequence number appears that makes the error correction status of each reread bit page data characterized as successful error correction.

13. The memory controller according to claim 11, wherein: The iterative rereading operation includes: Determine the corresponding target voltage adjustment gear in the target voltage gear table according to the current gear sequence number; Based on the target voltage adjustment level, adjusting a target read reference voltage in the reference voltage group corresponding to the target bit page type; and The target physical page is re-read using the adjusted reference voltage group to obtain re-read target data including a plurality of re-read bit page data corresponding to the plurality of bit page types and an error correction status corresponding to each re-read bit page data.

14. The memory controller according to claim 11, wherein: The processor is also configured to: Establishing a sorting table according to the target voltage gear table, wherein the sorting table prioritizes each gear sequence number according to the sorting information of each gear sequence number; Obtaining the ranking table, and selecting a gear number in order according to the priority of each gear number in the ranking table as the current gear number; and The sorting information of the current gear sequence number is updated, and the priority of the current gear sequence number in the sorting table is adjusted according to the updated sorting information.

15. The memory controller according to claim 11, wherein: The processor is also configured to: If the original data is successfully acquired after the iterative reread operation is performed on the target physical page through the current gear sequence number, the number of successful rereads corresponding to the current gear sequence number is accumulated; as well as After updating the number of successful rereads of the current gear sequence number, the multiple gear sequence numbers are sorted in descending order according to the number of successful rereads of each of the multiple gear sequence numbers to obtain the updated target voltage gear table, The gear sequence number with the largest number of successful re-read times will be selected first to perform the iterative re-read operation.

16. The memory controller according to claim 11, wherein: The processor is also configured to: If the original data is successfully obtained after performing the iterative reread operation on the target physical page through the current gear sequence number: Accumulate the number of successful rereads of the corresponding current gear sequence number; Obtaining the number of program-erase cycles of the target physical page; Determining a target program-erase cycle interval according to the program-erase cycle number; as well as According to the target bit page type and the target programming and erasing cycle interval, obtaining the target voltage level table corresponding to the target bit page type and the target programming and erasing cycle interval; Wherein updating the sorting information corresponding to the current gear sequence number includes: After updating the number of successful rereads of the current gear sequence number, the multiple gear sequence numbers are sorted in descending order according to the number of successful rereads of each of the multiple gear sequence numbers to obtain the updated target voltage gear table, The gear sequence number with the largest number of successful re-read times will be selected first to perform the iterative re-read operation.

17. The memory controller according to claim 11, wherein: The step of obtaining the target voltage level table corresponding to the target bit page type includes: Obtaining the number of program-erase cycles of the target physical page; Determining a target program-erase cycle interval according to the program-erase cycle number; and According to the target bit page type and the target programming-erasing cycle interval, the target voltage level table corresponding to the target programming-erasing cycle interval is acquired from a plurality of voltage level tables corresponding to the target bit page type.

18. The memory controller according to claim 17, wherein: The processor is also configured to: When it is necessary to establish a new voltage level table corresponding to a new programming-erasing cycle interval, if one or more adjacent voltage level tables corresponding to one or more adjacent programming-erasing cycle intervals adjacent to the new programming-erasing cycle interval have been established, copy one of the one or more adjacent voltage level tables as the initial content of the new voltage level table.

19. The memory controller according to claim 11, wherein: The processor is also configured to: Obtaining an original voltage range table; and According to the multiple gear data corresponding to the multiple bit page types in the original voltage gear table, the original voltage gear table is divided to obtain multiple voltage gear tables corresponding to the multiple bit page types respectively, wherein each voltage gear table has the gear data of the corresponding bit page type, and the target voltage gear table is one or more of the multiple voltage gear tables.

20. The memory controller according to claim 11, wherein: The processor is also configured to: After acquiring the plurality of voltage gear tables, deduplication processing is performed on the plurality of gear sub-data of the gear data of each voltage gear table, including: Acquire a plurality of target gear sub-data having the same content from the plurality of gear sub-data, wherein each gear sub-data corresponds to a different original gear sequence number of the original voltage gear table; retaining only one target gear position sub-data among the plurality of target gear position sub-data; and After the deduplication process is completed, a plurality of remaining gear sub-data are respectively assigned a plurality of gear sequence numbers to obtain the plurality of voltage gear tables corresponding to the plurality of bit page types respectively.

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