A method and device for instruction translation in dynamic binary translation

Abstract

The present invention proposes an instruction translation method and device for dynamic binary translation. The instruction translation method first analyzes the differences between the source instruction set architecture and the target instruction set architecture to find a specific instruction sequence in the source instruction set architecture instructions, and then designs translation rules for the specific instruction sequence based on the characteristics of the target instruction set architecture. During dynamic binary translation, the specific instruction sequence in the source instruction set architecture binary file is scanned and translated using the translation rules of the present invention; otherwise, conventional translation methods are still used. The present invention translates the binary instructions of the source instruction set architecture according to customized translation rules, reducing the number of instructions of the translated target instruction set architecture, improving translation quality, and thus improving binary translation efficiency.

Description

Technical Field

[0001] The present invention belongs to the technical field of binary translation, and in particular relates to an instruction translation method and device in dynamic binary translation. Background Art

[0002] With the advent of the golden age of architecture, a variety of emerging processor architectures are constantly emerging. Because software compiled for different instruction set architectures cannot run across platforms, the software ecosystem for new processor platforms has become a major bottleneck restricting their adoption. To overcome this dilemma and accelerate ecosystem development and market adoption, migrating software resources from existing mainstream architectures to new architectures has become an effective solution. Binary translation technology, which enables cross-platform software operation without requiring source code, has become a key tool for cross-architecture software migration.

[0003] Binary translation is categorized into static and dynamic binary translation. The former translates the complete binary code on the source platform into an executable binary program for the target platform. The translated program can be reused multiple times, offering high operational efficiency. Program execution and translation are independent of each other, allowing more time for in-depth optimization. The latter parses and translates code snippets during program execution, making it more suitable for handling issues such as indirect jumps, indirect calls, and self-modifying code. Furthermore, dynamic translation can identify optimization opportunities during the translation process that static translation cannot. It is a more flexible and scalable binary translation method, making it the mainstream choice in the binary translation field.

[0004] There is a certain semantic gap between different instruction sets. For example, the traditional complex instruction set X86 platform uses a dedicated flag register and corresponding computational logic in its hardware circuitry to store intermediate computations. These registers primarily serve to store additional results of executing related instructions, provide a basis for executing related instructions, and control the CPU's operating mode. However, in some emerging reduced instruction set architectures, dedicated flag registers are not designed to maintain instruction set simplicity and consistency. During binary translation, if the source platform uses a complex instruction set (CISC) and the target platform uses a reduced instruction set (RISC), the flags in the flag registers must be translated. Flag translation involves generating instructions with the same functionality on the target platform based on the semantics of the flag operations performed by the source platform's instructions. These generated target instructions are then executed to achieve the same semantically equivalent functionality as the flags on the source platform. However, reduced instruction sets are generally less expressive than complex instruction sets, requiring more instructions to express the same semantics. Therefore, during binary translation, to maintain semantic equivalence, the number of instructions in the target platform's translation often exceeds that of the source platform, resulting in code bloat and reduced translation quality.

[0005] A Chinese patent application, "Method for Optimizing Flag Bit Processing in Binary Translation" (Publication No. CN1296815A), also proposes a flag bit translation optimization strategy for binary translation. This invention combines immediate and delayed computation for interpretive execution in binary translation, optimizing flag bit processing during interpretive execution and reducing redundant target instructions.

[0006] China's national patent "A Translation Method in Dynamic Binary Translation" (publication number: CN1332308A) also introduces a dynamic binary translation strategy, which searches for translation code fragments that frequently appear in the translation code and affect the translation quality, and proposes a translation method based on instruction pattern recognition to reduce the system overhead caused by repeated code optimization. Summary of the Invention

[0007] In response to the problem of instruction redundancy generated during binary translation flag operations, the present invention proposes an instruction translation method in dynamic binary translation, including: obtaining the difference between a source instruction set architecture and a target instruction set architecture, identifying a specific instruction sequence in the source instruction set; designing a translation rule for the specific instruction sequence based on the target instruction set architecture; during the dynamic binary translation process, detecting a specific instruction sequence in a binary file of the source instruction set architecture; and translating the detected specific instruction sequence using the corresponding translation rule.

[0008] Furthermore, the translation rule includes: merging multiple source instructions in the specific instruction sequence into one or more target instructions.

[0009] The specific instruction sequence includes an instruction sequence related to a flag bit in the source instruction set. For common instructions other than the specific instruction sequence in the source instruction set architecture binary file, a conventional translation method is used for translation.

[0010] The present invention also proposes an instruction translation device in dynamic binary translation, including: a difference comparison module, used to obtain the difference between the source instruction set architecture and the target instruction set architecture, and identify the specific instruction sequence in the source instruction set; a rule generation module, used to design the translation rules of the specific instruction sequence based on the target instruction set architecture; a dynamic translation module, used to detect the specific instruction sequence in the binary file of the source instruction set architecture during the dynamic binary translation process; for the detected specific instruction sequence, the corresponding translation rules are used for translation.

[0011] Furthermore, the translation rule includes: merging multiple source instructions in the specific instruction sequence into one or more target instructions.

[0012] The specific instruction sequence includes an instruction sequence involving flag bits in the source instruction set. The dynamic translation module further includes: translating common instructions other than the specific instruction sequence in the source instruction set architecture binary file using a conventional translation method.

[0013] The present invention further provides an electronic device comprising the instruction translation device in the dynamic binary translation as described above.

[0014] The present invention provides a computer-readable storage medium storing computer-executable instructions, characterized in that when the computer-executable instructions are executed, the instruction translation method in the dynamic binary translation as described above is implemented.

[0015] The instruction translation method in dynamic binary translation of the present invention is based on the identified specific instruction sequence and formulates corresponding translation rules to maximize the elimination of instruction redundancy caused by translation, thereby effectively improving the quality of binary translation. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a flow chart of the instruction translation method in the dynamic binary translation of the present invention.

[0017] Figure 2 It is a partial detailed flow chart of the instruction translation method in the dynamic binary translation of the present invention.

[0018] Figure 3 It is a pseudo code diagram of the flag instruction sequence translation optimization algorithm of the present invention.

[0019] Figure 4 It is a schematic diagram of the translation rules of the present invention.

[0020] Figure 5 It is a schematic diagram of the instruction translation device in the dynamic binary translation of the present invention.

[0021] Figure 6 It is a schematic diagram of an electronic device of the present invention.

[0022] Figure 7 It is a schematic diagram of the hardware structure of an electronic device of the present invention.

[0023] Wherein, the accompanying drawings are marked as follows:

[0024] 100: Electronic device 10: Command translation device

[0025] 11: Difference comparison module 12: Rule generation module

[0026] 13: Dynamic translation module

[0027] S1, S2, S21, S22, S23, S24, S25, S26, S3: Steps DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings. It should be understood that the specific implementation methods described herein are only used to explain the present invention and are not intended to limit the present invention.

[0029] It should be noted that, in this application, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus.

[0030] Without further constraints, an element defined by the phrase "comprises a..." does not preclude the existence of additional identical elements in the process, method, article or apparatus that includes the element.

[0031] The technical solution of the present invention is intended to translate the binary instruction sequence of the source instruction set architecture into a fully optimized binary instruction sequence of the target instruction set architecture. Based on this expectation, the instruction translation method of the present invention first analyzes the semantic differences between the source instruction set architecture and the target instruction set architecture. Secondly, based on the semantic differences between the instruction sets and combined with statistical analysis of actual binary codes, corresponding translation methods are designed for several instruction sequences of the source instruction set architecture. The binary file of the source instruction set architecture is input into the binary translation system provided by the present invention, and the source instruction set architecture binary file is scanned instruction by instruction several times to find the instruction sequence involved in the present invention. If the instruction sequence involved in the present invention is encountered, a corresponding mark is set and the instruction sequence is recorded in a dedicated table. The binary instructions of the source instruction set architecture are then translated. If a corresponding mark is encountered and the instruction sequence exists in the record table, the optimized translation is performed according to the specific translation method provided by the present invention; otherwise, the translation is performed according to the conventional translation method. The above steps are repeated until the entire source instruction set architecture binary file is translated, and the optimized target instruction sequence is finally output.

[0032] Figure 1 This is a flow chart of the instruction translation method in the dynamic binary translation of the present invention. Figure 1As shown, in the first embodiment of the present invention, a method for instruction translation in dynamic binary translation is proposed. The following uses binary translation from X86 to RISC-V as an example to illustrate the translation method of the present invention. The same principle applies to binary translation from X86 to other RISC instruction sets (such as ARM).

[0033] The instruction translation method of the present invention comprises:

[0034] Step S1, analyzing and obtaining the differences between the source instruction set architecture and the target instruction set architecture, and identifying a specific instruction sequence in the source instruction set relative to the target instruction set;

[0035] This paper analyzes the semantic differences between the X86 and RISC-V architectures. As a complex instruction set, X86 uses the concept of "flags" in arithmetic and logical operations to store intermediate computational steps. X86 platforms utilize dedicated flag registers and corresponding computation logic within their hardware circuitry. These registers primarily store additional results of executing related instructions, provide a basis for executing related instructions, and control the CPU's operating mode. RISC-V, an emerging reduced instruction set architecture, lacks dedicated flag registers and corresponding flag computation circuitry to maintain simplicity and consistency within its instruction set. Therefore, in binary translation from X86 to RISC-V, additional RISC-V instructions are required to emulate X86 flag computations to maintain semantic consistency and prevent information loss. In actual binary translation, the flag changes caused by a single arithmetic or logical operation in an X86 instruction often require 10 to 30 additional RISC-V instructions to emulate these changes. Such translation will result in the number of instructions in the target platform being much greater than the number of instructions in the source platform, which will cause higher code bloat and reduce binary translation performance.

[0036] The specific instruction sequence of this embodiment includes an instruction sequence involving a flag bit, but the present invention is not limited thereto.

[0037] Step S2: Designing translation rules for specific instruction sequences based on the target instruction set architecture. The translation rules generate optimized target instructions based on operand information of the source instruction pattern to reduce the number of target instructions. The translation rules may include merging multiple source instructions into a single or multiple target instructions to reduce the number of target instructions.

[0038] Based on semantic differences, a translation method is designed for specific instruction sequences in the source instruction set architecture. If a flag bit modified by an instruction is not used in a subsequent instruction, or is modified again before being used, the flag bit modification by that instruction is redundant. For example, in the X86 instruction set, the JG (Jump if Greater) instruction compares two signed integers and jumps to the target address if the first operand is greater than the second. The JG instruction determines whether to jump based on the values of the sign flag (SF), overflow flag (OF), and zero flag (ZF). The logic is: if SF = OF and ZF = 0, jump to the target address; otherwise, continue to execute the next instruction. The CMP instruction compares two operands and performs a subtraction operation on them, but does not store the result and only updates the flag register. Because the JG instruction requires the ZF, OF, and SF flags, nearly 30 additional RISC-V instructions are required to emulate the calculation of these three flags. Compared with the original two X86 instructions, serious code expansion occurs.

[0039] However, through semantic difference analysis, it was found that when CMP and JG instructions appear in pairs and the modification of the flag bit by CMP is not used by subsequent instructions, the BLT instruction provided in the RISC-V instruction set can be used. After reasonable register mapping, only one target instruction is needed to complete the translation, which can greatly reduce the redundancy of target instructions.

[0040] Similar to the above example, after designing several instruction sequence translation methods and implementing them in the binary translation system, the binary file of the source instruction set architecture can be input. The binary translation system scans the binary file of the source instruction set architecture and recognizes each instruction one by one. Figure 2 Shown, including:

[0041] Step S21, sequentially scanning the basic blocks of the source instruction set, and first scanning to set "modify" and "use" flags for the instructions related to the flag bits;

[0042] Step S22, scanning again, when encountering a Jcc type conditional jump instruction, start searching backward until encountering the first instruction included in the preset instruction sequence and marked with "modify";

[0043] Step S23: If no other "modify" mark is found in the search, proceed to step S24; otherwise, return to step S22;

[0044] Step S24, recording the pair of instructions into a dedicated table;

[0045] In step S25, if all basic blocks are scanned, the process proceeds to step S26; otherwise, the process returns to step S22 and repeats the scanning operation until the entire code block is scanned.

[0046] Step S26: Translate the code blocks in sequence to generate an optimized target instruction sequence.

[0047] The pseudo code of the proposed flag instruction sequence translation optimization algorithm is as follows: Figure 3 As shown in Figure 1, line 1 defines the input X86_64 instruction stream I and the output optimized native instruction stream O. Line 3 initializes the flag instruction sequence record table P, which is used to store instruction sequences that modify flags, such as CMP. In lines 4-16 of the algorithm, the input instruction stream is traversed and each instruction is processed.

[0048] First, on lines 6-7, if the current instruction is a flag-modifying instruction such as CMP, its operands are extracted and recorded in the flag instruction sequence record table P. Then, on lines 8-9, if the current instruction is a conditional jump instruction Jcc and its predecessor exists in the instruction sequence record table P, the corresponding CMP instruction sequence is searched in P. On lines 10-11, if the search is successful, an optimized jump instruction is generated based on the sequence and added to the optimized instruction stream O.

[0049] For other instructions that do not meet the above conditions, in line 13, they are translated into local instructions according to the default rules and added to the optimized instruction stream O. Finally, the optimized local instruction stream O is returned.

[0050] Step S3, based on the translation rules obtained in step S2, the source instruction set is dynamically binary translated; during the dynamic binary translation process, a specific instruction sequence in the source instruction set architecture binary file is detected; for the detected specific instruction sequence, predefined translation rules are used for translation, and for the ordinary instruction sequence in the source instruction set architecture binary file, conventional translation methods are used for translation.

[0051] During the translation process, a flag instruction sequence record table is used to store the operand information of the instruction. The flag instruction sequence record table is used to match subsequent conditional jump instructions (Jcc) to optimize the translation of conditional jump instructions and generate optimized target instruction set architecture instructions.

[0052] Taking the binary translation from X86 to RISC-V as an example, some instruction sequence translation rules are as follows Figure 4As shown. The source instruction sequence refers to the instruction sequence in the source instruction set architecture to which the present invention relates. Generating a target instruction sequence refers to the corresponding instruction sequence on the target platform after the source platform instruction sequence is binary translated. Semantics refers to the overall meaning expressed by the combination of specific instruction sequences. Only some translation rules are listed in the figure, and the content of the present invention includes but is not limited to the instruction sequence in the figure.

[0053] The above instruction translation method can effectively reduce the target code expansion rate and improve the performance of dynamic binary translation by reducing redundant flag generation operations.

[0054] It should be noted that in various embodiments of the present invention, the size of the serial numbers of the above-mentioned steps does not mean the order of execution. The order of execution of each step should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0055] The following is a system embodiment corresponding to the above method embodiment. This embodiment can be implemented in conjunction with the above embodiment. The relevant technical details mentioned in the above embodiment are still valid in this embodiment and will not be repeated here to reduce repetition. Accordingly, the relevant technical details mentioned in this embodiment can also be applied to the above embodiment.

[0056] Figure 5 Schematic diagram of the instruction translation device in the dynamic binary translation of the present invention. Figure 5 As shown, in a second embodiment of the present invention, a command translation device 10 is provided, comprising:

[0057] a difference comparison module 11, configured to obtain the difference between the source instruction set architecture and the target instruction set architecture, and identify a specific instruction sequence in the source instruction set;

[0058] A rule generation module 12, configured to design a translation rule for the specific instruction sequence based on a target instruction set architecture;

[0059] The dynamic translation module 13 is used to detect a specific instruction sequence in the source instruction set architecture binary file during the dynamic binary translation process; for the detected specific instruction sequence, the corresponding translation rules are used for translation, and for the ordinary instructions other than the specific instruction sequence in the source instruction set architecture binary file, the conventional translation method is used for translation.

[0060] In a third embodiment of the present invention, a computer-readable storage medium is proposed. The function of the instruction translation device in the dynamic binary translation of the present invention, if implemented as a software functional unit and sold or used as an independent product, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or the portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a computer-readable storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present invention. Therefore, in a third embodiment of the present invention, a computer-readable storage medium is provided for storing a computer program for an instruction translation method in dynamic binary translation. It should be understood that the computer-readable storage medium in the embodiments of the present invention can be a volatile memory and / or a non-volatile memory. Among them, the non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of random access memory (RAM) are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus RAM (DRRAM).

[0061] Figure 6 Schematic diagram of an electronic device of the present invention. Figure 6As shown, in the fourth embodiment of the present invention, an electronic device 100 is proposed, including the instruction translation device 10 in the dynamic binary translation as described above. Those skilled in the art will understand that all or part of the steps in the above method can be completed by instructing related hardware (such as a processor, FPGA, ASIC, etc.) through a program. All or part of the steps in the above embodiment can also be implemented using one or more integrated circuits. Accordingly, each module in the above embodiment can be implemented in the form of hardware, such as implementing its corresponding functions through an integrated circuit, or can be implemented in the form of a software function module, such as implementing its corresponding functions through a processor executing a program / instruction stored in a memory. The embodiments of the present invention are not limited to any specific form of combination of hardware and software.

[0062] It should be noted that the structure of the electronic device shown in the drawings of the present invention does not constitute a limitation thereto, and the actual knowledge structure recognition device may include more or fewer components than shown in the drawings, or a combination of certain components, or a different arrangement of components.

[0063] The electronic device of the present invention may be any device with data processing capabilities, such as a computer or other device. Device embodiments may be implemented through software, hardware, or a combination of software and hardware. For example, a device implemented in software, as a logical device, is formed by a processor of any device with data processing capabilities reading corresponding computer program instructions from a non-volatile memory into memory and executing them. Figure 5 This is a schematic diagram of the hardware structure of an electronic device of the present invention. Figure 5 As shown in the figure, from the hardware level, it is a hardware structure diagram of any device with data processing capability where the instruction translation device in the dynamic binary translation of the present invention is located. Figure 5 In addition to the processor, memory, network interface, and non-volatile memory shown, any device with data processing capabilities in which the apparatus in the embodiment is located may also include other hardware, generally based on the actual functions of the device with data processing capabilities, which will not be described in detail.

[0064] When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product comprises one or more computer instructions or computer programs. When loaded or executed on a computer, the processes or functions described in accordance with the embodiments of the present invention are fully or partially performed. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired means (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium accessible by a computer or a data storage device such as a server or data center that contains a collection of one or more available media. The available medium can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media. The semiconductor media can be a solid-state drive.

[0065] The instruction translation method in the dynamic binary translation of the present invention is used to optimize the binary translation efficiency in computer systems. It can not only eliminate redundant instructions, but also further compress existing flag calculation operations without affecting the program semantics, thereby significantly reducing target instruction redundancy, obtaining a larger optimization space, and reducing target code instruction expansion to a greater extent.

[0066] The above embodiments are only used to illustrate the present invention, and are not intended to limit the present invention. Ordinary technicians in the relevant technical field may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, all equivalent technical solutions also fall within the scope of the present invention. The scope of patent protection of the present invention should be defined by the claims.

Claims

1. A method for translating instructions in dynamic binary translation, characterized in that: include: Obtaining the difference between a source instruction set architecture and a target instruction set architecture, identifying a specific instruction sequence in the source instruction set, the specific instruction sequence including an instruction sequence involving flag bits in the source instruction set, the instruction sequence involving flag bits including instructions for modifying flag bits and instructions for using flag bits; wherein the process of identifying the specific instruction sequence includes: sequentially scanning basic blocks of the source instruction set, setting scanned instructions related to flag bits to "modify" and "use" marks; scanning again, and when encountering a Jcc-type conditional jump instruction, starting a backward search until encountering the first instruction contained in a preset instruction sequence and marked with "modify", thereby forming the specific instruction sequence; Designing a translation rule for the specific instruction sequence based on the target instruction set architecture; During the dynamic binary translation process, a specific instruction sequence in the source instruction set architecture binary file is detected; for the detected specific instruction sequence, the corresponding translation rules are used for translation.

2. The instruction translation method according to claim 1, wherein: The translation rule includes: merging multiple source instructions in the specific instruction sequence into one or more target instructions.

3. The instruction translation method according to claim 1, wherein: Also includes: For common instructions in the source instruction set architecture binary file except for the specific instruction sequence, a conventional translation method is used for translation.

4. An instruction translation device in dynamic binary translation, characterized in that: include: a difference comparison module, configured to obtain a difference between a source instruction set architecture and a target instruction set architecture, and identify a specific instruction sequence in the source instruction set, wherein the specific instruction sequence includes an instruction sequence in the source instruction set involving flag bits, and the instruction sequence involving flag bits includes instructions for modifying flag bits and instructions for using flag bits; wherein the process of identifying the specific instruction sequence includes: sequentially scanning basic blocks of the source instruction set, setting scanned instructions related to flag bits to "modify" and "use" marks; scanning again, and when encountering a Jcc-type conditional jump instruction, starting a backward search until encountering the first instruction contained in a preset instruction sequence and marked with "modify", thereby forming the specific instruction sequence; A rule generation module, configured to design a translation rule for the specific instruction sequence based on the target instruction set architecture; The dynamic translation module is used to detect a specific instruction sequence in a source instruction set architecture binary file during the dynamic binary translation process; for the detected specific instruction sequence, the corresponding translation rules are used for translation.

5. The instruction translation device according to claim 4, wherein: The translation rule includes: merging multiple source instructions in the specific instruction sequence into one or more target instructions.

6. The instruction translation device according to claim 4, wherein: The dynamic translation module further includes: translating common instructions other than the specific instruction sequence in the source instruction set architecture binary file using a conventional translation method.

7. An electronic device comprising the instruction translation device in dynamic binary translation according to any one of claims 4 to 6.

8. A computer-readable storage medium storing computer-executable instructions, characterized in that: When the computer-executable instruction is executed, the instruction translation method in the dynamic binary translation according to any one of claims 1 to 3 is implemented.

Images