Memory access violation prediction device and method, chip and computer equipment

Abstract

The invention discloses a memory access violation prediction device and method, a chip and computer equipment, and belongs to the technical field of computers. Comprising a first register group, a second register group, a read-write controller, a first multiplexer and an access instruction transmitting queue, the first register group is used for storing a memory access violation table; the second register group is used for storing a to-be-transmitted counting table; the read-write controller is used for querying a memory access violation table in the first register group based on a first access instruction storage address of the access instruction, and controlling the first register group to transmit a first counting index to a selection input end of the first multiplexer; the first multiplexer is used for selecting a first to-be-transmitted count value corresponding to the access instruction from the to-be-transmitted count table based on the received first count index; and the access instruction transmitting queue is used for storing the access instruction under the condition that the access instruction is received, and controlling to transmit the access instruction based on the first to-be-transmitted count value corresponding to the access instruction.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and in particular to a memory access violation prediction device, method, chip and computer equipment. Background Art

[0002] The main function of the processor in a computer is to store and process input data, perform various mathematical and logical calculations, and provide output data to the user, so that the computer can work. In modern processors, there are related access (load)-storage (store) instructions, and the related storage-access instructions must be processed strictly in the order of storage instructions and access instructions, otherwise semantic errors will occur.

[0003] In the related art, after being decoded, load instructions and store instructions are usually dispatched to the waiting queue of the corresponding computing unit, and wait in the waiting queue to be sent to the computing unit. In this process, usually according to the complete storage order model, before sending the load instruction, it is necessary to first detect whether the store instruction with a dependency relationship with the load instruction is successfully sent. If it is detected that the store instruction is sent, it is determined that the load instruction can be sent.

[0004] However, when instructions are issued according to the complete storage order model, in the process of detecting whether a store instruction is issued, it is usually necessary to wait until all preceding store instructions of the load instruction are calculated before the detection can be performed, resulting in a long detection time, thereby causing a large delay in the load instruction issuance. Summary of the invention

[0005] The embodiment of the present application provides a memory access violation prediction device, method, chip and computer equipment, which increases the accuracy of memory access violation prediction by constructing a to-be-issued count table to control the issuance of access instructions. The technical solution includes the following aspects.

[0006] On the one hand, an embodiment of the present application provides a memory access violation prediction device, the device comprising:

[0007] A first register group, a second register group, a read / write controller, a first multiplexer, and an access instruction issue queue;

[0008] The first register group is used to store a memory access violation table, the memory access violation table is used to indicate memory access violation information and count indexes of historical storage instructions and historical access instructions, the memory access violation information is used to characterize the memory access violation conditions of the historical storage instructions and the historical access instructions, the count index is the index of the entry in the second register group where the to-be-issued count value corresponding to the access instruction is located, and the to-be-issued count value is used to characterize the number of to-be-issued storage instructions having a memory access dependency relationship with the access instruction;

[0009] The second register group is used to store a to-be-issued count table, where the to-be-issued count table is used to represent the to-be-issued count values ​​corresponding to different access instructions;

[0010] The read / write controller is configured to query the memory access violation table in the first register group based on the first access instruction storage address of the access instruction when the access instruction is received, and control the first register group to transmit the first counting index corresponding to the access instruction to the selection input terminal of the first multiplexer when the memory access violation information corresponding to the access instruction indicates that the access instruction has generated a memory access violation;

[0011] The first multiplexer is configured to select, based on the first count index corresponding to the received access instruction, a first to-be-transmitted count value corresponding to the access instruction from the to-be-transmitted count table;

[0012] The access instruction transmission queue is used to save the access instruction when the access instruction is received, and control the transmission of the access instruction based on the first to-be-transmitted count value corresponding to the access instruction.

[0013] On the other hand, an embodiment of the present application provides a memory access violation prediction method, which is used in the memory access violation prediction device as described in the above aspect, and the method includes:

[0014] The read / write controller, when receiving the access instruction, queries the memory access violation table in the first register group based on the first access instruction storage address of the access instruction, and when the memory access violation information corresponding to the access instruction indicates that the access instruction has generated a memory access violation, controls the first register group to transmit the first counting index corresponding to the access instruction to the selection input end of the first multiplexer;

[0015] The first multiplexer selects a first to-be-transmitted count value corresponding to the access instruction from the to-be-transmitted count table based on the first count index corresponding to the received access instruction;

[0016] When receiving the access instruction, the access instruction transmitting queue saves the access instruction and controls the transmitting of the access instruction based on the first to-be-transmitted count value corresponding to the access instruction.

[0017] In some embodiments, the access instruction emission queue includes a third register group, a first numerical comparator and an emission controller. When the access instruction emission queue controls the emission of an access instruction, the third register group stores a first to-be-emitted count value corresponding to the access instruction to be emitted; the first numerical comparator compares the first to-be-emitted count value with 0 to obtain a first comparison result; the emission controller emits the access instruction when the first comparison result indicates that the first to-be-emitted count value is 0, or controls the access instruction to wait for emission when the first comparison result indicates that the first to-be-emitted count value is not 0.

[0018] In some embodiments, the access instruction emission queue also includes a fourth register group, a second numerical comparator and a first subtractor. When the access instruction emission queue controls the emission of an access instruction, the fourth register group stores the first count index corresponding to the access instruction transmitted by the first multiplexer; when the storage instruction emission queue emits a storage instruction, the second count index corresponding to the storage instruction is transmitted to the selection input of the second numerical comparator; the second numerical comparator compares the received second count index with the first count index to obtain a second comparison result; when the second comparison result indicates that the second count index is the same as the first count index, the first subtractor reads the first count value to be emitted corresponding to the access instruction from the third register group based on the second count index; the first subtractor subtracts one from the read first count value to be emitted to obtain a subtraction result, and fills the subtraction result into the entry corresponding to the second count index in the third register group.

[0019] In some embodiments, the read-write controller includes a first hash unit and a query unit. When the read-write controller queries the memory access violation table in the first register group, the first hash unit determines the first memory access violation table index corresponding to the access instruction based on the first access instruction storage address of the access instruction. The first memory access violation table index is used to represent the index of the entry in the memory access violation table where the memory access violation information corresponding to the access instruction is located; the query unit queries the memory access violation table based on the first memory access violation table index to obtain the memory access violation information corresponding to the access instruction and the first counting index.

[0020] In some embodiments, the method also includes: a storage instruction emission queue controls the emission of storage instructions, and transmits a third count index corresponding to the storage instruction to the selection input of a second multiplexer; the second multiplexer selects a second to-be-emitted count value corresponding to the storage instruction from a to-be-emitted count table based on the third count index; a second subtractor performs a subtraction operation on the input second to-be-emitted count value, and fills the subtraction result into the entry corresponding to the third count index in the second register group.

[0021] In some embodiments, the read-write controller includes a second hash unit and a query unit, and the method also includes: the second hash unit determines a second memory access violation table index corresponding to the storage instruction based on the storage instruction storage address of the storage instruction, and the second memory access violation table index is used to represent the index of the entry in the memory access violation table where the memory access violation information corresponding to the storage instruction is located; the query unit queries the memory access violation table based on the second memory access violation table index to obtain the memory access violation information corresponding to the storage instruction and a third counting index.

[0022] In some embodiments, the method also includes: a third multiplexer selects a third count value to be transmitted corresponding to the storage instruction from the count table to be transmitted based on the received third count index, and transmits the third count value to be transmitted to an adder, and the third count index is transmitted from the first register group to the third multiplexer; the adder adds one to the input third count value to be transmitted to obtain an addition result, and fills the addition result into the entry corresponding to the third count index in the second register group.

[0023] In some embodiments, the method further includes: a memory access dependency recorder fills a memory access violation table based on historical storage instructions that have generated memory access violations, instruction storage addresses of historical access instructions, and entry occupancy status of the second register group.

[0024] In some embodiments, the memory access dependency recorder includes a third hash unit and a storage control unit. When the memory access dependency recorder fills the memory access violation table, the third hash unit performs a hash operation on the second access instruction storage address corresponding to the historical access instruction to obtain a third memory access violation table index corresponding to the historical access instruction; the third hash unit performs a hash operation on the second storage instruction storage address corresponding to the historical storage instruction to obtain a fourth memory access violation table index corresponding to the historical storage instruction; the storage control unit fills the entry corresponding to the third memory access violation table index in the memory access violation table with the memory access violation information and the target count index corresponding to the historical access instruction; the storage control unit fills the entry corresponding to the fourth memory access violation table index in the memory access violation table with the memory access violation information and the target count index corresponding to the historical storage instruction.

[0025] In some embodiments, the storage control unit includes a pseudo least recently used unit and an allocation unit. When the memory access dependency recorder fills the memory access violation table, the pseudo least recently used unit accesses the first register group and determines the occupancy of each entry in the second register group based on the count index in the memory access violation table; the pseudo least recently used unit selects a target entry from the second register group for a historical access instruction and a historical storage instruction based on the occupancy of each entry in the second register group, and transmits the target count index of the target entry to the allocation unit; the allocation unit fills the entries corresponding to the fourth memory access violation table index and the third memory access violation table index in the first register group with memory access violation information and the target count index; the allocation unit fills the entries corresponding to the third memory access violation table index in the first register group with memory access violation information and the target count index.

[0026] On the other hand, an embodiment of the present application provides a chip, which includes the memory access violation prediction device as described in the above aspects.

[0027] On the other hand, an embodiment of the present application provides a computer device, which includes a processor and a memory, wherein the processor is connected to the memory via a bus, and the processor is provided with a memory access violation prediction device as described in the above aspect.

[0028] In the embodiment of the present application, in the case of an access instruction to be transmitted, based on the access instruction storage address of the access instruction, the memory access violation table is queried to determine whether the access instruction has generated a memory access violation. In the case of determining that the access instruction has generated a memory access violation, the count table to be transmitted is queried based on the count index corresponding to the access instruction stored in the memory access violation table to determine the count value to be transmitted corresponding to the access instruction, so that the access instruction emission queue controls the emission of the access instruction. The count value stored in the count table to be transmitted represents the number of storage instructions to be transmitted that have a memory access dependency relationship with the access instruction, so that the access instruction emission queue can accurately determine whether the access instruction meets the emission condition according to the count value in the count table to be transmitted, and avoid the generation of memory access violations. In addition, the device shown in the embodiment of the present application only queries the memory access violation table according to the access instruction storage address of the access instruction, and does not need to determine whether there is a memory access dependency relationship between the access instruction and the storage instruction according to the data storage address indicated by the access instruction and the storage instruction, and does not need to wait for all the preceding storage instructions to be calculated before detection, thereby reducing the emission delay of the access instruction. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0030] Figure 1 A schematic diagram of a memory access dependency is shown;

[0031] Figure 2 A schematic diagram of the structure of a memory access violation prediction device provided by an exemplary embodiment of the present application is shown;

[0032] Figure 3 A schematic diagram of the structure of an access instruction emission queue provided by an exemplary embodiment of the present application is shown;

[0033] Figure 4 A schematic diagram of updating a fourth register group provided by an exemplary embodiment of the present application is shown;

[0034] Figure 5 A schematic diagram showing an update of a pending transmission count table provided by an exemplary embodiment of the present application is shown;

[0035] Figure 6 A schematic diagram of updating a second register group provided by an exemplary embodiment of the present application is shown;

[0036] Figure 7 A schematic diagram of updating a memory access violation table provided by an exemplary embodiment of the present application is shown;

[0037] Figure 8 A schematic diagram showing the structure of a memory access violation prediction device provided by another embodiment of the present application is shown;

[0038] Fig. 9 A flowchart of a memory access violation prediction method provided by an embodiment of the present application is shown;

[0039] Fig.10 A structural block diagram of a computer device provided by an exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0040] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0041] Nowadays, memory access performance determines the upper limit of processor performance, and there may be a dependency between access instructions (load) and storage instructions (store). For example, the storage instruction indicates a write operation to address A, and the access instruction is a read operation to address A. In this case, the data needs to be written to address A first and then address A is accessed to read the data from it.

[0042] For illustration, please refer to Figure 1 , which shows a schematic diagram of memory access dependency. Wherein, pc (Program Counter) is the storage address of the instruction, store A is a write operation on the address A of the memory, and load A is a read operation on the address A of the memory. In the figure, the two instructions with instruction storage addresses of 0 and 24 both perform read and write operations on the address A in the memory, and the three instructions with instruction storage addresses of 8, 12 and 20 all perform read and write operations on the address B in the memory. Therefore, there is a memory access dependency between the two instructions with instruction storage addresses of 0 and 24, and there is a memory access dependency between the three instructions with instruction storage addresses of 8, 12 and 20. The load B instruction with pc=20 depends on the write results of the store B instruction with pc=8 and 12, and the loadA instruction with pc=24 depends on the write result of the storeA instruction with pc=0.

[0043] During the process of issuing a load instruction, if the issuing status of the store instruction on which the load instruction depends is not detected, the store instruction may not be issued yet, but the load instruction with dependency may be issued first. In this case, when the load instruction is executed to access the memory, the data read is the old value stored in the storage address, resulting in data error of the load instruction. In this case, the entire instruction pipeline needs to be redirected and the load instruction needs to be re-executed.

[0044] In the related art, there are multiple models for accessing memory, such as the complete sequential model and the complete storage sequencing model. In the complete sequential model, it is required that all read and write operations (storage instructions + access instructions) of the external memory must be performed in complete sequence, so as to ensure that the access instruction is issued after the storage instruction is issued. In the complete storage sequencing model, the issuance of the storage instruction will be detected before the access instruction is issued, and it is necessary to wait until the address of the preceding storage instruction is fully calculated before the detection.

[0045] However, in the solution provided by the related technology, it is necessary to wait for the data addresses indicated by the preceding storage instructions to be fully calculated, and then determine whether the store instruction that has a dependency on the load instruction has been issued based on the data storage address. The detection delay is large, which has a great impact on the performance of the processor.

[0046] Therefore, an embodiment of the present application provides a memory access violation prediction device, which controls the issuance of access instructions by querying a to-be-issued count table based on the instruction storage addresses of access instructions and storage instructions, thereby increasing the accuracy of memory access violation prediction.

[0047] Please refer to Figure 2 , which shows a schematic diagram of the structure of a memory access violation prediction device provided by an exemplary embodiment of the present application. The memory access violation prediction device includes a first register group 210, a second register group 220, a read / write controller 230, a first multiplexer 240 and an access instruction issuance queue 250.

[0048] The first register group 210 is connected to the read / write controller 230; the first register group 210 is connected to the selection input end of the first multiplexer 240; the output end of the second register group 220 is connected to the data input end of the first multiplexer 240, and the output end of the first multiplexer 240 is connected to the access instruction emission queue 250;

[0049] The first register group 210 is used to store a memory access violation table.

[0050] Among them, the memory access violation table is used to indicate the memory access violation information and counting index of historical storage instructions and historical access instructions, the memory access violation information is used to characterize the memory access violation situations of historical storage instructions and historical access instructions, the counting index refers to the index of the entry in the second register group where the to-be-emitted count value corresponding to the access instruction is located, and the to-be-emitted count value is used to characterize the number of to-be-emitted storage instructions that have a memory access dependency relationship with the access instruction.

[0051] In some embodiments, the first register group is a first register array, and the first register array includes two register groups, and the two register groups are respectively used to store memory access violation information and count index. In addition, in the two register groups, different instructions correspond to different registers, and the index corresponding to the access instruction indicates the register number corresponding to the access instruction. The register where the memory access violation information corresponding to the same access instruction is located and the register where the count index is located constitute the same entry.

[0052] Optionally, the value of the memory access violation information is 0 or 1, where 0 indicates that the access instruction does not generate an over-memory access violation, and 1 indicates that the access instruction generates an over-memory access violation. Alternatively, the value of the memory access violation information is true or false, where false indicates that the access instruction does not generate an over-memory access violation, and true indicates that the access instruction generates an over-memory access violation.

[0053] Optionally, the value range of the count index is related to the depth of the second register group, the minimum value of the count index is 0, corresponding to the 0th entry in the second register group, and the maximum value of the count index is the same as the depth value of the second register.

[0054] The depth of the first register group may be configured according to actual applications, which is not limited in this embodiment.

[0055] Furthermore, the reading and writing logic of the data in the first register group is controlled by the read-write controller.

[0056] It should be noted that the memory access violation information and the counting index in the memory access violation table will not change according to the issuance of the access instruction and the storage instruction.

[0057] The second register group 220 is used to store a to-be-issued count table, where the to-be-issued count table is used to represent to-be-issued count values ​​corresponding to different access instructions.

[0058] The depth of the second register group may be configured according to actual applications, which is not limited in this embodiment.

[0059] Optionally, the second register group is composed of a plurality of registers, and different registers correspond to different access instructions. The second register group also corresponds to a read / write controller for controlling the reading and writing of data in the second register group.

[0060] The pending-to-be-issued count value in the pending-to-be-issued count table will change according to the issuance of the storage instruction and the access instruction. Since the pending-to-be-issued count value is used to represent the number of pending-to-be-issued storage instructions that have a memory access dependency relationship with the access instruction, after the pending-to-be-issued storage instruction that has an access dependency relationship with the access instruction is issued, the pending-to-be-issued count value will also decrease accordingly.

[0061] Optionally, the pending-to-be-emitted count value is used to characterize the number of pending-to-be-emitted storage instructions that have a memory access dependency relationship with the access instruction. If the pending-to-be-emitted count value is 0, it means that the number of pending-to-be-emitted storage instructions that have a memory access dependency relationship with the access instruction is 0, which means that all pending-to-be-emitted storage instructions that have a memory access dependency relationship with the access instruction have been completed.

[0062] The pending issuance count values ​​stored in the pending issuance count table are all corresponding to the access instructions that have generated the over-access violation, while the access instructions that have not generated the over-access violation can directly enter the access instruction issuance queue for issuance.

[0063] The read-write controller 230 is used to query the memory access violation table in the first register group based on the first access instruction storage address of the access instruction when an access instruction is received, and control the first register group to transmit the first counting index corresponding to the access instruction to the selection input end of the first multiplexer when the memory access violation information corresponding to the access instruction indicates that the access instruction has generated a memory access violation.

[0064] The read / write controller can determine the entry index corresponding to the access instruction in the first register according to the first access instruction storage address of the access instruction, and then query the memory access dependency table according to the index to determine whether the access instruction generates a memory access violation.

[0065] In the case of a memory access violation in the access instruction, it is necessary to determine whether the access instruction meets the emission condition according to the emission status of the storage instructions to be emitted that have a memory access dependency relationship with the access instruction. In the case that all the storage instructions that have a dependency relationship with the access instruction are emitted, it indicates that the access instruction meets the emission condition.

[0066] When the read-write controller queries the memory access violation table and determines that the memory access violation information corresponding to the access instruction indicates that the access instruction has generated a memory access violation, the read-write controller controls the first register group to transmit the first count index to the first multiplexer, so that the access instruction transmission queue can control the access instruction transmission according to the count value to be transmitted read by the first multiplexer.

[0067] The first multiplexer 240 is configured to select a first to-be-transmitted count value corresponding to the access instruction from the to-be-transmitted count table based on a first count index corresponding to the received access instruction.

[0068] The first multiplexer includes multiple data input terminals and a selection input terminal, different data input terminals are connected to output terminals of different registers in the second register group, and the selection input terminal is connected to the output terminal of the first register group to receive the first count index determined by the read-write controller.

[0069] During the operation of the multiplexer, a data input terminal is selected from multiple data input terminals to receive data according to the information input from the selection input terminal, so as to select a register from multiple registers to read the count value to be transmitted stored therein. For example, if the determined first count index is 3, the multiplexer sets the third data input terminal and the third register as a path to read the first count value to be transmitted from the third register.

[0070] In addition, after the third multiplexer reads the first count value to be transmitted, it will also transmit the first count value to be transmitted to the access instruction transmission queue through the output end, so that the access instruction transmission queue controls the transmission of the access instruction based on the first count value to be transmitted.

[0071] The access instruction emission queue 250 is used to save the access instruction when receiving the access instruction, and control the emission of the access instruction based on the first to-be-emitted count value corresponding to the access instruction.

[0072] The first to-be-issued count value represents the number of storage instructions to be issued that have a memory access dependency relationship with the access instruction. If there are storage instructions with a memory access dependency relationship with the access instruction that have not been issued, the access instruction does not meet the issuance condition; if there are no storage instructions with a memory access dependency relationship with the access instruction that have not been issued, the access instruction meets the issuance condition.

[0073] In the embodiment of the present application, the access instruction and the storage instruction are used as the input of the memory access violation prediction device. Since there may be access instructions and emission instructions with memory access violation relations, when the access instruction is received, the memory access violation prediction device needs to determine whether all storage instructions with memory access violation relations with the access instruction have been emitted. Therefore, when the access instruction is received, on the one hand, the memory access instruction emission queue saves the access instruction, and on the other hand, the read-write controller queries the memory access violation table to determine whether the memory access instruction has generated a memory access violation. In the case of a memory access violation, the first to-be-emitted count value corresponding to the access instruction is transmitted to the access instruction emission queue through the first multiplexer, so that the access instruction emission queue can control the emission of the access instruction based on the first to-be-emitted count value to avoid a memory access violation.

[0074] In summary, in the embodiment of the present application, in the case of an access instruction to be transmitted, based on the access instruction storage address of the access instruction, the memory access violation table is queried to determine whether the access instruction has generated an access violation. In the case of determining that the access instruction has generated an access violation, the count table to be transmitted is queried based on the count index corresponding to the access instruction stored in the memory access violation table to determine the count value to be transmitted corresponding to the access instruction, so that the access instruction emission queue controls the emission of the access instruction. The count value stored in the count table to be transmitted represents the number of storage instructions to be transmitted that have a memory access dependency relationship with the access instruction, so that the access instruction emission queue can accurately determine whether the access instruction meets the emission condition according to the count value in the count table to be transmitted, and avoid the generation of memory access violations. In addition, the device shown in the embodiment of the present application only queries the memory access violation table according to the access instruction storage address of the access instruction, and does not need to determine whether there is a memory access dependency relationship between the access instruction and the storage instruction according to the data storage address indicated by the access instruction and the storage instruction, and does not need to wait for all the preceding storage instructions to be calculated before detection, thereby reducing the emission delay of the access instruction.

[0075] Since the pending issuance count value is used to represent the number of pending storage instructions that have a memory access dependency relationship with the access instruction, in order to determine whether the access instruction meets the issuance conditions, the access instruction issuance queue needs to determine whether all pending storage instructions that have a memory access dependency relationship with the access instruction have been issued.

[0076] In one possible design, the access instruction issue queue includes a third register group, a first value comparator, and an issue controller;

[0077] The input end of the first numerical comparator is connected to the output end of the third register group, and the output end of the first numerical comparator is connected to the transmission controller.

[0078] The third register group is used to store a first to-be-issued count value corresponding to the to-be-issued access instruction.

[0079] After the third multiplexer transmits the first count value to be transmitted to the access instruction transmission queue, the access instruction transmission queue stores the first count value to be transmitted corresponding to each received access instruction in the third register group. The first count values ​​to be transmitted corresponding to different access instructions in the third register group are stored in different registers.

[0080] The first numerical comparator is used to compare the first to-be-transmitted count value with 0 to obtain a first comparison result.

[0081] Among them, there may be two possible situations for the first comparison result. When all the storage instructions to be issued that have a memory access dependency relationship with the access instruction have been issued, the first count value to be issued should be equal to 0; when all the storage instructions to be issued that have a memory access dependency relationship with the access instruction have not been issued, the first count value to be issued should be greater than 0.

[0082] The transmission controller is used to transmit the access instruction when the first comparison result indicates that the first to-be-transmitted count value is 0, or to control the access instruction to wait for transmission when the first comparison result indicates that the first to-be-transmitted count value is not 0.

[0083] When the first comparison result indicates that the first count value to be emitted is 0, it means that all the storage instructions to be emitted that have a memory access dependency relationship with the access instruction have been emitted, and the emission condition of the access instruction is met; and when the first comparison result indicates that the first count value to be emitted is not 0, it means that not all the storage instructions to be emitted that have a memory access dependency relationship with the access instruction have been emitted, and the emission condition of the access instruction is not met.

[0084] If the emission condition of the access instruction is not met, the access instruction shall wait for emission in the access instruction emission queue and be emitted if the emission condition is met. The process of the access instruction waiting for emission in the emission queue is the process of the access instruction being stored in the access instruction emission queue and waiting for all storage instructions that have access dependency with the access instruction to complete emission. Therefore, after the storage instruction that has memory dependency with the access instruction is emitted, the first count value to be emitted is updated, and then it is re-determined whether the emission condition is met.

[0085] In a possible design, the memory access violation prediction device further includes a storage instruction issuance queue, and the access instruction issuance queue further includes a fourth register group, a second numerical comparator, and a first subtractor.

[0086] The output end of the fourth register group is connected to the first input end of the second numerical comparator, and the output end of the storage instruction issuance queue is connected to the second input end of the second numerical comparator; the output end of the second numerical comparator is connected to the first subtractor; the input end of the first subtractor is connected to the third register group, and the output end of the first subtractor is connected to the input end of the third register group.

[0087] The fourth register group is used to store the first counting index corresponding to the access instruction transmitted by the first multiplexer.

[0088] The storage instruction issuing queue is used to transmit the second counting index corresponding to the storage instruction to the selection input terminal of the second numerical comparator when issuing the storage instruction.

[0089] A second numerical comparator, used to compare the received second counting index with the first counting index to obtain a second comparison result;

[0090] In the embodiment of the present application, in the memory access dependency table, the count index values ​​corresponding to the storage instruction and the access instruction having the memory access dependency are the same. Then, in the access instruction emission queue, in order to determine whether the emitted storage instruction has a memory access dependency relationship with the access instruction, it is possible to determine whether the emitted storage instruction has a memory access dependency relationship with the access instruction by comparing the count indexes corresponding to the emitted storage instruction and the access instruction.

[0091] The fourth register stores first counting indexes corresponding to different access instructions transmitted by the first multiplexer. When making a judgment, the first counting indexes corresponding to different access instructions are compared with the second counting indexes respectively.

[0092] When the first counting index and the second counting index of an access instruction are the same, it is determined that the transmitted storage instruction has a memory access dependency relationship with the access instruction, and the count value to be transmitted corresponding to the access instruction can be adjusted; when the first counting index and the second counting index of an access instruction are not the same, it is determined that the transmitted storage instruction has no memory access dependency relationship with each access instruction, and the access instruction continues to wait for transmission.

[0093] A first subtractor, configured to read a first to-be-transmitted count value corresponding to the access instruction from the third register group based on the second count index when the second comparison result indicates that the second count index is the same as the first count index;

[0094] The first subtractor is further used to perform a subtraction operation on the read first count value to be transmitted to obtain a subtraction result, and fill the subtraction result into the entry corresponding to the first count index in the third register group.

[0095] In the case where the first count index of an access instruction is the same as the second count index, the first subtractor needs to first read the first count value to be transmitted corresponding to the access instruction from the third register group, and then subtract one from the first count value to be transmitted, and then re-fill the first count value to be transmitted into the entry corresponding to the first count index.

[0096] Indicatively, Figure 3 As shown, it shows a schematic diagram of the structure of an access instruction emission queue provided by an exemplary embodiment of the present application. In the figure, the access instruction emission queue includes a third register group, a first numerical comparator, an emission controller, a first numerical comparator and an emission controller. Different access instructions and a first counting index corresponding to the access instruction are stored in the fourth register group. The second comparator compares the first counting index with the second counting index to determine whether the storage instruction that has been emitted is a dependency instruction of the access instruction. And when the first counting index is the same as the second counting index, it is determined that the storage instruction that has been emitted has a dependency relationship with the access instruction, then the first count value to be emitted is subtracted by one by a subtractor, and then the subtraction result is filled into the entry corresponding to the first counting index in the third register group. Finally, the updated first count value to be emitted is compared with 0 by the first comparator. When the first count value is 0, the access instruction is emitted. When the first count value to be emitted is not 0, the access instruction is continued to be controlled to wait for emission.

[0097] For illustration, please refer to Figure 4 , which shows a schematic diagram of updating the fourth register group provided by an exemplary embodiment of the present application.

[0098] Assume that there is an access instruction load A, whose corresponding count index is 1, and the to-be-transmitted count value corresponding to the count index is also 1. When the transmit instruction transmission queue receives the count index (issue_OCT_index) corresponding to the sent storage instruction (store A), a numerical comparator is used to determine whether issue_OCT_index is the same as the count index (load_OCT_index) corresponding to the access instruction (load A) to be transmitted in the transmission queue. When the issue_OCT_index of store A is also 1, the to-be-transmitted count value corresponding to load A in the fourth register is reduced by one, and the subtraction result is 0. Then the to-be-transmitted count value corresponding to load A is 0, and load A is transmitted.

[0099] In the embodiment of the present application, by comparing the first to-be-emitted count value corresponding to different access instructions stored in the third register group with 0, it is determined whether the access instruction meets the emission condition. This is conducive to accurately determining the emission condition of the access instruction. In addition, after the storage instruction is emitted, it is determined according to the count index whether the emitted storage instruction has a memory access dependency relationship with the access instruction, and the emission status of the access instruction can be determined in real time according to the emission status of the storage instruction, without waiting for the data storage addresses corresponding to all storage instructions to be calculated, thereby reducing the emission delay of the access instruction.

[0100] In the embodiment of the present application, the read / write controller is used to query the memory access violation table in the first register group based on the first access instruction storage address of the access instruction. In the process of querying the memory access violation table, it is first necessary to determine the memory access violation table index corresponding to the access instruction, and then query according to the index.

[0101] In one possible design, the read-write controller includes a first hash unit and a query unit;

[0102] The first hash unit is used to determine a first memory access violation table index corresponding to the access instruction based on a first access instruction storage address of the access instruction, wherein the first memory access violation table index is used to represent the index of an entry in the memory access violation table where the memory access violation information corresponding to the access instruction is located.

[0103] Optionally, the hash unit performs an XOR operation on the first access instruction storage address of the access instruction to obtain a first memory access violation table index corresponding to the access instruction.

[0104] Different access instructions have different instruction storage addresses, so the first memory access violation table indexes of different access instructions are different.

[0105] The query unit is used to query the memory access violation table based on the first memory access violation table index to obtain the memory access violation information corresponding to the access instruction and the first counting index.

[0106] After obtaining the first memory access violation table index, the hash unit sends the first memory access violation table index to the query unit, so that the query unit can query the entry corresponding to the first memory access violation table index in the memory access violation table to obtain the memory access violation information corresponding to the access instruction and the first counting index.

[0107] After obtaining the memory access violation information and the first counting index, when the memory access violation information indicates that the access instruction has generated a memory access violation, the read-write controller transmits the first counting index to the first multiplexer, so that the first multiplexer obtains the first to-be-transmitted count value corresponding to the first counting index. In addition, the read-write controller also transmits the first counting index to the access instruction transmission queue, so that the access instruction transmission queue determines whether the transmitted storage instruction has a memory access dependency relationship with the access instruction.

[0108] For illustration, please refer to Figure 5 , which shows a schematic diagram of updating the to-be-issued count table provided by an exemplary embodiment of the present application. In the case of receiving a newly dispatched storage instruction, the value of the storage instruction storage address (store A_pc) of the storage instruction after hash calculation is 1, then the query unit queries the entry with index 1 in the memory access violation table (i.e., entry1) to determine that the memory access violation information corresponding to the storage instruction is 1, indicating that the storage instruction has generated an over-memory access violation, and the query unit can obtain the count index corresponding to the storage instruction as 1, then the count value in the entry (entry1) with count index 1 in the memory access violation table is added by one by the adder. Subsequently, if the value of the access instruction storage address (load A_pc) of the newly dispatched access instruction after hash calculation is 3, the query unit queries the entry with index 3 in the memory access violation table to determine that the access instruction has generated an over-memory access violation, and the count index corresponding to the memory access violation is 3, then the read-write controller sends the count index to the third multiplexer, and the third multiplexer reads the count value in entry3 in the second register group and transmits it to the access instruction emission queue.

[0109] The emission of a storage instruction that has a memory access dependency with an access instruction will affect the emission of the access instruction. When a new storage instruction with a memory access dependency is added, the to-be-emitted count value corresponding to the access instruction should be increased by one. When a storage instruction with a memory access dependency has been emitted, the to-be-emitted count value corresponding to the access instruction should be reduced by one.

[0110] In one design, the memory access violation prediction device further includes: a storage instruction issue queue, a second multiplexer, and a second subtractor.

[0111] The selection input end of the second multiplexer is connected to the output end of the storage instruction issue queue, and the data input end of the second multiplexer is connected to the output end of the second register group; the output end of the second multiplexer is connected to the input end of the second subtractor, and the output end of the second subtractor is connected to the input end of the second register group;

[0112] a storage instruction emission queue, used for controlling the emission of the storage instruction and transmitting the third counting index corresponding to the storage instruction to the selection input terminal of the second multiplexer;

[0113] The store instruction issuance queue (store IQ) is used to control the issuance of store instructions. After receiving the dispatched store instructions, the store instruction issuance queue sends different store instructions in sequence.

[0114] Optionally, the storage instruction emitted by the storage instruction emission queue may or may not generate an over-memory access violation. Therefore, in order to enable the access instruction emitter to determine whether the storage instruction has a memory access dependency with the access instruction to be emitted in the access queue, the storage instruction emission queue sends the count index of the emitted storage instruction to the access instruction emission queue.

[0115] Optionally, when the storage instruction generates an over-access violation, in order to update the to-be-issued count table, the storage instruction issue queue transmits a third count index corresponding to the storage instruction to the second multiplexer.

[0116] A second multiplexer, configured to select, based on a third count index, a second to-be-transmitted count value corresponding to the storage instruction from the to-be-transmitted count table;

[0117] The second multiplexer includes a plurality of data input terminals and a selection input terminal, and the number of the data input terminals is consistent with the number of registers in the second register group. The second multiplexer reads the second to-be-transmitted count value from the entry corresponding to the third count index in the second register group according to the third count index received by the selection input terminal.

[0118] Optionally, an XOR operation is performed on a storage instruction storage address corresponding to the issued storage instruction to obtain a memory access violation table index corresponding to the storage instruction, and based on the memory access violation table index, a third counting index corresponding to the storage instruction is read from the first register group through a reading controller.

[0119] The second subtractor is used to perform a subtraction operation on the input second count value to be transmitted, and fill the subtraction result into the entry corresponding to the third count index in the second register group.

[0120] After the second multiplexer reads the second count value to be transmitted from the second register group based on the third count index, the second count value to be transmitted is transmitted to the first subtractor, so that the first subtractor performs a subtraction operation to obtain a subtraction result.

[0121] The subtraction operation indicates that a storage instruction having a memory access dependency relationship with the access instruction has been issued.

[0122] Optionally, the second register group corresponds to a read-write controller, and the read-write controller fills the subtraction result into the entry corresponding to the third count index in the second register group.

[0123] In another possible design, the read / write controller includes a second hash unit and a query unit; the memory access violation predictor also includes a third multiplexer and an adder;

[0124] The second hash unit is used to determine the second memory access violation table index corresponding to the storage instruction based on the storage instruction storage address of the storage instruction, and the second memory access violation table index is used to represent the index of the entry in the memory access violation table where the memory access violation information corresponding to the storage instruction is located.

[0125] Optionally, the hash unit is used to perform an XOR operation on the storage instruction address of the storage instruction to obtain a second memory access violation table index corresponding to the storage instruction.

[0126] The query unit is used to query the memory access violation table based on the second memory access violation table index to obtain the memory access violation information corresponding to the storage instruction and the third counting index.

[0127] After receiving the dispatched storage instruction, the query unit queries the memory access violation table based on the second memory access violation table index corresponding to the storage instruction to determine whether the storage instruction generates an over-memory access violation. If the storage instruction generates an over-memory access violation, a third counting index corresponding to the storage instruction is obtained from the memory access violation table.

[0128] Furthermore, the read / write controller controls the first register group to transmit the third count index to the selection input terminal of the third multiplexer, so that the third selector reads the third count value to be transmitted from the second register.

[0129] The third multiplexer is used to select the third count value to be transmitted corresponding to the storage instruction from the count table to be transmitted based on the received third count index, and transmit the third count value to be transmitted to the adder. The third count index is transmitted from the first register group to the third multiplexer.

[0130] The third multiplexer includes a plurality of data input terminals and a selection input terminal, and the number of the data input terminals is consistent with the number of registers in the second register group. The third multiplexer reads the third count value to be transmitted from the entry corresponding to the third count index in the second register group according to the third count index received by the selection input terminal.

[0131] The adder is used to perform an addition operation on the input third count value to be transmitted to obtain an addition result, and fill the addition result into an entry corresponding to the third count index in the second register group.

[0132] When the third multiplexer reads the third count value to be transmitted, the third count value to be transmitted is transmitted to the adder. The adder adds one to the count value, indicating that a new access instruction corresponding to the third count index has a storage instruction to be transmitted with a memory access dependency. The access instruction needs to wait until all storage instructions with a memory access dependency are transmitted before being transmitted.

[0133] For illustration, please refer to Figure 6 , which shows a schematic diagram of updating the second register group provided by an exemplary embodiment of the present application. For the storage instruction received and dispatched, the memory access dependency table index is determined according to the storage instruction storage address of the storage instruction, and then the memory access violation information and the third counting index are obtained according to the memory access dependency table index. In the case where the memory access violation information indicates that the storage instruction has generated a memory access dependency violation, the third count value to be transmitted stored in the entry corresponding to the index in the second register is read through the third multiplexer, and the third count value to be transmitted is added by one and then updated to the second register group. On the other hand, after the storage instruction emission queue emits the storage instruction that has generated a memory access violation, the third counting index corresponding to the storage instruction is transmitted to the second multiplexer, so that the second multiplexer reads the second count value to be transmitted from the second register group, and then updates it to the second register group after subtracting one.

[0134] In the embodiment of the present application, if the storage instruction has the same to-be-emitted count value as the access instruction with the memory access dependency, then when there is a newly added storage instruction and the storage instruction generates a memory access dependency violation, the to-be-emitted count value corresponding to the storage instruction is increased by one, and when the access instruction is emitted, it is possible to accurately determine whether the emission condition is met based on the to-be-emitted count value. In addition, after the storage instruction that generates the dependency violation is emitted, the to-be-emitted count value corresponding to the storage instruction is reduced by one, that is, the second to-be-emitted count table is updated, so that when the access instruction emission queue obtains the to-be-emitted count value of the access instruction through the first multiplexer, the updated to-be-emitted count value can be obtained, thereby accurately updating the to-be-emitted count value corresponding to the access instruction according to the emission status of the candidate storage instruction.

[0135] The memory access violation table queried in the above embodiment includes memory access violation information and a counting index. The memory access violation table is constructed based on historical storage instructions and historical access instructions that generate violations in the store pipeline.

[0136] In one design, the memory access violation prediction apparatus includes a memory access dependency recorder.

[0137] The output end of the memory access dependency recorder is connected to the input end of the first register group, and the input end of the memory access dependency recorder is connected to the output end of the second register group;

[0138] The memory access dependency recorder is used to fill the memory access violation table based on the historical storage instructions that have generated the memory access violation and the instruction storage address of the historical access instructions, as well as the entry occupancy of the second register group.

[0139] The memory access dependency register is connected to the store pipeline, and historical storage instructions and historical access instructions that generate memory access violations are detected from the store pipeline.

[0140] After detecting the historical storage instruction and the historical access instruction of the memory access violation, the instruction storage addresses of the historical access instruction and the historical storage instruction are obtained to determine the entries of the historical access instruction and the historical storage instruction in the memory access dependency table.

[0141] Optionally, the memory access dependency recorder includes a third hash unit and a storage control unit.

[0142] The third hash unit is used to perform a hash operation on the storage address of the second access instruction corresponding to the historical access instruction to obtain the third memory access violation table index corresponding to the historical access instruction.

[0143] Optionally, the third hash unit performs an XOR operation on the second access instruction storage address corresponding to the historical access instruction to obtain a third memory access violation instruction index corresponding to the historical access instruction.

[0144] The third hash unit is further used to perform a hash operation on the storage address of the second storage instruction corresponding to the historical storage instruction to obtain a fourth memory access violation table index corresponding to the historical storage instruction.

[0145] Optionally, the third hash unit performs an XOR operation on the storage address of the second storage instruction corresponding to the historical storage instruction to obtain a fourth memory access violation table index corresponding to the historical storage instruction.

[0146] Correspondingly, when the dispatched access instruction and storage instruction are received, the memory access violation table index corresponding to the access instruction is determined based on the access instruction storage address of the access instruction, and the memory access violation table index corresponding to the storage instruction is determined based on the storage instruction storage address of the storage instruction.

[0147] The storage control unit is used to fill the entry corresponding to the third memory access violation table index in the memory access violation table with the memory access violation information corresponding to the historical access instruction and the target count index.

[0148] Optionally, the memory access violation information of the entry corresponding to the third memory access violation table index in the memory access violation table is filled with 1, and the count index of the entry corresponding to the third memory access violation table index is filled with the target count index.

[0149] The storage control unit is further used to fill the entry corresponding to the fourth memory access violation table index in the memory access violation table with the memory access violation information corresponding to the historical storage instruction and the target count index.

[0150] Optionally, the memory access violation information of the entry corresponding to the fourth memory access violation table index in the memory access violation table is filled with 1, and the count index of the entry corresponding to the fourth memory access violation table index is filled with the target count index.

[0151] Optionally, the storage control unit includes a pseudo most recently used unit and an allocation unit.

[0152] The pseudo least recently used unit is used to access the first register group and determine the occupancy of each entry in the second register group based on the count index in the memory access violation table.

[0153] The pseudo least recently used unit is further used to select a target entry from the second register group for a historical access instruction and a historical storage instruction based on the occupancy of each entry in the second register group, and transmit a target count index of the target entry to the allocation unit.

[0154] The pseudo least recently used unit determines the least recently occupied entry from the second register group based on the least recently used algorithm. In the second register group, different entries may store to-be-issued count values ​​corresponding to different storage instructions and access instructions, and after the storage instructions and access instructions with memory access dependency are all issued, the register of the entry will not be accessed by the multiplexer in a short period of time until the pseudo least recently used unit reallocates the entry to a newly detected group of historical storage instructions and historical access instructions that generate memory access violations.

[0155] When historical access instructions and historical storage instructions that generate memory access violations are detected, the pseudo least recently used unit accesses the first register group to obtain the count index in the memory access violation table, thereby determining the least recently used register entry in the second register group, and assigning the entry to the newly detected historical storage instructions and historical access instructions, thereby avoiding affecting the access instructions and storage instructions that have not been issued.

[0156] The allocation unit is used to fill the memory access violation information and the target count index into the entries corresponding to the fourth memory access violation table index and the third memory access violation table index in the first register group.

[0157] The allocation unit fills the memory access violation information into the entries corresponding to the fourth memory access violation table index and the third memory access violation table index in the first register group with 1, and fills the count index into the entries corresponding to the fourth memory access violation table index and the third memory access violation table index with the target count index.

[0158] The allocation unit is further used to fill the entry corresponding to the third memory access violation table index in the first register group with the memory access violation information and the target count index.

[0159] Figure 7 A schematic diagram of updating a memory access violation table provided by an exemplary embodiment of the present application is shown. In the initial state, the memory access violation table is empty, that is, the memory access violation information and the count index in the memory access violation table are both false (invalid), and the count table to be emitted is not indexed by any historical storage instruction and historical access instruction, that is, the counter (count) data in the count table to be emitted is invalid. When a historical storage instruction and a historical access instruction with a memory access violation are detected, the instruction storage address corresponding to the historical access instruction is violation_load_pc, and the instruction storage address corresponding to the historical storage instruction is violation_store_pc. Assume that the third memory access violation table index obtained by hash calculation of violation_load_pc is 3, the fourth memory access violation table index obtained by hash calculation of violation_store_pc is 1, and the count index assigned by the pseudo least recently used unit to the historical storage instruction and the historical access instruction is 1. Then the filling unit sets the value of the memory access violation information of entry 1 and entry3 in the memory access violation table to 1, and fills the count index of entry1 and entry3 in the memory access violation table to 1.

[0160] In an implementation manner of the present application, entries of different access instructions and historical storage instructions in a memory access violation table (i.e., memory access violation table index) are determined based on instruction storage addresses of historical access instructions and historical storage instructions. Thus, in the reflection process of storage instructions and access instructions, the corresponding memory access violation situation can be queried based on the instruction storage address, thereby determining the to-be-emitted count values ​​corresponding to different access instructions, and then controlling the emission of the access instruction.

[0161] Please refer to Figure 8, which shows a schematic diagram of the structure of a memory access violation predictor provided by another embodiment of the present application. The memory access violation recorder includes a pseudo least recently used unit, a hash unit, and a filling unit, which are used to fill the memory access violation table based on the access instruction storage address violation_load_pc of the historical access instruction that has generated the memory access violation and the storage instruction storage address violation_store_pc of the historical storage instruction. The pseudo least recently used unit is used to allocate entries of the second register group for the historical access instruction and the historical storage instruction. The first register group is used to store memory access violation information and count indexes, and the second register group is used to store count values ​​to be transmitted. The first multiplexer is used to select a corresponding entry from the second register group based on the count index of the access instruction, read the count value to be transmitted counter corresponding to the access instruction, and send it to the access instruction transmission queue. The access instruction transmission queue is used to control the transmission of the access instruction based on the count value to be transmitted. The storage instruction transmission queue is used to control the transmission of the storage instruction, and send the count index corresponding to the transmitted storage instruction to the access instruction transmission queue and the second multiplexer. The second multiplexer is used to select the to-be-transmitted count value corresponding to the sent storage instruction from the second register based on the count index of the sent storage instruction, and transmit the to-be-transmitted count value to the calculation unit, and the calculation unit performs a subtraction operation on the to-be-transmitted count value and updates it to the second register group. The third multiplexer is used to read the to-be-transmitted count value corresponding to the storage instruction from the second register group according to the count index corresponding to the access instruction when receiving a newly dispatched storage instruction, and transmit it to the calculation unit, and the calculation unit performs a plus operation on the to-be-transmitted count value and updates it to the second register group.

[0162] Please refer to Fig. 9 , which shows a flowchart of a memory access violation prediction method provided by an embodiment of the present application.

[0163] The method is used for the memory access violation prediction device provided in each of the above embodiments, and the method includes:

[0164] Step 901, when the read-write controller receives an access instruction, the read-write controller queries the memory access violation table in the first register group based on the first access instruction storage address of the access instruction, and when the memory access violation information corresponding to the access instruction indicates that the access instruction has generated a memory access violation, the read-write controller controls the first register group to transmit the first count index corresponding to the access instruction to the selection input end of the first multiplexer.

[0165] Step 902: The first multiplexer selects a first to-be-transmitted count value corresponding to the access instruction from a to-be-transmitted count table based on a first count index corresponding to the received access instruction.

[0166] Step 903 , when receiving the access instruction, the access instruction transmission queue saves the access instruction, and controls the transmission of the access instruction based on the first to-be-transmitted count value corresponding to the access instruction.

[0167] In some embodiments, the access instruction emission queue includes a third register group, a first numerical comparator and an emission controller. When the access instruction emission queue controls the emission of an access instruction, the third register group stores a first to-be-emitted count value corresponding to the access instruction to be emitted; the first numerical comparator compares the first to-be-emitted count value with 0 to obtain a first comparison result; the emission controller emits the access instruction when the first comparison result indicates that the first to-be-emitted count value is 0, or controls the access instruction to wait for emission when the first comparison result indicates that the first to-be-emitted count value is not 0.

[0168] In some embodiments, the access instruction emission queue also includes a fourth register group, a second numerical comparator and a first subtractor. When the access instruction emission queue controls the emission of an access instruction, the fourth register group stores the first count index corresponding to the access instruction transmitted by the first multiplexer; when the storage instruction emission queue emits a storage instruction, the second count index corresponding to the storage instruction is transmitted to the selection input of the second numerical comparator; the second numerical comparator compares the received second count index with the first count index to obtain a second comparison result; when the second comparison result indicates that the second count index is the same as the first count index, the first subtractor reads the first count value to be emitted corresponding to the access instruction from the third register group based on the second count index; the first subtractor subtracts one from the read first count value to be emitted to obtain a subtraction result, and fills the subtraction result into the entry corresponding to the second count index in the third register group.

[0169] In some embodiments, the read-write controller includes a first hash unit and a query unit. When the read-write controller queries the memory access violation table in the first register group, the first hash unit determines the first memory access violation table index corresponding to the access instruction based on the first access instruction storage address of the access instruction. The first memory access violation table index is used to represent the index of the entry in the memory access violation table where the memory access violation information corresponding to the access instruction is located; the query unit queries the memory access violation table based on the first memory access violation table index to obtain the memory access violation information corresponding to the access instruction and the first counting index.

[0170] In some embodiments, the method also includes: a storage instruction emission queue controls the emission of storage instructions, and transmits a third count index corresponding to the storage instruction to the selection input of a second multiplexer; the second multiplexer selects a second to-be-emitted count value corresponding to the storage instruction from a to-be-emitted count table based on the third count index; a second subtractor performs a subtraction operation on the input second to-be-emitted count value, and fills the subtraction result into the entry corresponding to the third count index in the second register group.

[0171] In some embodiments, the read-write controller includes a second hash unit and a query unit, and the method also includes: the second hash unit determines a second memory access violation table index corresponding to the storage instruction based on the storage instruction storage address of the storage instruction, and the second memory access violation table index is used to represent the index of the entry in the memory access violation table where the memory access violation information corresponding to the storage instruction is located; the query unit queries the memory access violation table based on the second memory access violation table index to obtain the memory access violation information corresponding to the storage instruction and a third counting index.

[0172] In some embodiments, the method also includes: a third multiplexer selects a third count value to be transmitted corresponding to the storage instruction from the count table to be transmitted based on the received third count index, and transmits the third count value to be transmitted to an adder, and the third count index is transmitted from the first register group to the third multiplexer; the adder adds one to the input third count value to be transmitted to obtain an addition result, and fills the addition result into the entry corresponding to the third count index in the second register group.

[0173] In some embodiments, the method further includes: a memory access dependency recorder fills a memory access violation table based on historical storage instructions that have generated memory access violations, instruction storage addresses of historical access instructions, and entry occupancy status of the second register group.

[0174] In some embodiments, the memory access dependency recorder includes a third hash unit and a storage control unit. When the memory access dependency recorder fills the memory access violation table, the third hash unit performs a hash operation on the second access instruction storage address corresponding to the historical access instruction to obtain a third memory access violation table index corresponding to the historical access instruction; the third hash unit performs a hash operation on the second storage instruction storage address corresponding to the historical storage instruction to obtain a fourth memory access violation table index corresponding to the historical storage instruction; the storage control unit fills the entry corresponding to the third memory access violation table index in the memory access violation table with the memory access violation information and the target count index corresponding to the historical access instruction; the storage control unit fills the entry corresponding to the fourth memory access violation table index in the memory access violation table with the memory access violation information and the target count index corresponding to the historical storage instruction.

[0175] In some embodiments, the storage control unit includes a pseudo least recently used unit and an allocation unit. When the memory access dependency recorder fills the memory access violation table, the pseudo least recently used unit accesses the first register group and determines the occupancy of each entry in the second register group based on the count index in the memory access violation table; the pseudo least recently used unit selects a target entry from the second register group for the historical access instruction and the historical storage instruction based on the occupancy of each entry in the second register group, and transmits the target count index of the target entry to the allocation unit; the allocation unit fills the memory access violation information and the target count index to the entries corresponding to the fourth memory access violation table index and the third memory access violation table index in the first register group; the allocation unit fills the memory access violation information and the target count index to the entries corresponding to the third memory access violation table index in the first register group.

[0176] The detailed process of the memory access violation prediction device controlling the issuance of access instructions can be referred to the above device embodiment, which will not be described in detail in this embodiment.

[0177] In some embodiments, the matrix transposition device in the embodiments of the present application may be integrated in a chip. The embodiments of the present application provide a chip, the chip comprising the memory access violation prediction device provided in any of the above embodiments.

[0178] Optionally, the chip may be a processor, such as an AI processor, a CPU processor, or other processor with data memory access requirements, which is not limited in the embodiments of the present application.

[0179] Please refer to Fig.10 , which shows a block diagram of a computer device 1000 provided by an exemplary embodiment of the present application. The computer device 1000 may be a portable mobile terminal, such as a smart phone, a tablet computer, a Moving Picture Experts Group Audio Layer III (MP3) player, or a Moving Picture Experts Group Audio Layer IV (MP4) player. The computer device 1000 may also be called a user device, a portable terminal, a workstation, a server, or other names.

[0180] Typically, the computer device 1000 includes a processor 1001 and a memory 1002 .

[0181] The processor 1001 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 1001 may be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA). The processor 1001 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a central processing unit (CPU); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 1001 may be integrated with a graphics processing unit (GPU), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 1001 may also include an artificial intelligence (AI) processor, which is used to process computing operations related to machine learning.

[0182] In some embodiments, the processor 1001 may be integrated with the matrix transposition device provided in the above embodiments. When the processor 1001 has a matrix transposition requirement, the matrix transposition device may be used to perform a transposition operation.

[0183] The memory 1002 may include one or more computer-readable storage media, which may be tangible and non-transitory. The memory 1002 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices, flash memory storage devices.

[0184] In some embodiments, the computer device 1000 may also optionally include a peripheral device interface 1003 and at least one peripheral device.

[0185] Those skilled in the art can understand that Fig.10 The structure shown in the figure does not constitute a limitation on the computer device 1000, and the computer device 1000 may include more or less components than those shown in the figure, or combine some components, or adopt a different component arrangement.

[0186] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0187] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A memory access violation prediction device, characterized in that: The device comprises: A first register group, a second register group, a read / write controller, a first multiplexer, and an access instruction issue queue; The first register group is used to store a memory access violation table, the memory access violation table is used to indicate memory access violation information and count indexes of historical storage instructions and historical access instructions, the memory access violation information is used to characterize the memory access violation conditions of the historical storage instructions and the historical access instructions, the count index is the index of the entry in the second register group where the to-be-issued count value corresponding to the access instruction is located, and the to-be-issued count value is used to characterize the number of to-be-issued storage instructions having a memory access dependency relationship with the access instruction; The second register group is used to store a to-be-issued count table, where the to-be-issued count table is used to represent the to-be-issued count values ​​corresponding to different access instructions; The read / write controller is configured to query the memory access violation table in the first register group based on the first access instruction storage address of the access instruction when the access instruction is received, and control the first register group to transmit the first counting index corresponding to the access instruction to the selection input terminal of the first multiplexer when the memory access violation information corresponding to the access instruction indicates that the access instruction has generated a memory access violation; The first multiplexer is configured to select, based on the first count index corresponding to the received access instruction, a first to-be-transmitted count value corresponding to the access instruction from the to-be-transmitted count table; The access instruction transmission queue is used to save the access instruction when the access instruction is received, and control the transmission of the access instruction based on the first to-be-transmitted count value corresponding to the access instruction.

2. The device according to claim 1, characterized in that The access instruction issue queue includes a third register group, a first value comparator and an issue controller; The third register group is used to store the first to-be-issued count value corresponding to the to-be-issued access instruction; The first numerical comparator is used to compare the first to-be-transmitted count value with 0 to obtain a first comparison result; The transmission controller is used to transmit the access instruction when the first comparison result indicates that the first to-be-transmitted count value is 0, or to control the access instruction to wait for transmission when the first comparison result indicates that the first to-be-transmitted count value is not 0.

3. The device according to claim 2, characterized in that The apparatus also includes a storage instruction issue queue; The access instruction issue queue also includes a fourth register group, a second value comparator and a first subtractor; The fourth register group is used to store the first counting index corresponding to the access instruction transmitted by the first multiplexer; The storage instruction emission queue is used for transmitting the second counting index corresponding to the storage instruction to the selection input terminal of the second value comparator when the storage instruction is emitted; The second numerical comparator is used to compare the received second counting index with the first counting index to obtain a second comparison result; The first subtractor is configured to read the first to-be-transmitted count value corresponding to the access instruction from the third register group based on the second count index when the second comparison result indicates that the second count index is the same as the first count index; The first subtractor is further configured to perform a subtraction operation on the first to-be-transmitted count value read from the third register group to obtain a subtraction result, and fill the subtraction result into an entry corresponding to the first count index in the third register group.

4. The device according to claim 1, characterized in that The read-write controller includes a first hash unit and a query unit; The first hash unit is used to determine a first memory access violation table index corresponding to the access instruction based on the first access instruction storage address of the access instruction, wherein the first memory access violation table index is used to represent the index of the entry in the memory access violation table where the memory access violation information corresponding to the access instruction is located; The query unit is used to query the memory access violation table based on the first memory access violation table index to obtain the memory access violation information corresponding to the access instruction and the first counting index.

5. The device according to claim 1, characterized in that The device also includes: storing an instruction issue queue, a second multiplexer, and a second subtractor; The storage instruction emission queue is used to control the emission of the storage instruction and transmit the third counting index corresponding to the storage instruction to the selection input terminal of the second multiplexer; The second multiplexer is used to select a second to-be-transmitted count value corresponding to the storage instruction from the to-be-transmitted count table based on the third count index; The second subtractor is used to perform a subtraction operation on the input second count value to be transmitted, and fill the subtraction result into the entry corresponding to the third count index in the second register group.

6. The device according to claim 1, characterized in that The read-write controller includes a second hash unit and a query unit; The second hash unit is used to determine a second memory access violation table index corresponding to the storage instruction based on the storage instruction storage address of the storage instruction, and the second memory access violation table index is used to represent the index of the entry in the memory access violation table where the memory access violation information corresponding to the storage instruction is located; The query unit is used to query the memory access violation table based on the second memory access violation table index to obtain the memory access violation information corresponding to the storage instruction and a third counting index.

7. The device according to claim 6, characterized in that The device also includes a third multiplexer and an adder; The third multiplexer is used to select a third count value to be transmitted corresponding to the storage instruction from the count table to be transmitted based on the received third count index, and transmit the third count value to be transmitted to the adder, and the third count index is transmitted from the first register group to the third multiplexer; The adder is used to perform an addition operation on the input third count value to be transmitted to obtain an addition result, and fill the addition result into the entry corresponding to the third count index in the second register group.

8. The device according to claim 1, characterized in that The device also includes a memory access dependency recorder; The memory access dependency recorder is used to fill the memory access violation table based on the historical storage instructions that have generated memory access violations and the instruction storage addresses of the historical access instructions, as well as the entry occupancy of the second register group.

9. The device according to claim 8, characterized in that The memory access dependency recorder includes a third hash unit and a storage control unit; The third hash unit is used to perform a hash operation on the storage address of the second access instruction corresponding to the historical access instruction to obtain a third memory access violation table index corresponding to the historical access instruction; The third hash unit is further used to perform a hash operation on the storage address of the second storage instruction corresponding to the historical storage instruction to obtain a fourth memory access violation table index corresponding to the historical storage instruction; The storage control unit is used to fill the memory access violation information corresponding to the historical access instruction and the target count index into the entry corresponding to the third memory access violation table index in the memory access violation table; The storage control unit is further used to fill the memory access violation information corresponding to the historical storage instruction and the target count index into the entry corresponding to the fourth memory access violation table index in the memory access violation table.

10. The device according to claim 9, characterized in that The storage control unit includes a pseudo least recently used unit and an allocation unit; The pseudo least recently used unit is used to access the first register group and determine the occupancy of each entry in the second register group based on the count index in the memory access violation table; The pseudo least recently used unit is further used to select a target entry from the second register group for the historical access instruction and the historical storage instruction based on the occupancy of each entry in the second register group, and transmit a target count index of the target entry to the allocation unit; The allocation unit is used to fill the memory access violation information and the target count index into the entries corresponding to the fourth memory access violation table index and the third memory access violation table index in the first register group.

11. A memory access violation prediction method, characterized in that: The method is used for the memory access violation prediction device according to any one of claims 1 to 10, and the method comprises: The read / write controller, when receiving the access instruction, queries the memory access violation table in the first register group based on the first access instruction storage address of the access instruction, and when the memory access violation information corresponding to the access instruction indicates that the access instruction has generated a memory access violation, controls the first register group to transmit the first counting index corresponding to the access instruction to the selection input end of the first multiplexer; The first multiplexer selects a first to-be-transmitted count value corresponding to the access instruction from the to-be-transmitted count table based on the first count index corresponding to the received access instruction; When receiving the access instruction, the access instruction transmitting queue saves the access instruction and controls the transmitting of the access instruction based on the first to-be-transmitted count value corresponding to the access instruction.

12. A chip, characterized in that: The chip includes the memory access violation prediction device as claimed in any one of claims 1 to 10.

13. A computer device, characterized in that: The computer device comprises a processor and a memory, wherein the processor is connected to the memory via a bus, and the processor is provided with a memory access violation prediction device as claimed in any one of claims 1 to 10.

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