Asynchronous recording out-of-order processor register renaming check point and rollback method

Abstract

The invention provides an asynchronous recording out-of-order processor register renaming check point and rollback method, which belongs to the technical field of register storage, and comprises the following steps: S1, a scalar instruction processing step: mapping all instructions from a logic register to a physical register through a scalar register renaming module, recording a historical mapping relation of the scalar target register; s2, a vector instruction processing step: after a scalar instruction is distributed, the vector instruction is subjected to flexible configuration such as mapping from a logic register to a physical register, support vector length and the like through a vector register renaming module, and aiming at the problem of instruction delay, the rollback process through two renaming modules is parallel, so that the problem of instruction delay is solved; and if the rollback time of the vector renaming module is relatively long, the scalar renaming module can directly start to work without synchronizing the state of the vector renaming module, and the processing correctness and efficiency are ensured by a back pressure mechanism of the vector renaming module.

Description

Technical Field

[0001] The present invention relates to the technical field of checkpoints and rollbacks, and particularly relates to a method for asynchronously recording checkpoints and rollbacks of register renaming in an out-of-order processor. Background Art

[0002] The purpose of register renaming technology is to solve the register alias problem in traditional architectures (Register Alias Problem). In an out-of-order execution processor, since instructions may be executed in different orders, the dependency relationships of operands become complex, especially when the same register may be modified in different instructions. Register renaming eliminates read-after-write (WAR, Write-After-Read) and write-after-write conflicts (WAW, Write-After-Write) of registers by assigning different logical registers to physical registers. By resolving data dependencies, more instructions are allowed to execute in parallel. Out-of-order execution is achieved, reducing the performance bottleneck caused by data dependencies. For traditional out-of-order processors, the function of register renaming is implemented within the same component, so recording its checkpoint and recovering after an exception can be achieved within the above-mentioned component. However, currently, it is difficult to solve the challenges brought by the V Extension of the RISC-V processor. In the V Extension, control registers (Control and Status Register, CSR) such as vector length, vector register group multiplier setting, and the number of registers operated by a vector instruction (Vector instructions) are defined. This flexible configuration makes it impossible to efficiently implement the renaming of vector registers and scalar registers in the same component. Vector instructions require more processing, while scalar instructions do not require the same processing, and for scalar instructions, the increase in instruction latency will affect the execution performance of the processor. Therefore, the renaming of scalar registers and vector registers, the establishment of checkpoints, and exception recovery need to be implemented in different modules. Summary of the Invention

[0003] By separating the scalar and vector renaming modules, the coupling problem caused by the dynamic configuration of the RISC-V V Extension control register is solved, and asynchronous rollback of scalar and vector checkpoints is supported to adapt to the difference between the instruction completion order and the submission order in out-of-order execution, thereby overcoming the problems in the above background art.

[0004] Based on the above technical idea, the technical solution adopted by the present invention is as follows: A method for asynchronously recording out-of-order processor register renaming checkpoints and rollbacks, comprising the following steps: S1 scalar instruction processing step, in which all instructions complete the mapping from logical registers to physical registers through the scalar register renaming module, and record the historical mapping relationship of scalar target registers. All instructions 1 include vector instructions and scalar instructions; S2 vector instruction processing step, in which after the scalar instructions are dispatched, the vector instructions perform the mapping from logical registers to physical registers through the vector register renaming module, supporting flexible configuration of vector length; S3 checkpoint recording step, which records checkpoints for scalar instructions and vector instructions; S4 management history table step, which generates a scalar history table and a vector history table according to the instructions; S5 exception rollback step, which includes a scalar rollback link, a vector rollback link, and a parallel recovery link.

[0005] For further limitation of the above technical solution, in the S1 scalar instruction processing step, this step further includes a scalar register renaming link, a recording scalar historical mapping link, and a passing historical pointer link. The scalar register renaming link maps logical registers to physical registers through a scalar renaming table (sRAT). The scalar registers use a register free list (Freelist) to allocate physical registers to ensure no data dependency conflicts between scalar instructions; the recording scalar historical mapping link includes writing the old logical-physical mapping relationship of the scalar target register into the scalar renaming history table (Scalar HistoryTable) and updating the write pointer. The history table stores in the instruction execution order and supports rollback according to the pointer; the passing historical pointer includes binding the history table pointer to the instruction and sending it to the instruction dispatch module together with the instruction.

[0006] For further limitation of the above technical solution, in the S2 vector instruction processing step, this step further includes a vector register renaming link and a recording vector historical mapping link. The vector register renaming link maps vector logical registers to physical registers through a vector renaming table (vRAT), supporting dynamic configuration of vector length (VL) and register bank specification (VLMUL). The vector registers use an independent vector free list to allocate physical registers to adapt to the parallelism requirements of vector instructions; the recording vector historical mapping link includes writing the old logical-physical mapping relationship of the vector target register into the vector renaming history table (Vector History Table), indexed by the global instruction number (Global ID). The history table supports rollback according to the global number range to avoid dependency confusion caused by out-of-order execution of vector instructions.

[0007] For further limitation of the above technical solution, in the S3 checkpoint recording step, this step includes a scalar checkpoint link and a vector checkpoint link. The scalar checkpoint link records the scalar rename table (sRAT), the free list, and the history table pointer before dispatching each scalar instruction, and passes them to the vector module through the instruction dispatching module. The vector checkpoint link records the vector rename table (vRAT), the free list, and the associated global scalar checkpoint number when dispatching vector instructions.

[0008] For further limitation of the above technical solution, in the S4 history table management step, in this step, the scalar history table records the mapping changes of scalar target registers in the order of instructions, and needs to roll back to the state before the specified pointer when released; the vector history table uses the instruction global number as an index to record the mapping relationship of vector instructions, and rolls back according to the number range when released.

[0009] For further limitation of the above technical solution, in the S5 exception rollback step, in this step, scalar rollback is used to locate the scalar history pointer of the exception instruction → find the nearest scalar checkpoint to restore the sRAT and the free list → if there is no checkpoint, roll back from the history pointer to the exception point; the vector rollback link is used to locate the global number of the exception instruction → find the associated vector checkpoint to restore the vRAT and the free list → if there is no checkpoint, roll back from the global scalar checkpoint number to the exception point; parallel recovery is used for concurrent execution of scalar and vector rollbacks, and the vector module synchronizes to complete the state recovery through the backpressure mechanism.

[0010] For further limitation of the above technical solution, in the S4 history table management step, this step further includes a history mapping recording link. The history mapping recording link includes a scalar history table and write pointer management. The scalar history table stores triples (logical register, old physical register, new physical register) in the order of instruction execution; the write pointer management maintains the history table write pointer (HTWP). For each recorded history mapping of an instruction, the pointer is incremented, and the pointer value is carried with the instruction to subsequent modules for locating the recovery starting point during rollback.

[0011] For further limitation of the above technical solution, in the S5 exception rollback step, this step includes an exception detection and location link, a scalar state recovery link, and a vector state recovery link. The exception detection and location link includes exception signal capture and instruction pointer backtracking to the root. In exception signal capture, when branch prediction fails, an interrupt or an exception occurs, the ROB (reorder buffer) records the original PC address and the commit status of the exception instruction; according to the original PC of the exception instruction, the instruction pointer backtracking finds its corresponding scalar history table pointer (HTWP) and global number (GID) in the instruction dispatching module.

[0012] For further limitation of the above technical solution, the scalar state recovery link includes checkpoint matching and state coverage. In the scalar checkpoint linked list, the nearest checkpoint greater than or equal to HTWP is searched. If there is no matching checkpoint, roll back from the current HTWP to the exception point; directly write the sRAT and Freelist of the checkpoint into the hardware register to overwrite the current state, and release the physical registers in the history table between the exception point.

[0013] For further limitation of the above technical solution, the vector state recovery link includes a global number matching link. In the vector checkpoint linked list, the nearest checkpoint greater than or equal to GID is searched. If there is no matching checkpoint, roll back from GID = 1024 to the exception point, write the vRAT and V-Freelist of the checkpoint into the hardware register to overwrite the current state, and release the physical registers in the history table between the checkpoint and the exception point.

[0014] For further limitation of the above technical solution, it further includes an instruction dispatch module. After receiving an instruction, the instruction dispatch module sends the instruction to the instruction reorder buffer for caching, differentiates scalar instructions and vector instructions in the instruction reorder buffer, submits different instructions in the instruction order, and performs out-of-order execution on scalar instructions and vector instructions according to the out-of-order execution of scalar instructions and vector instructions during the instruction order submission process. When scalar instructions and vector instructions are executed, different instructions are passed to the scalar instruction dispatch and vector instruction dispatch, and vector instruction preprocessing is performed on the vector instructions.

[0015] Compared with the prior art, the beneficial effects of the present invention are: 1. Asynchronous recording and recovery, independent recording of scalar and vector checkpoints, and collaborative recovery through global instruction numbers and history pointers during rollback, improving the efficiency of exception handling; 2. Flexible adaptation of vector instructions, supporting dynamic configuration of vector length control registers, and avoiding coupling of scalar and vector processing paths; 3. Parallel rollback optimization, concurrent state recovery of scalar and vector modules, combined with the backpressure mechanism to ensure correctness, and reducing the overall recovery latency. Description of the Drawings

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0017] Figure 1Schematic flow diagram of a method for asynchronous recording of register renaming checkpoints and rollback in an out-of-order processor according to the present invention; wherein, 1. all instructions; 2. scalar register renaming module; 3. scalar checkpoint; 4. register renaming table; 5. register free list; 6. renaming history table; 7. instruction dispatch module; 8. instruction reorder buffer; 9. scalar instruction dispatch; 10. vector instruction dispatch; 11. instruction sequential commit; 12. scalar instruction out-of-order execution; 13. vector instruction preprocessing; 14. vector register renaming module; 15. vector checkpoint; 19. vector instruction out-of-order execution. Detailed implementation manners

[0018] The following further describes the present invention in detail with reference to the Figure 1 accompanying drawings.

[0019] Embodiment 1: This embodiment provides a method for asynchronous recording of register renaming checkpoints and rollback in an out-of-order processor, as Figure 1 shown, including the following steps: S1 Scalar instruction processing step: In this step, all instructions 1 are mapped from logical registers to physical registers through the scalar register renaming module 2, and the historical mapping relationship of scalar target registers is recorded. All instructions 1 include vector instructions and scalar instructions; S2 Vector instruction processing step: After scalar instructions are dispatched, vector instructions are mapped from logical registers to physical registers through the vector register renaming module 14, supporting flexible configuration of vector length; S3 Recording step: In this step, scalar instructions and vector instructions are recorded; S4 Managing history table step: In this step, scalar history tables and vector history tables are generated according to instructions; S5 Exception rollback step: This step includes a scalar rollback link, a vector rollback link, and a parallel recovery link.

[0020] In the S1 scalar instruction processing step, this step further includes a scalar register renaming link, a recording scalar historical mapping link, and a passing historical pointer link. In the scalar register renaming link, logical registers are mapped to physical registers through the scalar renaming table (sRAT). Scalar registers use the register free list 5 (Freelist) to allocate physical registers to ensure no data dependency conflicts between scalar instructions; the recording scalar historical mapping link includes writing the old logical-physical mapping relationship of scalar target registers into the scalar renaming history table 6 (Scalar History Table) and updating the write pointer. The history table stores data in the instruction execution order and supports rollback according to the pointer; the passing historical pointer includes binding the history table pointer to the instruction and sending it to the instruction dispatch module together with the instruction.

[0021] The S2 vector instruction processing step further includes a vector register renaming stage and a vector history mapping recording stage. In the vector register renaming stage, the vector logical registers are mapped to physical registers through a vector renaming table (vRAT), supporting dynamic configuration of the vector length (VL) and register bank specification (VLMUL). The vector registers use an independent vector free list to allocate physical registers to adapt to the parallelism requirements of vector instructions. The vector history mapping recording stage includes writing the old logical-physical mapping relationship of the vector destination register into the Vector History Table 6, indexed by the Global ID. The history table supports rollback by global number range to avoid dependency confusion caused by out-of-order execution of vector instructions.

[0022] The S3 recording step includes a scalar stage and a vector stage. In the scalar stage, before dispatching each scalar instruction, the scalar renaming table (sRAT), free list, and history table pointer are recorded and passed to the vector module through the instruction dispatch module. In the vector stage, when dispatching vector instructions, the vector renaming table (vRAT), free list, and associated scalar global ID are recorded.

[0023] In the S4 history table management step, the scalar history table records the mapping changes of scalar destination registers in instruction order and needs to roll back to the state before the specified pointer when released. The vector history table is indexed by the instruction global ID and records the mapping relationships of vector instructions, and rolls back by number range when released.

[0024] In the S5 exception rollback step, scalar rollback is used to locate the scalar history pointer of the exception instruction → find the nearest scalar recovery sRAT and free list → if not available, roll back from the history pointer to the exception point; the vector rollback stage is used to locate the global ID of the exception instruction → find the associated vector recovery vRAT and free list → if not available, roll back from the scalar global ID to the exception point; parallel recovery is used for concurrent execution of scalar and vector rollbacks, and the vector module synchronizes to complete the state recovery through a backpressure mechanism.

[0025] The S4 history table management step further includes a history mapping recording stage. The history mapping recording stage includes scalar history table and write pointer management. The scalar history table stores triples (logical register, old physical register, new physical register) in instruction execution order; the write pointer management maintains the history table write pointer (HTWP). For each recorded history mapping of an instruction, the pointer is incremented, and the pointer value is carried with the instruction to subsequent modules for locating the recovery starting point during rollback.

[0026] The S5 exception rollback step includes an exception detection and localization link, a scalar state recovery link, and a vector state recovery link. The exception detection and localization link includes exception signal capture and instruction pointer backtracking root. For exception signal capture, when branch prediction fails, an interrupt or an exception occurs, the ROB (Reorder Buffer) records the original PC address and submission status of the exception instruction. For instruction pointer backtracking, based on the original PC of the exception instruction, its corresponding scalar history table pointer (HTWP) and global ID (GID) are found in the instruction dispatch module.

[0027] The scalar state recovery link includes matching and state overwriting. For matching, in the scalar linked list, the nearest one ≥ HTWP is found. If there is no match, roll back from the current HTWP to the exception point. The sRAT and Freelist are directly written into the hardware register to overwrite the current state, and the physical registers of the history table between the current state and the exception point are released.

[0028] The vector state recovery link includes a global ID matching link. In the vector linked list, the nearest one ≥ GID is found. If there is no match, roll back from GID = 1024 to the exception point. The vRAT and V-Freelist are written into the hardware register to overwrite the current state, and the physical registers of the history table between the current state and the exception point are released.

[0029] It also includes an instruction dispatch module 7. After receiving an instruction, the instruction dispatch module 7 sends the instruction to the instruction reorder buffer 8 for caching. In the instruction reorder buffer 8, scalar instructions and vector instructions are distinguished, and different instructions are submitted in instruction order 11. During the instruction order submission 11 process, the scalar instructions and vector instructions are out-of-order executed according to the out-of-order execution 12 of scalar instructions and the out-of-order execution 19 of vector instructions. When scalar instructions and vector instructions are executed, different instructions are passed to the scalar instruction dispatch 9 and vector instruction dispatch 10, and vector instruction preprocessing 13 is performed on vector instructions.

[0030] The logic of scalar and vector renaming, recording renaming, and history tables is in different modules. The instruction reorder buffer records the recovery pointers and instruction numbers of the two tables, enabling the two tables to be restored to the state before the same instruction renaming respectively. The rollback processes of the two renaming modules are parallel. If the rollback time of the vector renaming module is long, the scalar renaming module can start working directly without synchronizing the state of the vector renaming module. The anti-pressure mechanism of the vector renaming module ensures the correctness of processing.

[0031] Embodiment 2: This embodiment provides a method for asynchronous recording of out-of-order processor register renaming and rollback, as Figure 1 shown, including the following steps: The functions of renaming, recording, and renaming history for scalar and vector registers are implemented in two independent modules respectively. The process of recording and renaming history is as follows: 1. All instructions 1 enter the scalar register renaming module 2 for processing. This module renames the scalar logical registers used in scalar and vector instructions into physical registers; 2. Record the logical-to-physical mapping relationship of the scalar destination register of the instruction into the rename history table 6, record the write table pointer, and send it together with the instruction to the instruction dispatch module; 3. The scalar register renaming module 2 decides when to record according to a certain strategy. The recorded content (including the register rename table 16, free list, and the pointer to the rename history table 6 at this time). After recording the scalar, the first subsequent vector instruction carries the recorded flag; 4. After the instructions enter the instruction dispatch module in order, they need to enter the instruction reorder buffer (stored together with the pointer to the rename history table 6 carried by the instruction) and obtain a global number; 5. The scalar instructions that obtain the global number are then dispatched out-of-order into the scalar out-of-order execution module; 6. The vector instructions that obtain the global number are then dispatched, enter the vector instruction preprocessing module in order, and then enter the vector register renaming module 14 in order, which renames the vector logical registers used in the vector instructions into physical registers; 7. Record the logical-to-physical mapping relationship of the vector destination register into the rename history table 6, and this table is indexed by the instruction global number; 8. The vector register renaming module 14 records according to the flag carried by the instruction, and the recorded content should include the global number of this vector instruction; 9. The vector instructions that have passed through the vector register renaming module 14 enter the vector instruction out-of-order execution module out-of-order; 10. After the scalar instruction out-of-order module and the vector instruction out-of-order execution module complete execution, they return the completion status to the instruction reorder buffer; 11. The instruction reorder buffer submits in the original instruction order. Use the pointer to the scalar rename history table 6 of the last instruction submitted per cycle to release the scalar and scalar rename history table 6 entries smaller than this pointer, and use its instruction global number to release the vector and vector rename history table 6 entries smaller than this instruction global encoding. When releasing the rename history table 6 entries, the released physical registers need to be put into the corresponding register free list 5 and all recorded register free lists 5.

[0032] The rollback process is as follows: 1. When an exception occurs during instruction execution, a branch instruction prediction error occurs, or an interruption occurs, all this information has to be sent to the instruction reorder buffer, which determines to which instruction state the processor has to revert; 2. Obtain the pointer to the scalar renaming history table 6 of this instruction, send it to the scalar register renaming module 2, find the one with the pointer to the scalar renaming history table 6 closest to and greater than this pointer, and directly write the status of the stored register renaming table 16 and the free list into the register renaming table 16 and the free list. If none is found, step 3 can be directly performed; 3. Restore the scalar renaming history table 6 entries between the pointer to the scalar renaming history table 6 of the instruction and the pointer to the scalar renaming history table 6 (if none is found in step 2, use the current scalar renaming history table 6 write pointer instead) into the register renaming table 16, and put the physical registers before the modified register renaming table 16 entries this time into the register free list 5; 4. Can be performed simultaneously with steps 2 and 3 above. Obtain the global instruction number of this instruction, send it to the vector register renaming module 14, find the one with the global instruction number of the vector instruction closest to and greater than this global instruction number, and directly write the status of the stored register renaming table 16 and the free list into the register renaming table 16 and the free list. If none is found, step 5 can be directly performed; 5. Restore the vector renaming history table 6 entries between the global instruction number of the instruction and the global instruction number (if none is found in step 4, use the current scalar renaming history table 6 write pointer instead) into the register renaming table 16, and put the physical registers before the modified register renaming table 16 entries this time into the register free list 5; 6. After steps 2 and 3 are completed, scalar instruction renaming can continue. If steps 4 and 5 are not completed yet, the vector register renaming module 14 will block instructions from entering and backpressure forward. After steps 2, 3, 4, and 5 are all completed, scalar instructions and vector instructions can run normally.

[0033] Scalars and vectors do not correspond one by one. It is possible that there is no vector between two scalars on the time axis. This situation occurs when there is no vector instruction between two scalars. This situation does not affect the functional correctness and performance and is a normal processing process..

[0034] Data structure: Register renaming table 16: This table is used to store the mapping relationship between logical registers and physical registers.

[0035] Register free list 5: This table is used to store unmapped physical registers.

[0036] Write-back process: After an instruction retires, the physical register is written back to the free list.

[0037] Rename Rewind Rename Rewind is an operation that needs to roll back the register renaming when the processor discovers an error during out-of-order execution (such as a branch prediction error) or other situations that require rollback (such as exceptions or interrupts).

[0038] Implementation method: 1) Save the Rename History: During the execution process, the processor updates the rename table in real time to record the mapping relationship between the latest logical register and the physical register. To be able to roll back when needed, the processor records the mapping relationship before the target register is renamed for each instruction. When an exception occurs, the mapping of the rename table can be restored through the records in the Rename History Table 6 until the state before the instruction where the exception occurred is restored.

[0039] 2) Save the Checkpoint of the rename table: In the actual processor design, rollback needs to be performed efficiently and quickly. Therefore, the processor records all the information of the rename table at some moments according to a certain strategy. When rolling back, it first returns to the one closest to the exception point, and then searches the Rename History Table 6 for rollback based on this. The processor can maintain multiple. The above content is a further detailed description of the present invention in combination with specific preferred implementation embodiments, which is convenient for those skilled in the art of this technology to understand and apply the present invention. It cannot be determined that the specific implementation of the present invention is only limited to these descriptions.

Claims

1. A method for asynchronously recording out-of-order processor register renaming checkpoints and rollbacks, characterized in that: The following steps are involved: S1 scalar instruction processing step, in which all instructions (1) are mapped from logical registers to physical registers through the scalar register renaming module (2), and the historical mapping relationship of the scalar target register is recorded. All instructions (1) include vector instructions and scalar instructions; S2 vector instruction processing step, in which after the scalar instruction is dispatched, the vector instruction is mapped from the logical register to the physical register through the vector register renaming module (14), and supports flexible configuration of the vector length; S3 checkpoint recording step, which performs checkpoint recording on scalar instructions and vector instructions; S4 is a history table management step, in which a scalar history table and a vector history table are generated according to the instruction; S5 abnormal rollback step, which includes scalar rollback phase, vector rollback phase and parallel recovery phase.

2. The method for asynchronously recording out-of-order processor register renaming checkpoint and rollback according to claim 1, characterized in that: The S1 scalar instruction processing step also includes a scalar register renaming link, a scalar history mapping recording link and a history pointer transfer link. The scalar register renaming link maps the logical register to the physical register through the scalar renaming table. The scalar register uses the register free list (5) to allocate the physical register to ensure that there is no data dependency conflict between scalar instructions; the scalar history mapping recording link includes writing the old logical-physical mapping relationship of the scalar target register into the scalar renaming history table (6) and updating the write pointer. The history table is stored in the order of instruction execution and supports rollback by pointer; the history pointer transfer includes binding the history table pointer to the instruction and sending it to the instruction dispatch module together with the instruction.

3. The method for asynchronously recording out-of-order processor register renaming checkpoint and rollback according to claim 2, characterized in that: The S2 vector instruction processing step also includes a vector register renaming step and a vector history mapping recording step. The vector register renaming step maps the vector logical register to the physical register through the vector renaming table, supports dynamic configuration of the vector length and register group specification, and the vector register uses an independent vector free list to allocate physical registers to adapt to the parallel requirements of the vector instructions; the vector history mapping recording step includes writing the old logical-physical mapping relationship of the vector target register into the vector renaming history table (6), with the global instruction number as the index. The history table supports rollback according to the global number range to avoid dependency confusion caused by out-of-order execution of vector instructions (19).

4. The method for asynchronously recording out-of-order processor register renaming checkpoint and rollback according to claim 3, characterized in that: The S3 checkpoint recording step includes a scalar checkpoint (3) link and a vector checkpoint (15) link. The scalar checkpoint (3) link records the scalar renaming table, free list and history table pointer before each scalar instruction is dispatched, and transmits them to the vector module through the instruction dispatch module. The vector checkpoint (15) link records the vector renaming table, free list and associated scalar checkpoint (3) global number when the vector instruction is dispatched.

5. The method for asynchronously recording out-of-order processor register renaming checkpoint and rollback according to claim 4, characterized in that: The S4 management history table step, in which the scalar history table records the mapping changes of the scalar target register in the order of instructions, and needs to be rolled back to the state before the specified pointer when released; the vector history table uses the instruction global number as the index, records the mapping relationship of the vector instructions, and rolls back according to the number range when released.

6. The method for asynchronously recording out-of-order processor register renaming checkpoint and rollback according to claim 5, characterized in that: The S5 abnormal rollback step, in which the scalar rollback is used to locate the scalar history pointer of the abnormal instruction → find the most recent scalar checkpoint (3) to restore the sRAT and free list → if there is no checkpoint, roll back from the history pointer to the abnormal point; the vector rollback link is used to locate the global number of the abnormal instruction → find the associated vector checkpoint (15) to restore the vRAT and free list → if there is no checkpoint, roll back from the scalar checkpoint (3) global number to the abnormal point; parallel recovery is used for concurrent execution of scalar and vector rollbacks, and the vector module synchronously completes state recovery through the back pressure mechanism.

7. The method for asynchronously recording out-of-order processor register renaming checkpoint and rollback according to claim 6, characterized in that: The S4 step of managing the history table also includes a history mapping record link. The history mapping record link includes a scalar history table and write pointer management. The scalar history table stores triplets in the order of instruction execution. The write pointer management maintains the history table write pointer. Each time a history mapping of an instruction is recorded, the pointer is incremented. The pointer value is carried with the instruction to the subsequent module for locating the recovery starting point during rollback.

8. The method for asynchronously recording out-of-order processor register renaming checkpoint and rollback according to claim 7, characterized in that: The S5 exception rollback step includes an exception detection and positioning link, a scalar state recovery link and a vector state recovery link. The exception detection and positioning link includes exception signal capture and instruction pointer backtracking root. When the branch prediction fails, an interrupt or an exception occurs, the ROB records the original PC address and submission status of the exception instruction; the instruction pointer backtracking searches for the corresponding scalar history table pointer and global number in the instruction dispatch module according to the original PC of the exception instruction.

9. The method for asynchronously recording out-of-order processor register renaming checkpoint and rollback according to claim 8, characterized in that: The scalar state recovery link includes checkpoint matching and state coverage. The checkpoint matching searches for the nearest checkpoint ≥ HTWP in the scalar checkpoint (3) linked list. If there is no matching checkpoint, roll back from the current HTWP to the abnormal point; write the sRAT and Freelist of the checkpoint directly into the hardware register, overwrite the current state, and release the physical register of the history table between the checkpoint and the abnormal point. The vector state recovery link includes a global number matching link in the vector checkpoint (15) linked list. Search for the nearest checkpoint ≥ GID. If there is no matching checkpoint, roll back from GID = 1024 to the abnormal point, write the vRAT and V-Freelist of the checkpoint into the hardware register, overwrite the current state, and release the physical register of the history table between the checkpoint and the abnormal point.

10. The method for asynchronously recording out-of-order processor register renaming checkpoint and rollback according to claim 9, characterized in that: The system also includes an instruction dispatch module (7). After receiving the instruction, the instruction dispatch module (7) sends the instruction to the instruction reordering cache (8) for caching. In the instruction reordering cache (8), scalar instructions and vector instructions are distinguished, and different instructions are submitted according to the instruction sequence (11). During the instruction sequence submission (11), the scalar instructions and vector instructions are executed out of order according to the scalar instruction out of order execution (12) and the vector instruction out of order execution (19). When executing the scalar instructions and vector instructions, the different instructions are passed to the scalar instruction dispatch (9) and the vector instruction dispatch (10), and the vector instruction is preprocessed (13).

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