Method and system for incremental development of chip verification platform and storage medium

Abstract

The invention provides an incremental development method for a chip verification platform, which comprises the following steps of: analyzing stock codes of the chip verification platform, and extracting code topological information; filling in demand information according to the input template; the filled demand information and the topological information serve as input and are transmitted to a large language model, and code change information output by the large language model according to a guide template format is obtained; applying the code change information to the stock code to obtain an updated code; and verifying the updated code according to the demand information to obtain a verification platform corresponding to the demand information. The invention further discloses a corresponding system and a storage medium. According to the application, through automatic and intelligent means, the verification efficiency can be improved, the verification period can be shortened, and the requirement of rapid iteration can be met.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit design, and in particular to an incremental development method, system and storage medium for a chip verification platform. Background Art

[0002] As the scale and complexity of integrated circuit design continue to expand, chip verification faces huge challenges. The verification workload is growing exponentially, while the verification time window is shrinking, which requires that verification methods and tools must be continuously innovated to improve efficiency. In this context, there are currently two main verification platform development methods in the industry:

[0003] The first is to adopt a manual development method. This is the most traditional method, where verification engineers rely entirely on manual coding to build a verification environment. Although it is highly flexible, it is inefficient and difficult to cope with the verification needs of complex chips.

[0004] The second is to use an automated verification environment generation method based on templates and Universal Verification Methodology (UVM) technology. This is a method widely used in the industry. This method predefines a template containing verification component descriptions such as universal or custom verification intellectual property (VIP), and uses UVM's phase, generation mechanism, transaction level modeling (TLM) and other technologies to quickly generate a verification framework based on hardware description and verification language (such as SystemVerilog language) that meets UVM specifications, and integrates the predefined VIP in the template.

[0005] This template-based automated verification environment generation method accelerates the initial construction process of the verification environment and avoids repetitive common work. However, although this method has made significant progress in the initial verification environment construction, it still has obvious limitations in the subsequent incremental development process:

[0006] First, there is a lack of intelligent incremental update capabilities. Existing methods cannot automatically make changes, additions, and other modifications in the generated verification environment. In particular, for core logic closely related to the design under test (DUT), such as signal driving logic and reference models, chip verification engineers still need to manually write code and repeatedly iterate tests.

[0007] Second, it is difficult to cope with the demand for rapid iteration. In the process of modern chip development, design changes are frequent and verification requirements evolve rapidly. Existing methods are not flexible enough to respond to these changes and are difficult to meet the demand for rapid iteration.

[0008] These limitations lead to low incremental development efficiency of verification platforms, which cannot meet the needs of rapid iteration of modern chip design. Especially in the development of complex system on chip (SoC), verification often becomes a bottleneck in the entire development cycle, seriously affecting the time to market of products. Summary of the invention

[0009] The technical problem to be solved by this application is to provide an incremental development method, system and storage medium for a chip verification platform, which can improve verification efficiency, shorten verification cycle and meet the needs of rapid iteration through automation and intelligent means.

[0010] To solve the above technical problems, as one aspect of the present application, a method for incremental development of a chip verification platform is provided, which comprises the following steps: parsing the stock code of the chip verification platform and extracting code topology information;

[0011] Fill in the required information according to the input template;

[0012] Passing the filled-in requirement information and the topology information as input to the large language model, and obtaining the code change information output by the large language model in the guidance template format;

[0013] Applying the code change information to the stock code to obtain an updated code;

[0014] The updated code is verified according to the requirement information to obtain a verification platform corresponding to the requirement information.

[0015] The parsing of the stock code of the chip verification platform includes:

[0016] The stock code of the chip verification platform is parsed using a code parsing tool, including: identifying SystemVerilog syntax in the stock code, and obtaining the file hierarchy structure, class definition, class members and UVM-specific structure content in the stock code.

[0017] The input template adopts the YAML format and includes component type, interface definition, function description, parameter configuration, constraint conditions, UVM characteristics, and dependency fields.

[0018] The LLM output guidance template includes: change summary, file change details, operation instruction type, precautions and subsequent steps fields, which are used to describe code changes in a structured manner.

[0019] Wherein, applying the code change information to the stock code includes:

[0020] Parsing code change information generated by large language models;

[0021] Converting the code change information into an executable operation instruction, wherein the operation instruction is at least one of an add code operation, a modify code operation, and a delete code operation;

[0022] Apply the converted operation instructions to the original code.

[0023] The updated code is checked according to the requirement information, including:

[0024] Use a code analysis tool to analyze the updated code to obtain code topology information of the updated code;

[0025] Input the code topology information of the updated code and the requirement information into the big data model and perform the following checks: syntax check, interface consistency check, functional integrity check, naming convention check and UVM specific check;

[0026] If problems are found during the inspection process, detailed code modification suggestions are generated for users to manually review and correct.

[0027] As another aspect of the present application, a chip verification platform incremental development system is also provided, comprising at least:

[0028] The code parsing module is used to parse the stock code of the chip verification platform and extract the code topology information;

[0029] A demand information filling unit is used to fill in demand information according to an input template;

[0030] A code change information acquisition module, used to pass the filled-in requirement information and the topology information as input to the large language model, and obtain the code change information output by the large language model according to the guidance template format;

[0031] A code application module, used for applying the code change information to the stock code to obtain an updated code;

[0032] The code verification module is used to verify the updated code according to the requirement information and obtain a verification platform corresponding to the requirement information.

[0033] The code parsing module further includes a code parsing tool for identifying SystemVerilog syntax in the stock code to obtain the file hierarchy structure, class definition, class members and UVM-specific structure content in the stock code.

[0034] Among them, the input template acquisition module in the input template acquisition module adopts YAML format, including component type, interface definition, function description, parameter configuration, constraint conditions, and UVM characteristic fields.

[0035] The output guidance template in the output template acquisition module includes a change summary, file change details, operation instruction type, precautions and subsequent steps fields, which are used to describe the code changes in a structured manner.

[0036] Wherein, the code application module includes:

[0037] Parsing module, used to parse the code change information generated by the large language model;

[0038] A conversion module, used for converting the code change information into an executable operation instruction, wherein the operation instruction is at least one of an add code operation, a modify code operation and a delete code operation;

[0039] The application module is used to apply the operation instructions obtained by conversion to the original code.

[0040] Wherein, the code checking module includes:

[0041] A re-analysis module is used to parse the updated code using a code analysis tool to obtain updated code topology information;

[0042] A checking module is used to input the updated code topology information and the requirement information into the large language model, and perform the following checks: syntax check, interface consistency check, functional integrity check, naming specification check and UVM specific check;

[0043] The modification suggestion acquisition module is used to generate detailed code modification suggestions for users to manually review and correct when the inspection module finds problems during the inspection process.

[0044] Wherein, the system further comprises:

[0045] The input template setting module is used to set the input template used to describe the verification component for users to fill in according to their needs;

[0046] The output template setting module is used to set the output guidance template for guiding the output of the large language model.

[0047] As another aspect of the present application, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the aforementioned method are implemented.

[0048] Implementing this embodiment has the following beneficial effects:

[0049] The present application provides a chip verification platform incremental development method, system and storage medium. It can realize efficient incremental development of the chip verification platform, greatly improving the efficiency and quality of verification environment construction. The method and system provided by the present application are particularly suitable for the iterative verification process of complex chip design, which can significantly reduce the workload of manual coding and accelerate the evolution and improvement of the verification platform. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, without paying creative labor, other drawings obtained based on these drawings still belong to the scope of the present application.

[0051] Figure 1 A schematic diagram of the main process of an embodiment of a method for incremental development of a chip verification platform provided by the present application;

[0052] Figure 2 A schematic diagram of the structure of an embodiment of a system for incremental development of a chip verification platform provided by the present application;

[0053] Figure 3 for Figure 2 The structural diagram of the code application module;

[0054] Figure 4 for Figure 2 Schematic diagram of the structure of the code checking module. DETAILED DESCRIPTION

[0055] In order to make the objectives, technical solutions and advantages of the present application more clear, the present application will be further described in detail below with reference to the accompanying drawings.

[0056] like Figure 1 As shown, a main flow diagram of an embodiment of a method for incremental development of a chip verification platform provided by the present application is shown; in this embodiment, the incremental development method of the chip verification platform includes the following steps:

[0057] Step S10, parsing the stock code of the chip verification platform and extracting the code topology information;

[0058] Step S11, fill in the required information according to the input template;

[0059] Step S12, passing the filled-in requirement information and the topology information as input to a large language model (LLM), obtaining the code change information output by the large language model in the guidance template format, and outputting it in the output guidance template format;

[0060] Step S13, applying the code change information generated by LLM to the original stock code to obtain the updated code;

[0061] Step S14, verifying the updated code according to the requirement information, and obtaining a verification platform corresponding to the requirement information.

[0062] It is understandable that in the present application, an input template for describing the verification component needs to be pre-set for the user to fill in according to the needs; and an output guidance template for guiding the output of the large language model (LLM) needs to be pre-set.

[0063] The following will describe in detail each step in this application with reference to specific examples.

[0064] In the step S10, parsing the stock code of the chip verification platform includes:

[0065] The code parsing tool is used to parse the stock code of the chip verification platform, including: identifying the SystemVerilog syntax in the stock code, obtaining the file hierarchy structure, class definition, class members and UVM-specific structure in the stock code. The code topology information includes: overall code topology, structure, parameters and other information;

[0066] In a specific example, in this step S10, the application uses a specially developed code parsing tool to fully parse the existing verification platform stock code. The tool is customized and developed, and is particularly adapted to the characteristics of the UVM (Universal Verification Methodology) project, which can not only identify standard SystemVerilog syntax, but also understand UVM's unique structure and macro.

[0067] In specific implementation, the parsing tool will recursively scan the entire UVM project directory, analyze all related SystemVerilog files (.sv suffix), and generate a detailed project structure map (repo map). This map is represented in a tree structure and contains the following key information:

[0068] File hierarchy: reflects the directory and file organization of the project.

[0069] Class definition: includes class name and parent class (if there is an inheritance relationship).

[0070] Class members: include variables, functions, and tasks.

[0071] UVM specific structures: such as phase functions, factory registrations, etc.

[0072] The parsing results will be saved in a structured data format (such as JSON).

[0073] A typical parsing result sample code is as follows:

[0074]

[0075] This parsing result provides a complete structural view of the project, including:

[0076] File hierarchy: such as the various .sv files in the "dsp_uvm_testbench / " directory.

[0077] Class definition: The class defined in each file, such as "dsp_env", "dsp_sequence", etc.

[0078] Inheritance relationship: such as "dsp_env extends uvm_env".

[0079] Member functions and tasks: such as "new", "build_phase", "run_phase", etc.

[0080] Function / task parameters: such as "string name", "uvm_component parent", etc.

[0081] This detailed structured information provides the basis for subsequent incremental development steps. For example, when adding new components or modifying existing components, the system can accurately locate the relevant files that need to be modified based on the component definition expected to be modified in the template, ensuring that the generated incremental code meets expectations and that the new code is consistent with the existing structure.

[0082] In step S11, the input template is pre-set and adopts the YAML format, including component type, interface definition, function description, parameter configuration, constraint conditions, UVM characteristics, and dependency fields.

[0083] In a specific example, the input module used in step S11 is a predefined set of input templates specifically used for verification components such as signal drivers and reference models. The template adopts a YAML format that is easy to fill in and parse to provide a clear structure and good readability. The template design takes into account the characteristics of the UVM verification environment and includes detailed fields to describe various aspects of the verification component.

[0084] The main fields of the template include but are not limited to:

[0085] Component Type: Specifies the type of verification component, such as "Signal Driver", "Reference Model", etc.

[0086] Interface definition: describes the input and output signals of the component in detail, including name, bit width, timing requirements, etc.

[0087] Functional description: Use natural language to describe the main functions and behaviors of the component.

[0088] Parameter Configuration: Lists configurable parameters and their default values.

[0089] Constraints: Specify constraints such as valid value ranges and mutually exclusive relationships.

[0090] UVM characteristics: define specific properties related to UVM, such as phase function, TLM port, etc.

[0091] A wealth of information is provided in the input templates, enabling verification engineers to describe in detail every aspect of the verification component:

[0092] Basic information: including component type, name and function description.

[0093] Interface Definition: Lists all signals of the AXI4 interface in detail, including direction and bit width.

[0094] Configuration parameters: Defines configurable parameters such as the maximum number of outstanding transactions and address width.

[0095] Constraints: Valid burst types and address alignment requirements are specified.

[0096] UVM Features: Lists the UVM phase functions and TLM ports that need to be implemented.

[0097] Extra methods: Defines component-specific methods, such as functions for sending read and write transactions.

[0098] Dependencies: Indicates other classes or components that the component depends on.

[0099] Verification engineers can fill in this template according to actual needs. The completed template will provide detailed component descriptions for subsequent steps, allowing the Large Language Model (LLM) to generate more accurate and compliant code.

[0100] This structured template design has the following advantages:

[0101] Standardization: Provides a unified way to describe different types of verification components.

[0102] Completeness: Covers all important aspects of the verification component, ensuring that the generated code is comprehensive and fully functional.

[0103] Flexibility: Templates can be expanded or customized based on project requirements.

[0104] Readability: YAML format is easy for humans to read and edit, and is also easy for machines to parse.

[0105] UVM-friendly: Special consideration is given to the features of the UVM verification environment, such as phase functions and TLM ports.

[0106] By using such a detailed and structured input template, this application significantly improves the accuracy and completeness of the verification component description, lays a solid foundation for subsequent automated code generation, and thus greatly improves the incremental development efficiency of the chip verification platform.

[0107] The LLM output guidance template involved in step S12 includes: change summary, file change details, operation instruction type, line number, notes and subsequent steps fields, which are used to describe the code changes in a structured manner.

[0108] Change Summary: Briefly summarize the main content and purpose of this change.

[0109] File Change Details: Lists all file changes one by one.

[0110] a) For each file, specify the exact line number range and change operation.

[0111] b) Use code block format to display the specific content of multiple line changes.

[0112] c) Allows inline description of simple single-line changes.

[0113] Action Types: mainly include Add, Modify and Delete, which can be expanded as needed.

[0114] Line Numbers: Can be a single line number or a range.

[0115] Notes: List any points or potential impacts that require special attention.

[0116] Next Steps: List any subsequent actions that need to be performed after completing these changes.

[0117] This template will help LLM generate structured, easy-to-understand change descriptions, allowing verification engineers to quickly understand and implement the required code modifications. It provides enough details to accurately describe the changes while keeping the output concise. By using this template, you can ensure that LLM's output is both detailed and consistent, facilitating the subsequent code implementation and review process.

[0118] The information is spliced ​​and formatted to form a prompt that LLM can understand, including the necessary context, requirements and constraints, and the API call method is used to interact with LLM. LLM determines all the required dependent code information based on the user-defined requirements in step S11 and adds it to the current context. Then, all requirements and related contexts are jointly determined to generate incremental code change information in the format required by the user.

[0119] In step S13, applying the code change information generated by LLM to the original stock code includes the following steps:

[0120] Step S130, parsing the code change information generated by LLM;

[0121] Step S131, converting the code change information into an executable operation instruction, wherein the operation instruction is at least one of an add code operation, a modify code operation, and a delete code operation;

[0122] Step S132, applying the converted operation instructions to the original code.

[0123] In the specific example, in step S13, the code generated by LLM needs to be applied to the original stock verification platform code. First, the output of LLM needs to be parsed and converted into executable operation instructions. According to the parsed change information, the following three main code modification operations can be implemented:

[0124] Add: Insert new code at the specified location.

[0125] Modify: Replace the code in the specified range.

[0126] Delete: Remove the code in the specified range.

[0127] In step S14, the updated code is verified according to the requirement information, including:

[0128] Step S140, using a code analysis tool to analyze the updated code to obtain code topology information of the updated code; that is, using the code analysis tool in step S10 to re-analyze the updated full code.

[0129] Step S141, the code topology information of the updated code and the requirement information filled in the input template by the user are input into the LLM together, and the following checks are performed: syntax check, interface consistency check, function integrity check, naming specification check and UVM specific check;

[0130] It can be understood that in this solution, the original step S11 is skipped, step S12 is re-executed, and at the same time, the inspection content is made clear to the LLM, including:

[0131] Syntax Check: Make sure your code is syntactically correct.

[0132] Interface consistency check: Verify whether the generated code interface is consistent with the interface defined in the input template.

[0133] Functional completeness check: Checks whether all functions described in the input template are implemented.

[0134] Naming standard check: Ensure that the naming of variables, functions, and classes conforms to predefined standards.

[0135] UVM-specific checks: Verify that UVM-specific structures and usages are correct.

[0136] Step S142: If problems are found during the inspection process, detailed code modification suggestions are generated for manual review and correction by the user.

[0137] In a specific example, if a problem is found during the inspection process, the system will generate detailed code modification suggestions for the user to manually review and correct. At this time, you can choose to repeat step S14 or manually confirm and modify.

[0138] It is understandable that in the method provided by this application, by using a code parsing tool to automatically analyze the stock code, combined with a structured input template and a large language model LLM output guidance template, the manual coding workload can be significantly reduced. The incremental development efficiency of the verification platform is improved, making the iteration and update of the verification platform more efficient and able to adapt to changes in chip design more quickly.

[0139] Based on the predefined input template and output guidance template, this application ensures that the generated code conforms to the standardized structure and format. This method can effectively solve the problem of hallucination and unstable output caused by the lack of deep knowledge of the current large language model LLM, and significantly improve the quality of the large prediction model LLM output. At the same time, it improves the readability of the code, ensures the consistency of the entire verification platform code, and reduces errors and inconsistencies caused by human factors.

[0140] Through a modular approach and standardized interface definition, this application makes it easier to add new functions. Verification engineers can describe new verification components by simply filling in templates without having to deeply understand the complex structure of the entire system.

[0141] By automating the code generation and update process, the present application greatly reduces the need for manual code maintenance, which not only reduces the risk of errors, but also reduces the time and labor costs required to maintain the verification platform.

[0142] By encoding the knowledge of verification experts into templates and LLM prompts, this application achieves effective accumulation and reuse of verification experience. This helps to pass on knowledge within the team and improves the verification capabilities of the entire team.

[0143] Through rapid iteration and automated incremental development, this application enables the verification platform to adapt to new design changes and verification requirements more quickly, thereby accelerating the entire chip design and verification cycle.

[0144] like Figure 2 As shown, a chip verification platform incremental development system provided by the present application is shown. Figure 3 to Figure 4 As shown, in this embodiment, the chip verification platform incremental development system 1 at least includes:

[0145] The code parsing module 10 is used to parse the stock code of the chip verification platform and extract the code topology information;

[0146] Wherein, the code parsing module 10 further includes a code parsing tool for identifying SystemVerilog syntax in the stock code to obtain the file hierarchy structure, class definition, class members and UVM-specific structure content in the stock code;

[0147] Demand information filling unit 11, used to fill in demand information according to the input template

[0148] The code change information obtaining module 12 is used to pass the filled-in requirement information and the topology information as input to the large language model (LLM), and obtain the code change information output by the large language model in the guidance template format; and output it in the output guidance template format;

[0149] The code application module 13 is used to apply the code change information generated by the LLM to the original stock code to obtain the updated code;

[0150] The code verification module 14 is used to verify the updated code according to the requirement information and obtain a verification platform corresponding to the requirement information.

[0151] Further including:

[0152] An input template setting module 15 is used to set an input template for describing a verification component, so that the user can fill it out according to the requirements;

[0153] Among them, the input template acquisition module in the input template setting module 15 adopts the YAML format, including component type, interface definition, function description, parameter configuration, constraint conditions, and UVM characteristic fields.

[0154] An output template setting module 16, used to set an output guidance template for guiding the output of a large language model;

[0155] The output guidance template in the output template setting module 16 includes fields for change summary, file change details, operation instruction type, notes and subsequent steps, which are used to describe the code changes in a structured manner.

[0156] More specifically, if Figure 3 As shown, in a specific example, the code application module 13 includes:

[0157] A parsing module 130, used for parsing the code change information generated by the LLM;

[0158] A conversion module 131, used to convert the code change information into an executable operation instruction, wherein the operation instruction is at least one of an add code operation, a modify code operation and a delete code operation;

[0159] The application module 132 is used to apply the operation instructions obtained by conversion to the original code.

[0160] More specifically, if Figure 4 As shown, in a specific example, the code checking module 14 includes:

[0161] A re-analysis module 140 is used to parse the updated code using a code analysis tool to obtain updated code topology information;

[0162] The checking module 141 is used to input the updated code topology information and the requirement information filled in the input template by the user into the LLM, and perform the following checks: syntax check, interface consistency check, function integrity check, naming specification check and UVM specific check;

[0163] The modification suggestion obtaining module 142 is used to generate detailed code modification suggestions for manual review and correction by the user when the inspection module finds problems during the inspection process.

[0164] For more details, please refer to and combine the above Figure 1 The description is not repeated here.

[0165] It can be understood that in the system provided in this application, a special code parsing tool has been developed that can automatically analyze the code of the existing verification platform and extract detailed structured information, laying the foundation for subsequent intelligent incremental development.

[0166] At the same time, by designing a set of detailed and flexible YAML format templates to describe various aspects of the verification component, including interfaces, functions, parameters, etc., the component description is standardized and easy to expand.

[0167] By innovatively designing an output guidance template for standardizing LLM output, the generated code change information is ensured to be structured, accurate and easy to execute, thus improving the degree of automation.

[0168] By organically combining code structure information, user requirements and output guidance templates, high-quality incremental code is generated through LLM, realizing the intelligent update of the verification platform.

[0169] By developing a mechanism to automatically apply LLM-generated code changes to the original code, and designing a multi-level automatic checking process, we ensure the correctness and consistency of the generated code.

[0170] By calling LLM multiple times for code generation and checking, the verification platform is continuously optimized and improved, ensuring the quality of incremental development.

[0171] In summary, the system provided in this application can significantly improve the verification efficiency and quality, and provide strong support for the verification process of complex chip designs.

[0172] As another aspect of the present application, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the above-mentioned Figure 1 For more details, please refer to and combine the above Figure 1 The description is not repeated here.

[0173] Implementing this embodiment has the following beneficial effects:

[0174] The present application provides a chip verification platform incremental development method, system and storage medium. It can realize efficient incremental development of the chip verification platform, greatly improving the efficiency and quality of verification environment construction. The method and system provided by the present application are particularly suitable for the iterative verification process of complex chip design, which can significantly reduce the workload of manual coding and accelerate the evolution and improvement of the verification platform.

[0175] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, devices, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0176] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0177] The above disclosure is only a preferred embodiment of the present application, and certainly cannot be used to limit the scope of rights of the present application. Therefore, equivalent changes made according to the claims of the present application are still within the scope covered by the present application.

Claims

1. A method for incremental development of a chip verification platform, characterized in that: The following steps are involved: Parse the stock code of the chip verification platform and extract the code topology information; Fill in the required information according to the input template; Passing the filled-in requirement information and the topology information as input to the large language model, and obtaining the code change information output by the large language model in the guidance template format; Applying the code change information to the stock code to obtain an updated code; The updated code is verified according to the requirement information to obtain a verification platform corresponding to the requirement information.

2. The method according to claim 1, characterized in that The parsing of the stock code of the chip verification platform includes: The stock code of the chip verification platform is parsed using a code parsing tool, including: identifying SystemVerilog syntax in the stock code, and obtaining the file hierarchy structure, class definition, class members and UVM-specific structure content in the stock code.

3. The method according to claim 2, characterized in that The input template adopts YAML format, including component type, interface definition, function description, parameter configuration, constraint conditions, UVM characteristics, and dependency fields; The LLM output guidance template includes: change summary, file change details, operation instruction type, precautions and subsequent steps fields, which are used to describe code changes in a structured manner.

4. The method according to claim 3, characterized in that: Applying the code change information to the stock code includes: Parsing code change information generated by large language models; Converting the code change information into an executable operation instruction, wherein the operation instruction is at least one of an add code operation, a modify code operation, and a delete code operation; Apply the converted operation instructions to the original code.

5. The method according to claim 4, characterized in that Verify the updated code according to the requirement information, including: Use a code analysis tool to analyze the updated code to obtain code topology information of the updated code; Input the code topology information of the updated code and the requirement information into the big data model and perform the following checks: syntax check, interface consistency check, functional integrity check, naming convention check and UVM specific check; If problems are found during the inspection process, detailed code modification suggestions are generated for users to manually review and correct.

6. A chip verification platform incremental development system, characterized in that: At least: The code parsing module is used to parse the stock code of the chip verification platform and extract the code topology information; A demand information filling unit is used to fill in demand information according to an input template; A code change information acquisition module, used to pass the filled-in requirement information and the topology information as input to the large language model, and obtain the code change information output by the large language model in the guidance template format; A code application module, used for applying the code change information to the stock code to obtain an updated code; The code verification module is used to verify the updated code according to the requirement information and obtain a verification platform corresponding to the requirement information.

7. The system according to claim 6, characterized in that The code parsing module further includes a code parsing tool for identifying SystemVerilog syntax in the stock code to obtain the file hierarchy structure, class definition, class members and UVM-specific structure content in the stock code.

8. The system according to claim 7, characterized in that The input template acquisition module in the input template acquisition module adopts YAML format, including component type, interface definition, function description, parameter configuration, constraint conditions, and UVM characteristic fields; The output guidance template in the output template acquisition module includes a change summary, file change details, operation instruction type, precautions and subsequent steps fields, which are used to describe the code changes in a structured manner.

9. The system according to claim 8, characterized in that The code application module includes: Parsing module, used to parse the code change information generated by the large language model; A conversion module, used for converting the code change information into an executable operation instruction, wherein the operation instruction is at least one of an add code operation, a modify code operation and a delete code operation; The application module is used to apply the operation instructions obtained by conversion to the original code.

10. The system according to claim 9, characterized in that The code checking module comprises: A re-analysis module is used to parse the updated code using a code analysis tool to obtain updated code topology information; A checking module is used to input the updated code topology information and the requirement information into the large language model, and perform the following checks: syntax check, interface consistency check, functional integrity check, naming specification check and UVM specific check; The modification suggestion acquisition module is used to generate detailed code modification suggestions for users to manually review and correct when the inspection module finds problems during the inspection process.

11. The system according to any one of claims 6 to 10, characterized in that: Also includes: The input template setting module is used to set the input template used to describe the verification component for users to fill in according to their needs; The output template setting module is used to set the output guidance template for guiding the output of the large language model.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

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