Debugging interface multiplexing method based on data and control signaling separation

Abstract

The invention belongs to the technical field of semiconductors, and discloses a debugging interface multiplexing method based on data and control signaling separation. The method comprises the following steps: analyzing a JTAG request to obtain an access type; when the access type is an in-band command, selecting an instruction register, inputting a switching instruction to the instruction register, returning to a test running idle state, selecting a data register, and keeping in a shift data register state, so that a data sub-interface is switched from a standard function to an alternative function; transmitting debugging data through the data sub-interface in the alternative function; and when the JTAG request is an out-of-band command, selecting a data register for scanning, entering a data register capturing state, then immediately quitting to a data register pausing state, detecting a scanning sequence, activating an out-of-band function according to the scanning sequence, sending a pin multiplexing request to equipment to be tested, and multiplexing a TMS pin into a bidirectional pin. The transmission rate of debugging data can be improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a debugging interface multiplexing method based on separation of data and control signaling. Background Art

[0002] In the field of chip debugging, the industry generally adopts the standard JTAG interface solution, which includes four main signals: test clock (TCK, Test Clock Input), test data input (TDI, Test Data Input), test mode select (TMS, Test Mode Select) and test data output (TDO, Test Data Output). The user establishes a connection with the device under test through the debug adapter and transmits debug data. There are two common application scenarios for FPGA debugging: one is to use the logic analyzer (CWC, Chip Watcher) inside the chip to capture the timing information of the internal logic nodes; the other is to inject or obtain specific timing signals into the internal logic nodes through the virtual IO interface (VIO, Virtual IO). In both cases, data transmission is completed through the JTAG interface. For FPGA chips that integrate a processor subsystem, a common practice is to connect the test access point (TAP) of the processor subsystem and the TAP of the FPGA subsystem to the same JTAG link, so that the two subsystems can share the same debug interface. When the processor is in trace debugging (Trace mode), the processor transmits trace data through a dedicated trace interface equipped in its debug subsystem, such as the ARM TPIU parallel interface.

[0003] In the case of deep integration of processor system and FPGA system, such as Xilinx's Zynq series devices, the two share JTAG bandwidth, resulting in reduced debugging efficiency. In cascade mode, debugging one of the subsystems requires inserting escape sequences in the JTAG access sequence to avoid misoperation of the other part, which further reduces the bandwidth of the debug bus. For the processor subsystem, JTAG is not the most optimized debug signaling carrier. JTAG relies on the alternating operation of the IR (Instruction Register) and DR (Data Register) registers. Frequent switching of IR / DR will reduce the debug bus bandwidth and the debugging efficiency of the processor subsystem. The TPIU / SWO interface proposed by ARM allows the system to actively send processor execution status tracking data and debug data, but these functions cannot be applied to FPSoC debugging based on the JTAG interface. The TPIU / SWO interface is independent and incompatible with the JTAG interface, and there is no similarity in function, so it cannot be directly integrated.

[0004] In summary, with the deep integration of processor systems and FPGA systems, JTAG debugging faces challenges in bandwidth sharing, low efficiency, interface incompatibility, and physical implementation. Summary of the invention

[0005] To this end, an embodiment of the present application provides a debugging interface multiplexing method based on separation of data and control signaling, which separates the data transmission interface and the control signaling interface and efficiently transmits the debugging data.

[0006] In a first aspect, the present application provides a debugging interface multiplexing method based on separation of data and control signaling.

[0007] The present application is implemented by the following technical solution: a debugging interface based on the separation of a data sub-interface and a control signaling sub-interface, the method comprising:

[0008] S1: receiving a JTAG request, parsing the JTAG request to obtain an access type, where the access type includes an in-band command and an out-of-band command;

[0009] When the access type is an in-band command, steps S2 to S5 are executed:

[0010] S2: Select an instruction register and input a switching instruction into the instruction register, wherein the switching instruction is used to specify an alternative function of the data sub-interface in a multiplexing mode in which data and control signaling are separated;

[0011] S3: Return to the test running idle state;

[0012] S4: Select the data register and keep it in the shift data register state so that the data sub-interface switches from the standard function to the alternative function;

[0013] S5: transmitting debugging data through the data sub-interface in the alternative function;

[0014] When the JTAG request is an out-of-band command, steps S6 to S8 are executed:

[0015] S6: Select data register scan, enter the capture data register state and immediately exit to the pause data register state;

[0016] S7: Detect the scan sequence and activate the out-of-band function according to the scan sequence;

[0017] S8: Send a pin multiplexing request to the device under test to multiplex the TMS pin into a bidirectional pin.

[0018] In a preferred example of the present application, it can be further configured that after the debugging data is transmitted through the data sub-interface in the alternative function, the method further includes:

[0019] When the host needs to reuse the standard functions of the TDI pin and the TDO pin in the data sub-interface, the TMS pin returns to the test run idle state, so that the data sub-interface switches from the alternative function to the standard function.

[0020] In a preferred example of the present application, it can be further configured that after the debugging data is transmitted through the data sub-interface in the alternative function, the method further includes:

[0021] When the host needs to reuse the standard function of the alternative pins in the data sub-interface, the command register is selected through the TMS pin and a switching command is input into the command register.

[0022] In a preferred example of the present application, it can be further configured that after the TMS pin is multiplexed as a bidirectional pin, the method further includes:

[0023] When you need to switch the TMS pin back to standard JTAG mode, use the TMS bidirectional multiplexing timing to send a sequence to the device under test to move the JTAG state machine to the TEST-LOGIC-RESET state.

[0024] In a preferred example of the present application, it can be further configured that after the TMS pin is multiplexed as a bidirectional pin, the method further includes:

[0025] A preset number of consecutive high levels are output to the TMS pin using a weak driver to implement a forced debug interface reset operation without relying on the state of the JTAG state machine.

[0026] In a preferred example of the present application, it can be further configured as follows: Step S6: detecting a scan sequence, and activating an out-of-band function according to the scan sequence, including:

[0027] After the host sends a data register scan request, the counter counts that the host repeatedly sends 8 data register scan requests that do not enter the shift data register state and 1 data register scan request that enters the shift data register state, and then activates the out-of-band function.

[0028] In a preferred example of the present application, it can be further configured to multiplex the TMS pin into a bidirectional pin, including:

[0029] The time division multiplexing mode is adopted to transmit the original TMS signal, TDI signal and TDO signal bidirectionally on the TMS pin.

[0030] In a preferred example of the present application, it can be further configured that the alternative functions include the following functions:

[0031] Standard JTAG functions, CWC capture data output, processor trace signal output, VIO interface input and output, processor core semi-hosting interface input and output.

[0032] Secondly, the present application is realized through the following technical solutions:

[0033] A computer device comprises a memory, a processor and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the processor implements any of the steps of the above-mentioned debugging interface multiplexing method based on separation of data and control signaling.

[0034] In a third aspect, the present application provides a computer-readable storage medium.

[0035] This application is achieved through the following technical solutions:

[0036] A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the computer program implements any of the steps of the above-mentioned debugging interface multiplexing method based on separation of data and control signaling.

[0037] In summary, compared with the prior art, the technical solution provided in the embodiment of the present application has at least the following beneficial effects:

[0038] The present application obtains the access type by parsing the JTAG request; when the access type is an in-band command, the instruction register is selected, a switching instruction is input into the instruction register, the test run idle state is returned, the data register is selected, and the shift data register state is maintained so that the data sub-interface switches from the standard function to the alternative function, and the debug data is transmitted through the data sub-interface in the alternative function; when the JTAG request is an out-of-band command, the data register scan is selected, and the capture data register state is entered and then immediately exited to the pause data register state, the scan sequence is detected, the out-of-band function is activated according to the scan sequence, a pin multiplexing request is sent to the device under test, and the TMS pin is multiplexed as a bidirectional pin. The data interface and the control signaling interface can be separated, and the data interface can be specially optimized for rate and coding, which is not restricted by the host polling transmission model in the JTAG protocol, thereby improving the transmission rate and efficiency; the mode switching can flexibly use in-band and out-of-band signaling. The former facilitates the use of all-digital circuits in traditional JTAG state machines to implement high-speed debugging subsystems, and the latter allows JTAG operations to be performed simultaneously while the debugging subsystem is running; the control interface is compatible with JTAG, and the control interface can be switched to TMS multiplexing mode to reduce the line density of the debug port and reduce unstable data transmission caused by poor contact. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1A flowchart of a debug interface multiplexing method based on separation of data and control signaling provided in one embodiment of the present application. DETAILED DESCRIPTION

[0040] This specific embodiment is merely an explanation of the present application and is not a limitation of the present application. After reading this specification, those skilled in the art may make modifications to the present embodiment without any creative contribution as needed, but such modifications are protected by the patent law as long as they are within the scope of the claims of the present application.

[0041] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0042] In addition, the term "and / or" in this application is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this application, unless otherwise specified, generally indicates that the associated objects before and after are in an "or" relationship.

[0043] In this application, the terms "first", "second", etc. are used to distinguish identical or similar items with basically the same effects and functions. It should be understood that there is no logical or temporal dependency between "first", "second", and "nth", nor is there any limitation on quantity and execution order.

[0044] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0045] The embodiments of the present application are further described in detail below in conjunction with the drawings in the specification.

[0046] Figure 1The first exemplary embodiment of the present application provides a debug interface multiplexing method based on data and control signaling separation. The debug interface multiplexing method proposed in the present application is based on a debug interface with a data sub-interface and a control signaling sub-interface separated, wherein the control signaling sub-interface includes a test clock pin (TCK pin) and a test mode pin (TMS pin), and the control signaling sub-interface is configured to be unable to change the function; the data sub-interface includes a test data input (TDI pin), a test data output (TDO pin) and other optional spare pins, and the data sub-interface is configured to be able to change the function according to the switching instruction. At the same time, the debug interface of the present application fully supports the control timing of the traditional JTAG interface, ensuring that the traditional debugging host can communicate with the debug interface in the present application without obstacles. The original JTAG interface with mixed control commands and data transmission is split into a control signaling sub-interface and a data sub-interface, and the data interface can be specially optimized for rate and coding. The JTAG interface is not limited by the transmission model of host polling in the JTAG protocol, which improves the transmission rate and efficiency.

[0047] After JTAG reset or debug subsystem reset, this debug interface returns to standard JTAG mode by default. Specifically, when the host sends a special command, the function of the data sub-interface can be switched to the alternative function, and the alternative function includes at least the following functions: standard JTAG function, CWC capture data output, processor tracking signal output, VIO interface input and output, processor core semi-hosting interface input and output. Alternative electrical characteristics include but are not limited to single-ended signals, low-voltage differential signals, and bidirectional low-voltage differential signals with echo cancellation. In the multiplexing mode where data and control signaling are separated, the link coding of the data sub-interface uses a DC-free coding scheme, preferably an 8b / 10b scrambling method or a Manchester coding method. The use of a DC-free coding scheme facilitates the recovery time of the receiving end and digital isolation of the signal transformer, reduces system complexity, and can provide an easy and low-cost electrical isolation solution for systems that require electrical isolation.

[0048] The specific debugging interface multiplexing method is carried out according to the following steps:

[0049] S1: Receive a JTAG request, parse the JTAG request to obtain an access type, and the access type includes an in-band command and an out-of-band command.

[0050] Specifically, JTAG requests from external devices are received and processed by the JTAG control logic (JTAG master state machine). JTAG requests include IR scan requests (instruction register scan requests), DR scan requests (data register scan requests), and other requests. Other access requests are JTAG accesses other than IR scan (instruction register scan) and DR scan (data register scan), such as RUN TEST IDLE (test logic reset) / TEST-LOGIC-RESET (test logic run).

[0051] Determine the access type of the JTAG request and judge whether it is a special command or other command. Special commands include in-band commands and out-of-band commands, and other commands are commands other than special commands. Special commands are parsed and executed by the serial debug controller (also called multiplexed state machine logic).

[0052] When the access type is an in-band command, steps S2 to S5 are executed:

[0053] S2: Select an instruction register and input a switching instruction into the instruction register. The switching instruction is used to specify an alternative function of the data sub-interface in a multiplexing mode in which data and control signaling are separated.

[0054] Specifically, the instruction register is selected through the TMS pin, and the switching instruction is input into the instruction register through the TDI pin and the TDO pin. The above instruction register belongs to the register of the JTAG interface itself. The switching instruction can be input into the instruction register by selecting the instruction register-update instruction register scanning route in the standard JTAG timing. After the JTAG control logic parses the special command, it sends an enable signal to the multiplexing state machine logic to complete the selection of the alternative function of the data sub-interface and the switching of the electrical characteristics.

[0055] S3: Return to the test run idle state.

[0056] Specifically, the TMS pin is used to control the JTAG interface to return to the test run idle state. In the test run idle state, the data sub-interface of the debug interface is still in the default standard function, such as the standard JTAG TDI function and the standard JTAG TDO function.

[0057] S4: Select the data register and keep it in the shift data register state so that the data sub-interface switches from the standard function to the alternative function.

[0058] Through the TMS pin, the data register is selected and kept in the shift data register state (SHIFT-DR). In the shift data register state, the data sub-interface is truly switched from the standard function to the alternative function. The alternative functions include the following functions: standard JTAG function, CWC capture data output, processor trace signal output, VIO interface input and output, processor core semi-hosting interface input and output.

[0059] S5: Debug data is transmitted via the data sub-interface in the alternative function.

[0060] After switching the data sub-interface to the alternative function, the host can communicate efficiently with the device under test through the alternative function multiplexed by the data sub-interface. Because after the data and control signaling separation mode is selected, the TDI pin and TDO pin in the data sub-interface will be independent of the traditional JTAG interface and used to transmit debugging data independent of control signaling, improving debugging efficiency and maintaining compatibility with the traditional JTAG interface.

[0061] When the JTAG request is an out-of-band command, steps S6 to S8 are executed:

[0062] S6: Select data register scan, enter the capture data register state and immediately exit to the pause data register state.

[0063] Among them, through the TMS pin data register scan, after entering the capture data register state (CAPTURE-DR), it immediately exits to the pause data register state (EXIT1-DR). At this time, the data in the data register has not been affected.

[0064] S7: Detects the scan sequence and activates out-of-band functions based on the scan sequence, including:

[0065] After the host sends a data register scan request, the out-of-band function is activated after the counter counts that the host repeatedly sends eight data register scan requests that do not enter the shift data register state and one data register scan request that enters the shift data register state.

[0066] The device under test has an internal counter that counts the number of times a specific scan sequence occurs continuously. This scan sequence is part of the JTAG operation and can be achieved by sending a specific signal sequence through the TMS (Test Mode Select) pin. In order to be compatible with the industrial standard IEEE 1149.7, when the counter detects that the scan sequence is repeated 2 or more times in a row, an action is triggered, that is, turning off (disabling) the traditional JTAG debugging function. This means that under this condition, the JTAG interface will no longer be used for standard debugging operations. If the device under test detects that the scan sequence is repeated 2 or more times in a row, and the host (the device controlling the JTAG operation) sends a data register scan request at this time, but enters the SHIFT-DR state (shift data register state), the control function to be entered will be determined based on the value of the counter. The host needs to repeat the scan request without entering the SHIFT-DR state 8 times, and then send a scan request to enter the SHIFT-DR state once, so that the counter value will reach 8, thereby activating the out-of-band function. At this time, the JTAG interface will be used for functions other than standard debugging. After the out-of-band function is activated, the host can send a pin multiplexing request unidirectionally through the TMS pin to multiplex the TMS pin into a bidirectional pin, so that the TMS, TDI, and TDO signals can be transmitted bidirectionally on the TMS pin, and a commutation cycle can be added to prevent short circuits.

[0067] S8: Send a pin multiplexing request to the device under test to multiplex the TMS pin into a bidirectional pin.

[0068] Specifically, the TMS pin is multiplexed into a bidirectional pin, including:

[0069] The time division multiplexing mode is adopted to transmit the original TMS signal, TDI signal and TDO signal bidirectionally on the TMS pin.

[0070] Pin multiplexing adopts time-division multiplexing mode, which means that the same physical pin can be used to transmit different signals in different time periods. The mode of pin multiplexing request is represented by the number of cycles that the host stays in SHIFT-DR. For example, staying for 1 cycle means that the multiplexing mode is 1. Furthermore, when pin multiplexing adopts time-division multiplexing mode, the original TMS, TDI, and TDO signals are transmitted bidirectionally on the TMS pin, and the corresponding switching cycle (turn) is added to prevent the host and the device under test from driving TMS at the same time and causing a short circuit.

[0071] In another embodiment of the present application, when the access type is an in-band command, after the debugging data is transmitted through the data sub-interface in the alternative function, the following is further included:

[0072] When the host needs to reuse the standard functions of the TDI pin and the TDO pin in the data sub-interface, the TMS pin is used to return to the test run idle state, so that the data sub-interface switches from the alternative function to the standard function. Specifically, the host sends a specific timing signal through the TMS pin to control the transition of the JTAG state machine. The TMS signal is sampled on the rising edge of TCK and is used to control the state transition of the TAP state machine. This process allows the JTAG interface to flexibly restore to its standard functional state after executing special commands to support subsequent standard JTAG operations.

[0073] In another embodiment of the present application, after the debugging data is transmitted through the data sub-interface in the alternative function, the method further includes:

[0074] When the host needs to reuse the standard function of the alternative pins in the data sub-interface, the command register is selected through the TMS pin and a switching command is input into the command register.

[0075] In another embodiment of the present application, after the TMS pin is multiplexed as a bidirectional pin, the method further includes:

[0076] When you need to switch the TMS pin back to standard JTAG mode, use the TMS bidirectional multiplexing timing to send a sequence to the device under test to move the JTAG state machine to the TEST-LOGIC-RESET state.

[0077] In another embodiment of the present application, after the TMS pin is multiplexed as a bidirectional pin, the method further includes:

[0078] A weak driver is used to output a preset number of continuous high levels to the TMS pin to implement a mandatory debug interface reset operation without relying on the state of the JTAG state machine. It should be noted that after the JTAG interface enters the out-of-band mode, the TMS pin transmits the original TMS signal, TDI signal, and TDO signal in time-division multiplexing. The purpose of using a weak driver to output a high level to the TMS pin is: 1. Reset the state machine. When the standard JTAG state machine receives the TMS signal in a continuous high level (1) state for 5 times, it will be forced to enter the reset (Test Logic Reset, TLR) state regardless of the current state; 2. Prevent short circuit. After entering the out-of-band mode, the TMS line becomes a bidirectional signal. In order to prevent the host and the device from outputting signals at the same time and causing a short circuit at the IO port, the host will switch to a weak driver state. In this way, even if the TMS line is in the output cycle, it will not cause a short circuit due to signal conflict, thereby protecting the interface from being burned.

[0079] The number of high levels is the time division multiplexing frame period multiplied by 5. Exemplarily, when the time division multiplexing frame format is TMS, TDI, TURN, TDO, TURN, then the length of a time division multiplexing frame is 5 periods. In order to enter the reset state, 25 periods of high level (1) need to be continuously sent to the TMS line. To ensure the reliability of the reset, the debugger should select the longest number of time division multiplexing frame periods to determine how many consecutive weak drive 1 states should be used to reset the debug interface.

[0080] An embodiment of the present application provides a computer device, which may include a processor, a memory, a network interface, and a database connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, the processor executes the steps of the debug interface multiplexing method based on data and control signaling separation as in any of the above embodiments.

[0081] The working process, working details and technical effects of the computer device provided in this embodiment can be found in the above embodiment of the debug interface multiplexing method based on separation of data and control signaling, which will not be described in detail here.

[0082] The embodiment of the present application provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the debug interface multiplexing method based on separation of data and control signaling as in any of the above embodiments are implemented. The computer-readable storage medium refers to a carrier for storing data, which may include but is not limited to a floppy disk, an optical disk, a hard disk, a flash memory, a USB flash drive and / or a memory stick, etc. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.

[0083] The working process, working details and technical effects of the computer-readable storage medium provided in this embodiment can be found in the above embodiment of the debug interface multiplexing method based on separation of data and control signaling, which will not be described in detail here.

[0084] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0085] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0086] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the system described in the present application is divided into different functional units or modules to complete all or part of the functions described above.

Claims

1. A debug interface multiplexing method based on separation of data and control signaling, characterized in that: Based on a debug interface separated from a data sub-interface and a control signaling sub-interface, the method comprises: S1: receiving a JTAG request, parsing the JTAG request to obtain an access type, where the access type includes an in-band command and an out-of-band command; When the access type is an in-band command, steps S2 to S5 are executed: S2: Select an instruction register and input a switching instruction into the instruction register, wherein the switching instruction is used to specify an alternative function of the data sub-interface in a multiplexing mode in which data and control signaling are separated; S3: Return to the test running idle state; S4: Select the data register and keep it in the shift data register state so that the data sub-interface switches from the standard function to the alternative function; S5: transmitting debugging data through the data sub-interface in the alternative function; When the JTAG request is an out-of-band command, steps S6 to S8 are executed: S6: Select data register scan, enter the capture data register state and immediately exit to the pause data register state; S7: Detect the scan sequence and activate the out-of-band function according to the scan sequence; S8: Send a pin multiplexing request to the device under test to multiplex the TMS pin into a bidirectional pin.

2. The debug interface multiplexing method based on separation of data and control signaling according to claim 1, characterized in that: After the debugging data is transmitted through the data sub-interface in the alternative function, it also includes: When the host needs to reuse the standard functions of the TDI pin and the TDO pin in the data sub-interface, the TMS pin returns to the test run idle state, so that the data sub-interface switches from the alternative function to the standard function.

3. The debug interface multiplexing method based on separation of data and control signaling according to claim 2, characterized in that: After the debugging data is transmitted through the data sub-interface in the alternative function, it also includes: When the host needs to reuse the standard function of the alternative pins in the data sub-interface, the command register is selected through the TMS pin and a switching command is input into the command register.

4. The debugging interface multiplexing method based on separation of data and control signaling according to claim 1, characterized in that: After multiplexing the TMS pin as a bidirectional pin, it also includes: When you need to switch the TMS pin back to standard JTAG mode, use the TMS bidirectional multiplexing timing to send a sequence to the device under test to move the JTAG state machine to the TEST-LOGIC-RESET state.

5. The debug interface multiplexing method based on separation of data and control signaling according to claim 1, characterized in that: After multiplexing the TMS pin as a bidirectional pin, it also includes: A preset number of consecutive high levels are output to the TMS pin using a weak driver to implement a mandatory debug interface reset operation independent of the current state of the JTAG state machine.

6. The debug interface multiplexing method based on separation of data and control signaling according to claim 1, characterized in that: Step S6: Detecting a scan sequence and activating an out-of-band function according to the scan sequence, including: After the host sends a data register scan request, the counter counts that the host repeatedly sends 8 data register scan requests that do not enter the shift data register state and 1 data register scan request that enters the shift data register state, and then activates the out-of-band function.

7. The debug interface multiplexing method based on separation of data and control signaling according to claim 1, characterized in that: Multiplex the TMS pin into a bidirectional pin, including: The time division multiplexing mode is adopted to transmit the original TMS signal, TDI signal and TDO signal bidirectionally on the TMS pin.

8. The debug interface multiplexing method based on separation of data and control signaling according to any one of claims 1 to 7, characterized in that: The alternative functions include the following: Standard JTAG functions, CWC capture data output, processor trace signal output, VIO interface input and output, processor core semi-hosting interface input and output.

9. A computer device, characterized in that: The method comprises a memory, a processor and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 8 are implemented.

Images