Method and apparatus, system, device, medium and program product for testing a board card

Abstract

The application provides a board card testing method, device, system, equipment, medium and program product. The method comprises the following steps: obtaining a target load; wherein the target load is a load that enables the power of the processor under test to reach the rated power; the target load is issued to the processor under test every first preset time interval until the test time reaches a second preset time; the test time is the time interval between the time when the target load is issued for the first time and the current time; the running condition of the processor under test is obtained, and whether the board card where the processor under test is located normally runs the load is determined according to the running condition; the running condition comprises the execution result of the processor under test processing the target load and / or the board card power of the board card where the processor under test is located. In this way, by simulating the running condition of the processor under test in a real use scenario, it can be tested whether the power supply design of the board card meets the actual use scenario.

Description

Technical Field

[0001] This application relates to the field of circuit board testing technology, and more specifically, to a circuit board testing method, apparatus, system, equipment, medium, and program product. Background Technology

[0002] Servers typically consist of circuit boards containing processors. As processor computing power increases, so does the power consumption of these circuit boards, posing significant challenges to their power supply design. Current testing of these circuit boards usually only addresses whether they can achieve the expected power output, neglecting to consider whether the power supply design meets the requirements of real-world usage scenarios. Summary of the Invention

[0003] The purpose of this application is to provide a testing method, apparatus, system, device, medium, and program product for circuit boards, in order to solve the problem in related technologies that it is impossible to assess whether the power supply design of the circuit board meets the actual use scenario during actual use.

[0004] This application provides a method for testing a circuit board, wherein the circuit board is equipped with a processor under test. The method includes: acquiring a target load; wherein the target load is a load that enables the processor under test to reach its rated power during processing; sending the target load to the processor under test at first preset time intervals until the test duration reaches a second preset time interval; the test duration is the time between the first time the target load is sent and the current time; acquiring the operating status of the processor under test, and determining whether the circuit board on which the processor under test is located is operating normally under load based on the operating status; the operating status includes the execution result of the processor under test processing the target load and / or the power of the circuit board on which the processor under test is located.

[0005] In the above implementation, it is considered that in actual use, the processor on the board will not process a task only once, nor will it continuously process a certain task. That is, the workload of the processor under test is intermittent. By sending the target load to the processor under test at intervals of the first preset time interval within the second preset time interval, the operation of the processor under test in a real-world usage scenario can be simulated. Based on the operation, it is possible to evaluate whether the processor on the board can operate normally in actual use. Considering that the processor requires appropriate power supply from the board when processing the load, if the processor on the board cannot correctly execute the target load or the power consumption of the board does not match expectations when the processor is running, then there may be a problem with the board's power supply design. By simulating the operation of the processor under test in a real-world usage scenario, it is possible to test whether the board's power supply design meets the actual usage scenario.

[0006] Further, obtaining the target load includes: obtaining the model of the processor under test; searching for the load type corresponding to the model and the minimum load dimension corresponding to the load type in a preset association relationship; the association relationship records the correspondence between the model, load type, and minimum load dimension; wherein, the load dimension is used to describe the size of the load; issuing alternative loads to the processor under test; the alternative loads are: loads belonging to the load type and having the minimum load dimension of the load type; obtaining the actual power of the processor under test when processing the alternative loads; if the actual power is less than the rated power, increasing the load dimension to obtain alternative load dimensions, and issuing a new alternative load belonging to the load type and having the alternative load dimension to the processor under test; repeating the above process until the actual power is greater than or equal to the rated power; the alternative load when the actual power is greater than or equal to the rated power is the target load.

[0007] In the above embodiments, it is considered that different types of processors can drive different types of loads, and that the size of the loads they can drive also differs due to the different performance of different types of processors. By obtaining the load type corresponding to the model of the processor under test and the minimum load dimension corresponding to the load type, it is easy to obtain the load that the processor under test can handle. By continuously increasing the load dimension, it is easy to obtain the minimum load that allows the processor under test to reach its rated power.

[0008] Furthermore, increasing the load dimension to obtain alternative load dimensions includes: obtaining the current load dimension; and calculating the sum of the current load dimension and a preset dimension as alternative load dimensions.

[0009] In the above implementation, the alternative load dimension is obtained by directly adding the load dimension to the preset dimension. The calculation is simple and the load dimension can be increased conveniently.

[0010] Furthermore, the target load is sent to the processor under test at first preset intervals until the test duration reaches a second preset duration, including: repeatedly executing the first test strategy until the test duration reaches the second preset duration; the first test strategy includes: sending a first preset number of target loads to the processor under test, waiting for the processor under test to process the first preset number of target loads, and then waiting for a third preset duration; the third preset duration is equal to the time it takes for the processor under test to process the first preset number of target loads; correspondingly, the first preset duration is equal to the sum of the third preset duration and the time it takes for the processor under test to process the first preset number of target loads.

[0011] In the above implementation, by sending a target load to the processor on the board every first preset time interval, the usage scenario in which the processor on the board continuously receives and processes tasks during actual use can be simulated, so as to determine whether the power supply design of the board is reasonable under the usage scenario in which the processor on the board continuously receives and processes tasks.

[0012] Furthermore, the target load is sent to the processor under test at first preset intervals until the test duration reaches a second preset duration, including: repeatedly executing the second test strategy until the test duration reaches the second preset duration; the second test strategy includes: obtaining a first random number n, sending n target loads to the processor under test; waiting for the processor under test to process the n target loads, and then waiting for a fourth preset duration; the fourth preset duration is equal to the time it takes for the processor under test to process the n target loads; correspondingly, the first preset duration is equal to the sum of the fourth preset duration and the time it takes for the processor under test to process the n target loads.

[0013] In the above implementation, by changing the number of target loads sent in each round within the second preset time period, it is possible to simulate the usage scenario in which the processor on the board needs to process different numbers of tasks at different times during actual use, so as to determine whether the power supply design of the board is reasonable in usage scenarios where the amount of processing received by the processor on the board varies greatly.

[0014] Furthermore, the target load is sent to the processor under test at first preset intervals until the test duration reaches a second preset duration, including: repeatedly executing a third test strategy until the test duration reaches the second preset duration; the third test strategy includes: obtaining a second random number m and a random duration, sending m target loads to the processor under test; waiting for the processor under test to process the m target loads, and then waiting for the random duration; correspondingly, the first preset duration is equal to the sum of the random duration and the duration for the processor under test to process the m target loads.

[0015] In the above implementation, by changing the number of target loads issued in each round within the second preset time period, and changing the waiting time after each target load is processed, it is possible to simulate the usage scenario of issuing tasks to the processor on the board at irregular intervals and in varying quantities, so as to determine whether the power supply design of the board is reasonable when the processor on the board receives tasks at irregular intervals and in varying quantities.

[0016] Furthermore, the random duration is obtained by: obtaining a third random number k; and determining the random duration based on k and the time taken for the tested processor to process m target loads.

[0017] In the above implementation, the time taken for the processor under test to process m target loads is adjusted by using a third random number. The calculation is simple and the random duration can be obtained conveniently.

[0018] Furthermore, the operational status includes the execution result of the processor under test processing the target load and the board power of the board on which the processor under test is located; determining whether the board on which the processor under test is located is operating normally based on the operational status includes: if the execution result is correctly represented and the board power is normal, determining that the board on which the processor under test is located is operating normally; otherwise, determining that the board on which the processor under test is located is operating abnormally.

[0019] In the above implementation, verifying the correctness of the processor's execution result in handling the target load indicates whether the processor is operating normally. Simultaneously, checking the board power consumption indicates whether the power generated by the processor during operation meets the expected power output of the board. Combining the processor's execution result in handling the target load and the board power consumption provides a more comprehensive and accurate assessment of the board's power supply design.

[0020] Furthermore, the operating status includes the board power of the board where the processor under test is located; determining whether the board where the processor under test is located is operating normally based on the operating status includes: if the difference between the board power and the preset power is within a preset range, determining that the board where the processor under test is located is operating normally; otherwise, determining that the board where the processor under test is located is operating abnormally; the preset power is equal to half of the rated power.

[0021] In the above embodiments, whether the board power is normal can reflect whether the power generated by the processor during operation reaches the power design expected by the board, and thus can reflect whether the board power supply design is reasonable.

[0022] Furthermore, the operational status includes the execution result of the processor under test processing the target load; determining whether the board on which the processor under test is located is operating normally under load based on the operational status includes: if the execution result is correct, determining that the board on which the processor under test is located is operating normally under load; otherwise, determining that the board on which the processor under test is located is operating abnormally under load.

[0023] In the above embodiments, by verifying whether the execution result of the processor in processing the target load is correct, it can be reflected whether the processor can operate normally, and thus whether the power supply design of the board will cause problems with the processor.

[0024] This application provides a testing system, including: a main control processor connected to a board; the main control processor is used to acquire a target load; send the target load to the processor under test at first preset intervals until the test duration reaches a second preset duration; wherein, the target load is a load that enables the processor under test to reach its rated power during processing; the test duration is the time between the first time the target load is sent and the current time; acquire the operating status of the processor under test, and determine whether the board on which the processor under test is located is operating normally under load based on the operating status; the operating status includes the execution result of the processor under test processing the target load and / or the board power of the board on which the processor under test is located; the processor under test, configured on the board, is used to receive the target load sent by the main control processor, process the target load, obtain the execution result of processing the target load, and send the execution result to the main control processor.

[0025] This application provides an electronic device, including a main control processor, a circuit board, and a memory. The memory stores computer-executable instructions that can be executed by the main control processor. The circuit board is equipped with the main control processor, which executes the computer-executable instructions to implement the aforementioned circuit board testing method.

[0026] This application provides a storage medium storing computer-executable instructions. When these computer-executable instructions are invoked and executed by a main control processor, they enable the main control processor to implement the aforementioned board testing method.

[0027] This application provides a computer program product, which includes a computer program that, when executed by a main control processor, implements the above-described board testing method.

[0028] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0029] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 A flowchart illustrating a testing method for a circuit board provided in an embodiment of this application;

[0031] Figure 2A flowchart illustrating a method for determining a target load, provided in an embodiment of this application;

[0032] Figure 3 A flowchart illustrating another testing method for a circuit board provided in an embodiment of this application;

[0033] Figure 4 A flowchart illustrating another testing method for a circuit board provided in this application embodiment;

[0034] Figure 5 A flowchart illustrating another method for testing a circuit board provided in this application embodiment;

[0035] Figure 6 A testing system provided for embodiments of this application.

[0036] Figure label:

[0037] 1: Main controller processor; 2: Board; 3: Processor under test. Detailed Implementation

[0038] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0039] Example 1:

[0040] In some embodiments, a main control processor and a circuit board are independently configured within the same electronic device. One or more processors under test are configured on the circuit board. The main control processor can interact with the processors on the circuit board.

[0041] To address the challenge of evaluating the rationality of a circuit board's power supply design during actual use, this application provides a testing method for the circuit board. See also... Figure 1 As shown, Figure 1 This is a basic flowchart illustrating the testing method for the circuit board provided in this application embodiment, including:

[0042] Step S101: Obtain the target load.

[0043] The target load is a load that ensures the processor under test (DUT) reaches its rated power during processing. Testing with a load that allows the DUT to operate at its rated power ensures it operates within a safe range, preventing potential damage from overload. Furthermore, it helps to understand the performance of both the board and the DUT under maximum power, providing a more accurate reflection of the board's power supply design's rationality.

[0044] The processor under test is the processor installed on the board. Processors include, for example, GPUs (Graphics Processing Units), TPUs (Tensor Processing Units), and NPUs (Neural Processing Units).

[0045] For example, if the board has one processor A, then processor A is the processor under test, and the target load is the load that ensures processor A reaches its rated power during processing. If the board has two processors, such as processor B and processor C, then both processor B and processor C are processors under test. In this case, there will be a load for processor B that ensures processor B reaches its rated power during processing, and a load for processor C that ensures processor C reaches its rated power during processing.

[0046] In some embodiments, obtaining the target load may involve: obtaining the model of the processor under test; searching for the load type corresponding to the model and the minimum load dimension corresponding to the load type in a preset association relationship; issuing alternative loads to the processor under test; obtaining the actual power of the processor under test when processing the alternative loads; if the actual power is less than the rated power, increasing the load dimension to obtain alternative load dimensions, and issuing a new alternative load that belongs to the load type and has alternative load dimensions to the processor under test; repeating the above process until the actual power is greater than or equal to the rated power; the alternative load when the actual power is greater than or equal to the rated power is the target load.

[0047] The association records the correspondence between model, load type, and minimum load dimension. Optionally, the load type recorded in the association is the type of load that causes the processor to consume the most energy per unit time.

[0048] The load type refers to the type of load, such as matrix calculation, image processing, video processing, etc.

[0049] The load dimension is used to describe the size of the load.

[0050] For example, when the payload is a matrix calculation, the size of the payload can be the number of rows and columns of the matrix; when the payload is an image, the size of the payload can be the width and height of the image. When the payload is video, since video is essentially composed of multiple frames of images, the size of the payload can also be the width and height of each frame that makes up the video.

[0051] Optionally, the alternative load is: the load that belongs to the load type corresponding to the model of the processor under test and has the smallest load dimension of that load type.

[0052] In one embodiment of the above examples, increasing the load dimension to obtain alternative load dimensions may include: obtaining the current load dimension; and calculating the sum of the current load dimension and a preset dimension as alternative load dimensions.

[0053] In another embodiment of the above embodiments, increasing the load dimension to obtain alternative load dimensions may include: obtaining the number of times the alternative load is sent; the number of times the alternative load is sent to the processor under test; calculating the product of the number of times the alternative load is sent and the preset dimension to obtain the dimension to be added; and calculating the sum of the minimum load dimension and the dimension to be added to obtain the alternative load dimension.

[0054] For example, in combination Figure 2 As shown, this application provides a method for determining target load for each processor under test, including:

[0055] Step S201: Obtain the rated power and model number of the processor under test.

[0056] Step S202: In the preset association relationship, find the load type corresponding to the model of the processor under test, and the minimum load dimension D corresponding to the load type.

[0057] Step S203: Send the load corresponding to the load dimension D+pE of the load type to the processor under test. While waiting for the processor under test to finish processing the load, obtain the actual power of the processor under test when processing the load once at a preset time interval.

[0058] Step S204: After the processor under test finishes processing the load, determine whether the actual power is greater than or equal to the rated power; if the actual power is less than the rated power, proceed to step S205; if the actual power is greater than or equal to the rated power, proceed to step S206.

[0059] Step S205: Calculate the sum of p and 1 as the new p, and then execute step S203.

[0060] Step S206: Record the current load dimension as the target dimension that enables the processor under test to reach its rated power; the load corresponding to the target dimension is the target load.

[0061] In the example above, D is the minimum load dimension, E is the preset dimension, and p is the preset parameter. If the initial value of p is 0, it means that after each round of load processing by the processor under test, the preset dimension is increased based on the current load dimension. Starting from dimension D, a load of the corresponding load type and dimension D is sent to the processor under test. After each time interval T, the actual power Pa of the processor under test is obtained and compared with the rated power Pe. If Pa does not reach Pe, the load dimension is increased by E, and a load of the corresponding load type and dimension D+pE is sent to the processor under test again. The actual power Pa is monitored again, and the above process is repeated until Pa reaches Pe. In this way, a minimum load dimension that allows the processor under test to work at its rated power can be obtained, and thus a minimum target load that allows the processor under test to work at its rated power can be obtained.

[0062] Step S102: Send the target load to the processor under test at first preset intervals until the test duration reaches the second preset duration.

[0063] The test duration is the time between the moment the target load is first distributed and the current moment.

[0064] In some embodiments, the target load can be sent to the processor under test at first preset intervals until the test duration reaches a second preset duration using the following test method:

[0065] Method 1: Repeat the first test strategy until the test duration reaches the second preset duration. The first test strategy includes: sending a first preset number of target loads to the processor under test, waiting for the processor under test to process the first preset number of target loads, and then waiting for a third preset duration.

[0066] Correspondingly, the first preset duration is equal to the sum of the third preset duration and the duration for the tested processor to process the first preset number of target loads.

[0067] The first preset number can be set by the engineer according to the testing requirements.

[0068] The third preset duration is equal to the time it takes for the tested processor to process the first preset number of target loads.

[0069] Method 2: Repeat the second test strategy until the test duration reaches the second preset duration. The second test strategy includes: obtaining a first random number n, sending n target loads to the processor under test; waiting for the processor under test to process the n target loads, and then waiting for the fourth preset duration.

[0070] Correspondingly, the first preset duration is equal to the sum of the fourth preset duration and the duration for the tested processor to process n target loads.

[0071] Wherein, the first random number n is a random positive integer.

[0072] The fourth preset duration is equal to the time it takes for the tested processor to process n target loads.

[0073] Method 3: Repeat the third test strategy until the test duration reaches the second preset duration. The third test strategy includes: obtaining a second random number m and a random duration, sending m target loads to the processor under test; waiting for the processor under test to process the m target loads, and then waiting for the random duration.

[0074] Correspondingly, the first preset duration is equal to the sum of the random duration and the duration for the tested processor to process m target loads.

[0075] Wherein, the second random number m is a random positive integer.

[0076] In one embodiment of the above examples, the random duration can be a randomly generated duration.

[0077] In another embodiment of the above embodiments, the random duration can also be obtained by: obtaining a third random number k; determining the random duration based on k and the time taken for the tested processor to process m target loads.

[0078] The third random number k can be a random positive integer.

[0079] In the above implementation, the random duration is determined based on k and the time it takes for the processor under test to process m target loads. This can be achieved by calculating the product of k and the time it takes for the processor under test to process m target loads as the random duration.

[0080] In the above implementation, the random duration is determined based on k and the time taken for the processor under test to process m target loads. This can be achieved by calculating the quotient of k and m to obtain a random parameter. The product of this random parameter and the time taken for the processor under test to process m target loads is then used as the random duration. By combining two random numbers to calculate the random duration, more variations in the random duration are possible, thus facilitating a more comprehensive implementation of scenarios where tasks are sent to the processor on the board at irregular intervals.

[0081] In the above embodiments, the first preset duration can also be a duration preset by the engineer. The engineer pre-assesses the time required for the processor under test to execute the target load and sets the first preset duration to be greater than the time required for the processor under test to execute the target load.

[0082] In the above embodiments, each time a target load is issued, the time required for the tested processor to execute the target load is recorded. A set coefficient is multiplied by this time to obtain the waiting time. The sum of the time required for the tested processor to execute the target load and the waiting time is calculated as the first preset time. Since the waiting time is set based on the time required for the tested processor to execute the target load, it is easier to understand the duty cycle of the tested processor, thus facilitating the evaluation of whether the board's power is normal. For example, in the first method above, the first preset time is equal to the sum of the fourth preset time and the time it takes for the tested processor to process n target loads. The fourth preset time is equal to the time it takes for the tested processor to process n target loads. In this case, the fourth preset time is equivalent to the waiting time, and the set coefficient is equivalent to 1. In this case, the tested processor runs the target load for half the time, and the overall power of the board should be approximately half of the board's rated power.

[0083] Step S103: Obtain the operating status of the processor under test, and determine whether the board on which the processor under test is located is operating normally under load based on the operating status.

[0084] The operational status includes the execution results of the processor under test in handling the target load and / or the power consumption of the board on which the processor under test is located.

[0085] In some embodiments, it may be possible to determine whether the execution result of the last tested processor completing the target load within the second preset time period is correct. In this case, the running status only includes the execution result of the last tested processor completing the target load. Alternatively, it may be possible to randomly determine whether the execution result of the tested processor completing the target load within the second preset time period is correct. In this case, the running status includes the execution results of the tested processor completing the target load multiple times. In this case, each execution result must be correct for the execution result representation to be considered correct.

[0086] In some embodiments, the power changes of the board can be monitored through preset system management software or interfaces. Specifically, the power changes of the board can be monitored through real-time power parameters of the board in the system management software or interface provided by the board manufacturer. The system management software provided by the board manufacturer may be a System Management Interface (SMI).

[0087] In some embodiments, the operating status includes the execution result of the processor under test handling the target load and the board power of the board on which the processor under test is located; for the test methods of mode one and mode two, determining whether the board on which the processor under test is located is operating normally based on the operating status may include: if the execution result is correctly represented and the board power is normal, determining that the board on which the processor under test is located is operating normally; otherwise, determining that the board on which the processor under test is located is operating abnormally.

[0088] In the above embodiments, the correctness of the execution result can be determined by the following methods: obtaining the execution result; comparing the execution result with the preset result; if the execution result is consistent with the preset result, the execution result is determined to be correct; otherwise, the execution result is determined to be incorrect.

[0089] The preset result can be obtained by the main control processor calculating the target load sent to the processor under test in advance, and then storing the preset result in the preset storage space as the preset result.

[0090] In the above embodiments, the correctness of the execution result can also be determined by the following methods: obtaining the execution result; obtaining the target load from which the execution result is obtained, and performing calculations on the target load to obtain the running result; comparing the execution result with the running result, if the execution result is consistent with the running result, the execution result is determined to be correct; otherwise, the execution result is determined to be incorrect.

[0091] In the above embodiments, the power of the board can be determined to be normal in the following way: if the difference between the power of the board and the preset power is within the preset range, the power of the board is determined to be normal; otherwise, the power of the board is determined to be abnormal.

[0092] By specifically configuring methods one and two to run the target load for half the time and not process any tasks for the remaining half, the overall power consumption of the board should be approximately half of its rated power if the processor under test is operating normally. Therefore, setting the preset power consumption to half of the rated power indicates that the board's power consumption is normal.

[0093] The preset range can be determined by engineers based on the allowable error range of the design. In this way, considering that the power consumption of the processor may fluctuate slightly when handling the same target load, the board power can be considered normal if it is close to the preset power.

[0094] Alternatively, the board power can be the average power of the board over the test duration.

[0095] In some embodiments, the operating status includes the board power of the board containing the processor under test. For the test methods of Method 1 and Method 2, determining whether the board containing the processor under test is operating under normal load based on the operating status includes: if the difference between the board power and the preset power is within a preset range, determining that the board containing the processor under test is operating under normal load; otherwise, determining that the board containing the processor under test is operating under abnormal load; the preset power is equal to half of the rated power.

[0096] In some embodiments, the operational status includes the execution results of the processor under test handling the target load. For the test methods of Mode 1, Mode 2, and Mode 3, determining whether the board on which the processor under test is located is operating under normal load based on the operational status includes: if the execution result characterization is correct, determining that the board on which the processor under test is located is operating under normal load; otherwise, determining that the board on which the processor under test is located is operating under abnormal load.

[0097] The steps for determining whether the execution result is correct are described above and will not be repeated here.

[0098] In some embodiments, after determining whether the board on which the processor under test is located is operating normally under load based on the operating conditions, the method may further include: displaying the test results of whether the board on which the processor under test is located is operating normally under load to the user.

[0099] For example, the test results regarding whether the board containing the processor under test is operating normally under load can be sent to a preset display screen for display, or the test results regarding whether the board containing the processor under test is operating normally under load can be sent to a preset email address. The preset display screen can be the display screen of an electronic device bound to corresponding user information.

[0100] In some embodiments, after determining whether the board containing the processor under test is operating under normal load based on the operating conditions, if it is determined that the board containing the processor under test is operating under normal load, then the power supply design of the board is determined to be reasonable; if it is determined that the board containing the processor under test is operating under abnormal load, then the power supply design of the board is determined to be unreasonable.

[0101] Correspondingly, the test results of whether the power supply design of the board is reasonable can be displayed to the user.

[0102] For example, in combination Figure 3 As shown in the figure, this application embodiment provides a method for testing a circuit board, including:

[0103] Step S301: Record the start time of the test.

[0104] Step S302: Send a first preset number of target loads to the processor under test and record the first working time; wait for the processor under test to finish processing the first preset number of target loads and record the second working time.

[0105] Step S303: Calculate the difference between the second working time and the first working time to obtain the third preset duration, and wait for the third preset duration.

[0106] Step S304: After waiting for completion, obtain the third working time and calculate the difference between the third working time and the start time to obtain the test duration.

[0107] Step S305: Determine whether the test duration is greater than or equal to the second preset duration; if the test duration is less than the second preset duration, proceed to step S302. If the test duration is greater than or equal to the second preset duration, proceed to step S306.

[0108] Step S306: Obtain the average power of the board from the start time to the third working time.

[0109] Step S307: Determine whether the execution result of the processor under test in processing the target load is correct. If correct, proceed to step S308; if incorrect, proceed to step S310.

[0110] Step S308: Determine whether the difference between the average power of the board and the preset power is within the preset range; if it is within the preset range, proceed to step S309; ​​if it is not within the preset range, proceed to step S310.

[0111] Step S309: The output test result is normal.

[0112] Step S310: The output test result is abnormal.

[0113] In this way, by sending a target load to the processor on the board every first preset time interval, it is possible to simulate the scenario in actual use where the processor on the board continuously receives and processes tasks, so as to determine whether the power supply design of the board is reasonable under the scenario where the processor on the board continuously receives and processes tasks.

[0114] For example, in combination Figure 4 As shown in the figure, this application embodiment provides a method for testing a circuit board, including:

[0115] Step S401: Record the start time of the test.

[0116] Step S402: Obtain the first random number n, send n target loads to the processor under test, and record the fourth working time; wait for the processor under test to finish processing the n target loads, and record the fifth working time.

[0117] Step S403: Calculate the difference between the fourth working time and the fifth working time to obtain the fourth preset duration, and wait for the fourth preset duration.

[0118] Step S404: After waiting for completion, obtain the sixth working moment and calculate the difference between the sixth working moment and the start moment to obtain the test duration.

[0119] Step S405: Determine whether the test duration is greater than or equal to the second preset duration; if the test duration is less than the second preset duration, proceed to step S402. If the test duration is greater than or equal to the second preset duration, proceed to step S406.

[0120] Step S406: Obtain the average power of the board from the start time to the sixth working time.

[0121] Step S407: Determine whether the execution result of the processor under test in processing the target load is correct. If correct, proceed to step S408; if incorrect, proceed to step S410.

[0122] Step S408: Determine whether the difference between the average power of the board and the preset power is within the preset range; if it is within the preset range, proceed to step S409; if it is not within the preset range, proceed to step S410.

[0123] Step S409, the output test result is normal.

[0124] Step S410: The output test result is abnormal.

[0125] In this way, by changing the number of target loads sent in each round within the second preset time period, it is possible to simulate the scenario in actual use where the processor on the board needs to handle different numbers of tasks at different times, so as to determine whether the power supply design of the board is reasonable in the scenario where the amount of processing received by the processor on the board varies greatly.

[0126] For example, in combination Figure 5 As shown in the figure, this application embodiment provides a method for testing a circuit board, including:

[0127] Step S501: Record the start time of the test.

[0128] Step S502: Obtain the second random number m and the third random number k, send m target loads to the processor under test, and record the seventh working time; wait for the processor under test to finish processing the m target loads, and record the eighth working time.

[0129] Step S503: Calculate the product between the candidate duration and the random parameter to obtain the random duration; wherein, the candidate duration is the difference between the eighth working time and the seventh working time; and the random parameter is the quotient between the third random number and the second random number.

[0130] Step S504: After waiting for completion, obtain the ninth working time and calculate the difference between the ninth working time and the start time to obtain the test duration.

[0131] Step S505: Determine whether the test duration is greater than or equal to the second preset duration; if the test duration is less than the second preset duration, proceed to step S502. If the test duration is greater than or equal to the second preset duration, proceed to step S506.

[0132] Step S506: Determine whether the execution result of the processor under test in processing the target load is correct. If correct, proceed to step S507; if incorrect, proceed to step S508.

[0133] Step S507: The output test result is normal.

[0134] Step S508: The output test result is abnormal.

[0135] In this way, by changing the number of target loads issued in each round within the second preset time period, and changing the waiting time after each target load is processed, it is possible to simulate the scenario of issuing tasks to the processor on the board at irregular intervals and in varying quantities, so as to determine whether the power supply design of the board is reasonable when the processor on the board receives tasks at irregular intervals and in varying quantities.

[0136] In some embodiments, the board can be tested sequentially using methods one, two, and three. If all three tests are normal, the board is considered to be operating under normal load; otherwise, it is considered to be operating under abnormal load. Furthermore, the method one test can be performed multiple times with different preset numbers of samples. For example, the first preset number can be set to 1 initially, and then 5 samples can be used for testing after the first preset number is completed.

[0137] In other examples, assume the board has two processors, such as a GPU and an NPU. The main controller acquires a load 'a' that allows the GPU to reach its rated power during processing, and a load 'b' that allows the NPU to reach its rated power during processing. Load 'a' is sent to the GPU at intervals of a first preset time interval within a second preset time period. Simultaneously, load 'b' is sent to the NPU at intervals of the first preset time interval within the second preset time period. The execution results of the GPU processing load 'a' and the NPU processing load 'b' are then obtained. If both the GPU and NPU processes load 'a' correctly, the board can correctly run the load. If the GPU and NPU are tested using either method one or method two, the average power of the board within the second time period can also be obtained. Whether the board is running the load correctly can be determined by whether the average power is approximately half of the board's rated power.

[0138] Example 2

[0139] The same inventive concept, combined Figure 6 As shown in the figure, this application provides a testing system, including: a main control processor 1 and a board 2. The main control processor 1 is connected to the board 2; the main control processor 1 is used to acquire a target load; send the target load to the processor under test 3 at first preset intervals until the test duration reaches a second preset duration; wherein, the target load is a load that enables the processor under test 3 to reach its rated power during processing; the test duration is the time between the first time the target load is sent and the current time; acquire the operating status of the processor under test 3, and determine whether the board on which the processor under test 3 is located is operating the load normally based on the operating status; the operating status includes the execution result of the processor under test 3 processing the target load and / or the board power of the board 2 on which the processor under test 3 is located; the processor under test, mounted on the board 2, is used to receive the target load sent by the main control processor 1, process the target load, obtain the execution result of processing the target load, and send the execution result back to the main control processor 1.

[0140] The main control processor can be a CPU (Central Processing Unit).

[0141] In some embodiments, the main control processor is used to obtain the target load by: obtaining the model of the processor under test; searching for the load type corresponding to the model and the minimum load dimension corresponding to the load type in a preset association relationship; the association relationship records the correspondence between the model, load type, and minimum load dimension; wherein, the load dimension is used to describe the size of the load; issuing alternative loads to the processor under test; the alternative loads are: loads that belong to the load type and have the minimum load dimension of the load type; obtaining the actual power of the processor under test when processing the alternative loads; if the actual power is less than the rated power, increasing the load dimension to obtain alternative load dimensions, and issuing new alternative loads that belong to the load type and have alternative load dimensions to the processor under test; repeating the above process until the actual power is greater than or equal to the rated power; the alternative load when the actual power is greater than or equal to the rated power is the target load.

[0142] In some embodiments, the main control processor is used to increase the load dimension and obtain alternative load dimensions by: obtaining the current load dimension; and calculating the sum of the current load dimension and the preset dimension as alternative load dimensions.

[0143] In some embodiments, the main control processor is configured to send target loads to the processor under test at first preset time intervals in the following manner until the test duration reaches a second preset time: repeatedly executing a first test strategy until the test duration reaches the second preset time; the first test strategy includes: sending a first preset number of target loads to the processor under test, waiting for the processor under test to process the first preset number of target loads, and then waiting for a third preset time; the third preset time is equal to the time it takes for the processor under test to process the first preset number of target loads; correspondingly, the first preset time is equal to the sum of the third preset time and the time it takes for the processor under test to process the first preset number of target loads.

[0144] In some embodiments, the main control processor is configured to send target loads to the processor under test at first preset intervals in the following manner until the test duration reaches a second preset duration: repeatedly executing a second test strategy until the test duration reaches the second preset duration; the second test strategy includes: obtaining a first random number n, sending n target loads to the processor under test; waiting for the processor under test to process the n target loads, and then waiting for a fourth preset duration; the fourth preset duration is equal to the time it takes for the processor under test to process the n target loads; correspondingly, the first preset duration is equal to the sum of the fourth preset duration and the time it takes for the processor under test to process the n target loads.

[0145] In some embodiments, the main control processor is configured to send target loads to the processor under test at first preset intervals in the following manner until the test duration reaches a second preset duration: repeatedly execute a third test strategy until the test duration reaches the second preset duration; the third test strategy includes: obtaining a second random number m and a random duration, sending m target loads to the processor under test; waiting for the processor under test to process the m target loads, and then waiting for a random duration; correspondingly, the first preset duration is equal to the sum of the random duration and the duration for the processor under test to process the m target loads.

[0146] In some embodiments, the main control processor is used to obtain the random duration by: obtaining a third random number k; and determining the random duration based on k and the time taken for the processor under test to process m target loads.

[0147] In some embodiments, the operational status includes the execution result of the processor under test handling the target load and the board power of the board on which the processor under test is located. The main control processor is used to determine whether the board on which the processor under test is located is operating under normal load based on the operational status in the following ways: if the execution result is correctly represented and the board power is normal, it is determined that the board on which the processor under test is located is operating under normal load; otherwise, it is determined that the board on which the processor under test is located is operating under abnormal load.

[0148] In some embodiments, the operating status includes the board power of the board containing the processor under test. The main control processor is used to determine whether the board containing the processor under test is operating under normal load based on the operating status in the following ways: if the difference between the board power and the preset power is within a preset range, the board containing the processor under test is determined to be operating under normal load; otherwise, the board containing the processor under test is determined to be operating under abnormal load; the preset power is equal to half of the rated power.

[0149] In some embodiments, the operational status includes the execution results of the processor under test processing the target load. The main control processor is used to determine whether the board on which the processor under test is located is operating under normal load based on the operational status in the following ways: if the execution result characterizes correctly, it is determined that the board on which the processor under test is located is operating under normal load; otherwise, it is determined that the board on which the processor under test is located is operating under abnormal load.

[0150] This application provides an electronic device, including a main control processor, a circuit board, and a memory. The memory stores computer-executable instructions that can be executed by the main control processor. The circuit board is equipped with a processor, and the main control processor executes the computer-executable instructions to implement the aforementioned circuit board testing method.

[0151] This application provides a storage medium storing computer-executable instructions configured to execute the test method of the aforementioned board.

[0152] This application provides a computer program product, which includes a computer program that, when executed by a main control processor, implements the aforementioned board testing method.

[0153] The technical solutions of this application embodiment can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in this application embodiment. The aforementioned storage medium can be a non-transitory storage medium, including various media capable of storing program code such as USB flash drives, portable hard drives, read-only memory, random access memory, magnetic disks, or optical disks, or it can be a transient storage medium.

[0154] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0155] In the embodiments provided in this application, it should be understood that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of the embodiments of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data used can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. Unless otherwise stated, the term "a plurality of" means two or more. The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B. The term "corresponding" can refer to an association or binding relationship; A corresponding to B means that there is an association or binding relationship between A and B.

[0156] The above descriptions are merely embodiments of this application and are not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application. Furthermore, the above embodiments can be combined with each other to form new embodiments without conflict.

Claims

1. A testing method for a circuit board, characterized in that, The circuit board is equipped with the processor under test, and the method includes: Obtain the target load; wherein the target load causes the actual power consumption of the processor under test when processing the load to be greater than or equal to the rated power. The target load is sent to the processor under test at a first preset time interval until the test duration reaches a second preset time; the test duration is the time between the first time the target load is sent and the current time. The operating status of the processor under test is obtained, and the normal operating load of the board on which the processor under test is located is determined based on the operating status; the operating status includes the execution result obtained by the processor under test in processing the target load and / or the board power of the board on which the processor under test is located.

2. The method according to claim 1, characterized in that, Obtain the target load, including: Obtain the model number of the processor under test; The system searches for the load type corresponding to the model number and the minimum load dimension corresponding to the load type in a preset association relationship. The association relationship records the correspondence between the model number, load type, and minimum load dimension. The load dimension is used to describe the size of the load. A candidate load is sent to the processor under test; the candidate load is a load that belongs to the load type and has the smallest load dimension corresponding to the load type. Obtain the actual power of the processor under test when processing the candidate load; if the actual power is less than the rated power, increase the load dimension to obtain a candidate load dimension, and issue a new candidate load belonging to the load type and having the candidate load dimension to the processor under test; repeat the above process until the actual power is greater than or equal to the rated power; the candidate load when the actual power is greater than or equal to the rated power is the target load.

3. The method according to claim 2, characterized in that, Increasing the load dimension to obtain alternative load dimensions includes: Obtain the current load dimension; The sum of the current load dimension and the preset dimension is calculated as the alternative load dimension.

4. The method according to claim 1, characterized in that, The target load is sent to the processor under test at first preset intervals until the test duration reaches a second preset duration, including: Repeat the first test strategy until the test duration reaches the second preset duration; The first test strategy includes: sending a first preset number of target loads to the processor under test, waiting for the processor under test to process the first preset number of target loads, and then waiting for a third preset time; the third preset time is equal to the time it takes for the processor under test to process the first preset number of target loads. Accordingly, the first preset duration is equal to the sum of the third preset duration and the duration for the tested processor to process the first preset number of target loads.

5. The method according to claim 1, characterized in that, The target load is sent to the processor under test at first preset intervals until the test duration reaches a second preset duration, including: Repeat the second testing strategy until the test duration reaches the second preset duration; The second testing strategy includes: obtaining a first random number n, and sending n target loads to the processor under test; waiting for the processor under test to process the n target loads, and then waiting for a fourth preset time; the fourth preset time is equal to the time it takes for the processor under test to process the n target loads. Accordingly, the first preset duration is equal to the sum of the fourth preset duration and the duration for the tested processor to process n target loads.

6. The method according to claim 1, characterized in that, The target load is sent to the processor under test at first preset intervals until the test duration reaches a second preset duration, including: Repeat the third testing strategy until the test duration reaches the second preset duration; The third testing strategy includes: obtaining a second random number m and a random duration, sending m target loads to the processor under test; waiting for the processor under test to finish processing the m target loads, and then waiting for the random duration. Accordingly, the first preset duration is equal to the sum of the random duration and the duration for the tested processor to process m target loads.

7. The method according to claim 6, characterized in that, The random duration is obtained in the following way: Get the third random number k; The random duration is determined based on k and the time taken for the tested processor to process m target loads.

8. The method according to any one of claims 1 to 5, characterized in that, The operational status includes the execution results obtained by the processor under test processing the target load and the power of the board on which the processor under test is located; Determine whether the board containing the tested processor is operating normally under load based on the operating conditions, including: If the execution result is correct and the board power is normal, determine the normal operating load of the board where the tested processor is located; Otherwise, it is determined that the board on which the tested processor is located is operating under abnormal load.

9. The method according to any one of claims 1 to 5, characterized in that, The operating status includes the power of the board on which the tested processor is located; Determine whether the board containing the tested processor is operating normally under load based on the operating conditions, including: If the difference between the power of the board and the preset power is within a preset range, the normal operating load of the board where the processor under test is located is determined. Otherwise, it is determined that the board on which the tested processor is located is operating under abnormal load; the preset power is equal to half of the rated power.

10. The method according to claim 6, characterized in that, The operational status includes the execution results obtained by the tested processor processing the target load; Determine whether the board containing the tested processor is operating normally under load based on the operating conditions, including: If the execution result is correct, determine the normal operating load of the board on which the tested processor is located; Otherwise, it is determined that the board on which the tested processor is located is operating under abnormal load.

11. A testing system, characterized in that, include: The main control processor connects to the board. The main control processor is used to acquire the target load; it sends the target load to the processor under test at a first preset time interval until the test duration reaches a second preset time interval; wherein, the target load makes the actual power of the processor under test when processing the load greater than or equal to the rated power; the test duration is the time between the first time the target load is sent and the current time. The operating status of the processor under test is obtained, and the normal operating load of the board on which the processor under test is located is determined based on the operating status; the operating status includes the execution result obtained by the processor under test in processing the target load and / or the board power of the board on which the processor under test is located; The processor under test (DUT) on the board is used to receive the target load sent by the main control processor, process the target load, obtain the execution result of processing the target load, and send the execution result to the main control processor.

12. An electronic device, characterized in that, The device includes a main control processor, a board, and a memory. The memory stores computer-executable instructions that can be executed by the main control processor. The main control processor is mounted on the board. The main control processor executes the computer-executable instructions to implement the testing method of the board according to any one of claims 1 to 10.

13. A storage medium, characterized in that, The storage medium stores computer-executable instructions, which, when called and executed by the main control processor, cause the main control processor to implement the test method for the board according to any one of claims 1 to 10.

14. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by the main control processor, implements the test method for the board according to any one of claims 1 to 10.

Images