Single-chip microcomputer performance test method, board card, equipment, storage medium and program product

Abstract

The invention provides a single-chip microcomputer performance test method, a board card, equipment, a storage medium and a program product. The FPGA board card comprises a diagnostic analysis module and a single-chip microcomputer module used for simulating functions of a single-chip microcomputer model in a design stage. When the diagnosis analysis module determines that the preset message from the upper computer is a first type of message, the first type of message is analyzed to obtain test case information; according to the test case information, the single-chip microcomputer module is controlled to conduct a simulation test on a to-be-tested function of the single-chip microcomputer model, a test result of the to-be-tested function is obtained, and program data for running the to-be-tested function is burnt in the single-chip microcomputer module; according to the test result of the to-be-tested function, the UDP message of the test result is generated, and the UDP message of the test result is sent to the upper computer, so that the upper computer analyzes to obtain the test result representing whether the to-be-tested function passes the test and displays the test result, the MCU performance verification efficiency is improved, meanwhile, the dependence on hardware test equipment is reduced, and the test efficiency of the to-be-tested function is improved. And the test cost is reduced.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit verification technology, and in particular to a single-chip performance testing method, board, device, storage medium and program product. Background Art

[0002] During the microcontroller unit (MCU) design phase, functional and performance verification of the designed MCU model is one of the key links. Through MCU model verification, the performance of the MCU design model can be evaluated to ensure that its functional design meets the requirements.

[0003] Traditional MCU performance testing methods usually rely on physical interfaces to burn MCU firmware and use external hardware circuits and instruments (such as oscilloscopes) to capture and analyze signals. The operation is complex and time-consuming, resulting in low verification efficiency and high cost. Summary of the invention

[0004] The present invention provides a single-chip microcomputer performance testing method, board, device, storage medium and program product to solve the problem of low verification efficiency and high cost caused by single-chip microcomputer performance testing mode in related technologies.

[0005] In a first aspect, an embodiment of the present application provides a single-chip microcomputer performance testing method, which is applied to a field programmable gate array board, wherein the field programmable gate array board includes a diagnostic analysis module and a single-chip microcomputer module, wherein the single-chip microcomputer module is used to simulate the function of a single-chip microcomputer model in the design stage; The execution subject of the method is a diagnosis and analysis module, and the method includes: Receive preset messages from the host computer; When it is determined that the preset message is a first-class message, the first-class message is parsed to obtain the test case information in the first-class message; According to the test case information, the single-chip microcomputer module is controlled to simulate the function to be tested of the single-chip microcomputer model and obtain the test result of the function to be tested, and the program data for running the function to be tested is burned into the single-chip microcomputer module; Generate test result data of the function to be tested according to the test result of the function to be tested; The test result data of the function to be tested is sent to the host computer, so that the host computer analyzes and obtains the test result indicating whether the function to be tested has passed the test, and displays the test result.

[0006] In one embodiment, the functional structure simulated by the single-chip microcomputer module includes a single-chip microcomputer core, a memory and a plurality of external devices, and the memory of the single-chip microcomputer is burned with the operation data required to run the function to be tested; Among them, according to the test case information, the single-chip microcomputer module is controlled to simulate the function to be tested of the single-chip microcomputer model, and the test result of the function to be tested is obtained, including: Determine test target data of the function to be tested according to the test case information, and determine a target device associated with the function to be tested from a plurality of external devices; Trigger the microcontroller core to run the function to be tested to start the test of the function to be tested; The test simulation signal collected by the target device is acquired in real time, and the test result of the function to be tested is determined according to the test target data and the test simulation signal acquired in real time.

[0007] In one embodiment, the test case information includes a test time limit, real-time acquisition of a test simulation signal collected by a target device, and determination of a test result of a function to be tested based on the test target data and the real-time acquired test simulation signal, including: After the single-chip microcomputer core is triggered to run the function to be tested, the timeout timer in the diagnosis and analysis module is started, and the timing duration of the timeout timer is the test limit duration; During the timing of the timeout timer, the test simulation signal collected by the target device is obtained in real time; According to the test target data and the test simulation signal obtained in real time, the operation of the function to be tested is monitored until the timeout timer stops timing or the test completion is determined according to the test target data and the test simulation signal, and the test result of the function to be tested is output.

[0008] In one embodiment, the test case information includes a test case identifier, and the test target data of the function to be tested is determined according to the test case information, including: Determine the test case corresponding to the test case identifier in the test case data pre-stored in the diagnosis and analysis module, and obtain the target test case corresponding to the function to be tested; In the target test case, test target data of the function to be tested is extracted, and a target device associated with the function to be tested is extracted.

[0009] In one embodiment, parsing the first type of message to obtain the test case information in the first type of message includes: Parse the first type of message to obtain the test case identifier and the test time limit, where the test time limit is the maximum time limit for testing the function to be tested; The test case identifier and the test time limit are used as the test case information.

[0010] In one embodiment, after receiving the preset message from the host computer, the method further includes: When it is determined that the preset message is a second-class message, the second-class message is parsed to obtain program data of the function to be tested in the single-chip microcomputer model in the second-class message; The program data of the function to be tested is burned into the memory in the single-chip microcomputer module so that the single-chip microcomputer module can run the function to be tested.

[0011] In one embodiment, the second type of message includes a test case and a test case identifier of a function to be tested; after parsing the second type of message to obtain program data of the function to be tested in the single-chip microcomputer model in the second type of message, the method further includes: The test cases and the test case identifiers are stored in the diagnosis and analysis module in a one-to-one correspondence.

[0012] In a second aspect, an embodiment of the present application provides a field programmable gate array board for single-chip microcomputer performance testing, comprising: MCU module, used to simulate the functions of the MCU model in the design stage; Diagnostic analysis module for: Receive preset messages from the host computer; When it is determined that the preset message is a first-class message, the first-class message is parsed to obtain the test case information in the first-class message; According to the test case information, the single-chip microcomputer module is controlled to simulate the function to be tested of the single-chip microcomputer model and obtain the test result of the function to be tested, and the program data for running the function to be tested is burned into the single-chip microcomputer module; Generate test result data of the function to be tested according to the test result of the function to be tested; The test result data of the function to be tested is sent to the host computer, so that the host computer analyzes and obtains the test result indicating whether the function to be tested has passed the test, and displays the test result.

[0013] In a third aspect, an embodiment of the present application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above-mentioned single-chip microcomputer performance testing method when executing the computer program.

[0014] In a fourth aspect, an embodiment of the present application provides a readable storage medium, which stores a computer program, and when the computer program is executed by a processor, the steps of the above-mentioned single-chip microcomputer performance testing method are implemented.

[0015] In a fifth aspect, an embodiment of the present application provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the above-mentioned single-chip microcomputer performance testing method is executed.

[0016] In one solution provided by the above-mentioned single-chip microcomputer performance test method, board, device, storage medium and program product, the FPGA board includes a diagnostic analysis module and a single-chip microcomputer module. The single-chip microcomputer module is used to simulate the function of the single-chip microcomputer model in the design stage, and the single-chip microcomputer module is burned with program data for running the function to be tested. Among them, the diagnostic analysis module receives a preset message from the host computer, and when it is determined that the preset message is a first-class message, the first-class message is parsed to obtain the test case information in the first-class message; then, the diagnostic analysis module simulates the function to be tested of the single-chip microcomputer model according to the test case information, and obtains the test result of the function to be tested; finally, the diagnostic analysis module generates the test result data of the function to be tested according to the test result of the function to be tested, and sends the test result data of the function to be tested to the host computer, so that the host computer parses and obtains the test result indicating whether the function to be tested has passed the test, and displays the test result. Traditional MCU testing usually requires physical chips and debugging tools (such as oscilloscopes, logic analyzers, etc.). However, this solution can directly simulate the test functions of the MCU model on the FPGA through the microcontroller module in the FPGA board, without the need for actual MCU hardware. The diagnostic analysis module can automatically parse the host computer test case information to execute the test and automatically capture the test result data, realizing the MCU performance test closed loop. The test can be completed only by relying on the FPGA board, without the need for external tools to monitor and capture the test result data, making the test process highly automated and ensuring the reusability of the test, improving the efficiency of MCU performance verification, while reducing the dependence on hardware test equipment and reducing testing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0018] Figure 1 It is a structural schematic diagram of a single chip microcomputer performance testing system in one embodiment of the present invention; Figure 2 is another structural schematic diagram of a single chip microcomputer performance testing system in one embodiment of the present invention; Figure 3 It is a schematic diagram of a flow chart of a single chip microcomputer performance testing method in one embodiment of the present invention; Figure 4 is another schematic flow chart of a single chip microcomputer performance testing method according to an embodiment of the present invention; Figure 5 yes Figure 3 A schematic diagram of an implementation process of step S20; Figure 6 yes Figure 3 A schematic diagram of an implementation process of step S30; Figure 7 yes Figure 1 or Figure 2 A structural schematic diagram of a field programmable gate array board; Figure 8 It is a schematic diagram of the structure of an electronic device in one embodiment of the present invention. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or their collections. It should also be understood that the term "and / or" used in the present specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0021] In addition, in the description of the present specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0022] References to "one embodiment" or "some embodiments" etc. described in the present specification mean that one or more embodiments of the present invention include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0023] It should be understood that the order of execution of the steps in the following embodiments does not imply a precedence of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0024] In order to illustrate the technical solution of the present invention, specific embodiments are provided below for illustration.

[0025] It should be understood that the traditional single-chip microcomputer performance test method usually relies on physical interface burning MCU firmware, and uses external hardware circuits and instruments (such as oscilloscopes) to capture and analyze signals to obtain performance test result data and performance test results. The operation is complex and time-consuming. In addition, some single-chip microcomputer performance tests can also be carried out through software verification, such as the prototype verification method based on FPGA (Field Programmable Gate Array). It transplants the functional firmware designed by MCU into the FPGA chip, and tests the MCU function and performance in the design stage through software burning verification. However, this type of verification method can only simulate the MCU core, and still needs to connect hardware circuits (such as MCU external devices), as well as oscilloscopes, logic analyzers and other instruments for signal monitoring, capture and analysis to obtain performance test results. It has strong hardware dependence, complex operation, and long time consumption, resulting in low verification efficiency, high cost, and poor reusability.

[0026] In view of the above problems, the embodiment of the present application provides a single-chip microcomputer performance test method, FPGA board, electronic device, storage medium and program product. By setting a diagnostic analysis module and a single-chip microcomputer module in the FPGA board, the single-chip microcomputer module can simulate the function of the single-chip microcomputer model in the design stage. In the application process, the diagnostic analysis module receives a preset message from the host computer. When it is determined that the preset message is a first-class message, the first-class message is parsed to obtain the test case information in the first-class message; then, the diagnostic analysis module controls the single-chip microcomputer module to simulate the function to be tested of the single-chip microcomputer model according to the test case information, and obtains the test result of the function to be tested, and the program data for running the function to be tested is burned in the single-chip microcomputer module; finally, the diagnostic analysis module generates the test result data of the function to be tested according to the test result of the function to be tested, and sends the test result data of the function to be tested to the host computer, so that the host computer parses and obtains the test result representing whether the function to be tested passes the test, and displays the test result. Compared with traditional MCU testing, which usually requires physical chips and debugging tools (such as oscilloscopes and logic analyzers), this solution can directly simulate the functions to be tested of the MCU model on the FPGA through the microcontroller module in the FPGA board, without the need for actual MCU hardware. The diagnostic analysis module can automatically parse the host computer test case information to execute the test and automatically capture the test result data, thus realizing the MCU performance test closed loop. The test can be completed only by relying on the FPGA board, without the need for external tools to monitor and capture the test result data, making the test process highly automated and ensuring the reusability of the test, thus improving the efficiency of MCU performance verification, while also reducing the dependence on hardware test equipment and reducing the test cost.

[0027] The single chip microcomputer performance testing method provided by the embodiment of the present invention can be applied in Figure 1 In the single-chip microcomputer performance test system shown, the single-chip microcomputer performance test system includes an FPGA board (i.e., a field programmable gate array board) and a host computer. The host computer communicates with the FPGA board through a network. The FPGA board includes a diagnostic analysis module and a single-chip microcomputer module; the single-chip microcomputer module is used to simulate the functions of the single-chip microcomputer model in the design stage.

[0028] During the test process, the host computer receives the user's test instructions and sends a first-class message to the FPGA board to instruct the FPGA board to perform performance testing. The diagnostic analysis module in the FPGA board receives the preset message from the host computer. When it is determined that the preset message is a first-class message, it parses the first-class message to obtain the test case information in the first-class message. Then, the diagnostic analysis module controls the single-chip microcomputer module to simulate the function to be tested of the single-chip microcomputer model according to the test case information, and obtains the test result of the function to be tested, wherein the single-chip microcomputer module is burned with program data for running the function to be tested. Finally, the diagnostic analysis module generates the test result data of the function to be tested according to the test result of the function to be tested, and sends the test result data of the function to be tested to the host computer, so that the host computer parses and obtains the test result indicating whether the function to be tested has passed the test, and displays the test result.

[0029] Traditional MCU testing usually requires physical chips and debugging tools (such as oscilloscopes, logic analyzers, etc.). However, this solution can directly simulate the test functions of the MCU model on the FPGA through the microcontroller module in the FPGA board, without the need for actual MCU hardware. The diagnostic analysis module can automatically parse the host computer test case information to execute the test and automatically capture the test result data, realizing the MCU performance test closed loop. The test can be completed only by relying on the FPGA board, without the need for external tools to monitor and capture the test result data, making the test process highly automated and ensuring the reusability of the test, improving the efficiency of MCU performance verification, while reducing the dependence on hardware test equipment and reducing the test cost.

[0030] The host computer may be any terminal device, including but not limited to any personal computer, laptop computer, smart phone, tablet computer, and portable wearable device. In other embodiments, the host computer may also be a server, which may be implemented as an independent server or a server cluster composed of multiple servers.

[0031] In one embodiment, if Figure 2As shown in the figure, the FPGA board includes a field programmable gate array chip (i.e., FPGA chip) and a network port physical layer for communicating with the host computer, i.e., network PHY (Physical Layer). The FPGA chip includes a network protocol stack, a diagnostic analysis module, and a single-chip microcomputer module. The single-chip microcomputer module is used to simulate the core and external devices of the MCU (i.e., MCU soft core peripherals), as well as memory, such as flash memory. The network PHY is used to receive message data sent by the host computer, and convert the message data sent by it into a test simulation signal and send it to the network protocol stack, and the network protocol stack sends the converted message data to the diagnostic analysis module. The diagnostic analysis module performs data burning or performance testing based on the received message data, and sends the burning results and test results to the host computer through the network protocol stack and network PHY.

[0032] Among them, the host computer sends the program data of the function to be tested of the MCU to the FPGA board, the network PHY and network protocol stack of the FPGA board receive the data, and send the program data of the function to be tested to the diagnostic analysis module, the diagnostic analysis module burns the program data (bin file) of the function to be tested to the memory of the single-chip module, so that the MCU core can run the function to be tested, and sends the program data burning result of the function to be tested (i.e., whether the burning is successful) to the host computer, so that the user can know it in time. After the host computer receives the program data burning result of the function to be tested, the user sends a first-class message to the FPGA board through the host computer, and the message includes the test case information of the function to be tested, which is used to instruct the diagnostic analysis module to test the function to be tested. The diagnostic analysis module receives the preset message from the host computer. When it is determined that the preset message is the first-class message, according to the test case information in the first-class message, the single-chip module is controlled to simulate the function to be tested of the single-chip model, and the test result of the function to be tested is obtained. The program data for running the function to be tested is burned in the single-chip module. Finally, according to the test results of the function to be tested, the test result data of the function to be tested is generated, and the test result data of the function to be tested is sent to the host computer, so that the host computer can parse and obtain the test results that characterize whether the function to be tested has passed the test, and display the test results, so as to achieve the purpose of verifying the performance of the single-chip microcomputer model. In this solution, the test can be completed only by relying on the FPGA board, and no external tools are required to monitor and capture the test result data, which makes the test process highly automated and ensures the reusability of the test, improves the efficiency of MCU performance verification, and reduces the dependence on hardware test equipment and reduces the test cost.

[0033] The host computer and the FPGA board communicate based on the User Datagram Protocol, also known as UDP (User Datagram Protocol). The host computer acts as the UDP server, and the FPGA board acts as the UDP client, establishing a communication link through Ethernet. UDP is a connectionless transport layer protocol. UDP does not establish a connection. The sending and receiving of data packets does not require the establishment and maintenance of a connection state, which means that the server does not need to create a new process or thread for each client to handle the connection request.

[0034] In the traditional MCU performance verification method, the host computer usually transmits data through physical interfaces such as JTAG (Joint Test Action Group) interface and Serial Wire Debug (SWD) interface to perform operations such as functional data (bin file) burning and functional testing. However, JTAG / SWD itself does not have high-speed data transmission capability, and cannot effectively obtain and process the large amount of data generated by MCU in complex tests. The relevant test signals can only be viewed through an oscilloscope or logic analyzer. After the FPGA performs operations such as functional data burning and functional testing, the test results cannot be obtained in time, and the test result acquisition efficiency is low. In this solution, UDP line is used for data transmission. All data is transmitted through Ethernet, without the need for additional physical interfaces, and UDP is suitable for high-throughput data transmission, avoiding the problem of inefficient data transmission of JTAG / SWD; through Ethernet, the test process can be performed remotely without the need for physical connection, reducing the hardware dependence of physical connection methods such as JTAG / SWD, and can achieve remote performance testing, with fewer communication lines, enhanced reliability, and faster communication speed.

[0035] In one embodiment, if Figure 3 As shown, a single chip performance test method is provided, which is applied in Figure 1 or Figure 2 The FPGA board in the example is used as an example to illustrate the process, including the following steps: S10: Receive the preset message from the host computer.

[0036] Among them, the FPGA board includes a diagnostic analysis module and a single-chip microcomputer module. The single-chip microcomputer module is burned with program data for running the function to be tested. The single-chip microcomputer module is used to simulate the function of the single-chip microcomputer model in the design stage.

[0037] During the test, the host computer receives the user's test instruction and sends the first type of message to the FPGA board to instruct the FPGA board to perform performance testing. The diagnostic analysis module receives the preset message from the host computer.

[0038] The host computer can act as a UDP server to send a preset message to the FPGA board, and the preset message can be a unicast message.

[0039] S20: When it is determined that the preset message is a first-category message, the first-category message is parsed to obtain test case information in the first-category message.

[0040] After receiving the preset message from the host computer, the diagnosis and analysis module performs message type analysis on the received preset message. When determining that the preset message is a first-class message, the first-class message is parsed to obtain test case information in the first-class message, such as the test case information may include a test case for the function to be tested. The test case is a test file written in advance according to needs and used to instruct the diagnosis and analysis module to execute the test of the function to be tested.

[0041] In other embodiments, the test case information may also include a test time limit for the function to be tested. The test time limit is used to instruct the diagnostic analysis module to complete the test of the function to be tested within the test time limit. If the test of the function to be tested is not completed within the test time limit, a test result of test timeout is output.

[0042] Among them, after receiving the preset message from the host computer, the diagnostic analysis module can read the frame header of the preset message to determine the message type of the preset message according to the frame header of the preset message. The message type includes a first type of message and a second type of message. Among them, the first type of message is used to instruct the diagnostic analysis module to control the single-chip microcomputer module to simulate the function to be tested of the single-chip microcomputer model; the second type of message is used to instruct the diagnostic analysis module to burn the program data (i.e., bin file) of the function to be tested in the preset message to the single-chip microcomputer module, so that the single-chip microcomputer module can run the function to be tested, so as to conduct subsequent testing of the function to be tested.

[0043] Among them, the data of different frame headers in the preset message represent different message types. For example, after receiving the preset message from the host computer, the diagnostic analysis module can read the frame header of the preset message. If the frame header of the preset message is the first preset frame header (such as 0xAA55), the preset message is determined to be a first-class message; if the frame header of the preset message is the second preset frame header (such as 0x3F00), the preset message is determined to be a second-class message. The message type is determined by the message frame header, so that data burning or function testing operations can be performed according to the message type, which is simple and convenient.

[0044] S30: According to the test case information, the single-chip microcomputer module is controlled to perform a simulation test on the function to be tested of the single-chip microcomputer model, and a test result of the function to be tested is obtained.

[0045] After obtaining the test case information in the first type of message, the diagnostic analysis module controls the single-chip microcomputer module to simulate the function to be tested of the single-chip microcomputer model according to the test case information, and obtains the test result of the function to be tested. The single-chip microcomputer module is burned with program data for running the function to be tested.

[0046] S40: Generate test result data of the function to be tested according to the test result of the function to be tested.

[0047] After obtaining the test result of the function to be tested, the diagnosis and analysis module generates a UDP message of the test result according to the test result of the function to be tested to obtain the test result data of the function to be tested, and the test result data of the function to be tested at least includes the test result of the function to be tested.

[0048] In other embodiments, the test result data of the function to be tested may also include signal changes of each analog structure in the single-chip microcomputer module during the test process, test timeout information of the function to be tested (such as whether the test duration has timed out), etc., so as to facilitate subsequent MCU performance analysis.

[0049] The test result of the function to be tested is used to indicate whether the test is failed or successful. That is, the test result of the function to be tested includes three test results: test success, test failure and test timeout.

[0050] For example, the test result data of the function to be tested includes a test case identifier, and the test results of test timeout, test success or test failure. Among them, test success or test failure can be represented by 1 bit, for example, 0 represents success, and 1 represents failure; test timeout information includes one of test timeout or test not timeout, and test timeout information can also be represented by 1 bit, for example, 0 represents test not timeout, and 1 represents test timeout. The test case identifier is used to distinguish the test result of the test case of the function to be tested, so as to facilitate subsequent data aggregation, recording and analysis. The test result of test success or test failure, as well as the test case identifier and test timeout information are used as feedback messages, and then the feedback messages are sequentially encapsulated by UDP, IP, and Ethernet to obtain UDP protocol messages, that is, the test results of the function to be tested are obtained, so that the test results of the function to be tested are finally sent to the host computer.

[0051] In summary, it can be seen that 2 bits of data and ID can represent the test result data of the function to be tested, and because the UDP protocol message is transmitted in bytes, one byte can be used to express this information.

[0052] S50: Sending the test result data of the function to be tested to the host computer, so that the host computer analyzes and obtains the test result indicating whether the function to be tested passes the test, and displays the test result.

[0053] After obtaining the test result data of the function to be tested, the diagnostic analysis module sends the test result data of the function to be tested to the host computer, so that the host computer performs UDP message parsing after receiving the test result data, obtains the test result in the test result data used to characterize whether the function to be tested has passed the test, and displays the test result, so that relevant personnel can quickly know whether the function to be tested has passed the test, and then determine whether the performance of the microcontroller model meets the requirements.

[0054] For example, after the upper computer receives the test result data of the function to be tested, it decapsulates the test result data of the function to be tested in the UDP message, obtains test results such as the test case identification, test timeout information, whether the test case test is successful, and directly displays the test result of the function to be tested, so that relevant personnel can quickly know whether the function to be tested has passed the test.

[0055] In this embodiment, through the single-chip microcomputer module in the FPGA board, the function to be tested of the MCU model can be directly simulated on the FPGA without the need for actual MCU hardware, and the diagnostic analysis module can automatically parse the host computer test case information to execute the test and automatically capture the test result data, thereby realizing a closed loop of MCU performance testing. The test can be completed relying only on the FPGA board, without the need for external tools to monitor and capture the test result data, making the test process highly automated and ensuring the reusability of the test, thereby improving the efficiency of MCU performance verification, while also reducing dependence on hardware testing equipment and reducing testing costs.

[0056] In one embodiment, if Figure 4 As shown, after step S10, that is, after receiving the preset message from the host computer, the following steps are specifically included: S01: When it is determined that the preset message is a second-category message, the second-category message is parsed to obtain program data of a function to be tested in a single-chip microcomputer model in the second-category message.

[0057] After receiving the preset message from the host computer, the diagnosis and analysis module performs message type analysis on the received preset message; when determining that the preset message is a second-class message, the second-class message is parsed to obtain program data of the function to be tested in the single-chip microcomputer model in the second-class message.

[0058] In other embodiments, the second type of message also includes test cases and test case identifiers of the function to be tested, that is, when it is determined that the preset message is a second type of message, the second type of message is parsed to obtain the program data of the function to be tested in the single-chip microcomputer model in the second type of message, as well as the test cases and test case identifiers of the function to be tested.

[0059] S02: Burn the program data of the function to be tested into the memory in the single-chip microcomputer module, so that the single-chip microcomputer module can run the function to be tested.

[0060] The functional structure simulated by the MCU module includes a MCU core, a memory and multiple external devices. The memory includes a non-volatile memory, such as a flash memory (i.e., a flash memory), and a volatile memory, such as a random access memory RAM.

[0061] After obtaining the program data of the function to be tested in the microcontroller model in the second type of message, the diagnostic analysis module burns the program data of the function to be tested into the memory in the microcontroller module so that the microcontroller module can call the program data of the function to be tested in the memory to run the function to be tested.

[0062] Wherein, after the host computer sends the second type of message or while sending the second type of message, the host computer may send the first type of message so that the diagnostic analysis module of the FPGA board responds to the first type of message for testing.

[0063] In one embodiment, after the program data of the function to be tested is burned into the memory in the single-chip microcomputer module, the program data burning result of the function to be tested is obtained, and the data burning result includes data burning success or data burning failure; the diagnostic analysis module can also send the program data burning result of the function to be tested to the host computer. The host computer receives and displays the program data burning result of the function to be tested, so that relevant personnel can obtain the data burning result and perform corresponding measures.

[0064] In one embodiment, after determining that the program data of the function to be tested is successfully burned according to the program data burning result of the function to be tested, the host computer can prompt the user whether to test the function to be tested; after receiving the test instruction of the function to be tested, the host computer sends a first type of message to the FPGA board card to avoid the situation where subsequent tests fail due to data burning failure, thereby increasing the probability of test success. The first type of message includes test case information.

[0065] Among them, the test case information may include the test case and test limit time of the function to be tested, so that the diagnostic analysis module tests the function to be tested on the single-chip microcomputer module according to the test case and test limit time in the first type of message, so as to obtain the test result of the function to be tested, generate the test result data of the function to be tested and send it to the host computer. In other embodiments, the test case information may include the test case identification (i.e., test case ID) and test limit time of the function to be tested, wherein the test case of the function to be tested corresponding to the test case identification is pre-stored in the diagnostic analysis module, so that the diagnostic analysis module reads the test case of the function to be tested in the diagnostic analysis module according to the test case identification in the first type of message, and tests the function to be tested on the single-chip microcomputer module according to the test case and test limit time of the function to be tested.

[0066] In this embodiment, after receiving the preset message from the host computer, the diagnostic analysis module parses the second-class message when determining that the preset message is a second-class message, obtains the program data of the function to be tested in the single-chip model in the second-class message, and burns the program data of the function to be tested into the memory in the single-chip module, so that the single-chip module can run the function to be tested. From the burning of functional data to the functional test process, it can be remotely controlled by the host computer, without relying on external tools for functional firmware burning, as well as monitoring and capturing of test result data, which can realize the closed loop of the entire functional test, making the MCU performance verification highly automated, ensuring the reusability of the test, and improving the efficiency of MCU performance verification. At the same time, it also reduces the dependence on hardware testing equipment and reduces the test cost.

[0067] In one embodiment, the second type of message includes the program data of the function to be tested, and the test case and test case identification of the function to be tested. After step S01, that is, when the preset message is determined to be the second type of message, the second type of message is parsed, and after the program data of the function to be tested in the single-chip model in the second type of message is obtained, the following steps are specifically included: the test case and the test case identification are stored in the diagnosis and analysis module in a one-to-one correspondence. Among them, the storage result of the test case can be sent to the host computer together with the program data burning result of the function to be tested, so that the host computer sends the first type of message including the test case identification after determining that the program data of the function to be tested is successfully burned, so as to avoid the situation that the subsequent test fails due to data burning failure or test case storage failure. Through the second type of message carrying the program data of the function to be tested, the test case and the test case identification of the function to be tested, the diagnosis and analysis module can complete the data burning and the test case pre-embedding according to the second type of message, so that the function to be tested is tested later, and the analysis and reading operation of the test case in the subsequent test process is reduced, and the efficiency of the subsequent test is improved.

[0068] That is, in one embodiment, after step S10, that is, after receiving the preset message from the host computer, the following steps are specifically included: S01: When it is determined that the preset message is a second-class message, the second-class message is parsed to obtain program data of the function to be tested in the single-chip microcomputer model in the second-class message, as well as a test case and a test case identifier of the function to be tested.

[0069] After receiving the preset message from the host computer, the diagnostic analysis module performs message type analysis on the received preset message; when it is determined that the preset message is a second-class message, the second-class message is parsed to obtain the program data of the function to be tested in the single-chip microcomputer model in the second-class message, as well as the test case and test case identifier of the function to be tested.

[0070] Among them, the preset message is a UDP protocol message, that is, the second type of message is a UDP protocol message; the diagnostic analysis module determines the frame header of the UDP message. If the frame header of the UDP message is the second preset frame header (such as 0x3F00), it is determined that the preset message is a second type of message, and the data frame of the second type of message can be parsed to obtain the data in the second type of message.

[0071] Among them, the specific process of parsing the second type of message includes: the diagnostic analysis module reads the destination physical address (i.e., the destination MAC address) in the second type of message, and determines whether the destination MAC address in the second type of message matches the MAC address of the FPGA board; if the two MAC addresses match, the frame header of the second type of message is removed, the network protocol datagram (i.e., IP datagram) in the second type of message is extracted, and the destination IP address (i.e., the destination network protocol address) in the IP datagram is extracted; it is determined whether the destination IP address in the IP datagram matches the IP address of the FPGA board; if the two IP addresses match, the IP header of the IP datagram is removed to obtain a UDP message. The diagnostic analysis module extracts the destination port number in the UDP message and determines whether the destination port number in the UDP message matches the port number it monitors. If the two port numbers match, it means that the second type of message is a message sent to the FPGA board and the message is sent and received correctly. Then, the header of the UDP message is removed to extract the application layer data in the second type of message, which includes the program data of the function to be tested, as well as the test cases and test case identifiers of the function to be tested. According to the pre-agreed data format, the application layer data is split to obtain the program data of the function to be tested in the application layer data, as well as the test cases and test case identifiers of the function to be tested.

[0072] In this embodiment, by parsing the address or port number information of the link layer, network layer and transport layer layer by layer, and decapsulating the data layer by layer, when the MAC address, IP address and port number all match, the real application layer data is extracted to ensure the accuracy of data transmission and reception, avoid data burning and storage errors caused by data transmission and reception errors, and provide an accurate data basis for subsequent functional testing.

[0073] S02: Store the test cases and the test case identifiers in a one-to-one correspondence in the diagnosis and analysis module.

[0074] After parsing the second type of message, the diagnostic analysis module stores the test cases and test case identifiers in the second type of message in a one-to-one correspondence in the diagnostic analysis module, so that the test cases can be directly called according to the test case identifiers in the first type of message, thereby reducing data processing operations during the test process and improving test efficiency.

[0075] S03: Burn the program data of the function to be tested into the memory in the single-chip microcomputer module, so that the single-chip microcomputer module can run the function to be tested.

[0076] At the same time, the diagnostic analysis module burns the program data of the function to be tested into the memory in the single-chip microcomputer module, so that the single-chip microcomputer module can run the function to be tested. Data burning and test case storage are carried out simultaneously, which can reduce the amount of data processing and improve processing efficiency.

[0077] Among them, the functional structure simulated by the single-chip microcomputer module includes a single-chip microcomputer core, a memory and multiple external devices. The memory includes a flash memory and a RAM memory. The program data of the function to be tested is a binary bin file. After obtaining the program data of the function to be tested, the binary bin file is burned page by page to the flash memory in the single-chip microcomputer module, so that the subsequent single-chip microcomputer core can run the function to be tested.

[0078] Among them, after the test cases and test case identifiers are stored in the diagnostic analysis module in a one-to-one correspondence, and the program data of the function to be tested is burned into the memory in the single-chip module, the diagnostic analysis module sends the storage results of the test cases and the program data burning results of the function to be tested to the host computer. The host computer receives the storage results of the test cases and the program data burning results of the function to be tested, and after determining that the program data of the function to be tested is successfully burned according to the storage results of the test cases, prompts the user whether to test the function to be tested; after receiving the test instruction of the function to be tested, the first type of message is sent to the FPGA board to avoid the situation where subsequent tests fail due to data burning failure or test case storage failure. Among them, the first type of message includes the test case identifier and the test limit time, so that the diagnostic analysis module can test the function to be tested on the single-chip microcomputer module according to the test case identifier and the test limit time, which is simple and convenient.

[0079] In this embodiment, when it is determined that the preset message is a second-class message, the second-class message is parsed to obtain the program data of the function to be tested in the single-chip microcomputer model in the second-class message, as well as the test case and test case identifier of the function to be tested; the test case and the test case identifier are stored in the diagnostic analysis module in a one-to-one correspondence; the program data of the function to be tested is burned into the memory in the single-chip microcomputer module so that the single-chip microcomputer module can run the function to be tested; the storage result of the test case and the result of burning the program data of the function to be tested are sent to the host computer so that the host computer sends the first-class message including the test case identifier after determining that the program data of the function to be tested is burned successfully. By carrying the program data of the function to be tested, the test case and the test case identifier of the function to be tested in the second-class message, the diagnostic analysis module can complete data burning and pre-embed the test case according to the second-class message, so as to test the function to be tested later, reduce the analysis and reading operation of the test case in the subsequent test process, and improve the efficiency of the subsequent test.

[0080] In one embodiment, if Figure 5 As shown, in step S20, the first type of message is parsed to obtain the test case information in the first type of message, which specifically includes the following steps: S21: Parse the first type of message to obtain a test case identifier and a test time limit.

[0081] Among them, the preset message is a UDP protocol message, that is, the first type of message is a UDP protocol message; the diagnostic analysis module determines the frame header of the UDP message. If the frame header of the UDP message is the first preset frame header (such as 0xAA55), the preset message is determined to be a first type of message, and the data frame of the first type of message can be parsed to obtain the application layer data in the first type of message. The application layer data in the first type of message includes the test case identifier and the test limit time; the test limit time is the maximum limit time of the test function to be tested, which is used to limit the test time of the function to be tested to avoid test timeout.

[0082] Among them, when it is determined that the preset message is a first-class message, the specific process of parsing the first-class message includes: the diagnostic analysis module reads the destination physical address (i.e., the destination MAC address) in the first-class message, and determines whether the destination MAC address in the first-class message matches the MAC address of the FPGA board; if the two MAC addresses match, the frame header of the first-class message is removed, the network protocol datagram (i.e., IP datagram) in the first-class message is extracted, and the destination IP address (i.e., the destination network protocol address) in the IP datagram is extracted; it is determined whether the destination IP address in the IP datagram matches the IP address of the FPGA board; if the two IP addresses match, the IP header of the IP datagram is removed to obtain a UDP message. The diagnostic analysis module extracts the destination port number in the UDP message and determines whether the destination port number in the UDP message matches the port number it monitors. If the two port numbers match, it means that the first type of message is a message sent to the FPGA board and the message is sent and received correctly. Then, the header of the UDP message is removed to extract the application layer data in the second type of message. The application layer data includes the test case identifier (test case ID) and the test limit time of the function to be tested. According to the pre-agreed data format, the application layer data is split to obtain the test case identifier and the test limit time in the application layer data.

[0083] In other embodiments, the application layer data may include test cases and test time limits of the functions to be tested. That is, if the two port numbers match, it means that the first type of message is a message sent to the FPGA board, and the message is sent and received correctly, then the header of the UDP message is removed, and the application layer data in the second type of message is extracted, and the application layer data includes the test cases and test time limits of the functions to be tested; the application layer data is split according to the pre-agreed data format, and the test cases and test time limits in the application layer data can be obtained.

[0084] In this embodiment, by parsing the address or port number information of the link layer, network layer and transport layer layer by layer, and decapsulating the data layer by layer, when the MAC address, IP address and port number all match, the real application layer data is extracted to ensure the accuracy of data sending and receiving, avoid test case execution errors caused by data sending and receiving errors, and ensure that the test of the function to be tested can proceed normally.

[0085] S22: Use the test case identifier and the test time limit as the test case information.

[0086] After parsing the first type of message to obtain the test case identifier and the test time limit, the diagnosis and analysis module uses the test case identifier and the test time limit as the test case information.

[0087] In this embodiment, when the diagnostic analysis module determines that the preset message is a first-class message, it parses the first-class message to obtain the test case identifier and the test limit time, and the test limit time is the maximum limit time for testing the function to be tested; the test case identifier and the test limit time are used as the test case information. The first-class message sent this time includes the test case ID and the test limit time of the function to be tested. On the one hand, there is no need to carry test cases with too much data. Only the test case ID is needed to read the pre-stored test cases in the diagnostic analysis module, which improves the security and efficiency of message transmission; on the other hand, the test time of the function to be tested is limited by the test limit time to avoid test timeout, so that the function operation is completed within a certain time, and the accuracy and test efficiency of the function test are improved.

[0088] In one embodiment, the functional structure simulated by the single-chip microcomputer module includes a single-chip microcomputer core, a memory, and multiple external devices, and the memory of the single-chip microcomputer is burned with the operation data required to run the function to be tested. Figure 6 As shown, in step S30, that is, according to the test case information, the single-chip microcomputer module is controlled to simulate the function to be tested of the single-chip microcomputer model, and the test result of the function to be tested is obtained, which specifically includes the following steps: S31: Determine test target data of the function to be tested according to the test case information, and determine a target device associated with the function to be tested from a plurality of external devices.

[0089] The functional structure simulated by the single-chip microcomputer module includes a single-chip microcomputer core, a memory and multiple external devices; the memory of the single-chip microcomputer is burned with the operation data required to run the function to be tested. The memory includes a flash memory and a RAM memory.

[0090] After obtaining the test case information in the first type of message, the diagnostic analysis module in the FPGA board determines the test target data of the function to be tested according to the test case information, and determines the target device associated with the function to be tested from multiple external devices. The target device may include an external device corresponding to the function to be tested, and may also include an external device determined according to a signal corresponding to the test target data.

[0091] Among them, the test case information may include pre-written test cases for the function to be tested, and the diagnostic analysis module extracts test targets from the test cases of the function to be tested to obtain one or more test targets for the function to be tested in this test, that is, to obtain test target data for the function to be tested; and from the test cases of the function to be tested, the external device corresponding to the signal that needs to be captured and monitored when testing the function to be tested in this test is extracted, that is, the target device associated with the function to be tested is determined from the multiple external devices simulated in the single-chip microcomputer module. The target device is an external device that needs to monitor signals when the function to be tested is tested later.

[0092] Taking the entry and exit interrupt function of the timer in the MCU as an example, the test target data for testing the timer function in the test case of the timer function may include whether the signal values ​​of the timer during operation are consistent with the calibrated signal values ​​in the test case, such as the timer initial value, timer frequency division factor, and interrupt flag during the test process, and whether they are consistent with the timer target initial value, timer target frequency division factor, and timer interrupt flag calibrated in the test case. In the process of testing the timer function, the signals that need to be monitored and captured include the timer enable signal, timer initial value, timer frequency division factor, and interrupt flag, that is, it can be determined that the target device associated with the function to be tested is the timer.

[0093] S32: Trigger the microcontroller core to run the function to be tested, so as to start the test of the function to be tested.

[0094] After determining the test target data of the function to be tested and determining the target device, the diagnosis and analysis module starts to trigger the microcontroller core to run the function to be tested to start the test of the function to be tested.

[0095] Among them, the diagnostic analysis module sends the running instruction of the function to be tested to the single-chip microcomputer core. After receiving the running instruction of the function to be tested, the single-chip microcomputer core loads the program data of the function to be tested stored in the flash memory into the RAM storage, and runs the function to be tested in the RAM storage, and the test of the function to be tested starts normally; after running the function to be tested, the function to be tested sends an enable signal so that the diagnostic analysis module captures the enable signal. After capturing the enable signal, the diagnostic analysis module determines that the function to be tested starts normally, so as to continuously monitor the test simulation signals collected by other target devices in the future, so as to judge whether the function to be tested is running normally according to the test simulation signals obtained in real time.

[0096] S33: Acquire the test simulation signal collected by the target device in real time, and determine the test result of the function to be tested according to the test target data and the test simulation signal acquired in real time.

[0097] After triggering the microcontroller core to run the function to be tested, the test process begins. During the test, the diagnostic analysis module obtains the test simulation signal of the target device related to the function to be tested in real time, where the test simulation signal is converted and monitored by an external device; the test result of the function to be tested is determined based on the test target data and the test simulation signal obtained in real time.

[0098] Taking the entry and exit interrupts of the timer function as an example, after determining the test target data of the function to be tested and determining the target device associated with the function to be tested, the diagnostic analysis module sends the operation instruction of the timer function to the microcontroller core. After receiving the operation instruction of the timer function, the microcontroller core loads the program data of the timer function stored in the flash memory into the RAM storage, and runs the timer function in the RAM storage, and the test of the timer function starts normally. After running the timer function, the timer sends an enable signal so that the diagnostic analysis module captures the enable signal.

[0099] After capturing the enable signal, the diagnostic analysis module determines that the timer starts normally, reads the initial value (initial value) and division factor of the timer at startup, and determines whether the initial value of the timer is the target initial value of the timer in the test case, and determines whether the division factor of the timer is the target division factor of the timer in the test case; if the initial value of the timer at startup is not the target initial value of the timer, or the division factor of the timer at startup is not the target division factor, it indicates that the timer operation has an error, the test failure is determined, the test process of the timer function is ended, and the test result of the timer function is output as test failure.

[0100] If the initial value of the timer at startup is the target initial value of the timer, and the division factor of the timer at startup is not the target division factor, it means that the timer is currently running normally and enters the next test phase, waiting for the interrupt flag of the timer to be set; if the interrupt flag of the timer is not read within a certain period of time (the duration is the interrupt flag waiting time set in the test case), it means that the timer is running abnormally, the test failure is determined, the test process of the timer function is ended, and the test result of the timer function is output as test failure.

[0101] If the interrupt flag of the timer is read within a certain period of time, that is, it is determined that the interrupt flag of the timer is set, it is determined that the timer is currently running normally, and the next test phase is entered, waiting for the interrupt flag of the timer to be cleared; if the interrupt flag of the timer is not cleared within a certain period of time after the interrupt flag of the timer is read (the period of time is the interrupt flag clearing period set in the test case), it is determined that the timer is running abnormally and the test has failed, the test process of the timer function is ended, and the test result of the timer function is output as test failure.

[0102] If the interrupt flag of the timer is cleared within a certain period of time after the interrupt flag of the timer is read, that is, the interrupt flag in the timer is cleared, it is determined that the timer is currently operating normally, and the next test phase is entered until all test targets are completed or the test is determined to have failed, and the test result of the function to be tested is output, that is, the test result of the timer function. Among them, if all test targets in the test case are completed, the test result of the function to be tested is output as a successful test; if any test target in the test case is not completed, the test result of the function to be tested is output as a test failure. Among them, the enable signal of the above-mentioned timer, the initial value of the timer, the division factor of the timer and other signals are all collected by the external device simulated in the single-chip microcomputer module.

[0103] In this solution, by real-time monitoring of the timer's enable signal, timing time, interrupt flag, interrupt flag clear status and other signal data, and judging the monitored signal with the test target of the test case, online test result analysis can be achieved, and additional equipment can be used wirelessly to summarize and analyze data results, thereby reducing the test cycle and improving test efficiency.

[0104] In this embodiment, according to the test case information, the test target data of the function to be tested is determined, and the target device associated with the function to be tested is determined in multiple external devices; the single-chip microcomputer kernel is triggered to run the function to be tested to start the test of the function to be tested; during the test process, the test simulation signal collected by the target device is obtained in real time, and the test result of the function to be tested is determined according to the test target data and the test simulation signal obtained in real time. Through the single-chip microcomputer module to simulate the MCU soft core and peripherals, the diagnostic analysis module can capture the test signals of related peripherals in real time during the test process to monitor the test process and perform online signal analysis on the captured signals, without relying on external hardware devices for signal monitoring and analysis, shortening the debugging cycle and reducing the test cost. In addition, the FPGA board can support multi-function and multi-scenario regression testing, improve the efficiency of MCU performance testing, and reduce the cost of MCU chip development.

[0105] In one embodiment, the test case information includes a test case identifier. In step S31, the test target data of the function to be tested is determined according to the test case information, which specifically includes the following steps: S311: Determine the test case corresponding to the test case identifier in the test case data pre-stored in the diagnosis and analysis module, and obtain the target test case corresponding to the function to be tested.

[0106] The test case information in the first type of message includes a test case identifier. After obtaining the test case information in the first type of message, the diagnosis and analysis module determines the test case corresponding to the test case identifier in the test case data pre-stored in the diagnosis and analysis module, and obtains the target test case corresponding to the function to be tested.

[0107] S312: In the target test case, extract the test target data of the function to be tested, and extract the target device associated with the function to be tested.

[0108] In the target test case, the test target data of the function to be tested is extracted, and the target device associated with the function to be tested is extracted. The determination process of the test target data and the target device is as described above and will not be repeated here.

[0109] In this embodiment, the test case information in the first type of message includes a test case identifier. After obtaining the test case information in the first type of message, the diagnostic analysis module determines the test case corresponding to the test case identifier in the test case data pre-stored in the diagnostic analysis module, and obtains the target test case corresponding to the function to be tested; in the target test case, the test target data of the function to be tested is extracted, and the target device associated with the function to be tested is extracted. By pre-storing test cases for different functions to be tested in the diagnostic analysis module in advance, the test case can be directly read according to the test case identifier of the first type of message to extract relevant information during subsequent testing, which is simple and intuitive, and can improve test efficiency.

[0110] In one embodiment, the test case information includes a test time limit. In step S33, i.e., during the test process, the test simulation signal collected by the target device is acquired in real time, and the test result of the function to be tested is determined according to the test target data and the test simulation signal acquired in real time, which specifically includes the following steps: S331: After the single-chip microcomputer core is triggered to run the function to be tested, the timeout timer in the diagnosis and analysis module is started.

[0111] The test case information in the first type of message includes a test case identifier and a test limit duration. After extracting the test target data of the function to be tested and the target device associated with the function to be tested, the diagnostic analysis module triggers the microcontroller core to run the function to be tested to start the test of the function to be tested; after triggering the microcontroller core to run the function to be tested, the diagnostic analysis module starts the timeout timer in the diagnostic analysis module. The timing duration of the timeout timer is the test limit duration.

[0112] S332: During the timing of the timeout timer, a test simulation signal collected by the target device is acquired in real time.

[0113] During the timing of the timeout timer, the diagnosis and analysis module obtains the test simulation signal collected by the target device in real time.

[0114] S333: Monitor the operation of the function to be tested according to the test target data and the test simulation signal obtained in real time, until the timeout timer stops timing or the test is determined to be completed according to the test target data and the test simulation signal, and output the test result of the function to be tested.

[0115] When acquiring the test simulation signal collected by the target device, the diagnostic analysis module monitors the operation of the function to be tested according to the test target data and the test simulation signal acquired in real time, until the timeout timer stops timing or the test is determined to be completed according to the test target data and the test simulation signal, and outputs the test result of the function to be tested. Among them, if the test simulation signal acquired in real time is inconsistent with the corresponding signal value in the test target data, the test result of the function to be tested is determined to be a test failure, or if the timeout timer stops timing and the test is not completed, the test result of the function to be tested is determined to be a test failure. If the test simulation signal acquired in real time is consistent with the corresponding signal value in the test target data, continue to enter the next test stage until the test is completed and the timeout timer stops timing, then the test result of the function to be tested is determined to be a test success.

[0116] In this embodiment, after extracting the test target data of the function to be tested and the target device associated with the function to be tested, the diagnostic analysis module triggers the single-chip microcomputer core to run the function to be tested to start the test of the function to be tested; after triggering the single-chip microcomputer core to run the function to be tested, the timeout timer in the diagnostic analysis module is started, and the timing duration of the timeout timer is the test limit duration; during the timing process of the timeout timer, the test simulation signal collected by the target device is obtained in real time; according to the test target data and the test simulation signal obtained in real time, the operation of the function to be tested is monitored until the timeout timer stops timing or the test is determined to be completed according to the test target data and the test simulation signal, and the test result of the function to be tested is output. During the test process, the test duration is limited by the timeout timer to ensure that the timeout is not exceeded, thereby ensuring the accuracy of the function test and providing the accuracy of the MCU performance test.

[0117] In one embodiment, if Figure 7 The specific structure of the FPGA board is shown in FIG. FPGA board includes a diagnosis and analysis module and a single-chip microcomputer module.

[0118] like Figure 7As shown, the diagnostic analysis module includes a message parsing unit, a test command execution unit, a timeout timer and multiple use case execution units (including use case execution unit 0, use case execution unit 1...use case execution unit N). Each use case execution unit stores a test case of a function to be tested, which is used to execute the test case during the test process, obtain the test simulation signal that needs to be captured to test the function to be tested (the test simulation signal collected by the external device), and determine the test result of the function to be tested according to the test target data in the test case and the captured test simulation signal. The single-chip microcomputer module includes a single-chip microcomputer core (i.e., CPU), internal resources of the single-chip microcomputer and multiple external devices. The internal resources of the single-chip microcomputer include memory, timer, watchdog, pulse width modulator, and programmable counter array. The memory includes flash memory and random access memory RAM. The flash memory includes a first flash memory main flash and a first flash memory nvr flash. The main flash is used to store the binary bin file to be run by the MCU, and the nvr flash is used to configure the default parameters of the MCU before leaving the factory. Multiple external devices may include general input and output, universal asynchronous receiver and transmitter, analog-to-digital converter and other devices for internal and external communication, signal conversion, etc.

[0119] Taking the function to be tested, that is, the entry and exit interruption functions of the timer as an example, the specific process of the single-chip microcomputer performance testing method in this embodiment is explained.

[0120] The host computer receives the program data, test cases and test case identifiers of the timer function input by the user, and obtains the address information of the FPGA board participating in the test, including the MAC address, IP address and port number. The host computer encapsulates the program data, test cases and test case identifiers of the timer function into a UDP message, and adds the header information of the UDP message, which includes the source port number (UDP port number of the host computer), the destination port number (UDP port number of the FPGA board), the data length, and the checksum. The host computer encapsulates the UDP message into an IP datagram, and adds the header information of the IP datagram, which includes: source IP address (IP address of the host computer), destination IP address (IP address of the FPGA board), protocol field such as (UDP protocol number can be 17), TTL (time to live), checksum, etc. The host computer encapsulates the IP datagram into an Ethernet frame, adds Ethernet header information (i.e., frame header), including the destination MAC address (MAC address of the FPGA board), source MAC address (MAC address of the host computer), and message type field, obtains a UDP protocol message, i.e., a preset message, and sends the preset message to the FPGA board via unicast.

[0121] The diagnosis and analysis module of the FPGA board receives the preset message sent by the host computer, and determines the message type of the preset message according to the message type field in the frame header of the preset message.

[0122] When it is determined that the preset message is a second-class message, that is, when the preset message is a message instructing the FPGA board to burn data, the diagnostic analysis module parses the second-class message to obtain the program data of the timer function in the single-chip model in the second-class message, as well as the test case and test case identifier of the timer function. The diagnostic analysis module stores the test case and test case identifier of the timer function in a one-to-one correspondence to the case execution unit in the diagnostic analysis module, such as the case execution unit 1; the diagnostic analysis module burns the program data of the timer function to the memory in the single-chip module, such as the first flash memory, so that the single-chip module can run the timer function. Then, the storage result of the test case of the timer function and the program data burning result are sent to the host computer. The host computer receives the storage result of the test case of the timer function and the program data burning result, and after determining that the program data of the function to be tested has been burned successfully, it sends a first-class message for prompting the FPGA board to perform a functional test. The first-class message includes a test case identifier and a test limit time.

[0123] When it is determined that the preset message is a first-class message, the diagnostic analysis module parses the first-class message to obtain the test case identifier and the test limit duration, and then, according to the test case identifier, determines the test case corresponding to the test case identifier in the test case data pre-stored in the diagnostic analysis module, and obtains the target test case of the timer function; in the target test case, extracts the test target data of the timer function, and extracts the target device associated with the timer function. The diagnostic analysis module triggers the microcontroller core to run the timer function to start the test; after triggering the microcontroller core to run the timer function, the case execution unit starts the timeout timer in the diagnostic analysis module, and during the timeout timer timing process, the test simulation signal collected by the target device is obtained in real time at a frequency of 200Mhz, and the operation of the timer function is monitored according to the test target data and the test simulation signal obtained in real time, until the timeout timer stops timing or the test is determined to be completed according to the test target data and the test simulation signal, and the test result of the timer function is output. Among them, the main frequency of MCU is basically 100Mhz, and the diagnosis and analysis module captures (or samples) the test analog signal to be observed at a frequency of 200Mhz. For example, using 200Mhz to sample the enable signal of the timer can obtain more accurate signals in time. After the timeout timer stops timing, the test stops and the microcontroller module is reset for subsequent testing.

[0124] In this embodiment, the entire process from functional data burning to functional testing can be remotely controlled by the host computer, and the peripheral signals can be captured in real time through the internal logic of the FPGA to replace the external oscilloscope or logic analyzer. There is no need to rely on external tools to burn functional firmware and monitor and capture test result data. The closed loop of the entire functional test can be achieved, making the MCU performance verification highly automated, ensuring the reusability of the test, and improving the efficiency of the MCU performance verification. At the same time, it also reduces the dependence on hardware testing equipment and reduces the testing cost.

[0125] It should be understood that the order of execution of the steps in the above embodiment does not necessarily mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present invention.

[0126] It should be noted that the information interaction, execution process, etc. between the above-mentioned devices / units are based on the same concept as the method embodiment of the present application. Their specific functions and technical effects can be found in the method embodiment part and will not be repeated here.

[0127] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0128] The present application also provides an electronic device, which may be an FPGA board or a host computer. Figure 8 As shown, the electronic device includes: at least one processor, a memory, and a computer program stored in the memory and executable on the at least one processor, wherein the processor implements the steps in any of the above-mentioned method embodiments when executing the computer program, or implements the functions of the modules / units in the above-mentioned device embodiments when executing the computer program.

[0129] Exemplarily, the computer program may be divided into one or more modules / units, which are stored in the memory and executed by the processor to complete the present application. The one or more modules / units may be a series of computer program instruction segments capable of completing specific functions, which are used to describe the execution process of the computer program in the electronic device.

[0130] Those skilled in the art will understand that Figure 8 These are merely examples of the electronic device and do not constitute a limitation of the electronic device. The electronic device may include more or fewer components than those shown in the figure, or a combination of certain components, or different components. For example, the electronic device may also include input and output devices, network access devices, buses, etc.

[0131] The processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), FPGAs (Field-Programmable Gate Arrays) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0132] The memory may be an internal storage unit of the electronic device, such as a hard disk or memory of the electronic device. The memory may also be an external storage device of the electronic device, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc. equipped on the electronic device. Furthermore, the memory may also include both an internal storage unit of the electronic device and an external storage device.

[0133] An embodiment of the present application further provides a readable storage medium, wherein the readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in the above-mentioned method embodiments can be implemented.

[0134] An embodiment of the present application provides a computer program product. When the computer program product runs on an electronic device, the electronic device can implement the steps in the above-mentioned method embodiments when executing the computer program product.

[0135] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium can at least include: any entity or device that can carry the computer program code to the camera / terminal device, recording medium, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, RandomAccess Memory), electric carrier signal, telecommunication signal and software distribution medium. For example, a USB flash drive, a mobile hard disk, a magnetic disk or an optical disk. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electric carrier signals and telecommunication signals.

[0136] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0137] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0138] In the embodiments provided in the present application, it should be understood that the disclosed devices / equipment and methods can be implemented in other ways. For example, the device / equipment embodiments described above are merely schematic, for example, the division of the modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0139] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0140] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A single chip microcomputer performance testing method, characterized in that: Applied to a field programmable gate array board, the field programmable gate array board includes a diagnostic analysis module and a single-chip microcomputer module, the single-chip microcomputer module is used to simulate the function of the single-chip microcomputer model in the design stage; The method is performed by the diagnostic analysis module, and includes: Receive preset messages from the host computer; When it is determined that the preset message is a first-category message, parsing the first-category message to obtain test case information in the first-category message; According to the test case information, control the single-chip microcomputer module to perform a simulation test on the function to be tested of the single-chip microcomputer model, and obtain the test result of the function to be tested, wherein the single-chip microcomputer module is burned with program data for running the function to be tested; Generating test result data of the function to be tested according to the test result of the function to be tested; The test result data of the function to be tested is sent to the host computer, so that the host computer analyzes and obtains the test result indicating whether the function to be tested passes the test, and displays the test result.

2. The single chip microcomputer performance testing method according to claim 1, characterized in that: The functional structure simulated by the single-chip microcomputer module includes a single-chip microcomputer core, a memory and a plurality of external devices, and the memory of the single-chip microcomputer is burned with the operation data required to run the function to be tested; Wherein, controlling the single-chip microcomputer module to perform a simulation test on the function to be tested of the single-chip microcomputer model according to the test case information, and obtaining the test result of the function to be tested includes: Determine the test target data of the function to be tested according to the test case information, and determine the target device associated with the function to be tested among the multiple external devices; Triggering the single-chip microcomputer core to run the function to be tested to start the test of the function to be tested; The test simulation signal collected by the target device is acquired in real time, and the test result of the function to be tested is determined according to the test target data and the test simulation signal acquired in real time.

3. The single chip microcomputer performance testing method as claimed in claim 2, characterized in that: The test case information includes a test time limit, the real-time acquisition of a test simulation signal collected by the target device, and determining a test result of the function to be tested according to the test target data and the real-time acquired test simulation signal, including: After the single-chip microcomputer core is triggered to run the function to be tested, a timeout timer in the diagnosis and analysis module is started, and the timing duration of the timeout timer is the test limit duration; During the timing of the timeout timer, the test simulation signal collected by the target device is acquired in real time; According to the test target data and the test simulation signal acquired in real time, the operation status of the function to be tested is monitored until the timeout timer stops timing or the test completion is determined according to the test target data and the test simulation signal, and the test result of the function to be tested is output.

4. The single chip microcomputer performance testing method as claimed in claim 2, characterized in that: The test case information includes a test case identifier, and determining the test target data of the function to be tested according to the test case information includes: Determine the test case corresponding to the test case identifier in the test case data pre-stored in the diagnosis and analysis module, and obtain the target test case corresponding to the function to be tested; In the target test case, the test target data of the function to be tested is extracted, and the target device associated with the function to be tested is extracted.

5. The single chip microcomputer performance testing method according to any one of claims 1 to 4, characterized in that: The parsing the first type of message to obtain the test case information in the first type of message includes: Parsing the first type of message to obtain a test case identifier and a test time limit, wherein the test time limit is a maximum time limit for testing the function to be tested; The test case identifier and the test time limit are used as the test case information.

6. The single chip microcomputer performance testing method according to any one of claims 1 to 4, characterized in that: After receiving the preset message from the host computer, the method further includes: When it is determined that the preset message is a second-type message, parsing the second-type message to obtain program data of the function to be tested in the single-chip microcomputer model in the second-type message; The program data of the function to be tested is burned into the memory in the single-chip microcomputer module, so that the single-chip microcomputer module can run the function to be tested.

7. A field programmable gate array board, characterized in that: include: MCU module, used to simulate the functions of the MCU model in the design stage; Diagnostic analysis module for: Receive preset messages from the host computer; When it is determined that the preset message is a first-category message, parsing the first-category message to obtain test case information in the first-category message; According to the test case information, control the single-chip microcomputer module to perform a simulation test on the function to be tested of the single-chip microcomputer model, and obtain the test result of the function to be tested, wherein the single-chip microcomputer module is burned with program data for running the function to be tested; Generating test result data of the function to be tested according to the test result of the function to be tested; The test result data of the function to be tested is sent to the host computer, so that the host computer analyzes and obtains the test result indicating whether the function to be tested passes the test, and displays the test result.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the single chip microcomputer performance testing method as claimed in any one of claims 1 to 6 are implemented.

9. A readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the single chip microcomputer performance testing method as claimed in any one of claims 1 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed, the single chip computer performance testing method according to any one of claims 1 to 6 is executed.

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