CAN (Controller Area Network) communication driving circuit with self-adaptive input impedance

Abstract

The invention provides a CAN communication drive circuit with self-adaptive input impedance. The CAN communication drive circuit comprises an output voltage monitoring circuit, a CANH step-by-step opening control circuit, a CANL step-by-step opening control circuit, a CANH self-adaptive impedance matching drive circuit and a CANL self-adaptive impedance matching drive circuit. The output voltage monitoring circuit is used for detecting the voltage of the CANH port and the voltage of the CANL port, comparing the detected voltage of the CANH port and the detected voltage of the CANL port with a reference value of the CANH and a reference value of the CANL respectively, and outputting a first comparison result signal and a second comparison result signal; the CANH step-by-step opening control circuit outputs a switch control signal according to the first comparison result signal to control switches in m parallel branches in the CANH self-adaptive impedance matching drive circuit to be closed step by step; and the CANL step-by-step opening control circuit outputs a switch control signal according to the second comparison result signal to control switches in n parallel branches in the CANL self-adaptive impedance matching driving circuit to be closed step by step.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a CAN communication driving circuit with adaptive input impedance. Background Art

[0002] In industrial electronics and automotive electronics, CAN bus communication is widely used in bus interconnection communication because of its fast speed and strong anti-interference ability. CAN bus communication is generally divided into protocol control and CAN physical layer. Protocol control is divided into host and slave. In automotive applications, the host and slave nodes are far apart, so dedicated CAN physical layer chips are required on both the host and slave sides for signal drive conversion, such as Figure 1 As shown in the figure: the host (Master) transmits data to transmission chip 1 (CAN PHY chip) through the local TX / RX interface. Transmission chip 1 converts the single-ended signal into a common-mode interface signal and transmits it over long distances through the CANH / CANL bus. After the transmission chip 2 (CAN PHY chip) on the slave (Slave) side receives the CANH / CANL signal, it converts it into a local single-ended signal TX / RX and transmits it to the slave module to complete the data transmission.

[0003] In automotive electronic applications, the slave devices of the two communication buses, CANH and CANL, are diverse, and the number of slaves in different applications is also different. When the number of nodes on the CAN bus is different, the equivalent impedance of the CAN bus will also change significantly. When the equivalent impedance changes, the driving voltage of the nodes on the CAN bus will also change when transmitting high and low potentials. This may cause the CAN bus interface drive output characteristics of some nodes to fail to meet the electromagnetic compatibility and signal integrity of the bus system, and cause communication abnormalities, causing systemic risks.

[0004] In order to improve the voltage resistance of the CAN bus interface, the CAN PHY chip usually adopts a driving method combining high-voltage MOS tubes and anti-reverse diodes at the output stage. Usually, the CAN bus chip outputs current, and the bus voltage difference generated on the external load Rload is a high-level voltage drop, which is defined as the dominant mode. The CAN bus chip shuts off the output current, and the bus voltage difference generated on the external load Rload is a low-level voltage drop, which is defined as the recessive mode. The traditional CAN bus chip driver stage is as follows Figure 2 As shown: IB is the drive output reference current source. In the dominant state, EN_DOM=1, CANL is mirrored by N2 and N1, I CANL =I dom =β*IB, β is the size ratio of N2 to N1, CANH end mirrors the current of P1 through P2, I CANH =I P2 =β*IP1 =β*I N3 =β*IB=I CANL When the voltage is from recessive to dominant, the current of the high-side CANH and the low-side CANL are equal, achieving the purpose of output drive matching. At this time, the dominant differential voltage V DOM =V CANH -V CANL =I CANH *R LOAD In the recessive state, EN_DOM = 0, N6 is turned on, and the gate end of N2 is pulled down to GND, and N2 turns off I dom =0, at the same time, P3 is turned on, and the gate end of P2 is pulled up to the power supply VCC, P2 is turned off, and I dom =0, at this time the implicit differential voltage V REC =0.

[0005] However, this solution has two disadvantages in dealing with abnormal protection of automotive CAN transceiver chips: 1. During CAN bus communication, the switching speed between the dominant mode and the recessive mode is too fast, and there is no slope control, which will cause greater noise interference during communication.

[0006] 2. When the nodes on the CAN bus are different and Rload changes, Rload will vary greatly, causing V DOM The consistency is poor, which may make it impossible for the devices on the bus to correctly identify the status of the CAN bus.

[0007] It can be seen that the driving output circuit of the traditional CAN transceiver chip cannot meet the system's requirements for high signal integrity and low electromagnetic radiation interference of multiple nodes of the CAN transceiver chip in vehicle applications. Summary of the invention

[0008] The purpose of the present invention is to provide a CAN communication driving circuit with adaptive input impedance, which can improve the impedance matching characteristics of the vehicle-mounted CAN bus chip during the communication output process, so that the interface of the CAN bus chip has better driving compatibility characteristics and signal integrity characteristics.

[0009] In order to achieve the above object, the present invention provides a CAN communication driving circuit with adaptive input impedance, comprising: Output voltage monitoring circuit, CANH step-by-step start control circuit, CANL step-by-step start control circuit, CANH adaptive impedance matching drive circuit, CANL adaptive impedance matching drive circuit; The output voltage monitoring circuit is used to detect the voltage of the CANH port and the voltage of the CANL port, and compare the detected voltage of the CANH port and the voltage of the CANL port with the reference value of CANH and the reference value of CANL respectively, and output a first comparison result signal and a second comparison result signal; The CANH adaptive impedance matching driving circuit and the CANL adaptive impedance matching driving circuit each include a plurality of parallel branches, each of the branches including a switch and a resistor connected in series; In explicit mode: When the voltage of the CANH port does not reach its reference value, the CANH step-by-step opening control circuit receives the first comparison result signal; when the voltage of the CANL port does not reach its reference value, the CANL step-by-step opening control circuit receives the second comparison result signal; The CANH step-by-step opening control circuit outputs a switch control signal SP<1:m> (m is an integer greater than 1) according to the first comparison result signal and driven by the clock signal to control the switches in the m parallel branches in the CANH adaptive impedance matching drive circuit to be closed step by step, thereby connecting the resistors in parallel step by step, so that the voltage of the CANH port finally reaches the reference value; The CANL step-by-step opening control circuit outputs a switch control signal SN<1:n> (n is an integer greater than 1) according to the second comparison result signal and driven by the clock signal to control the switches in the n parallel branches in the CANL adaptive impedance matching drive circuit to be closed step by step, thereby connecting the resistors in parallel step by step, so that the voltage of the CANL port finally reaches the reference value.

[0010] In an optional solution, the CANH step-by-step opening control circuit includes: A first AND gate and m cascaded CANH single-stage start-up control circuits; each of the CANH single-stage start-up control circuits comprises a first trigger, a second inverter and a second AND gate; The input end of the first trigger of the first CANH single-stage start control circuit is used to input the first comparison result signal, and the input end of the first trigger of the subsequent CANH single-stage start control circuit is connected to the output end of the second AND gate of the previous CANH single-stage start control circuit; The output end of the first trigger of the CANH single-stage start-up control circuit is connected to the input end of the second inverter; one input end of the second AND gate is connected to the input end of the first trigger, and the other input end is connected to the output end of the second inverter; the output end of each of the second inverters outputs the switch control signal SP<1:m> respectively; the reset end of each of the first triggers is used to input the enable signal EN_DOM; One input terminal of the first AND gate is used to input the first comparison result signal, and the other input terminal is used to input a clock signal. The output terminal of the first AND gate is connected to the clock signal input terminal of each of the first triggers.

[0011] In an optional solution, the CANL step-by-step opening control circuit includes: A third AND gate and n cascaded CANL single-stage start control circuits; each of the CANL single-stage start control circuits includes a second trigger and a fourth AND gate; The input end of the second trigger of the first CANL single-stage start control circuit is used to input the second comparison result signal, and the input end of the second trigger of the subsequent single-stage start control circuit is connected to the output end of the fourth AND gate of the previous CANL single-stage start control circuit; One input end of the fourth AND gate of the CANL single-stage opening control circuit is connected to the input end of the second trigger, and the other input end of the fourth AND gate is connected to the output end of the second trigger; the output end of each of the second triggers outputs the switch control signal SN<1:n> respectively; the reset end of each of the second triggers is used to input the enable signal EN_DOM; One input terminal of the third AND gate is used to input the second comparison result signal, and the other input terminal is used to input the clock signal. The output terminal of the third AND gate is connected to the clock signal input terminal of each of the second triggers.

[0012] In an optional solution, the switches in the CANH adaptive impedance matching drive circuit are all MOS tubes, and the CANH adaptive impedance matching drive circuit further includes: A first high-voltage MOS tube and a first inverter; The first high-voltage MOS tube is connected between the CANH port and the m parallel branches, and the other ends of the m parallel branches are connected to the power supply; The input end of the first inverter is used to input an enable signal EN-DOM, and the output end is connected to the gate of the first high-voltage MOS tube; The gate of each of the MOS transistors is respectively used to input the switch control signal SP<1:m>.

[0013] In an optional solution, the switch in the CANL adaptive impedance matching drive circuit is a MOS tube, and the CANL adaptive impedance matching drive circuit further includes: A second high-voltage MOS tube, wherein the second high-voltage MOS tube is connected between the CANL port and the n parallel branches, and the other end of the n parallel branches is connected to the ground; The gate of the second high-voltage MOS tube is used to input an enable signal EN-DOM; The gate of each of the MOS transistors is respectively used to input the switch control signal SN<1:n>.

[0014] In an optional solution, the first high-voltage MOS tube is a high-voltage PMOS tube, and the MOS tube in the CANH adaptive impedance matching drive circuit is a PMOS tube; The drain of the high-voltage PMOS tube is connected to the anode of the first diode at the CANH end, the source of the high-voltage PMOS tube is connected to the drain of each of the PMOS tubes in the m parallel branches, and the source of each of the PMOS tubes is connected to a resistor.

[0015] In an optional solution, the second high-voltage MOS tube is a high-voltage NMOS tube; the MOS in the CANL adaptive impedance matching drive circuit is an NMOS tube; The drain of the high-voltage NMOS tube is connected to the cathode of the second diode at the CANL end, the source of the high-voltage NMOS tube is connected to the drain of each NMOS tube in the n parallel branches, and the source of each NMOS tube is connected to a resistor.

[0016] In an optional solution, the output voltage monitoring circuit includes: A first voltage-dividing resistor, a second voltage-dividing resistor, a third voltage-dividing resistor, a first reference current source, a second reference current source, a third diode, a fourth diode, a first comparator, and a second comparator; One end of the first voltage-dividing resistor is connected to a power supply, and the other end is connected to one end of the second voltage-dividing resistor, the other end of the second voltage-dividing resistor is connected to one end of the third voltage-dividing resistor, and the other end of the third voltage-dividing resistor is grounded; One end of the first reference current source is connected to the power supply, and the other end is connected to the anode of the third diode, and the cathode of the third diode is connected between the first voltage-dividing resistor and the second voltage-dividing resistor; The anode of the fourth diode is connected between the second voltage-dividing resistor and the third voltage-dividing resistor, the cathode is connected to one end of the second reference current source, and the other end of the second reference current source is grounded; The positive input end of the first comparator is connected to the connection between the first high-voltage MOS tube and the m parallel branches, the negative input end is connected to the anode of the third diode, and the output end outputs the first comparison result signal; The positive input end of the second comparator is connected to the connection between the second high-voltage MOS tube and the n parallel branches, the negative input end is connected to the cathode of the fourth diode, and the output end outputs the second comparison result signal.

[0017] The beneficial effects of the present invention are: 1. By monitoring the voltage on the CAN bus, the voltage of CANH and CANL is adaptively adjusted to reach the reference value, and it will not be affected by the number of output nodes on the bus and the load impedance.

[0018] 2. The conversion between dominant mode and recessive mode adopts the multi-stage switch step-by-step control method, and its turn-on slope is not affected by the output stage MOS tube ( Figure 2 MOS tube P2 / MOS tube N2) V TH , C GS These parameters are controlled by an internal precise high-frequency clock, so the chip has better electromagnetic compatibility characteristics and better consistency between chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other objects, features and advantages of the present invention will become more apparent through a more detailed description of exemplary embodiments of the present invention in conjunction with the accompanying drawings, in which like reference numerals generally represent like components.

[0020] Figure 1 It is a schematic diagram of CAN bus communication in automotive electronic applications in the prior art.

[0021] Figure 2 This is a circuit diagram of the explicit mode output driver stage of a CAN bus transceiver chip in the prior art.

[0022] Figure 3 This is a schematic diagram of a CAN communication driving circuit with adaptive input impedance in one embodiment of the present invention.

[0023] Figure 4 This is a schematic diagram of an output voltage monitoring circuit and a CANH / CANL step-by-step opening control circuit in an embodiment of the present invention.

[0024] Figure 5 1 is a driving waveform diagram of a CAN communication driving circuit with adaptive input impedance in one embodiment of the present invention. DETAILED DESCRIPTION

[0025] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description and drawings, the advantages and features of the present invention will become clearer. However, it should be noted that the concept of the technical solution of the present invention can be implemented in a variety of different forms and is not limited to the specific embodiments described herein. The drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0026] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0027] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0028] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0029] Example Reference Figures 3 to 5 , this embodiment provides a CAN communication driving circuit with adaptive input impedance, comprising: Output voltage monitoring circuit, CANH step-by-step start control circuit, CANL step-by-step start control circuit, CANH adaptive impedance matching drive circuit, CANL adaptive impedance matching drive circuit; The output voltage monitoring circuit is used to detect the voltage of the CANH port and the voltage of the CANL port, and compare the detected voltage of the CANH port and the voltage of the CANL port with the reference value of CANH and the reference value of CANL respectively, and output a first comparison result signal CANH_CMPOUT and a second comparison result signal CANL_CMPOUT; The CANH adaptive impedance matching driving circuit and the CANL adaptive impedance matching driving circuit each include a plurality of parallel branches, each of the branches including a switch and a resistor connected in series; In explicit mode: When the voltage of the CANH port does not reach its reference value, the CANH step-by-step opening control circuit receives the first comparison result signal; when the voltage of the CANL port does not reach its reference value, the CANL step-by-step opening control circuit receives the second comparison result signal; The CANH step-by-step opening control circuit outputs a switch control signal SP<1:m> (m is an integer greater than 1) according to the first comparison result signal and driven by the clock signal to control the switches in the m parallel branches in the CANH adaptive impedance matching driving circuit to be closed step by step, so as to connect the resistors in parallel step by step, thereby achieving an impedance matching effect, so that the voltage of the CANH port finally reaches the reference value; The CANL step-by-step opening control circuit outputs a switch control signal SN<1:n> (n is an integer greater than 1) according to the second comparison result signal and driven by the clock signal to control the switches in the n parallel branches in the CANL adaptive impedance matching drive circuit to be closed step by step, thereby connecting the resistors in parallel step by step, thereby achieving an impedance matching effect, so that the voltage of the CANL port finally reaches the reference value.

[0030] Specifically, in this embodiment, the CANH step-by-step start control circuit includes: a first AND gate NAND1 and m cascaded CANH single-stage start control circuits CANH_CTR; each of the CANH single-stage start control circuits CANH_CTR includes a first trigger DFF1, a second inverter INV2 and a second AND gate NAND2; the input end of the first trigger DFF1 of the first CANH single-stage start control circuit CANH_CTR is used to input the first comparison result signal, and the input end of the first trigger DFF1 of the subsequent CANH single-stage start control circuit CANH_CTR is connected to the output end of the second AND gate NAND2 of the previous CANH single-stage start control circuit CANH_CTR; the CANH single-stage start control circuit The output end of the first trigger DFF1 of the start control circuit CANH_CTR is connected to the input end of the second inverter INV2; one input end of the second AND gate NAND2 is connected to the input end of the first trigger DFF1, and the other input end is connected to the output end of the second inverter INV2; the output end of each second inverter INV2 outputs the switch control signal SP<1:m> respectively; the reset end of each first trigger DFF1 is used to input the enable signal EN_DOM; one input end of the first AND gate NAND1 is used to input the first comparison result signal, and the other input end is used to input the clock signal CLK_IN, and the output end of the first AND gate NAND1 is connected to the clock signal input end of each first trigger DFF1.

[0031] In this embodiment, the CANL step-by-step start control circuit includes: a third AND gate NAND3 and n cascaded CANL single-stage start control circuits CANL_CTR; each of the CANL single-stage start control circuits CANL_CTR includes a second trigger DFF2 and a fourth AND gate NAND4; the input end of the second trigger DFF2 of the first CANL single-stage start control circuit CANL_CTR is used to input the second comparison result signal, and the input end of the second trigger DFF2 of the subsequent single-stage start control circuit CANL_CTR is connected to the output end of the fourth AND gate NAND4 of the previous CANL single-stage start control circuit CANL_CTR; the CAN One input end of the fourth AND gate NAND4 of the L single-stage turn-on control circuit CANL_CTR is connected to the input end of the second trigger DFF2, and the other input end of the fourth AND gate NAND4 is connected to the output end of the second trigger DFF2; the output end of each second trigger DFF2 outputs the switch control signal SN<1:n> respectively; the reset end of each second trigger is used to input the enable signal EN_DOM; one input end of the third AND gate NAND3 is used to input the second comparison result signal, and the other input end is used to input the clock signal CLK_IN, and the output end of the third AND gate NAND3 is connected to the clock signal input end of each second trigger DFF2.

[0032] In this embodiment, the switches in the CANH adaptive impedance matching drive circuit are all MOS tubes, and the CANH adaptive impedance matching drive circuit also includes: a first high-voltage MOS tube and a first inverter INV1; the first high-voltage MOS tube is connected between the CANH port and the m parallel branches, and the other ends of the m parallel branches are connected to the power supply VCC; the input end of the first inverter INV1 is used to input the enable signal EN-DOM, and the output end is connected to the gate of the first high-voltage MOS tube; the gates of each of the MOS tubes are respectively used to input the switch control signal SP<1:m>.

[0033] In this embodiment, the first high-voltage MOS tube is a high-voltage PMOS tube HVMP11, and the MOS tube in the CANH adaptive impedance matching drive circuit is a PMOS tube; the drain of the high-voltage PMOS tube HVMP11 is connected to the anode of the first diode D1 at the CANH end, the source of the high-voltage PMOS tube HVMP11 is connected to the drain of each of the PMOS tubes in the m parallel branches, and the source of each of the PMOS tubes is connected to a resistor (such as Figure 3 As shown, the source of the first PMOS tube MP1 is connected to the first resistor R1, the source of the second PMOS tube MP2 is connected to the second resistor R2, and so on, and the source of the tenth PMOS tube MP10 is connected to the tenth resistor R10).

[0034] In this embodiment, the switch in the CANL adaptive impedance matching drive circuit is a MOS tube, and the CANL adaptive impedance matching drive circuit also includes: a second high-voltage MOS tube, the second high-voltage MOS tube is connected between the CANL port and the n parallel branches, and the other end of the n parallel branches is connected to the ground; the gate of the second high-voltage MOS tube is used to input the enable signal EN-DOM; the gates of the MOS tubes are respectively used to input the switch control signal SN<1:n>.

[0035] In this embodiment, the second high-voltage MOS tube is a high-voltage NMOS tube HVMN11; the MOS in the CANL adaptive impedance matching drive circuit is an NMOS tube; the drain of the high-voltage NMOS tube HVMN11 is connected to the cathode of the second diode D2 at the CANL end, the source of the high-voltage NMOS tube HVMN11 is connected to the drain of each of the NMOS tubes in the n parallel branches, and the source of each of the NMOS tubes is connected to a resistor.

[0036] In this embodiment, the output voltage monitoring circuit includes: a first voltage-dividing resistor RH, a second voltage-dividing resistor RDM, a third voltage-dividing resistor RL, a first reference current source IB1, a second reference current source IB2, a third diode D3, a fourth diode D4, a first comparator CMP1 and a second comparator CMP2; one end of the first voltage-dividing resistor RH is connected to a power supply VCC, and the other end is connected to one end of the second voltage-dividing resistor RDM, the other end of the second voltage-dividing resistor RDM is connected to one end of the third voltage-dividing resistor RL, and the other end of the third voltage-dividing resistor RL is grounded; the first reference current One end of the source IB1 is connected to the power supply VCC, and the other end is connected to the anode of the third diode D3, and the cathode of the third diode D3 is connected between the first voltage-dividing resistor RH and the second voltage-dividing resistor RDM; the anode of the fourth diode D4 is connected between the second voltage-dividing resistor RDM and the third voltage-dividing resistor RL, and the cathode is connected to one end of the second reference current source IB2, and the other end of the second reference current source IB2 is grounded; the positive input end of the first comparator CMP1 is connected to the connection between the first high-voltage MOS tube and the m parallel branches (where the voltage is V CANH_FB ), negative input terminal (input voltage is V CANH_REF ) is connected to the anode of the third diode D3, and the output terminal outputs the first comparison result signal; the positive input terminal of the second comparator CMP2 is connected to the connection point of the second high-voltage MOS tube and the n parallel branches (the voltage here is V CANL_FB ), negative input terminal (input voltage is V CANL_REF) is connected to the cathode of the fourth diode D4, and the output end outputs the second comparison result signal.

[0037] In this embodiment, taking the CANH adaptive impedance matching driving circuit as an example, assuming that m=10 (10 parallel branches, the number of m can be adjusted according to application requirements, the principle does not change due to the different number of m, and is within the protection scope of this solution), when the chip enters the dominant mode, the enable signal EN_DOM=1, the first high-voltage PMOS tube HVMP11 is turned on, and the driving current flows from the power supply VCC to the CANH port. When only SP <1> =0, SP<2:10>=1, the first PMOS tube MP1 is turned on, and the input equivalent impedance of CANH is R CANH =R1, when SP<1:10>=0, the first PMOS tube MP1 to the tenth PMOS tube MP10 are all turned on, and the input equivalent impedance of CANH is R CANH =R1 / / R2 / / R3 / / … / / R8 / / R9 / / R10. Usually R1=R2=…=Rm. From the above description, we can know that the input impedance of CANH will be dynamically adjusted according to the voltage of CANH port.

[0038] For the CANL adaptive impedance matching drive circuit, its principle is the same as above. Assuming n=10 (10 parallel branches, the number of n can be adjusted according to application requirements, the principle does not change due to the number of n, and is within the protection scope of this solution) when the chip enters the dominant mode, the enable signal EN_DOM=1, the second high-voltage NMOS tube HVMN11 is turned on, and the drive current flows from the CANL port to the ground GND. When only SN <1> =1, SN<2:10>=0, the first NMOS tube MN1 is turned on, and the input equivalent impedance of CANL is R CANL =R1A, when SN<1:10>=1, the first NMOS transistor MN1 to the tenth NMOS transistor MN10 are all turned on, and the input equivalent impedance of CANL is R CANL =R1A / / R2A / / R3A / / … / / R8A / / R9A / / R10A. Usually R1A=R2A=…=RnA. From the above description, we can know that the input impedance of CANL will be dynamically adjusted according to the voltage of CANL port.

[0039] Combine the following Figure 4 The output voltage monitoring circuit and the implementation schematic diagram of the step-by-step opening control circuit illustrate the dynamic adjustment process. The first voltage-dividing resistor RH, the second voltage-dividing resistor RDM, and the third voltage-dividing resistor RL are used to generate the dominant mode reference voltage V of CANH by performing resistor voltage division on the power supply VCC. CANH_int(When VCC = 5V, usually 3.5V) and the dominant mode reference voltage V CANL_int (When VCC=5V, it is usually 1.5V). Considering the voltage drop of the signal on the anti-reverse diode (the first diode D1 and the second diode D2), CANH_int and V CANL_int The third diode D3 and the fourth diode D4 are stacked on the V CANH_FB (the voltage at the connection point between the first high-voltage MOS tube and the CANH adaptive impedance matching drive circuit) and V CANL_FB (the voltage at the connection point between the second high-voltage MOS tube and the CANL adaptive impedance matching drive circuit) is compared, and the outputs of the first comparator CMP1 at the CANH end and the second comparator CMP2 at the CANL end are the first comparison signal CANH_CMPOUT and the second comparison signal CANL_CMPOUT respectively. In the CANH step-by-step start control circuit, the first trigger DFF1, the second inverter INV2, and the second AND gate NAND2 constitute a single-stage start control circuit CANH_CTR, and the first comparison signal CANH_CMPOUT is its input signal. The signal CLK_IN1 after CANH_CMPOUT and the clock signal CLK_IN (for example, 200MHz) pass through the first AND gate NAND1 is the clock input signal of CANH_CTR. In dominant mode, the enable signal EN_DOM is the reset control signal of the module, and SP<1:m> is the output of CANH_CTR. Among them, SP <1> Connect the gate of the first PMOS tube MP1 of the driving circuit. Similarly, the second trigger DFF2 and the fourth AND gate NAND4 constitute a single-stage start-up control circuit CANL_CTR, the second comparison signal CANL_CMPOUT is its input signal, and the signal CLK_IN2 after CANL_CMPOUT and the clock signal CLK_IN (for example, 200MHz) pass through the third AND gate NAND3 is the clock input signal of CANL_CTR. In dominant mode, the enable signal EN_DOM is the reset control signal of the module, and SN<1:n> is the output of CANL_CTR, where SN <1> The number of m and n can be equal or different. Figure 4 As shown, the number of stages of the step-by-step opening control circuit is consistent with the number of switch stages in the driving circuit. For the sake of convenience, 10 stages are taken as an example.

[0040] When the chip works in recessive mode, V CANH =V CANL =2.5V, EN_DOM=0, when the chip changes from recessive mode to dominant mode, EN_DOM=1, at this time V CANH_FB <V CANH_REF ,CANH_CMPOUT=1, VCANL_FB >V CANL_REF , CANL_CMPOUT = 1, when the rising edge of the clock signal CLK_IN arrives, SP <1> =0, SN <1> =1, thereby controlling the first PMOS tube MP1 and the first NMOS tube MN1 to turn on, and the current flows out of the CANH port and flows into the CANL port. As the rising edge of CLK_IN continues to arrive, the CANH voltage gradually increases, and the CANL voltage decreases step by step. When the port voltages of CANH and CANL reach the reference value, V CANH_FB >V CANH_REF ,CANH_CMPOUT=0, V CANL_FB <V CANL_REF , CANL_CMPOUT=0. At this time, when the rising edge of the clock CLK_IN arrives, the states of SP<1:m> and SN<1:n> no longer change, and the drive circuit maintains the current output to generate a dominant mode drive voltage.

[0041] The CAN communication driving circuit with adaptive input impedance proposed in this embodiment has the characteristics of adaptive input impedance matching, high bus output voltage consistency, and good electromagnetic compatibility. The CAN bus transceiver chip output control circuit of this embodiment can be widely used in vehicle communication chips.

[0042] This embodiment detects the switching state between the dominant mode and the recessive mode, and simultaneously monitors the voltage of the CANH interface and the CANL interface and opens them step by step during CAN bus communication, so that the output voltage difference VDOM of the CAN bus in the dominant mode does not change with the number of nodes (slaves) on the bus. At the same time, the control circuit that is opened step by step reduces electromagnetic interference and bus disturbance, thereby improving the impedance matching characteristics and electromagnetic compatibility of the CAN bus.

[0043] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A CAN communication driving circuit with adaptive input impedance, characterized in that: include: Output voltage monitoring circuit, CANH step-by-step start control circuit, CANL step-by-step start control circuit, CANH adaptive impedance matching drive circuit, CANL adaptive impedance matching drive circuit; The output voltage monitoring circuit is used to detect the voltage of the CANH port and the voltage of the CANL port, and compare the detected voltage of the CANH port and the voltage of the CANL port with the reference value of CANH and the reference value of CANL respectively, and output a first comparison result signal and a second comparison result signal; The CANH adaptive impedance matching driving circuit and the CANL adaptive impedance matching driving circuit each include a plurality of parallel branches, each of the branches including a switch and a resistor connected in series; In explicit mode: When the voltage of the CANH port does not reach its reference value, the CANH step-by-step opening control circuit receives the first comparison result signal; When the voltage of the CANL port does not reach its reference value, the CANL step-by-step opening control circuit receives the second comparison result signal; The CANH step-by-step opening control circuit outputs a switch control signal SP<1:m> under the drive of the clock signal according to the first comparison result signal, where m is an integer greater than 1, to control the switches in the m parallel branches in the CANH adaptive impedance matching drive circuit to be closed step by step, thereby connecting the resistors in parallel step by step, so that the voltage of the CANH port finally reaches the reference value; The CANL step-by-step opening control circuit outputs a switch control signal SN<1:n> according to the second comparison result signal and driven by the clock signal, where n is an integer greater than 1, to control the switches in the n parallel branches in the CANL adaptive impedance matching drive circuit to be closed step by step, thereby connecting the resistors in parallel step by step, so that the voltage of the CANL port finally reaches the reference value.

2. The CAN communication driving circuit with adaptive input impedance as claimed in claim 1, characterized in that: The CANH step-by-step opening control circuit comprises: A first AND gate and m cascaded CANH single-stage start-up control circuits; each of the CANH single-stage start-up control circuits comprises a first trigger, a second inverter and a second AND gate; The input end of the first trigger of the first CANH single-stage start control circuit is used to input the first comparison result signal, and the input end of the first trigger of the subsequent CANH single-stage start control circuit is connected to the output end of the second AND gate of the previous CANH single-stage start control circuit; The output end of the first trigger of the CANH single-stage start-up control circuit is connected to the input end of the second inverter; one input end of the second AND gate is connected to the input end of the first trigger, and the other input end is connected to the output end of the second inverter; the output end of each of the second inverters outputs the switch control signal SP<1:m> respectively; the reset end of each of the first triggers is used to input the enable signal EN_DOM; One input terminal of the first AND gate is used to input the first comparison result signal, and the other input terminal is used to input a clock signal. The output terminal of the first AND gate is connected to the clock signal input terminal of each of the first triggers.

3. The CAN communication driving circuit with adaptive input impedance as claimed in claim 1, characterized in that: The CANL step-by-step opening control circuit comprises: A third AND gate and n cascaded CANL single-stage start control circuits; each of the CANL single-stage start control circuits includes a second trigger and a fourth AND gate; The input end of the second trigger of the first CANL single-stage start control circuit is used to input the second comparison result signal, and the input end of the second trigger of the subsequent single-stage start control circuit is connected to the output end of the fourth AND gate of the previous CANL single-stage start control circuit; One input end of the fourth AND gate of the CANL single-stage opening control circuit is connected to the input end of the second trigger, and the other input end of the fourth AND gate is connected to the output end of the second trigger; the output end of each of the second triggers outputs the switch control signal SN<1:n> respectively; the reset end of each of the second triggers is used to input the enable signal EN_DOM; One input terminal of the third AND gate is used to input the second comparison result signal, and the other input terminal is used to input the clock signal. The output terminal of the third AND gate is connected to the clock signal input terminal of each of the second triggers.

4. The CAN communication driving circuit with adaptive input impedance as claimed in claim 1, characterized in that: The switches in the CANH adaptive impedance matching drive circuit are all MOS tubes, and the CANH adaptive impedance matching drive circuit also includes: A first high-voltage MOS tube and a first inverter; The first high-voltage MOS tube is connected between the CANH port and the m parallel branches, and the other ends of the m parallel branches are connected to the power supply; The input end of the first inverter is used to input an enable signal EN-DOM, and the output end is connected to the gate of the first high-voltage MOS tube; The gate of each of the MOS transistors is respectively used to input the switch control signal SP<1:m>.

5. The CAN communication driving circuit with adaptive input impedance as claimed in claim 4, characterized in that: The switch in the CANL adaptive impedance matching drive circuit is a MOS tube, and the CANL adaptive impedance matching drive circuit also includes: A second high-voltage MOS tube, wherein the second high-voltage MOS tube is connected between the CANL port and the n parallel branches, and the other end of the n parallel branches is connected to the ground; The gate of the second high-voltage MOS tube is used to input an enable signal EN-DOM; The gate of each of the MOS transistors is respectively used to input the switch control signal SN<1:n>.

6. The CAN communication driving circuit with adaptive input impedance as claimed in claim 4, characterized in that: The first high-voltage MOS tube is a high-voltage PMOS tube, and the MOS tube in the CANH adaptive impedance matching drive circuit is a PMOS tube; The drain of the high-voltage PMOS tube is connected to the anode of the first diode at the CANH end, the source of the high-voltage PMOS tube is connected to the drain of each of the PMOS tubes in the m parallel branches, and the source of each of the PMOS tubes is connected to a resistor.

7. The CAN communication driving circuit with adaptive input impedance as claimed in claim 5, characterized in that: The second high-voltage MOS tube is a high-voltage NMOS tube; the MOS in the CANL adaptive impedance matching drive circuit is an NMOS tube; The drain of the high-voltage NMOS tube is connected to the cathode of the second diode at the CANL end, the source of the high-voltage NMOS tube is connected to the drain of each NMOS tube in the n parallel branches, and the source of each NMOS tube is connected to a resistor.

8. The CAN communication driving circuit with adaptive input impedance as claimed in claim 5, characterized in that: The output voltage monitoring circuit comprises: A first voltage-dividing resistor, a second voltage-dividing resistor, a third voltage-dividing resistor, a first reference current source, a second reference current source, a third diode, a fourth diode, a first comparator, and a second comparator; One end of the first voltage-dividing resistor is connected to a power supply, and the other end is connected to one end of the second voltage-dividing resistor, the other end of the second voltage-dividing resistor is connected to one end of the third voltage-dividing resistor, and the other end of the third voltage-dividing resistor is grounded; One end of the first reference current source is connected to the power supply, and the other end is connected to the anode of the third diode, and the cathode of the third diode is connected between the first voltage-dividing resistor and the second voltage-dividing resistor; The anode of the fourth diode is connected between the second voltage-dividing resistor and the third voltage-dividing resistor, the cathode is connected to one end of the second reference current source, and the other end of the second reference current source is grounded; The positive input end of the first comparator is connected to the connection between the first high-voltage MOS tube and the m parallel branches, the negative input end is connected to the anode of the third diode, and the output end outputs the first comparison result signal; The positive input end of the second comparator is connected to the connection between the second high-voltage MOS tube and the n parallel branches, the negative input end is connected to the cathode of the fourth diode, and the output end outputs the second comparison result signal.

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