Joint debugging method and device of JTAG and OpenOCD based on UVM platform

Abstract

The invention relates to a joint debugging method and device for JTAG and OpenOCD based on a UVM platform. The method comprises the following steps: importing a JTAG DPI C function into a UVM verification platform; the JTAG DPI C function is used for controlling the OpenOCD to interact with a JTAG interface of the UVM verification platform; instantiating a JTAG DPI module on the UVM verification platform, and connecting a JTAG interface with a device to be tested; the method comprises the following steps: according to an OpenOCD configuration file, configuring the OpenOCD into a remote-bitbank mode; the OpenOCD configuration file comprises a remote host address, a remote host port number and a remote-bitbank interface; a JTAG time sequence packet received by the JTAG DPI module is converted into simulation test excitation interacting with a compiling simulator of the UVM verification platform through a TCP Socket interface and a direct programming interface DPI; and starting the OpenOCD, setting a preset port of the OpenOCD as a telnet connection port, and issuing a debugging command to the to-be-tested device through the preset port.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit digital chip verification, and in particular to a joint debugging method and device of JTAG and OpenOCD based on a UVM platform. Background Art

[0002] With the rapid development of digital integrated circuits, chip functions are becoming increasingly complex, and chip verification plays an important role in the chip design cycle.

[0003] In the related art, debugging and verification are performed by connecting the debugger through the hardware interface of the development board. This method requires the purchase of hardware equipment, which increases the verification cost, and the time cost of selecting and debugging the development board. In terms of debugging, the internal logic cannot be directly viewed, and the debugging cycle is long.

[0004] Therefore, how to improve debugging efficiency and efficiently locate and solve problems on the UVM platform is an issue that needs to be addressed urgently. Summary of the invention

[0005] In order to solve the above technical problems, the present disclosure provides a joint debugging method and device of JTAG and OpenOCD based on UVM platform.

[0006] In a first aspect, the present disclosure provides a joint debugging method of JTAG and OpenOCD based on a UVM platform, comprising:

[0007] Importing a JTAG DPI C function in the UVM verification platform; the JTAG DPI C function is used to control OpenOCD to interact with the JTAG interface of the UVM verification platform;

[0008] Instantiate the JTAG DPI module in the UVM verification platform and connect the JTAG interface to the device under test;

[0009] According to an OpenOCD configuration file, configuring the OpenOCD into a remote-bitbang mode; the OpenOCD configuration file includes: a remote host address, a remote host port number, and a remote-bitbang interface;

[0010] Through the TCP Socket interface and the direct programming interface DPI, the JTAG timing packet received by the JTAG DPI module is converted into a simulation test stimulus that interacts with the compilation simulator of the UVM verification platform;

[0011] The OpenOCD is started, a preset port of the OpenOCD is set as a telnet connection port, and a debugging command is sent to the device under test through the preset port.

[0012] As an optional implementation of the embodiment of the present disclosure, the importing of the JTAG DPI C function in the UVM verification platform includes:

[0013] The JTAG DPI C function is imported into the SystemVerilog of the UVM verification platform to make SystemVerilog interact with the C code.

[0014] As an optional implementation of the embodiment of the present disclosure, instantiating a JTAGDPI module in the UVM verification platform and connecting the JTAG interface to the device under test includes:

[0015] In the UVM verification platform, a proxy component is created; the proxy component is used to encapsulate JTAG related operations;

[0016] The JTAG DPI module is instantiated according to the proxy component, and the JTAG interface is connected to the device under test.

[0017] As an optional implementation of the embodiment of the present disclosure, configuring the OpenOCD to a remote-bitbang-based mode according to the OpenOCD configuration file includes:

[0018] In the OpenOCD configuration file, the interface remote_bitbang statement is used to specify the use of the remote-bitbang interface;

[0019] Set the host address of the remote JTAG device through the remote_bitbang_host parameter;

[0020] The remote_bitbang_port parameter sets the port number connected to the remote JTAG device and configures the OpenOCD to remote-bitbang based mode.

[0021] As an optional implementation of the embodiment of the present disclosure, the JTAG timing packet received by the JTAG DPI module is converted into a simulation test stimulus that interacts with the compilation simulator of the UVM verification platform through the TCP Socket interface and the direct programming interface DPI, including:

[0022] In the environment of receiving the JTAG timing packet, a TCP server is established;

[0023] In the environment corresponding to the UVM verification platform, a TCP client is built; the TCP client is used to connect to the TCP server to obtain the JTAG timing packet;

[0024] After the JTAG DPI module receives the JTAG timing packet, it parses the JTAG timing packet according to the JTAG protocol and converts the JTAG timing packet into a simulation test stimulus that interacts with the compilation simulator of the UVM verification platform.

[0025] As an optional implementation of the embodiment of the present disclosure, starting the OpenOCD, setting the preset port of the OpenOCD as the telnet connection port, and sending a debugging command to the device under test through the preset port includes:

[0026] Starting the OpenOCD, and setting the preset port as the telnet connection port in the OpenOCD configuration file;

[0027] Connect the remote host device to the OpenOCD via the telnet command;

[0028] A debugging command is sent to the device under test through the preset port.

[0029] As an optional implementation of the embodiment of the present disclosure, the debugging command includes: initializing the device under test, displaying the status of the device under test, reading data from the device under test, writing data to the device under test, setting breakpoints, and resetting the device under test.

[0030] In a second aspect, the embodiment of the present disclosure provides a joint debugging device of JTAG and OpenOCD based on a UVM platform, including:

[0031] An import module is used to import a JTAG DPI C function in a UVM verification platform; the JTAG DPI C function is used to control OpenOCD to interact with a JTAG interface of the UVM verification platform;

[0032] A connection module is used to instantiate a JTAG DPI module in the UVM verification platform and connect a JTAG interface to a device under test;

[0033] A configuration module, configured to configure the OpenOCD into a remote-bitbang mode according to an OpenOCD configuration file; the OpenOCD configuration file includes: a remote host address, a remote host port number, and a remote-bitbang interface;

[0034] A conversion module, used for converting the JTAG timing packet received by the JTAG DPI module into a simulation test stimulus that interacts with the compilation simulator of the UVM verification platform through a TCP Socket interface and a direct programming interface DPI;

[0035] The debugging module is used to start the OpenOCD, set the preset port of the OpenOCD as the telnet connection port, and send debugging commands to the device under test through the preset port.

[0036] As an optional implementation of the embodiment of the present disclosure, the import module is specifically used to:

[0037] The JTAG DPI C function is imported into the SystemVerilog of the UVM verification platform to make SystemVerilog interact with the C code.

[0038] As an optional implementation of the embodiment of the present disclosure, the connection module is specifically used for:

[0039] In the UVM verification platform, a proxy component is created; the proxy component is used to encapsulate JTAG related operations;

[0040] The JTAG DPI module is instantiated according to the proxy component, and the JTAG interface is connected to the device under test.

[0041] As an optional implementation of the embodiment of the present disclosure, the configuration module is specifically used to:

[0042] In the OpenOCD configuration file, the interface remote_bitbang statement is used to specify the use of the remote-bitbang interface;

[0043] Set the host address of the remote JTAG device through the remote_bitbang_host parameter;

[0044] The remote_bitbang_port parameter sets the port number connected to the remote JTAG device and configures the OpenOCD to remote-bitbang based mode.

[0045] As an optional implementation of the embodiment of the present disclosure, the conversion module is specifically used to:

[0046] In the environment of receiving the JTAG timing packet, a TCP server is established;

[0047] In the environment corresponding to the UVM verification platform, a TCP client is built; the TCP client is used to connect to the TCP server to obtain the JTAG timing packet;

[0048] After the JTAG DPI module receives the JTAG timing packet, it parses the JTAG timing packet according to the JTAG protocol and converts the JTAG timing packet into a simulation test stimulus that interacts with the compilation simulator of the UVM verification platform.

[0049] As an optional implementation of the embodiment of the present disclosure, the debugging module is specifically used to:

[0050] Starting the OpenOCD, and setting the preset port as the telnet connection port in the OpenOCD configuration file;

[0051] Connect the remote host device to the OpenOCD via the telnet command;

[0052] A debugging command is sent to the device under test through the preset port.

[0053] As an optional implementation of the embodiment of the present disclosure, the debugging command includes: initializing the device under test, displaying the status of the device under test, reading data from the device under test, writing data to the device under test, setting breakpoints, and resetting the device under test.

[0054] In a third aspect, an embodiment of the present disclosure provides an electronic device, comprising: a memory and a processor; the memory stores a computer program, and when the processor executes the computer program, it implements the joint debugging method of JTAG and OpenOCD based on the UVM platform as described in the first aspect or any implementation of the first aspect.

[0055] In a fourth aspect, an embodiment of the present disclosure provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the method for jointly debugging JTAG and OpenOCD based on the UVM platform as described in any implementation of the first aspect is implemented.

[0056] The technical solution provided by the embodiments of the present disclosure has the following advantages over the prior art: a JTAG DPI C function is imported into the UVM verification platform, wherein the JTAG DPI C function is used to control OpenOCD to interact with the JTAG interface of the UVM verification platform, a JTAG DPI module is instantiated in the UVM verification platform, and the JTAG interface is connected to the device under test; according to the OpenOCD configuration file, OpenOCD is configured to the remote-bitbang mode, wherein the OpenOCD configuration file includes: a remote host address, a remote host port number, and a remote-bitbang interface; through a TCP Socket interface and a direct programming interface DPI, a JTAG timing packet received by the JTAG DPI module is converted into a simulation test stimulus that interacts with a compilation simulator of the UVM verification platform, OpenOCD is started, a preset port of OpenOCD is set as a telnet connection port, and a debugging command is issued to the device under test through the preset port. Integrate OpenOCD in the UVM environment and debug through OpenOCD's JTAG interface. In the UVM verification platform, you can use OpenOCD to read or program the device under test (target hardware). Through the JTAG interface, you can directly access the registers, memory and other resources of the device under test (target hardware) to achieve hardware-level debugging functions, which is essential for verifying the correctness and stability of hardware design. OpenOCD also provides a wealth of debugging functions, such as single-step execution, breakpoint setting, etc., which can effectively locate and solve problems and greatly improve debugging efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0058] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0059] Figure 1 It is a flow chart of a joint debugging method of JTAG and OpenOCD based on a UVM platform provided by an embodiment of the present disclosure;

[0060] Figure 2 It is a schematic diagram of a joint debugging architecture of JTAG and OpenOCD based on a UVM platform provided by an embodiment of the present disclosure;

[0061] Figure 3It is a structural schematic diagram of a JTAG and OpenOCD joint debugging device based on a UVM platform provided by an embodiment of the present disclosure;

[0062] Figure 4 It is a structural schematic diagram of an electronic device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0063] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0064] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0065] Relational terms such as “first” and “second” in the description and claims of the present disclosure are merely used to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0066] In the embodiments of the present disclosure, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present disclosure should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete way. In addition, in the description of the embodiments of the present disclosure, unless otherwise specified, the meaning of "multiple" refers to two or more.

[0067] The joint debugging method of JTAG and OpenOCD based on the UVM platform provided by the embodiment of the present disclosure integrates OpenOCD in the UVM environment and debugs through the JTAG interface of OpenOCD. In the UVM verification platform, the target chip can be read or programmed through OpenOCD. That is, in the UVM verification environment, OpenOCD can be used as an interface to communicate with the target chip to implement the reading and programming operations on the chip.

[0068] In some embodiments, Figure 1 As shown, a joint debugging method of JTAG and OpenOCD based on a UVM platform is provided, comprising the following steps S11-S15:

[0069] S11. Import the JTAG DPI C function into the UVM verification platform.

[0070] The JTAG DPI C function is used to control OpenOCD to interact with the JTAG interface of the UVM verification platform.

[0071] In some embodiments, the above step S11 (importing the JTAG DPI C function in the UVM verification platform) can be implemented as follows:

[0072] The JTAG DPI C function is imported into the SystemVerilog of the UVM verification platform to make SystemVerilog interact with the C code.

[0073] Specifically, DPI can be declared as a function or task in the UVM component as an interface for the component to interact with external C or C++ code. Alternatively, UVM components communicate through ports, and DPI functions can be connected to these ports to achieve data transfer. For example, a scoreboard component may have an analysis port, which can pass data to external C code through the DPI function for further analysis and processing.

[0074] Exemplary, in the component of UVM verification platform, for example, in the proxy component or the monitor component, these DPI functions can be imported and used. In the proxy component of UVM verification platform, a DPI function can be declared to send or receive data, and this DPI function is a channel for the proxy component to interact with the external environment.

[0075] S12, instantiating a JTAG DPI module on the UVM verification platform, and connecting the JTAG interface to the device under test.

[0076] JTAG is mainly used for system simulation, debugging and internal chip testing. It is achieved by accessing the TAP (Test Access Port) packaged inside the chip. JTAG technology has three main functions: downloader, debug and boundary scan.

[0077] In some embodiments, the above step S12 (instantiating the JTAG DPI module in the UVM verification platform and connecting the JTAG interface to the device under test) can be implemented as follows:

[0078] In the UVM verification platform, a proxy component is created; the proxy component is used to encapsulate JTAG related operations;

[0079] Instantiate the JTAG DPI module according to the proxy component, and connect the JTAG interface to the device under test. Specifically, define the DPI function that interacts with JTAG in the Verilog code, these functions can be called by the SystemVerilog code, and are used to send and receive JTAG timing data. In the UVM environment of SystemVerilog, create an agent (agent) component to encapsulate JTAG related operations, which is responsible for instantiating the DPI module and interacting with the device under test, and integrates this JTAG proxy component into a complete UVM verification platform. In the top-level test platform (such as testbench) of UVM, instantiate the JTAG DPI module, and connect it to the JTAG interface. Instantiate the device under test in the top-level module of the UVM verification platform, and connect corresponding JTAG signals.

[0080] S13. According to the OpenOCD configuration file, configure the OpenOCD to a remote-bitbang mode.

[0081] The OpenOCD configuration file includes: a remote host address, a remote host port number, and a remote-bitbang interface. The remote-bitbang mode is used to connect the OpenOCD to the port number of the remote JTAG device.

[0082] In some embodiments, the above step S13 (configuring the OpenOCD to remote-bitbang mode according to the OpenOCD configuration file) can be implemented as follows:

[0083] In the OpenOCD configuration file, the interface remote_bitbang statement is used to specify the use of the remote-bitbang interface;

[0084] Set the host address of the remote JTAG device through the remote_bitbang_host parameter;

[0085] The remote_bitbang_port parameter sets the port number connected to the remote JTAG device and configures the OpenOCD to remote-bitbang based mode.

[0086] Specifically, in the OpenOCD configuration file, add the following content to configure the remote-bitbang mode, including: using the interface remote_bitbang statement to specify the use of the remote-bitbang interface, setting the host address of the remote JTAG device through the remote_bitbang_host parameter, and using the remote_bitbang_port parameter to set the port number connected to the remote JTAG device.

[0087] S14, converting the JTAG timing packet received by the JTAG DPI module into a simulation test stimulus that interacts with the compilation simulator of the UVM verification platform through a TCP Socket interface and a direct programming interface DPI.

[0088] Among them, DPI (Direct Programming Interface) is the interface for interaction between SV (abbreviation for SystemVerilog) language and other languages ​​(C / C++).

[0089] In some embodiments, the above step S14 (converting the JTAG timing packet received by the JTAG DPI module into a simulation test stimulus that interacts with the compilation simulator of the UVM verification platform through the TCP Socket interface and the direct programming interface DPI) can be implemented as follows:

[0090] In the environment of receiving the JTAG timing packet, a TCP server is established;

[0091] In the environment corresponding to the UVM verification platform, a TCP client is built; the TCP client is used to connect to the TCP server to obtain the JTAG timing packet;

[0092] After the JTAG DPI module receives the JTAG timing packet, it parses the JTAG timing packet according to the JTAG protocol and converts the JTAG timing packet into a simulation test stimulus that interacts with the compilation simulator of the UVM verification platform.

[0093] Specifically, a TCP server is built on the side that receives the JTAG timing packet and is implemented using a socket library; in the environment corresponding to the UVM verification platform, a TCP client is built to connect to the server to obtain the JTAG timing packet, and the JTAG timing packet is received based on the DPI function defined in the Verilog code and passed to the UVM verification platform; in the component of the UVM verification platform, after receiving the JTAG timing packet, the data packet is parsed according to the JTAG protocol, and the JTAG timing packet is converted into a simulation test stimulus that interacts with the compilation simulator of the UVM verification platform.

[0094] S15, starting the OpenOCD, setting the preset port of the OpenOCD as the telnet connection port, and sending a debugging command to the device under test through the preset port.

[0095] It should be noted that OpenOCD supports multiple network interfaces such as Telnet, TCL and GDB, which facilitates users to interact with OpenOCD in various ways. Therefore, you can also set the GDB connection port or TCL connection port to send debugging commands to the device under test through the GDB connection port or TCL connection port.

[0096] In some embodiments, the above step S15 (starting the OpenOCD, setting the preset port of the OpenOCD as the telnet connection port, and sending a debugging command to the device under test through the preset port) can be implemented as follows:

[0097] Starting the OpenOCD, and setting the preset port as the telnet connection port in the OpenOCD configuration file;

[0098] Connect the remote host device to the OpenOCD via the telnet command;

[0099] A debugging command is sent to the device under test through the preset port.

[0100] Optionally, the debugging command includes: initializing the device under test, displaying the status of the device under test, reading data from the device under test, writing data to the device under test, setting breakpoints, and resetting the device under test.

[0101] Specifically, specify the telnet port related settings in the OpenOCD configuration file, for example, set it to port 4444. After saving the OpenOCD configuration file, execute the OpenOCD command in the terminal. After running the command, OpenOCD will try to connect to the JTAG interface of the target device to complete the initialization. If the startup is successful, it will start to listen to the set telnet port (here is 4444). After the connection is successful, use telnet to connect and issue commands, for example, initialize the device under test, display the status of the device under test, read the register value of the device under test, write data to a specific register, start or pause the operation of the chip, set breakpoints, reset, etc.

[0102] For example, refer to Figure 2 As shown, Figure 2 This is a schematic diagram of the joint debugging architecture of JTAG and OpenOCD based on the UVM platform. Figure 2The upper layer connects to OpenOCD through telnet, and then connects to the C file through TCP SOCKET and DPI to achieve remote debugging; the lower layer builds test cases through the UVM platform and JTAG Instance, which includes multiple verification components (for example, environment components, register model components, reference model components, scoreboard components, sequence components, monitor components, sequencer components, transaction components, driver components, etc.) to verify the device under test dut. By combining remote debugging and UVM verification methods, the functional correctness of the device under test is ensured.

[0103] The present invention discloses a joint debugging method of JTAG and OpenOCD based on a UVM platform. The JTAG DPI C function is imported into the UVM verification platform, wherein the JTAG DPI C function is used to control OpenOCD to interact with the JTAG interface of the UVM verification platform, and a JTAG DPI module is instantiated in the UVM verification platform to connect the JTAG interface to a device under test; according to an OpenOCD configuration file, OpenOCD is configured to a remote-bitbang mode, wherein the OpenOCD configuration file includes: a remote host address, a remote host port number, and a remote-bitbang interface; through a TCP Socket interface and a direct programming interface DPI, a JTAG timing packet received by the JTAG DPI module is converted into a simulation test stimulus that interacts with a compilation simulator of the UVM verification platform, OpenOCD is started, a preset port of OpenOCD is set as a telnet connection port, and a debugging command is issued to the device under test through the preset port. Integrate OpenOCD in the UVM environment and debug through OpenOCD's JTAG interface. In the UVM verification platform, you can use OpenOCD to read or program the device under test (target hardware). Through the JTAG interface, you can directly access the registers, memory and other resources of the device under test (target hardware) to achieve hardware-level debugging functions, which is essential for verifying the correctness and stability of hardware design. OpenOCD also provides a wealth of debugging functions, such as single-step execution, breakpoint setting, etc., which can effectively locate and solve problems and greatly improve debugging efficiency.

[0104] In some embodiments, reference Figure 3 As shown, a joint debugging device 300 of JTAG and OpenOCD based on a UVM platform is provided, comprising:

[0105] An import module 310 is used to import a JTAG DPI C function into the UVM verification platform; the JTAG DPI C function is used to control OpenOCD to interact with the JTAG interface of the UVM verification platform;

[0106] A connection module 320 is used to instantiate a JTAG DPI module in the UVM verification platform and connect a JTAG interface to a device under test;

[0107] The configuration module 330 is used to configure the OpenOCD to a remote-bitbang mode according to an OpenOCD configuration file; the OpenOCD configuration file includes: a remote host address, a remote host port number, and a remote-bitbang interface;

[0108] The conversion module 340 is used to convert the JTAG timing packet received by the JTAG DPI module into a simulation test stimulus that interacts with the compilation simulator of the UVM verification platform through the TCP Socket interface and the direct programming interface DPI;

[0109] The debugging module 350 is used to start the OpenOCD, set the preset port of the OpenOCD as the telnet connection port, and send debugging commands to the device under test through the preset port.

[0110] As an optional implementation of the embodiment of the present disclosure, the import module is specifically used to:

[0111] The JTAG DPI C function is imported into the SystemVerilog of the UVM verification platform to make SystemVerilog interact with the C code.

[0112] As an optional implementation of the embodiment of the present disclosure, the connection module is specifically used for:

[0113] In the UVM verification platform, a proxy component is created; the proxy component is used to encapsulate JTAG related operations;

[0114] The JTAG DPI module is instantiated according to the proxy component, and the JTAG interface is connected to the device under test.

[0115] As an optional implementation of the embodiment of the present disclosure, the configuration module is specifically used to:

[0116] In the OpenOCD configuration file, the interface remote_bitbang statement is used to specify the use of the remote-bitbang interface;

[0117] Set the host address of the remote JTAG device through the remote_bitbang_host parameter;

[0118] The remote_bitbang_port parameter sets the port number connected to the remote JTAG device and configures the OpenOCD to remote-bitbang based mode.

[0119] As an optional implementation of the embodiment of the present disclosure, the conversion module is specifically used to:

[0120] In the environment of receiving the JTAG timing packet, a TCP server is established;

[0121] In the environment corresponding to the UVM verification platform, a TCP client is built; the TCP client is used to connect to the TCP server to obtain the JTAG timing packet;

[0122] After the JTAG DPI module receives the JTAG timing packet, it parses the JTAG timing packet according to the JTAG protocol and converts the JTAG timing packet into a simulation test stimulus that interacts with the compilation simulator of the UVM verification platform.

[0123] As an optional implementation of the embodiment of the present disclosure, the debugging module is specifically used to:

[0124] Starting the OpenOCD, and setting the preset port as the telnet connection port in the OpenOCD configuration file;

[0125] Connect the remote host device to the OpenOCD via the telnet command;

[0126] A debugging command is sent to the device under test through the preset port.

[0127] As an optional implementation of the embodiment of the present disclosure, the debugging command includes: initializing the device under test, displaying the status of the device under test, reading data from the device under test, writing data to the device under test, setting breakpoints, and resetting the device under test.

[0128] The present invention discloses a joint debugging device of JTAG and OpenOCD based on a UVM platform. The JTAG DPI C function is imported into the UVM verification platform, wherein the JTAG DPI C function is used to control OpenOCD to interact with the JTAG interface of the UVM verification platform, and a JTAG DPI module is instantiated in the UVM verification platform to connect the JTAG interface to a device under test; according to an OpenOCD configuration file, OpenOCD is configured to a remote-bitbang mode, wherein the OpenOCD configuration file includes: a remote host address, a remote host port number, and a remote-bitbang interface; through a TCP Socket interface and a direct programming interface DPI, a JTAG timing packet received by the JTAG DPI module is converted into a simulation test stimulus that interacts with a compilation simulator of the UVM verification platform, OpenOCD is started, a preset port of OpenOCD is set as a telnet connection port, and a debugging command is issued to the device under test through the preset port. Integrate OpenOCD in the UVM environment and debug through OpenOCD's JTAG interface. In the UVM verification platform, you can use OpenOCD to read or program the device under test (target hardware). Through the JTAG interface, you can directly access the registers, memory and other resources of the device under test (target hardware) to achieve hardware-level debugging functions, which is essential for verifying the correctness and stability of hardware design. OpenOCD also provides a wealth of debugging functions, such as single-step execution, breakpoint setting, etc., which can effectively locate and solve problems and greatly improve debugging efficiency.

[0129] The specific definition of the joint debugging device of JTAG and OpenOCD based on the UVM platform can be referred to the definition of the joint debugging method of JTAG and OpenOCD based on the UVM platform above, which will not be repeated here. Each module in the joint debugging device of JTAG and OpenOCD based on the UVM platform can be implemented in whole or in part by software, hardware and a combination thereof. Each of the above modules can be embedded in or independent of the processor of the electronic device in the form of hardware, or can be stored in the processor of the electronic device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0130] The present disclosure also provides an electronic device, Figure 4 This is a schematic diagram of the structure of an electronic device provided by an embodiment of the present disclosure. Figure 4As shown, the electronic device provided in this embodiment includes: a memory 41 and a processor 42, the memory 41 is used to store a computer program; the processor 42 is used to execute the steps executed in any embodiment of the joint debugging method of JTAG and OpenOCD based on the UVM platform of the electronic device provided by the above method embodiment when calling the computer program. The electronic device includes a processor, a memory, a communication interface, a display screen and an input device connected through a system bus. Among them, the processor of the electronic device is used to provide computing and control capabilities. The memory of the electronic device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. When the computer program is executed by the processor, a joint debugging method of JTAG and OpenOCD based on the UVM platform of an electronic device is implemented. The display screen of the electronic device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the electronic device can be a touch layer covered on the display screen, or a key, trackball or touchpad set on the housing of the computer device, or an external keyboard, touchpad or mouse.

[0131] Those skilled in the art will understand that Figure 4 The structure shown in the figure is only a block diagram of a part of the structure related to the scheme of the present disclosure, and does not constitute a limitation on the computer device to which the scheme of the present disclosure is applied. The specific electronic device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0132] In some embodiments, the JTAG and OpenOCD joint debugging device based on the UVM platform provided by the present disclosure can be implemented in the form of a computer, and the computer program can be used in a computer such as Figure 4 The computer program composed of various program modules enables the processor to execute the steps of the JTAG and OpenOCD joint debugging method based on the UVM platform of various embodiments of the present disclosure described in this specification.

[0133] The embodiment of the present disclosure also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the UVM platform-based JTAG and OpenOCD joint debugging method for an electronic device provided in the above method embodiment is implemented.

[0134] Those skilled in the art will appreciate that the embodiments of the present disclosure may be provided as methods, systems, or computer program products. Therefore, the present disclosure may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present disclosure may take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program code.

[0135] The processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0136] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0137] Computer readable media include permanent and non-permanent, removable and non-removable storage media. Storage media can be implemented by any method or technology to store information, and the information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0138] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0139] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A joint debugging method of JTAG and OpenOCD based on UVM platform, characterized in that: The method comprises: Importing a JTAG DPI C function in the UVM verification platform; the JTAG DPI C function is used to control OpenOCD to interact with the JTAG interface of the UVM verification platform; Instantiate the JTAG DPI module in the UVM verification platform and connect the JTAG interface to the device under test; According to an OpenOCD configuration file, configuring the OpenOCD into a remote-bitbang mode; the OpenOCD configuration file includes: a remote host address, a remote host port number, and a remote-bitbang interface; Through the TCP Socket interface and the direct programming interface DPI, the JTAG timing packet received by the JTAG DPI module is converted into a simulation test stimulus that interacts with the compilation simulator of the UVM verification platform; The OpenOCD is started, a preset port of the OpenOCD is set as a telnet connection port, and a debugging command is sent to the device under test through the preset port.

2. The method according to claim 1, characterized in that The JTAG DPI C function is imported into the UVM verification platform, including: The JTAG DPI C function is imported into the SystemVerilog of the UVM verification platform to make SystemVerilog interact with the C code.

3. The method according to claim 1, characterized in that: Instantiating the JTAG DPI module in the UVM verification platform and connecting the JTAG interface to the device under test includes: In the UVM verification platform, a proxy component is created; the proxy component is used to encapsulate JTAG related operations; The JTAG DPI module is instantiated according to the proxy component, and the JTAG interface is connected to the device under test.

4. The method according to claim 1, characterized in that: Configuring the OpenOCD to a remote-bitbang-based mode according to the OpenOCD configuration file includes: In the OpenOCD configuration file, the interface remote_bitbang statement is used to specify the use of the remote-bitbang interface; Set the host address of the remote JTAG device through the remote_bitbang_host parameter; The remote_bitbang_port parameter sets the port number connected to the remote JTAG device and configures the OpenOCD to remote-bitbang based mode.

5. The method according to claim 1, characterized in that The method of converting the JTAG timing packet received by the JTAG DPI module into a simulation test stimulus that interacts with the compilation simulator of the UVM verification platform through the TCP Socket interface and the direct programming interface DPI includes: In the environment of receiving the JTAG timing packet, a TCP server is established; In the environment corresponding to the UVM verification platform, a TCP client is built; the TCP client is used to connect to the TCP server to obtain the JTAG timing packet; After the JTAG DPI module receives the JTAG timing packet, it parses the JTAG timing packet according to the JTAG protocol and converts the JTAG timing packet into a simulation test stimulus that interacts with the compilation simulator of the UVM verification platform.

6. The method according to claim 4, characterized in that The starting of the OpenOCD, setting the preset port of the OpenOCD as the telnet connection port, and sending a debugging command to the device under test through the preset port, includes: Starting the OpenOCD, and setting the preset port as the telnet connection port in the OpenOCD configuration file; Connect the remote host device to the OpenOCD via the telnet command; A debugging command is sent to the device under test through the preset port.

7. The method according to claim 1, characterized in that The debugging command includes: initializing the device under test, displaying the state of the device under test, reading data from the device under test, writing data to the device under test, setting breakpoints, and resetting the device under test.

8. A joint debugging device of JTAG and OpenOCD based on UVM platform, characterized in that: include: An import module is used to import a JTAG DPI C function in a UVM verification platform; the JTAG DPI C function is used to control OpenOCD to interact with a JTAG interface of the UVM verification platform; A connection module is used to instantiate a JTAG DPI module in the UVM verification platform and connect a JTAG interface to a device under test; A configuration module, configured to configure the OpenOCD into a remote-bitbang mode according to an OpenOCD configuration file; the OpenOCD configuration file includes: a remote host address, a remote host port number, and a remote-bitbang interface; A conversion module, used for converting the JTAG timing packet received by the JTAG DPI module into a simulation test stimulus that interacts with the compilation simulator of the UVM verification platform through a TCP Socket interface and a direct programming interface DPI; The debugging module is used to start the OpenOCD, set the preset port of the OpenOCD as the telnet connection port, and send debugging commands to the device under test through the preset port.

9. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the JTAG and OpenOCD joint debugging method based on the UVM platform according to any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and when the computer program is executed by a processor, the combined debugging method of JTAG and OpenOCD based on the UVM platform described in any one of claims 1 to 7 is implemented.

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