Joint debugging method and device for JTAG and OpenOCD based on UVM platform

Abstract

This disclosure relates to a joint debugging method and apparatus for JTAG and OpenOCD based on the UVM platform. The method includes: importing a JTAG DPI C function into the UVM verification platform; the JTAG DPI C function is used to control the interaction between OpenOCD and the JTAG interface of the UVM verification platform; instantiating a JTAG DPI module on the UVM verification platform and connecting the JTAG interface to the device under test; configuring the OpenOCD in remote-bitbang mode according to the OpenOCD configuration file; the OpenOCD configuration file includes: remote host address, remote host port number, and remote-bitbang interface; converting the JTAG timing packets received by the JTAG DPI module into simulation test stimuli for interaction with the compiler simulator of the UVM verification platform through the TCP Socket interface and the Direct Programming Interface (DPI); starting the OpenOCD, setting the preset port of the OpenOCD to the telnet connection port, and sending debugging commands to the device under test through the preset port.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit digital chip verification technology, and in particular to a joint debugging method and apparatus based on the UVM platform using JTAG and OpenOCD. Background Technology

[0002] With the rapid development of digital integrated circuits, chip functions are becoming increasingly complex, and chip verification plays an important role in the chip design cycle.

[0003] In related technologies, debugging and verification are performed by connecting a debugger through the hardware interface of a development board. This method requires the purchase of hardware equipment, which increases the verification cost. Selecting and debugging the development board also increases the time cost. Furthermore, it does not allow direct access to the internal logic during debugging, resulting in a long debugging cycle.

[0004] Therefore, improving debugging efficiency and effectively locating and resolving problems on the UVM platform is an urgent issue that needs to be addressed. Summary of the Invention

[0005] To address the aforementioned technical issues, this disclosure provides a joint debugging method and apparatus for JTAG and OpenOCD based on the UVM platform.

[0006] Firstly, this disclosure provides a joint debugging method for JTAG and OpenOCD based on the UVM platform, including:

[0007] Import the JTAG DPI C function into the UVM verification platform; the JTAG DPI C function is used to control the interaction between OpenOCD and the JTAG interface of the UVM verification platform.

[0008] Instantiate the JTAG DPI module on the UVM verification platform and connect the JTAG interface to the device under test;

[0009] According to the OpenOCD configuration file, the OpenOCD is configured to remote-bitbang mode; the OpenOCD configuration file includes: remote host address, remote host port number, and remote-bitbang interface;

[0010] The JTAG timing packets received by the JTAG DPI module are converted into simulation test stimuli for interaction with the compiler simulator of the UVM verification platform through the TCP Socket interface and the Direct Programming Interface (DPI).

[0011] Start the OpenOCD, set the default port of the OpenOCD to the telnet connection port, and send debugging commands to the device under test through the default port.

[0012] As an optional implementation of this disclosure, importing the JTAG DPI C function into the UVM verification platform includes:

[0013] Import the JTAG DPI C function into the SystemVerilog of the UVM verification platform to enable SystemVerilog to interact with C code.

[0014] As an optional implementation of this disclosure, the step of instantiating the JTAG GDPI module on the UVM verification platform and connecting the JTAG interface to the device under test includes:

[0015] In the UVM verification platform, a proxy component is created; the proxy component is used to encapsulate JTAG-related operations.

[0016] The JTAG DPI module is instantiated based on the proxy component, and the JTAG interface is connected to the device under test.

[0017] As an optional implementation of this disclosure, configuring the OpenOCD to a remote-bitbang-based mode according to the OpenOCD configuration file includes:

[0018] In the OpenOCD configuration file, the remote-bitbang interface is specified to be used via the interface remote_bitbang statement;

[0019] Set the host address of the remote JTAG device using the remote_bitbang_host parameter;

[0020] By setting the port number to connect to the remote JTAG device using the remote_bitbang_port parameter, the OpenOCD is configured in remote-bitbang-based mode.

[0021] As an optional implementation of this disclosure, the step of converting the JTAG timing packets received by the JTAG DPI module into simulation test stimuli for interaction with the compiler simulator of the UVM verification platform via the TCP Socket interface and the Direct Programming Interface (DPI) includes:

[0022] In the environment where the JTAG time packets are received, a TCP server is set up;

[0023] In the environment corresponding to the UVM verification platform, a TCP client is set up; the TCP client is used to connect to the TCP server to obtain the JTAG timing packets.

[0024] After receiving the JTAG timing packet, the JTAG DPI module parses the JTAG timing packet according to the JTAG protocol and converts the JTAG timing packet into a simulation test stimulus for interaction with the compiler simulator of the UVM verification platform.

[0025] As an optional implementation of this disclosure, the step of starting the OpenOCD, setting the preset port of the OpenOCD to the telnet connection port, and sending debugging commands to the device under test through the preset port includes:

[0026] Start the OpenOCD and set the preset port to the telnet connection port in the OpenOCD configuration file;

[0027] Connect a remote host device to the OpenOCD using the telnet command;

[0028] Debugging commands are sent to the device under test through the preset port.

[0029] As an optional implementation of this disclosure, the debugging commands include: initializing the device under test, displaying the status of the device under test, reading data from the device under test, writing data to the device under test, setting breakpoints, and resetting the device under test.

[0030] Secondly, embodiments of this disclosure provide a joint debugging device for JTAG and OpenOCD based on the UVM platform, comprising:

[0031] An import module is used to import JTAG DPI C functions into the UVM verification platform; the JTAG DPI C functions are used to control the interaction between OpenOCD and the JTAG interface of the UVM verification platform.

[0032] The connection module is used to instantiate the JTAG DPI module on the UVM verification platform and connect the JTAG interface to the device under test.

[0033] The configuration module is used to configure the OpenOCD in remote-bitbang mode according to the OpenOCD configuration file; the OpenOCD configuration file includes: remote host address, remote host port number and remote-bitbang interface;

[0034] The conversion module is used to convert the JTAG timing packets received by the JTAG DPI module into simulation test stimuli for interaction with the compiler simulator of the UVM verification platform through the TCP Socket interface and the Direct Programming Interface (DPI).

[0035] The debugging module is used to start the OpenOCD, set the default port of the OpenOCD to the telnet connection port, and send debugging commands to the device under test through the default port.

[0036] As an optional implementation of this disclosure, the import module is specifically used for:

[0037] Import the JTAG DPI C function into the SystemVerilog of the UVM verification platform to enable SystemVerilog to interact with C code.

[0038] As an optional implementation of this disclosure, the connection module is specifically used for:

[0039] In the UVM verification platform, a proxy component is created; the proxy component is used to encapsulate JTAG-related operations.

[0040] The JTAG DPI module is instantiated based on the proxy component, and the JTAG interface is connected to the device under test.

[0041] As an optional implementation of this disclosure, the configuration module is specifically used for:

[0042] In the OpenOCD configuration file, the remote-bitbang interface is specified to be used via the interface remote_bitbang statement;

[0043] Set the host address of the remote JTAG device using the remote_bitbang_host parameter;

[0044] By setting the port number to connect to the remote JTAG device using the remote_bitbang_port parameter, the OpenOCD is configured in remote-bitbang-based mode.

[0045] As an optional implementation of this disclosure, the conversion module is specifically used for:

[0046] In the environment where the JTAG time packets are received, a TCP server is set up;

[0047] In the environment corresponding to the UVM verification platform, a TCP client is set up; the TCP client is used to connect to the TCP server to obtain the JTAG timing packets.

[0048] After receiving the JTAG timing packet, the JTAG DPI module parses the JTAG timing packet according to the JTAG protocol and converts the JTAG timing packet into a simulation test stimulus for interaction with the compiler simulator of the UVM verification platform.

[0049] As an optional implementation of this disclosure, the debugging module is specifically used for:

[0050] Start the OpenOCD and set the preset port to the telnet connection port in the OpenOCD configuration file;

[0051] Connect a remote host device to the OpenOCD using the telnet command;

[0052] Debugging commands are sent to the device under test through the preset port.

[0053] As an optional implementation of this disclosure, the debugging commands include: initializing the device under test, displaying the status of the device under test, reading data from the device under test, writing data to the device under test, setting breakpoints, and resetting the device under test.

[0054] Thirdly, embodiments of this disclosure provide an electronic device, including: a memory and a processor; the memory stores a computer program, and the processor executes the computer program to implement the joint debugging method of JTAG and OpenOCD based on the UVM platform as described in the first aspect or any embodiment of the first aspect.

[0055] Fourthly, embodiments of this disclosure provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the joint debugging method of JTAG and OpenOCD based on the UVM platform as described in any embodiment of the first aspect.

[0056] The technical solution provided in this disclosure has the following advantages compared with the prior art: A JTAG DPI C function is imported into the UVM verification platform. This function controls the interaction between OpenOCD and the JTAG interface of the UVM verification platform. A JTAG DPI module is instantiated on the UVM verification platform, and the JTAG interface is connected to the device under test. According to the OpenOCD configuration file, OpenOCD is configured in remote-bitbang mode. The OpenOCD configuration file includes the remote host address, remote host port number, and remote-bitbang interface. Through the TCP Socket interface and the Direct Programming Interface (DPI), the JTAG timing packets received by the JTAG DPI module are converted into simulation test stimuli for interaction with the compiler simulator of the UVM verification platform. OpenOCD is started, and its default port is set to the telnet connection port. Debug commands are then sent to the device under test through the default port. Integrating OpenOCD into the UVM environment and using its JTAG interface for debugging allows the UVM verification platform to read from or program the device under test (DUT, target hardware). The JTAG interface provides direct access to the DUT's registers, memory, and other resources, enabling hardware-level debugging. This is crucial for verifying the correctness and stability of hardware designs. Furthermore, OpenOCD offers rich debugging features such as single-step execution and breakpoint setting, efficiently locating and resolving problems, significantly improving debugging efficiency. Attached Figure Description

[0057] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0058] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0059] Figure 1 This is a flowchart illustrating a joint debugging method of JTAG and OpenOCD based on the UVM platform provided in this embodiment of the disclosure;

[0060] Figure 2 This is a schematic diagram of a joint debugging architecture for JTAG and OpenOCD based on the UVM platform provided in this embodiment of the disclosure;

[0061] Figure 3This is a schematic diagram of the structure of a joint debugging device for JTAG and OpenOCD based on the UVM platform provided in an embodiment of this disclosure;

[0062] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0063] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0064] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0065] The terms "first" and "second" and other relational terms used in this disclosure and claims are merely used to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0066] In this disclosure, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design described as "exemplary" or "for example" in this disclosure should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner. Furthermore, in the description of the embodiments in this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0067] The joint debugging method of JTAG and OpenOCD based on the UVM platform provided in this disclosure integrates OpenOCD in the UVM environment and performs debugging through the JTAG interface of OpenOCD. In the UVM verification platform, the target chip can be read or programmed through OpenOCD. That is, in the UVM verification environment, OpenOCD can serve as an interface for communicating with the target chip to realize chip reading and programming operations.

[0068] In some embodiments, such as Figure 1 As shown, a joint debugging method for JTAG and OpenOCD based on the UVM platform is provided, including the following steps S11-S15:

[0069] S11. Import the JTAG DPI C function into the UVM verification platform.

[0070] The JTAG DPI C function is used to control the interaction between OpenOCD and the JTAG interface of the UVM verification platform.

[0071] In some embodiments, step S11 (importing the JTAG DPI C function into the UVM verification platform) can be implemented in the following way:

[0072] Import the JTAG DPI C function into the SystemVerilog of the UVM verification platform to enable SystemVerilog to interact with C code.

[0073] Specifically, DPI can be declared as a function or task within a UVM component, serving as an interface for interaction between the component and external C or C++ code. Alternatively, UVM components communicate via ports, and DPI functions can connect to these ports to transfer data. For example, a scoreboard component might have an analysis port, which can pass data via DPI functions to external C code for further analysis and processing.

[0074] For example, these DPI functions can be imported and used in components of the UVM verification platform, such as the agent component or the monitor component. In the agent component of the UVM verification platform, a DPI function can be declared to send or receive data; this DPI function serves as a channel for the agent component to interact with the external environment.

[0075] S12. Instantiate the JTAG DPI module on the UVM verification platform and connect the JTAG interface to the device under test.

[0076] JTAG is primarily used for system simulation, debugging, and internal chip testing. It achieves this by accessing the internally packaged test circuitry (TAP). JTAG technology has three main functions: programmer, debug, and boundary scan.

[0077] In some embodiments, step S12 (instantiating the JTAG DPI module on the UVM verification platform and connecting the JTAG interface to the device under test) can be implemented in the following way:

[0078] In the UVM verification platform, a proxy component is created; the proxy component is used to encapsulate JTAG-related operations.

[0079] The JTAG DPI module is instantiated using the agent component, and the JTAG interface is connected to the device under test (DUT). Specifically, DPI functions for JTAG interaction are defined in the Verilog code. These functions are called by the SystemVerilog code to send and receive JTAG timing data. In the SystemVerilog UVM environment, an agent component is created to encapsulate JTAG-related operations. This agent is responsible for instantiating the DPI module and interacting with the DUT. This JTAG agent component is integrated into the complete UVM verification platform. In the top-level test platform of UVM (e.g., testbench), the JTAG DPI module is instantiated and connected to the JTAG interface. The DUT is instantiated in the top-level module of the UVM verification platform, and the corresponding JTAG signals are connected.

[0080] S13. Configure the OpenOCD to remote-bitbang mode according to the OpenOCD configuration file.

[0081] The OpenOCD configuration file includes: the remote host address, the remote host port number, and the remote-bitbang interface. The remote-bitbang mode is used to connect the OpenOCD to the port number of the remote JTAG device.

[0082] In some embodiments, step S13 (configuring the OpenOCD to remote-bitbang mode according to the OpenOCD configuration file) can be implemented as follows:

[0083] In the OpenOCD configuration file, the remote-bitbang interface is specified to be used via the interface remote_bitbang statement;

[0084] Set the host address of the remote JTAG device using the remote_bitbang_host parameter;

[0085] By setting the port number to connect to the remote JTAG device using the remote_bitbang_port parameter, the OpenOCD is configured in remote-bitbang-based mode.

[0086] Specifically, in the OpenOCD configuration file, add the following to configure remote-bitbang mode: specify the use of the remote-bitbang interface using the `interface remote_bitbang` statement; set the host address of the remote JTAG device using the `remote_bitbang_host` parameter; and set the port number for connecting to the remote JTAG device using the `remote_bitbang_port` parameter.

[0087] S14. The JTAG timing packets received by the JTAG DPI module are converted into simulation test stimuli for interaction with the compiler simulator of the UVM verification platform through the TCP Socket interface and the Direct Programming Interface (DPI).

[0088] DPI (Direct Programming Interface) is the interface between the SV (SystemVerilog) language and other languages ​​(C / C++).

[0089] In some embodiments, step S14 (converting the JTAG timing packets received by the JTAG DPI module into simulation test stimuli for interaction with the compiler simulator of the UVM verification platform via the TCP Socket interface and the Direct Programming Interface (DPI)) can be implemented in the following manner:

[0090] In the environment where the JTAG time packets are received, a TCP server is set up;

[0091] In the environment corresponding to the UVM verification platform, a TCP client is set up; the TCP client is used to connect to the TCP server to obtain the JTAG timing packets.

[0092] After receiving the JTAG timing packet, the JTAG DPI module parses the JTAG timing packet according to the JTAG protocol and converts the JTAG timing packet into a simulation test stimulus for interaction with the compiler simulator of the UVM verification platform.

[0093] Specifically, a TCP server is set up on the side receiving JTAG timing packets, implemented using a socket library; in the environment corresponding to the UVM verification platform, a TCP client is set up to connect to the server to obtain JTAG timing packets. The client receives JTAG timing packets based on the DPI function defined in the Verilog code and passes them to the UVM verification platform; in the components of the UVM verification platform, after receiving the JTAG timing packets, the data packets are parsed according to the JTAG protocol, and the JTAG timing packets are converted into simulation test stimuli for interaction with the compiler simulator of the UVM verification platform.

[0094] S15. Start the OpenOCD, set the default port of the OpenOCD to the telnet connection port, and send debugging commands to the device under test through the default port.

[0095] It should be noted that OpenOCD supports multiple network interfaces such as Telnet, TCL, and GDB, allowing users to interact with OpenOCD in various ways. Therefore, by configuring the GDB or TCL connection port, debugging commands can be sent to the device under test via either the GDB or TCL connection port.

[0096] In some embodiments, step S15 (starting the OpenOCD, setting the default port of the OpenOCD to the telnet connection port, and sending debugging commands to the device under test through the default port) can be implemented in the following way:

[0097] Start the OpenOCD and set the preset port to the telnet connection port in the OpenOCD configuration file;

[0098] Connect a remote host device to the OpenOCD using the telnet command;

[0099] Debugging commands are sent to the device under test through the preset port.

[0100] Optionally, the debugging commands include: initializing the device under test, displaying the status of the device under test, reading data from the device under test, writing data to the device under test, setting breakpoints, and resetting the device under test.

[0101] Specifically, specify the telnet port settings in the OpenOCD configuration file, for example, set it to port 4444. After saving the OpenOCD configuration file, execute the OpenOCD command in the terminal. After running the command, OpenOCD will attempt to connect to the target device's JTAG interface and complete initialization. If startup is successful, it will start listening on the configured telnet port (here, 4444). After a successful connection, use telnet to connect and issue commands, such as initializing the device under test (DUT), displaying the DUT's status, reading the DUT's register values, writing data to a specific register, starting or pausing the chip's operation, setting breakpoints, resetting, etc.

[0102] For example, refer to Figure 2 As shown, Figure 2 This is a schematic diagram of a joint debugging architecture for JTAG and OpenOCD based on the UVM platform. Figure 2The upper layer connects to OpenOCD via telnet, and then connects to the C file via TCP socket and DPI to achieve remote debugging. The lower layer builds test cases through the UVM platform and JTAG Instance, including multiple verification components (e.g., environment component, register model component, reference model component, scoreboard component, sequence component, monitor component, sequencer component, transaction component, driver component, etc.) for verifying the device under test (DUT). By combining remote debugging and UVM verification methods, the functional correctness of the DUT is ensured.

[0103] This disclosure provides a joint debugging method for JTAG and OpenOCD based on the UVM platform. The method involves importing the JTAG DPI C function into the UVM verification platform. This function controls the interaction between OpenOCD and the UVM verification platform's JTAG interface. A JTAG DPI module is instantiated on the UVM verification platform, and the JTAG interface is connected to the device under test (DUT). Based on the OpenOCD configuration file, OpenOCD is configured in remote-bitbang mode. The OpenOCD configuration file includes the remote host address, remote host port number, and remote-bitbang interface. Through the TCP Socket interface and the Direct Programming Interface (DPI), the JTAG timing packets received by the JTAG DPI module are converted into simulation test stimuli for interaction with the UVM verification platform's compiler simulator. OpenOCD is then started, and its default port is set to the telnet connection port. Debug commands are then sent to the DUT through this default port. Integrating OpenOCD into the UVM environment and using its JTAG interface for debugging allows the UVM verification platform to read from or program the device under test (DUT, target hardware). The JTAG interface provides direct access to the DUT's registers, memory, and other resources, enabling hardware-level debugging. This is crucial for verifying the correctness and stability of hardware designs. Furthermore, OpenOCD offers rich debugging features such as single-step execution and breakpoint setting, efficiently locating and resolving problems, significantly improving debugging efficiency.

[0104] In some embodiments, refer to Figure 3 As shown, a joint debugging device 300 for JTAG and OpenOCD based on the UVM platform is provided, comprising:

[0105] Import module 310 is used to import JTAG DPI C function into the UVM verification platform; the JTAG DPI C function is used to control the interaction between OpenOCD and the JTAG interface of the UVM verification platform.

[0106] The connection module 320 is used to instantiate the JTAG DPI module on the UVM verification platform and connect the JTAG interface to the device under test.

[0107] Configuration module 330 is used to configure the OpenOCD in remote-bitbang mode according to the OpenOCD configuration file; the OpenOCD configuration file includes: remote host address, remote host port number and remote-bitbang interface;

[0108] The conversion module 340 is used to convert the JTAG timing packets received by the JTAG DPI module into simulation test stimuli for interaction with the compiler simulator of the UVM verification platform through the TCP Socket interface and the Direct Programming Interface (DPI).

[0109] The debugging module 350 is used to start the OpenOCD, set the default port of the OpenOCD to the telnet connection port, and send debugging commands to the device under test through the default port.

[0110] As an optional implementation of this disclosure, the import module is specifically used for:

[0111] Import the JTAG DPI C function into the SystemVerilog of the UVM verification platform to enable SystemVerilog to interact with C code.

[0112] As an optional implementation of this disclosure, the connection module is specifically used for:

[0113] In the UVM verification platform, a proxy component is created; the proxy component is used to encapsulate JTAG-related operations.

[0114] The JTAG DPI module is instantiated based on the proxy component, and the JTAG interface is connected to the device under test.

[0115] As an optional implementation of this disclosure, the configuration module is specifically used for:

[0116] In the OpenOCD configuration file, the remote-bitbang interface is specified to be used via the interface remote_bitbang statement;

[0117] Set the host address of the remote JTAG device using the remote_bitbang_host parameter;

[0118] By setting the port number to connect to the remote JTAG device using the remote_bitbang_port parameter, the OpenOCD is configured in remote-bitbang-based mode.

[0119] As an optional implementation of this disclosure, the conversion module is specifically used for:

[0120] In the environment where the JTAG time packets are received, a TCP server is set up;

[0121] In the environment corresponding to the UVM verification platform, a TCP client is set up; the TCP client is used to connect to the TCP server to obtain the JTAG timing packets.

[0122] After receiving the JTAG timing packet, the JTAG DPI module parses the JTAG timing packet according to the JTAG protocol and converts the JTAG timing packet into a simulation test stimulus for interaction with the compiler simulator of the UVM verification platform.

[0123] As an optional implementation of this disclosure, the debugging module is specifically used for:

[0124] Start the OpenOCD and set the preset port to the telnet connection port in the OpenOCD configuration file;

[0125] Connect a remote host device to the OpenOCD using the telnet command;

[0126] Debugging commands are sent to the device under test through the preset port.

[0127] As an optional implementation of this disclosure, the debugging commands include: initializing the device under test, displaying the status of the device under test, reading data from the device under test, writing data to the device under test, setting breakpoints, and resetting the device under test.

[0128] The joint debugging device for JTAG and OpenOCD based on the UVM platform disclosed herein imports the JTAG DPI C function into the UVM verification platform. The JTAG DPI C function controls the interaction between OpenOCD and the JTAG interface of the UVM verification platform. The JTAG DPI module is instantiated on the UVM verification platform, and the JTAG interface is connected to the device under test (DUT). According to the OpenOCD configuration file, OpenOCD is configured in remote-bitbang mode. The OpenOCD configuration file includes the remote host address, remote host port number, and remote-bitbang interface. Through the TCP Socket interface and the Direct Programming Interface (DPI), the JTAG timing packets received by the JTAG DPI module are converted into simulation test stimuli for interaction with the compiler simulator of the UVM verification platform. OpenOCD is started, and its default port is set to the telnet connection port. Debug commands are then sent to the DUT through the default port. Integrating OpenOCD into the UVM environment and using its JTAG interface for debugging allows the UVM verification platform to read from or program the device under test (DUT, target hardware). The JTAG interface provides direct access to the DUT's registers, memory, and other resources, enabling hardware-level debugging. This is crucial for verifying the correctness and stability of hardware designs. Furthermore, OpenOCD offers rich debugging features such as single-step execution and breakpoint setting, efficiently locating and resolving problems, significantly improving debugging efficiency.

[0129] Specific limitations regarding the joint debugging device for JTAG and OpenOCD based on the UVM platform can be found in the above description of the joint debugging method for JTAG and OpenOCD based on the UVM platform, and will not be repeated here. Each module in the aforementioned joint debugging device for JTAG and OpenOCD based on the UVM platform can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independent of the processor of the electronic device, or stored in software within the processor of the electronic device, so that the processor can call and execute the corresponding operations of each module.

[0130] This disclosure also provides an electronic device. Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. Figure 4As shown, the electronic device provided in this embodiment includes a memory 41 and a processor 42. The memory 41 is used to store computer programs; the processor 42 is used to execute the steps performed in any embodiment of the joint debugging method of JTAG and OpenOCD based on the UVM platform for the electronic device provided in the above method embodiments when the computer program is invoked. The electronic device includes a processor, a memory, a communication interface, a display screen, and an input device connected via a system bus. The processor of the electronic device provides computing and control capabilities. The memory of the electronic device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. When the computer program is executed by the processor, it implements a joint debugging method of JTAG and OpenOCD based on the UVM platform for an electronic device. The display screen of the electronic device can be a liquid crystal display screen or an electronic ink display screen. The input device of the electronic device can be a touch layer covering the display screen, or a button, trackball, or touchpad set on the casing of a computer device, or an external keyboard, touchpad, or mouse, etc.

[0131] Those skilled in the art will understand that Figure 4 The structure shown is merely a block diagram of a portion of the structure related to the present disclosure and does not constitute a limitation on the computer device to which the present disclosure is applied. Specific electronic devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0132] In some embodiments, the joint debugging apparatus for JTAG and OpenOCD based on the UVM platform provided in this disclosure can be implemented as a computer, and the computer program can be implemented in, for example, Figure 4 The computer program, comprised of various program modules, causes the processor to execute the steps in the joint debugging method of JTAG and OpenOCD based on the UVM platform described in the various embodiments of this disclosure.

[0133] This disclosure also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the joint debugging method of JTAG and OpenOCD based on the UVM platform for the electronic device provided in the above method embodiments.

[0134] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, systems, or computer program products. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product embodied on one or more computer-usable storage media containing computer-usable program code.

[0135] The processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.

[0136] Memory may include non-persistent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, like read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0137] Computer-readable media include both permanent and non-permanent, removable and non-removable storage media. Storage media can store information using any method or technology; the information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media do not include transient computer-readable media, such as modulated data signals and carrier waves.

[0138] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0139] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A joint debugging method for JTAG and OpenOCD based on the UVM platform, characterized in that, The method includes: Import the JTAG DPI C function into the UVM verification platform; the JTAG DPI C function is used to control the interaction between OpenOCD and the JTAG interface of the UVM verification platform. Instantiate the JTAG DPI module on the UVM verification platform and connect the JTAG interface to the device under test; According to the OpenOCD configuration file, the OpenOCD is configured to remote-bitbang mode; the OpenOCD configuration file includes: remote host address, remote host port number, and remote-bitbang interface; The JTAG timing packets received by the JTAG DPI module are converted into simulation test stimuli for interaction with the compiler simulator of the UVM verification platform through the TCP Socket interface and the Direct Programming Interface (DPI). Start the OpenOCD, set the default port of the OpenOCD to the telnet connection port, and send debugging commands to the device under test through the default port.

2. The method according to claim 1, characterized in that, The importation of JTAG DPI C functions into the UVM verification platform includes: Import the JTAG DPI C function into the SystemVerilog of the UVM verification platform to enable SystemVerilog to interact with C code.

3. The method according to claim 1, characterized in that, The step of instantiating the JTAG DPI module on the UVM verification platform and connecting the JTAG interface to the device under test includes: In the UVM verification platform, a proxy component is created; the proxy component is used to encapsulate JTAG-related operations. The JTAG DPI module is instantiated based on the proxy component, and the JTAG interface is connected to the device under test.

4. The method according to claim 1, characterized in that, The step of configuring OpenOCD to a remote-bitbang-based mode according to the OpenOCD configuration file includes: In the OpenOCD configuration file, the remote-bitbang interface is specified to be used via the interface remote_bitbang statement; Set the host address of the remote JTAG device using the remote_bitbang_host parameter; By setting the port number to connect to the remote JTAG device using the remote_bitbang_port parameter, the OpenOCD is configured in remote-bitbang-based mode.

5. The method according to claim 1, characterized in that, The process of converting the JTAG timing packets received by the JTAG DPI module into simulation test stimuli for interaction with the compiler simulator of the UVM verification platform via the TCP Socket interface and the Direct Programming Interface (DPI) includes: In the environment where the JTAG time packets are received, a TCP server is set up; In the environment corresponding to the UVM verification platform, a TCP client is set up; the TCP client is used to connect to the TCP server to obtain the JTAG timing packets. After receiving the JTAG timing packet, the JTAG DPI module parses the JTAG timing packet according to the JTAG protocol and converts the JTAG timing packet into a simulation test stimulus for interaction with the compiler simulator of the UVM verification platform.

6. The method according to claim 4, characterized in that, The steps include starting the OpenOCD, setting the OpenOCD's default port to the telnet connection port, and sending debug commands to the device under test through the default port, including: Start the OpenOCD and set the preset port to the telnet connection port in the OpenOCD configuration file; Connect a remote host device to the OpenOCD using the telnet command; Debugging commands are sent to the device under test through the preset port.

7. The method according to claim 1, characterized in that, The debugging commands include: initializing the device under test, displaying the status of the device under test, reading data from the device under test, writing data to the device under test, setting breakpoints, and resetting the device under test.

8. A joint debugging device for JTAG and OpenOCD based on the UVM platform, characterized in that, include: An import module is used to import JTAG DPI C functions into the UVM verification platform; the JTAG DPI C functions are used to control the interaction between OpenOCD and the JTAG interface of the UVM verification platform. The connection module is used to instantiate the JTAG DPI module on the UVM verification platform and connect the JTAG interface to the device under test. The configuration module is used to configure the OpenOCD in remote-bitbang mode according to the OpenOCD configuration file; the OpenOCD configuration file includes: remote host address, remote host port number and remote-bitbang interface; The conversion module is used to convert the JTAG timing packets received by the JTAG DPI module into simulation test stimuli for interaction with the compiler simulator of the UVM verification platform through the TCP Socket interface and the Direct Programming Interface (DPI). The debugging module is used to start the OpenOCD, set the default port of the OpenOCD to the telnet connection port, and send debugging commands to the device under test through the default port.

9. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the joint debugging method of JTAG and OpenOCD based on the UVM platform as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, It stores a computer program, which, when executed by a processor, implements the joint debugging method of JTAG and OpenOCD based on the UVM platform as described in any one of claims 1 to 7.

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