Multi-laminated mainboard function test strategy method based on reliability analysis

Abstract

The invention relates to a multi-laminated mainboard function test strategy method based on reliability analysis, and belongs to the technical field of electric digital data processing, and the method comprises the following steps: 1, constructing a function parameter model of a multi-laminated mainboard; 2, constructing a reliability model of the multi-laminated mainboard; step 3, according to the reliability model, determining key test nodes of each layer of mainboard of the multi-laminated mainboard; 4, testing each layer of main board of the multi-laminated main board according to the key test nodes, and recording test data of each layer of main board; 5, analyzing the test data of each layer of mainboard, comparing and analyzing the test data of each layer of mainboard according to the reliability model, and judging whether the multi-laminated mainboard meets the reliability requirement or not; the method has the beneficial effects that if the reliability of each layer of main board is the same or different, the total reliability of the multi-laminated main board can be calculated, and if one of the reliability of each layer of main board does not have the reliability, the total reliability of the multi-laminated main board does not have the reliability.

Description

Technical Field

[0001] The invention belongs to the technical field of electrical digital data processing, and in particular relates to a multi-layer motherboard function test strategy method based on reliability analysis. Background Art

[0002] Multi-layer motherboards often have multiple functions, including high-speed data transmission and multi-channel communication. When writing test programs for multi-layer motherboards, it is difficult to test all functions of the multi-layer motherboard, and it is easy to miss some special function tests of the multi-layer motherboard, resulting in potential problems in the multi-layer motherboard not being discovered in time.

[0003] Generally, when testing some special performances of multi-layer motherboards, it is necessary to rely on specific algorithms for data processing and analysis. If the specific algorithm itself is defective or inaccurate, it may misjudge the functional status of the multi-layer motherboard, judge a normal multi-layer motherboard as having problems, and may miss the multi-layer motherboard with real problems. Therefore, it is necessary to test the functions of the multi-layer motherboard. Summary of the invention

[0004] The present invention provides a multi-layer motherboard function test strategy method based on reliability analysis, which is used to solve the technical problem of how to perform reliability testing and analysis on the functions of the multi-layer motherboard. The total reliability of the multi-layer motherboard is the product of the reliabilities of each layer of the motherboard. If the reliabilities of each layer of the motherboard are the same or different, the total reliability of the multi-layer motherboard can be calculated. If one of the reliabilities of each layer of the motherboard is not reliable, the total reliability of the multi-layer motherboard is not reliable.

[0005] In order to achieve the above object, the present invention is implemented by the following technical solutions:

[0006] A multi-layer motherboard functional test strategy method based on reliability analysis includes the following steps:

[0007] Step 1: Build a functional parameter model of a multi-layer motherboard , where the functional parameter model of the multi-layer motherboard includes electrical performance parameters and thermal performance parameters ;

[0008] Step 2: Construct a reliability model of a multi-layer motherboard. The reliability model is established based on a functional parameter model of the multi-layer motherboard. The reliability model takes into account the conductivity between each layer of the motherboard and the heat dissipation efficiency between each layer of the motherboard.

[0009] Step 3: According to the reliability model, determine the key test nodes of each layer of the multi-layer motherboard, where the key test nodes are the locations that have a greater impact on the motherboard function and are prone to failure in the reliability model;

[0010] Step 4: Test each layer of the multi-layer motherboard according to key test nodes, and record the test data of each layer of the motherboard;

[0011] Step 5: Analyze the test data of each layer of the motherboard, compare and analyze the test data of each layer of the motherboard according to the reliability model, and determine whether the multi-layer motherboard meets the reliability requirements. If not, locate the location of the fault.

[0012] Optionally, in step 1, the electrical performance parameters Including signal transmission delay and crosstalk;

[0013] Evaluating signal transmission delay is to evaluate the distortion of the transmission signal or the timing delay of the transmission signal;

[0014] Crosstalk is the mutual interference of transmission signals between two adjacent lines. The quantitative analysis of crosstalk is estimated through electromagnetic simulation.

[0015] Optionally, in step 1, the thermal performance parameters Mainly thermal conductivity. The thermal conductivity of each layer of a multi-layer motherboard determines the heat conduction speed inside the entire multi-layer motherboard. The equivalent thermal conductivity of the multi-layer motherboard requires the thermal conductivity of each layer of the motherboard. For a multi-layer motherboard, Layer, the materials of each layer of the multi-layer motherboard are different, so the equivalent thermal conductivity The calculation formula is expressed as: ,in, is the total thickness of the multi-layer motherboard, and They are The thermal conductivity of the motherboard and The thickness of the motherboard.

[0016] Optionally, in step 2, if the failures of each layer of the motherboard are independent of each other, and the failure of any layer of the motherboard causes the failure of the entire multi-layer motherboard, a multi-layer motherboard includes The total reliability of the multi-layer motherboard is the product of the reliability of each layer of the motherboard, specifically: , if the reliability of each layer of the motherboard is the same, then ;

[0017] Optionally, if a multi-stack motherboard contains The reliability of each motherboard is , , then the total reliability of the multi-layer motherboard is, , if the reliability of all layers of motherboards is the same ,but: .

[0018] Optionally, in step 3, based on the reliability model, the key test nodes of each layer of the multi-layer motherboard are tested by using Coffin-Manson software to test the thermal fatigue life of the key test nodes of each layer of the motherboard. The thermal fatigue life is ,in, and is the material constant, is the temperature variation range.

[0019] Optionally, in step 3, a correlation matrix method is used to determine the key test nodes of each layer of the multi-layer motherboard, specifically: construct a correlation matrix, where the rows represent the fault locations, the columns represent the key test nodes, and the matrix elements Indicates The fault location and The degree of correlation between the test nodes. The degree of correlation can be quantified based on experience or historical data. The value range of the degree of correlation is -1~1, where -1 indicates a completely negative correlation, 0 indicates no correlation, and 1 indicates a strong correlation.

[0020] When determining the key test nodes, the sum of the correlations between each key test node and all fault locations can be calculated. ,in, is the number of fault locations, The larger the value, the higher the correlation between the test node and the fault location, and the more likely it is a critical test node.

[0021] Optionally, in step 4, each layer of the multi-layer motherboard is tested according to key test nodes, wherein the electrical performance parameters are tested by through-hole array conductivity test, and the heat dissipation efficiency is tested by interlayer thermal resistance test;

[0022] The via array continuity test is: ;in, is the number of open holes on each layer of the motherboard, is the number of short-circuit holes on each layer of the motherboard, The total number of test holes for each layer of the motherboard; The total conductivity of the through holes of each layer of the mainboard;

[0023] The interlayer thermal resistance test is: ;in, is the thickness of each layer of the main board; is the thermal conductivity of each layer of the motherboard, is the heat dissipation area of ​​each layer of the motherboard. is the interface thermal resistance of each layer of the motherboard, is the thermal resistance of each layer of the motherboard.

[0024] Optionally, in step 5, the steps of comparing and analyzing the test data of each layer of the motherboard are as follows:

[0025] Step a: Construct a test data matrix;

[0026] Step b: Comparative analysis of multiple groups of data;

[0027] Step c: Generate a decision matrix, in which a priority improvement plan is developed based on the analysis results:

[0028] Step d: Create a reliability analysis report.

[0029] Beneficial effects of the present invention:

[0030] 1. The failure of each layer of the motherboard of the present invention is independent of each other, and the failure of any layer of the motherboard leads to the failure of the entire multi-layer motherboard. The total reliability of the multi-layer motherboard is the product of the reliabilities of each layer of the motherboard. If the reliabilities of each layer of the motherboard are the same or different, the total reliability of the multi-layer motherboard can be calculated. If one of the reliabilities of each layer of the motherboard is not reliable, the total reliability of the multi-layer motherboard is not reliable.

[0031] 2. The thermal conductivity of the present invention is that the materials of each layer of the multi-layer motherboard are different, and the thermal conductivity of each layer of the motherboard is different. The thermal conductivity of each layer of the multi-layer motherboard is calculated to obtain an equivalent thermal conductivity. The equivalent thermal conductivity makes the heat inside the entire multi-layer motherboard evenly distributed on each layer of the motherboard, and determines the thermal conduction speed of the heat inside the entire multi-layer motherboard. Under the same temperature of each layer of the motherboard and the total thickness of the entire multi-layer motherboard, the thermal conductivity of each layer of the motherboard of the entire multi-layer motherboard is made the same by equivalent heat of different materials, and the thermal conduction speed inside the entire multi-layer motherboard is the same.

[0032] 3. The correlation matrix method is used to determine the key test nodes of each layer of the multi-layer motherboard, that is, to construct a correlation matrix. The degree of correlation can be quantified based on experience or historical data. The correlation degree ranges from -1 to 1, where -1 indicates a completely negative correlation, 0 indicates no correlation, and 1 indicates a strong correlation. When determining the key test nodes, the sum of the correlations between each key test node and all fault locations can be calculated. The higher the correlation between the test node and the fault location, the more likely it is to be a key test node. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0034] Figure 1 It is a schematic diagram of the workflow of the present invention.

[0035] Figure 2 This is a flow chart of the test data of analyzing each layer of the motherboard according to the present invention. DETAILED DESCRIPTION

[0036] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0037] A multi-layer motherboard functional test strategy method based on reliability analysis includes the following steps:

[0038] Step 1: Build a functional parameter model of a multi-layer motherboard , where the functional parameter model of the multi-layer motherboard includes electrical performance parameters and thermal performance parameters , electrical performance parameters Including signal transmission delay and crosstalk;

[0039] Step 2: Construct a reliability model of a multi-layer motherboard. The reliability model is established based on a functional parameter model of the multi-layer motherboard. The reliability model takes into account the conductivity between each layer of the motherboard and the heat dissipation efficiency between each layer of the motherboard.

[0040] Step 3: According to the reliability model, determine the key test nodes of each layer of the multi-layer motherboard, where the key test nodes are the locations that have a greater impact on the motherboard function and are prone to failure in the reliability model;

[0041] Step 4: Test each layer of the multi-layer motherboard according to key test nodes, and record the test data of each layer of the motherboard;

[0042] Step 5: Analyze the test data of each layer of the motherboard, compare and analyze the test data of each layer of the motherboard according to the reliability model, and determine whether the multi-layer motherboard meets the reliability requirements. If not, locate the location of the fault (find the location prone to failure through the correlation of key test nodes).

[0043] In step 1, evaluating the signal transmission delay is evaluating the transmission signal distortion or the transmission signal timing delay. Specifically, evaluating the signal transmission delay is: ,in, is the transmission delay, is the line length (i.e. the fiber length), It is the speed at which a signal propagates in a medium (such as an optical fiber). , is the speed of light in a vacuum, is the relative permittivity of the medium;

[0044] Crosstalk is the mutual interference of transmission signals between two adjacent lines. Crosstalk is related to the spacing between lines (optical fibers), signal frequency and medium. The quantitative analysis of crosstalk is estimated by electromagnetic simulation. The quantitative analysis of crosstalk by electromagnetic simulation is the crosstalk analysis of microstrip lines, that is, , is the crosstalk coefficient (e.g. coupling voltage or power ratio), is the signal frequency, is the driving signal voltage, is the spacing between adjacent transmission lines, is the thickness of the microstrip line medium, The core method to reduce crosstalk in parallel microstrip lines is to increase the spacing between adjacent transmission lines. , reduce the thickness of the microstrip line dielectric , reduce the signal frequency Or reduce the driving signal voltage .

[0045] In parallel microstrip lines, crosstalk noise The calculation method is: ,in is the mutual capacitance, is the self capacitance, is the source signal voltage. Under the condition of no change, the mutual capacitance And the source signal voltage The larger the crosstalk noise The larger the mutual capacitance And the source signal voltage Under the condition of no change, the self-capacitance The larger the crosstalk noise The smaller.

[0046] Thermal performance parameters Mainly thermal conductivity. The thermal conductivity of each layer of a multi-layer motherboard determines the heat conduction speed inside the entire multi-layer motherboard. Specifically, for a multi-layer motherboard, the equivalent thermal conductivity requires the thermal conductivity of each layer of the motherboard. The thermal conductivity of each layer of the motherboard is determined by the material. The thermal conductivity of each layer of the motherboard is respectively , the thickness of each layer of the main board is divided into , for a multi-layer motherboard containing Layer, that is, the materials of each layer of the multi-layer motherboard are different, then the thermal conductivity of each layer of the motherboard Perform equivalent operations to obtain the equivalent thermal conductivity , equivalent thermal conductivity The calculation formula is expressed as: ,in, is the total thickness of the multi-layer motherboard, and They are The thermal conductivity of the motherboard (where the thermal conductivity of each layer of the motherboard can be the same or different) and the The thickness of the motherboard, To obtain the total thickness of the entire multi-layer motherboard and the equivalent thermal conductivity of each layer of the motherboard .

[0047] The different thermal conductivities of each layer of the motherboard are calculated equivalently to obtain a multi-layer motherboard with equivalent thermal conductivity. The material, under the same temperature of each layer of the mainboard and the total thickness of the entire multi-layer mainboard, the heat of different materials is equivalent to make the thermal conductivity of each layer of the entire multi-layer mainboard the same, and the heat conduction speed inside the entire multi-layer mainboard the same.

[0048] In step 2, a multi-layer motherboard includes If the failure of each layer of the motherboard is independent of each other, and the failure of any layer of the motherboard leads to the failure of the entire multi-layer motherboard, then the total reliability of the multi-layer motherboard is the product of the reliability of each layer of the motherboard, specifically: , if the reliability of each layer of the motherboard is the same, then ; If one of the reliability levels of each layer of the motherboard is not reliable, the overall reliability of the multi-layer motherboard is not reliable.

[0049] If a multi-layer motherboard contains The reliability of each motherboard is , is the reliability value, For the reliability of the 1st layer motherboard, For the The reliability of the motherboard, For the The reliability of each motherboard layer is the same. , then the total reliability of the multi-layer motherboard is, , if the reliability of all layers of motherboards is the same ,but: In addition, even if the reliability of each layer of the motherboard is different, there is no motherboard with no reliability among the reliability of each layer of the motherboard, so the total reliability of the multi-layer motherboard is still there.

[0050] In step 3, based on the reliability model, the key test nodes of each layer of the multi-layer motherboard are tested by using Coffin-Manson software to test the thermal fatigue life of the key test nodes of each layer of the motherboard. The thermal fatigue life is ;

[0051] and is the material constant (needs to be calibrated through experiments), is the temperature variation range. That is, the test is the thermal fatigue life of the key test nodes of each layer of the motherboard.

[0052] For example: a material in =200, =1.2×105, =1.2×105, then ≈275 cycles.

[0053] In step 3, the correlation matrix method is used to determine the key test nodes of each layer of the multi-layer motherboard. Specifically, a correlation matrix is ​​constructed, that is, assuming that Key test nodes , then the correlation matrix The dimension is ,in Represents a test node and The correlation coefficient between them, the rows represent the fault locations, the columns represent the key test nodes, and the matrix elements Indicates The fault location and The correlation degree between the test nodes is and , the calculation formula of Pearson correlation coefficient is:

[0054] ;

[0055] in, and They are test nodes and In the The data values ​​in the test, and They are test nodes and The average value of is the number of tests.

[0056] The degree of correlation can be quantified based on experience or historical data, and the correlation value range is -1~1. A value of −1 indicates a completely negative correlation. A value of 0 indicates no correlation. A value of 1 indicates a strong correlation;

[0057] Assume there are three key test nodes , and After multiple tests, their correlation matrix is ​​calculated as follows:

[0058] ;

[0059] From this matrix we can see that and There is a strong positive correlation between them (the correlation coefficient is 0.8). and There is also a certain positive correlation between them (the correlation coefficient is 0.6), and and The correlation between them is weak (correlation coefficient is −0.3).

[0060] When determining the key test nodes, the sum of the correlations between each key test node and all fault locations can be calculated as ,in, is the number of fault locations, The larger the value, the higher the correlation between the test node and the fault location, and the more likely it is a critical test node.

[0061] In step 4, each layer of the multi-layer motherboard is tested according to key test nodes, wherein the electrical performance parameters are tested by through-hole array conductivity test, and the heat dissipation efficiency is tested by interlayer thermal resistance test;

[0062] The via array continuity test is: ;in, is the number of open holes on each layer of the motherboard, is the number of short-circuit holes on each layer of the motherboard, The total number of test holes for each layer of the motherboard; is the total conductivity of the through holes of each layer of the motherboard; for example, the total number of test holes of the first layer motherboard is , To calculate the total conductivity of the through holes of the first layer motherboard, similarly, the total number of test holes of the second layer motherboard is , To calculate the total conductivity of the second layer motherboard through holes.

[0063] The interlayer thermal resistance test is: ;in, is the thickness of each layer of the main board; is the thermal conductivity of each layer of the motherboard, is the heat dissipation area of ​​each layer of the motherboard. is the interface thermal resistance of each layer of the motherboard, is the thermal resistance of each layer of the motherboard.

[0064] In step 5, the steps for comparing and analyzing the data are as follows:

[0065] Step a: Construct a test data matrix;

[0066] Combine all test data types into a matrix and calculate the total score of all types directly through matrix multiplication;

[0067] (1) Construct the test data matrix:

[0068] ;in, Score the coverage, Score the construction complexity, Score the error detection capability, Score the maintenance cost.

[0069] (2) Construct the total score vector calculation:

[0070] ;in, is the weight vector, , Score weights for coverage, is the construction complexity scoring weight, Score weights for error detection capability, Score weight for maintenance cost, is the weight distribution, that is To evaluate the weights in the weight vector.

[0071] For example: using 6 test data types (i.e. 6 functions of the motherboard), the test data matrix and the weight vector for:

[0072] , ;

[0073] The total score vector is: ;

[0074] The test data of each layer of the motherboard is organized into a matrix form for systematic comparison. Each row represents a motherboard layer (such as: Layer1, Layer2...):

[0075]

[0076] Step b: Compare and analyze multiple groups of data; among them, the difference comparison analysis method is adopted, that is, the performance fluctuation of different batches of the same motherboard layer is calculated (the deviation from the center of the specification is the correlation between the key test node and the fault location):

[0077]

[0078] Step c: Generate a decision matrix; that is, formulate a priority improvement plan based on the analysis results:

[0079]

[0080] Step d: Create a reliability analysis report;

[0081] Use scripts (Python+Pandas+ReportLab) to output the decision matrix analysis results as PDF / Excel reports, including:

[0082] 1. Comparison table of key test points; such as: comparison information table of correlation between key test points;

[0083] 2. Difference heat map and route map; Difference heat map is a visual chart that uses color depth to indicate the degree of data difference. It usually maps data values ​​to different colors. The darker the color, the greater the difference, and the lighter the color, the smaller the difference. The difference heat map combined with the route map reflects the different colors on the route.

[0084] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope of the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A multi-layer motherboard functional test strategy method based on reliability analysis, characterized in that: The steps include: Step 1: Build a functional parameter model of a multi-layer motherboard , where the functional parameter model of the multi-layer motherboard includes electrical performance parameters and thermal performance parameters ; Step 2: Construct a reliability model of a multi-layer motherboard. The reliability model is established based on a functional parameter model of the multi-layer motherboard. The reliability model takes into account the conductivity between each layer of the motherboard and the heat dissipation efficiency between each layer of the motherboard. Step 3: According to the reliability model, determine the key test nodes of each layer of the multi-layer motherboard, where the key test nodes are the locations that have a greater impact on the motherboard function and are prone to failure in the reliability model; Step 4: Test each layer of the multi-layer motherboard according to key test nodes, and record the test data of each layer of the motherboard; Step 5: Analyze the test data of each layer of the motherboard, compare and analyze the test data of each layer of the motherboard according to the reliability model, and determine whether the multi-layer motherboard meets the reliability requirements. If not, locate the location of the fault.

2. The multi-layer motherboard functional test strategy method based on reliability analysis according to claim 1 is characterized in that: In step 1, the electrical performance parameter Including signal transmission delay and crosstalk; Evaluating the signal transmission delay is evaluating the transmission signal distortion or the transmission signal timing delay; The crosstalk is the mutual interference of transmission signals between two adjacent lines, and the quantitative analysis of the crosstalk is estimated through electromagnetic simulation.

3. The multi-layer motherboard functional test strategy method based on reliability analysis according to claim 1 is characterized in that: In step 1, the thermal performance parameter Mainly thermal conductivity. The thermal conductivity of each layer of the multi-layer motherboard determines the heat conduction speed inside the entire multi-layer motherboard. The equivalent thermal conductivity of the multi-layer motherboard requires the thermal conductivity of each layer of the motherboard. For a multi-layer motherboard including Layer, the materials of each layer of the multi-layer motherboard are different, so the equivalent thermal conductivity The calculation formula is expressed as: ,in, is the total thickness of the multi-layer motherboard, and They are The thermal conductivity of the motherboard and The thickness of the motherboard.

4. The multi-layer motherboard functional test strategy method based on reliability analysis according to claim 1 is characterized in that: In the step 2, one of the multi-layer motherboards comprises If the failure of each layer of the motherboard is independent of each other, and the failure of any layer of the motherboard leads to the failure of the entire multi-layer motherboard, then the total reliability of the multi-layer motherboard is the product of the reliability of each layer of the motherboard, specifically: , if the reliability of each layer of motherboard is the same, is the reliability value, then .

5. The multi-layer motherboard functional test strategy method based on reliability analysis according to claim 4 is characterized in that: If a multi-layer motherboard comprises The reliability of each motherboard is , is the reliability value, For the reliability of the 1st layer motherboard, For the The reliability of the motherboard, For the The reliability of the motherboard layer. Specifically, the reliability of each motherboard layer is , is the reliability value, , then the total reliability of the multi-layer motherboard is, , if the reliability of all layers of motherboards is the same ,but: .

6. The multi-layer motherboard functional test strategy method based on reliability analysis according to claim 1 is characterized in that: In step 3, based on the reliability model, the key test nodes of each layer of the multi-layer motherboard are tested by using Coffin-Manson software to test the thermal fatigue life of the key test nodes of each layer of the motherboard. The thermal fatigue life is ,in, and is the material constant, is the temperature variation range.

7. A multi-layer motherboard functional test strategy method based on reliability analysis according to claim 6, characterized in that: In the step 3, the correlation matrix method is used to determine the key test nodes of each layer of the multi-layer motherboard, specifically: construct a correlation matrix, the rows represent the fault locations, the columns represent the key test nodes, and the matrix elements Indicates The fault location and The degree of correlation between the test nodes. The degree of correlation can be quantified based on experience or historical data. The value range of the degree of correlation is -1~1, where -1 indicates a completely negative correlation, 0 indicates no correlation, and 1 indicates a strong correlation. When determining the key test nodes, the sum of the correlations between each key test node and all fault locations can be calculated. ,in, is the number of fault locations, The larger the value, the higher the correlation between the test node and the fault location, and the more likely it is a critical test node.

8. The multi-layer motherboard functional test strategy method based on reliability analysis according to claim 1 is characterized in that: In the step 4, each layer of the multi-layer motherboard is tested according to key test nodes, wherein the electrical performance parameters are tested by through-hole array conductivity test, and the heat dissipation efficiency is tested by interlayer thermal resistance test; The through hole array conductivity test is: ;in, is the number of open holes on each layer of the motherboard, is the number of short-circuit holes on each layer of the motherboard, The total number of test holes for each layer of the motherboard; The total conductivity of the through holes of each layer of the mainboard; The interlayer thermal resistance test is: ;in, is the thickness of each layer of the main board; is the thermal conductivity of each layer of the motherboard, is the heat dissipation area of ​​each layer of the motherboard. is the interface thermal resistance of each layer of the motherboard, is the thermal resistance of each layer of the motherboard.

9. The multi-layer motherboard functional test strategy method based on reliability analysis according to claim 1 is characterized in that: In step 5, the steps of comparing and analyzing the test data of each layer of the motherboard are as follows: Step a: Construct a test data matrix; Step b: Comparative analysis of multiple groups of data; Step c: Generate a decision matrix, in which a priority improvement plan is developed based on the analysis results: Step d: Create a reliability analysis report.

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