Bayesian optimization-based EDA tool parameter automatic tuning method and system

Abstract

The invention aims to provide a Bayesian optimization-based EDA (Electronic Design Automation) tool parameter automatic tuning method and system. The method comprises the following steps of: setting a process library file, a hardware description language code of chip design and a constraint file, and configuring a parameter space formed by EDA tool parameters; inputting the process library file, the hardware description language code of the chip design, the constraint file and the parameter space into DGPSPMBO; and the DGPSPMBO outputs a chip layout design according to a diversity-guided multi-target Bayesian optimization framework. According to the method, important parameters are selected to ensure that optimization is concentrated on the most effective parameter dimension, and the search accuracy is improved. And meanwhile, a parallel optimization strategy considering parameter space and PPA index diversity is introduced, and exploration is guided by utilizing a batch selection mechanism and combining a hyper-volume improvement index, so that exploration is more sufficient, and a plurality of EDA tool parameter combinations capable of realizing high-quality chip design can be quickly and accurately found.

Description

Technical Field

[0001] The present invention relates to the technical field of digital integrated circuits, and in particular to an automatic tuning method and system for EDA tool parameters based on Bayesian optimization. Background Art

[0002] Modern very large scale integrated circuit (VLSI) design requires the use of electronic design automation (EDA) tools to implement integrated circuits. In order to adapt to different application scenarios and design requirements, these EDA tools provide many adjustable parameters. All EDA tool parameter value combinations constitute a complete parameter space, in which the setting of parameter combinations has an important impact on the performance, power and area of ​​chip design. In order to obtain high-quality chip design results, multiple parameters in EDA tools need to be accurately set. Manually selecting parameter values ​​is too laborious, limited by expert experience and difficult to extend to new designs. Therefore, there is an urgent need to find effective parameter automatic adjustment methods to improve the efficiency of chip design.

[0003] Currently, both academia and industry have begun to attach great importance to the automatic adjustment of EDA tool parameters. The proposed automatic parameter adjustment methods are mainly divided into heuristic search and model-based search. Frameworks based on heuristic algorithms, such as automatic parameter adjustment based on genetic algorithms, can quickly explore, but often lack the guarantee of global optimization and rely on a large number of iterations and domain knowledge. On the other hand, model-based frameworks show the potential to surpass traditional heuristic methods by building surrogate models to efficiently explore parameter space. For example, XGBoost and design-specific features extracted from the design process are used for learning to adjust tool parameters. In view of the over-parameterization situation, neural networks have the advantage of high accuracy, but require more data than non-parametric models such as Gaussian processes.

[0004] In recent years, multi-objective Bayesian optimization has shown significant advantages in the automatic adjustment of EDA tool parameters. It effectively finds the Pareto optimal solution set by modeling the relationship between objectives. For example, multi-objective BO is used to optimize VLSI design process parameters, model the correlation between multiple objectives and obtain the Pareto optimal parameter value set. When dealing with multi-objective optimization, how to efficiently explore the parameter space, balance exploration and utilization, and reduce optimization costs are still core challenges. Or through the fast parameter adjustment framework of transfer learning and multi-objective Bayesian optimization, the optimal design parameters can be quickly found, which further accelerates the optimization process. However, when this framework uses random embedding to process large parameter spaces, its ability to finely explore high-value parameter areas is still limited. Moreover, although its multi-objective trust region optimization strategy adopts clustering to divide the trust region in the initial stage, it does not directly integrate the diversity information of the design and performance space for global guidance, resulting in the possibility of missing the full exploration of the global optimal solution in iterative exploration. Summary of the invention

[0005] The purpose of the present invention is to provide an automatic tuning method and system for EDA tool parameters based on Bayesian optimization, which selects important parameters to ensure that the optimization is focused on the most effective parameter dimension and improves the accuracy of the search. At the same time, a parallel optimization strategy that considers the diversity of parameter space and PPA indicators is introduced, and a batch selection mechanism is used to guide the exploration in combination with the hypervolume improvement index, so that the exploration is more sufficient, thereby quickly and accurately finding many EDA tool parameter combinations that can achieve high-quality chip design.

[0006] An automatic tuning method for EDA tool parameters based on Bayesian optimization, comprising:

[0007] Set up process library files, hardware description language code and constraint files for chip design, and configure the parameter space composed of EDA tool parameters;

[0008] Input the process library file, the hardware description language code of the chip design, the constraint file and the parameter space into DGPSPMBO;

[0009] The DGPSPMBO outputs chip layout design according to a diversity-guided multi-objective Bayesian optimization framework.

[0010] Preferably, after setting the process library file, the hardware description language code and constraint file of the chip design, and configuring the parameter space formed by the EDA tool parameters, the method further includes pruning the parameter space to reduce the dimension of the parameter space, specifically:

[0011] Use SHAP to explain the proxy model and obtain the average absolute value of SHAP for each tool parameter in all samples;

[0012] Calculate the importance value of each parameter;

[0013] Setting contribution thresholds;

[0014] Calculating the contribution value of each parameter according to the importance value;

[0015] If the contribution value of the current parameter in multiple iterations exceeds the contribution threshold, the current parameter is marked as an important parameter.

[0016] Preferably, the use of the SHAP interpretation proxy model to obtain the SHAP average absolute value of each tool parameter in all samples includes:

[0017] SHAP's KernelExplainer is used to explain the output of the proxy model and obtain the SHAP average absolute value of each tool parameter k in all samples [SHAP performance , SHAP area SHAPpower ] k , used to measure the contribution of each parameter to the PPA index, where the parameter dimension k∈{1,…,d};

[0018] For PPA indicator j, given the model's predicted value f j (x) and a sample tool parameter vector x = (x 1 ,x 2 ,…,x d ), each parameter x k SHAP value φ k (x) is calculated by the following formula:

[0019]

[0020] Where N is the set of all tool parameters {1,2,…,d}; S is a subset of N that does not include parameter k; f j (S) is the model prediction value of target j on parameter subset S; f j (S∪{k}) is the model prediction of target j after adding parameter k to subset S; |S| is the size of subset S, and |N| is the total number of parameters

[0021] For the three objectives of performance, area, and power, the tool parameter k is calculated as the SHAP mean absolute value of all samples in the following way:

[0022]

[0023] Where n is the number of samples, x i is the instrument parameter vector of the i-th sample; |φ k (x i )| j It is the SHAP absolute value of the kth parameter of the ith sample on indicator j, that is, the contribution of tool parameter k to the prediction result of indicator j.

[0024] Preferably, calculating the importance value of each parameter includes:

[0025] The average impact of the SHAP value on all PPA metrics is calculated to quantify the overall importance of each parameter on the metric result:

[0026]

[0027] Preferably, calculating the contribution value of each parameter according to the importance value comprises:

[0028] In each iteration, the importance of each input parameter to the PPA indicator is calculated. k ;

[0029] Calculate the contribution rate of each parameter based on the importance value k , and sort the parameters according to their contribution rate:

[0030]

[0031] Where d is the number of parameters in the original parameter space;

[0032] Determine which parameters fall within the important contribution area, that is, start accumulating from the parameter i with the highest contribution rate, Not greater than the preset value, indicating that parameters i to j, sorted by contribution rate, fall into the important contribution area.

[0033] Preferably, the DGPSPMBO outputs chip layout design according to a diversity-guided multi-objective Bayesian optimization framework, including:

[0034] The Gaussian process is used to train the proxy model of the objective function;

[0035] The Pareto front is used to approximate the frontier of the mean function of the Gaussian process extension;

[0036] A batch selection strategy is adopted to obtain batch points with uniform distribution and hypervolume around the target area according to the output of the Pareto front approximation process.

[0037] Preferably, the adopting the Gaussian process model to train the objective function of the proxy model comprises:

[0038] The prior of the Gaussian process is the mean function and kernel function For the characteristics;

[0039] For a given input variable x, the prior distribution of GP is expressed as

[0040] Use the mean function m(x)=0 and the Matern kernel function to capture various function properties;

[0041] Train the Gaussian process posterior to improve the prior model by maximizing the log-marginal likelihood logp(y|x,θ) on the available dataset {X, Y}, where θ represents the parameters of the kernel function;

[0042] The posterior distribution of the Gaussian process is The output is in the form of, where the mean function is μ(x)=m(x)+kK -1 Y, and the covariance function Σ(x)=k(x,x)-kK -1 k T, where k = k(x,X) and K = k(X,X).

[0043] Preferably, the method of using the Pareto front to approximate the front of the mean function of the Gaussian process extension comprises:

[0044] Use local optimization methods to obtain a local Pareto optimal solution x for each sample i ;

[0045] Cover various Pareto frontier areas and explore different optimization directions;

[0046] Extract x i A first-order approximation of the surrounding Pareto frontier is obtained, and a dense set of solutions is obtained, resulting in a large Pareto optimal region around a single point in the Pareto set.

[0047] Preferably, the method of adopting a batch selection strategy to obtain batch points that are evenly distributed around the target area and have a super volume according to the output of the Pareto front approximation process includes:

[0048] The selection strategy is expressed as:

[0049]

[0050] Where X B ={x 1 ,…,x b} is a set of b samples in a batch, is the current Pareto frontier, for each region Function δ i (.) is defined as belonging to the region From X B Multiple elements x j ;

[0051] Using a greedy approach, select a point x with the maximum hypervolume improvement 1 , x 1 Add to the batch and Add to current Pareto front

[0052] Search for the next point with the largest hypervolume improvement, where the current point is equal to x 1 Not belonging to the same region;

[0053] Repeat the iteration while avoiding all areas of the selected points until all areas are covered;

[0054] If more points are still needed for the current batch, the counter of the covered area is reset and the same process is repeated to obtain a batch of points {x 1 , …, x b}.

[0055] An EDA tool parameter automatic tuning system based on Bayesian optimization, comprising:

[0056] Parameter configuration module, used to set process library files, hardware description language code and constraint files for chip design, and configure the parameter space composed of EDA tool parameters;

[0057] A data transmission module, used for inputting the process library file, the hardware description language code of the chip design, the constraint file and the parameter space into DGPSPMBO;

[0058] The data processing module is used for the DGPSPMBO to output the chip layout design according to the diversity-guided multi-objective Bayesian optimization framework.

[0059] The beneficial effect of the present invention is that the present invention uses explainable AI technology to quantify the impact of parameters on optimization goals, selects important parameters to ensure that the optimization is focused on the most effective parameter dimension, and improves the accuracy of the search. At the same time, a parallel optimization strategy that considers the diversity of parameter space and PPA indicators (performance, power, area) is introduced, and a batch selection mechanism is used to guide exploration in combination with hypervolume improvement indicators. More exploration is performed within a limited running time, making the exploration more complete, so that many EDA tool parameter combinations that can achieve high-quality chip design can be found quickly and accurately. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0061] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0062] Figure 1 A flow chart of an automatic tuning method for EDA tool parameters based on Bayesian optimization of the present invention;

[0063] Figure 2 Schematic diagram of parameter space pruning of the present invention;

[0064] Figure 3 This is a diagram of the algorithm framework based on Bayesian optimization of the present invention. DETAILED DESCRIPTION

[0065] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0066] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0067] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0068] In the methods described in the background technology section, in the past, researchers have made a lot of improvements in accurately and quickly exploring the parameter space of EDA tools. However, due to the high complexity and lack of parallelization, most of these improved parameter automatic adjustment methods cannot fully and accurately explore in a large search space.

[0069] To overcome these limitations, first, we should consider formulating strategies to find high-value parameter areas (i.e., effective subspaces) in the EDA tool parameter adjustment process, and enhance the ability to explore complex parameter spaces in detail. For example, we can use some sensitivity analysis techniques to evaluate the relative importance of each parameter to the chip design quality, thereby identifying the most contributing tool parameters. Secondly, we should consider extending multi-objective Bayesian optimization to parallelization, so that we can iteratively select the best batch samples for parallel evaluation. Each batch of samples can fully explore the parameter space and effectively explore promising areas.

[0070] The present invention uses explainable AI technology to quantify the impact of parameters on optimization goals, selects important parameters to ensure that optimization is focused on the most effective parameter dimensions, and improves the accuracy of the search. At the same time, a parallel optimization strategy that considers the diversity of parameter space and PPA indicators (performance, power, area) is introduced, and a batch selection mechanism is used to guide exploration in combination with hypervolume improvement indicators. More exploration is performed within a limited running time, making the exploration more complete, so that many EDA tool parameter combinations that can achieve high-quality chip design can be found quickly and accurately.

[0071] Example 1

[0072] A method for automatic tuning of EDA tool parameters based on Bayesian optimization, see Figure 1 ,include:

[0073] S100, setting a process library file, a hardware description language code and a constraint file for chip design, and configuring a parameter space composed of EDA tool parameters;

[0074] Determine the parameter space composed of d EDA tool parameter value combinations Each parameter has a set range of values. Determine the objective function f(x) = (f 1 (x), …, f m (x)), where m is the number of targets. Determine the number of Bayesian optimization iterations n.

[0075] S200, inputting the process library file, the hardware description language code of the chip design, the constraint file and the parameter space into DGPSPMBO;

[0076] From the parameter space The Latin Hypercube Sampling (LHS) method is used to select k initial sample points x 1 ,…,x k , and run the EDA tool to obtain the objective function values ​​f(x 1 ),…,f(x k ), forming the initial data set X 0 and Y 0 .

[0077] S300,DGPSPMBO outputs chip layout design based on a diversity-guided multi-objective Bayesian optimization framework.

[0078] In order to obtain chip layout design from the EDA process, it is necessary to prepare process library files, hardware description language (HDL) code of chip design and related constraint files, and specify the value range of each EDA tool parameter. Given these files and parameter space, DGPSPMBO can optimize the parameters of the EDA process and finally output the Pareto optimal parameter value solution set to obtain a high-quality chip layout design set.

[0079] Preferably, reference Figure 2 After configuring the parameter space formed by the EDA tool parameters at S100, the method further includes pruning the parameter space to reduce the dimension of the parameter space at S110, specifically:

[0080] S111, use SHAP to explain the proxy model and obtain the SHAP average absolute value of each tool parameter in all samples;

[0081] S112, calculating the importance value of each parameter;

[0082] S113, setting a contribution threshold;

[0083] S114, calculating the contribution value of each parameter according to the importance value;

[0084] S115: If the contribution value of the current parameter in multiple iterations exceeds the contribution threshold, the current parameter is marked as an important parameter.

[0085] Although there are a large number of parameters in EDA tools that affect chip design quality, some of them are more important than others for a given design. For example, timing optimization-driven layout parameters are very important for circuits that need to increase operating frequency during the global layout process. In other words, chip design quality is strongly affected by parameter vectors with lower dimensions than the parameter space. In order to enhance the ability to explore complex parameter spaces in detail, the present invention proposes an automatic pruning mechanism based on parameter importance.

[0086] In the initial stage of the process, explainable AI is used to calculate the contribution of each tool parameter to the PPA indicator and quantify the parameter importance. Subsequently, the parameters with the main contribution are automatically counted and selected, and the parameter space is pruned to a simplified subspace. The search dimension is effectively reduced. Specifically, SHapley Additive exPlanations (SHAP) is used, which proposes to explain the model prediction of a given input by calculating the contribution of each feature to the prediction. SHAP is a feature importance interpretation method that uses Shapley values ​​originally from game theory. It quantifies the importance of input features by evaluating the contribution of each input feature to the output result. Here, the surrogate model in Bayesian optimization (i.e., Gaussian Processes, GP) is the prediction model, and the input features are the EDA tool parameters. The purpose is to use SHAP to explain the contribution of EDA tool parameters to Gaussian process model predictions to quantify the importance of EDA tool parameters.

[0087] Preferably, S111, using SHAP to explain the proxy model, obtaining the SHAP average absolute value of each tool parameter in all samples includes:

[0088] SHAP's KernelExplainer is used to explain the output of the proxy model and obtain the SHAP average absolute value of each tool parameter k in all samples [SHAP performance SHAP area SHAP power ] k , used to measure the contribution of each parameter to the PPA index, where the parameter dimension k∈{1,…d};

[0089] For PPA indicator j, given the model's predicted value f j (x) and a sample tool parameter vector x = (x 1 ,x 2 ,…,x d ), each parameter x k SHAP value φ k (x) is calculated by the following formula:

[0090]

[0091] Where N is the set of all tool parameters {1,2,…,d}; S is a subset of N that does not include parameter k; f j (S) is the model prediction value of target j on parameter subset S; f j (S∪{k}) is the model prediction of target j after adding parameter k to subset S; |S| is the size of subset S, and |N| is the total number of parameters

[0092] For the three objectives of performance, area, and power, the tool parameter k is calculated as the SHAP mean absolute value of all samples in the following way:

[0093]

[0094] Where n is the number of samples, x i is the instrument parameter vector of the ith sample; |φ k (x i )| j It is the SHAP absolute value of the kth parameter of the ith sample on indicator j, that is, the contribution of tool parameter k to the prediction result of indicator j.

[0095] Preferably, S112, calculating the importance value of each parameter includes:

[0096] The average impact of the SHAP value on all PPA metrics is calculated to quantify the overall importance of each parameter on the metric result:

[0097]

[0098] Preferably, S114, calculating the contribution value of each parameter according to the importance value includes:

[0099] In each iteration, the importance of each input parameter to the PPA indicator is calculated. k ;

[0100] Calculate the contribution rate of each parameter based on the importance value k , and sort the parameters according to their contribution rate:

[0101]

[0102] Where d is the number of parameters in the original parameter space;

[0103] Determine which parameters fall within the important contribution area, that is, start accumulating from the parameter i with the highest contribution rate, Not greater than the preset value, indicating that parameters i to j, sorted by contribution rate, fall into the important contribution area.

[0104] Important contribution area setting: determine a preset value Threshold of an important contribution area, that is, the cumulative main contribution ratio of the parameter importance value, such as 95%; determine a stability threshold h, that is, the parameter must appear in the important contribution area at least h times to be marked as an important parameter.

[0105] Parameter contribution rate calculation: In each iteration, the importance of each input parameter to the target (PPA indicator) is calculated using the method mentioned in the previous section. k . Calculate the contribution rate of each parameter based on the importance value k , and sort the parameters according to their contribution rates.

[0106] Counting parameters in the important contribution area: Count the parameters that fall in the important contribution area in each iteration. If a parameter falls stably in the important contribution area in multiple iterations (at least h times), it is marked as an important parameter.

[0107] Finally determine the important parameters: until a certain iteration, the cumulative number of times all parameters in the important contribution area fall in the important contribution area is not less than h, then the final important parameters can be determined. Prune the parameter space into a simplified subspace according to the important parameters p≤d (where p is the number of final important parameters).

[0108] Through the above process, the parameter space can be reduced from d dimensions to p dimensions in the early stage, automatic pruning of the parameter space can be achieved, and then more accurate multi-objective Bayesian optimization can be continued in the p-dimensional effective subspace.

[0109] Preferably, reference Figure 3 , S300, DGPSPMBO outputs chip layout design based on a diversity-guided multi-objective Bayesian optimization framework including:

[0110] S310, training a proxy model of the objective function using a Gaussian process;

[0111] Define the model from each proxy Exported acquisition functions And build a multi-target acquisition function

[0112] S320, using the Pareto front approximation to calculate the frontier of the mean function of the Gaussian process extension;

[0113] Using the Multi-Objective Acquisition Function Approximate solution to Pareto set and its corresponding Pareto frontier

[0114] S330, adopting a batch selection strategy to obtain batch points that are evenly distributed around the target area and have a hypervolume according to the output of the Pareto front approximation process.

[0115] Pareto set The points in the

[0116] Select the next batch of points to be evaluated within these areas

[0117] For selected points Perform actual evaluation and calculate its objective function value

[0118] Update the dataset and

[0119] If the current number of iterations reaches the set number of iterations n, then according to the final data set Y n Calculate and output the Pareto optimal solution set (i.e., the EDA tool parameter combination that can achieve high-quality chip layout design) and Pareto frontier

[0120] The framework of the present invention combines the design space (i.e. parameter space) and performance space Based on the diversity of the multi-objective Bayesian optimization, a batch selection strategy is used to extend the multi-objective Bayesian optimization to parallel optimization, so as to improve the global optimization efficiency of the automatic adjustment of EDA tool parameters. The multi-objective Bayesian optimization framework guided by diversity mainly consists of three components: Gaussian process construction, Pareto front approximation, and batch selection strategy.

[0121] Preferably, S310, using the Gaussian process model to train the objective function of the proxy model includes:

[0122] The prior of the Gaussian process is the mean function and kernel function For the characteristics;

[0123] For a given input variable x, the prior distribution of GP is expressed as

[0124] Use the mean function m(x)=0 and the Matern kernel function to capture various function properties;

[0125] Train the Gaussian process posterior to improve the prior model by maximizing the log-marginal likelihood logp(y|x,θ) on the available dataset {X, Y}, where θ represents the parameters of the kernel function;

[0126] The posterior distribution of the Gaussian process is The output is in the form of, where the mean function is μ(x)=m(x)+kK -1 Y, and the covariance function Σ(x)=k(x,x)-kK -1 k T , where k = k(x,X) and K = k(X,X).

[0127] In each iteration of the BO algorithm, the first step is to train a statistical model, called a surrogate model, on all available evaluation points. Typically, a Gaussian process (GP) is used to model the unknown objective function f and provide the prediction and uncertainty of the model. For each objective function (Performance, Power, Area), a Gaussian process (GP) model is established separately. First, the prior of the GP is the mean function and kernel function For a given input variable x, the prior distribution of GP can be expressed as By choosing different mean and kernel functions, the GP prior can be used to incorporate any prior beliefs about the target function (if available) independent of the input data. Here, the mean function m(x) = 0 is used with the Matern kernel function, which can capture a variety of function properties. Next, the GP posterior is trained to refine the prior model by maximizing the log-marginal likelihood logp(y|x,θ) on the available dataset {X, Y}, where θ represents the parameters of the kernel function. Finally, the posterior distribution of the GP is given by The form of is given, where the mean function is μ(x)=m(x)+kK -1 Y, and the covariance function Σ(x)=k(x,x)-kK -1 k T , where k = k(x,X) and K = k(X,X).

[0128] Preferably, S320, using the Pareto front to approximate the front of the mean function of the Gaussian process extension includes:

[0129] Use local optimization methods to obtain a local Pareto optimal solution x for each sample i ;

[0130] Cover various Pareto frontier areas and explore different optimization directions;

[0131] Extract x i A first-order approximation of the surrounding Pareto frontier is obtained, and a dense set of solutions is obtained, resulting in a large Pareto optimal region around a single point in the Pareto set.

[0132] In order to obtain each objective function f j Proxy Model Afterwards, the mean function of the GP posterior is used as the acquisition function The next step is to calculate all Pareto frontier. To determine a smaller PPA metric, the Pareto front approximation method is used. This optimization method reduces the expensive L-PBF cost and seeks the global optimum with the fewest possible iterations in a limited design space. Using the acquisition function, the sampling is directed to areas that are likely to be better than the best observed value at the time.

[0133] The Pareto front approximation implements an iterative process consisting of three main steps. First, a random sampling method is used to generate a set of random samples among the samples with the best PPA indicator found so far to avoid local minima and achieve a balance between exploration and exploitation of the design space area. The second step uses a local optimization method to derive a local Pareto optimal solution x for each sample. i In order to cover various Pareto frontier regions, different optimization directions are explored. Finally, by extracting x i A first-order approximation of the surrounding Pareto front obtains a dense set of solutions, which effectively discovers large Pareto optimal regions around a single point in the Pareto set.

[0134] Preferably, S330, using a batch selection strategy to obtain batch points that are evenly distributed around the target area and have a super volume according to the output of the Pareto front approximation process includes:

[0135] The selection strategy is expressed as:

[0136]

[0137] Where X B ={x 1 ,…,x b} is a set of b samples in a batch, is the current Pareto frontier, for each region Function δ i (.) is defined as belonging to the region From X B Multiple elements x j ;

[0138] Using a greedy approach, select a point x with the maximum hypervolume improvement 1 , x 1 Add to the batch and Add to current Pareto front

[0139] Search for the next point with the largest hypervolume improvement, where the current point is equal to x 1 Not belonging to the same region;

[0140] Repeat the iteration while avoiding all areas of the selected points until all areas are covered;

[0141] If more points are still needed for the current batch, the counter of the covered area is reset and the same process is repeated to obtain a batch of points {x 1 , …, x b}.

[0142] Using a greedy approach, select a point x with the maximum hypervolume improvement 1 , x 1 Add to the batch and Add to current Pareto front Then, search for the next point with the largest hypervolume improvement, which is the same as x 1 do not belong to the same region. This process is repeated while avoiding all regions where points have been selected until all regions are covered. If more points are still needed for the batch, the counter of covered regions is reset and the same process is repeated. In this way, a batch of points {x 1 , …, x b}.

[0143] The last part of the framework of the present invention performs diversity region partitioning and selects a batch of samples for evaluation in the next iteration. Starting from the Pareto front approximation, the optimal points are grouped according to design attributes (EDA tool parameters) and performance (PPA indicators) to generate many diversity regions. Standard multi-objective optimization (MOO) methods (such as NSGA-II) tend to output the Pareto front as a sparse set of points uniformly dispersed around the performance space without considering the diversity of the parameter space. The Pareto front representation obtained from the previous section has a compact region and better spatial coverage. To solve the grouping problem, a data structure called performance buffer is used, which is optimized by the following steps: First, the optimal performance points of the Pareto front are mapped to an (m-1)-dimensional array using hyperspherical coordinates, and the points close to the origin are regarded as optimal points and sorted according to their hyperspherical coordinates. Secondly, the buffer records the performance, design space coordinates and corresponding first-order approximate design subspace of each selected point. This data structure is compatible with the graph cut algorithm and is designed to obtain the optimal design subspace from the grouping into k linear subspaces. A sparse subset is extracted from the best points of , which are grouped according to their performance quality and design space neighborhood to form diversity regions.

[0144] The selection strategy is based on two criteria: diversity and hypervolume improvement. The diversity metric combines information from parameter and performance space, and its goal is to evenly distribute the selected samples across the diversity region. This approach prevents the optimization from getting stuck in a local minimum and focusing too much on one high-performance region while ignoring other potentially promising regions. The goal of the selection strategy is to maximize the hypervolume improvement while requiring samples to be drawn from as many different regions as possible.

[0145] Example 2

[0146] An EDA tool parameter automatic tuning system based on Bayesian optimization, comprising:

[0147] Parameter configuration module, used to set process library files, hardware description language code and constraint files for chip design, and configure the parameter space composed of EDA tool parameters;

[0148] Data transmission module, used to input process library files, hardware description language codes of chip design, constraint files and parameter space into DGPSPMBO;

[0149] The data processing module is used to output the chip layout design based on the diversity-guided multi-objective Bayesian optimization framework of DGPSPMBO.

[0150] This algorithm has been verified on multiple open source and industry-authoritative Benchmarks, including AES, be_fe_top, and JPEG. Referring to Table 1, AES is a simple AES (Rijndael) IP core. be_fe_top is the front end of a 64-bit RISC core with a cache consistency directory. JPEG is an encoder core for a video compression system project. The technology node used is Nangate45nm. At the same time, in order to verify the scalability of the algorithm on large designs, experiments were also conducted on BlackParrot. However, since large designs take a lot of time to run VLSI processes, the number of Bayesian optimization samples was reduced.

[0151] Table 1 Circuit scale of benchmarks

[0152]

[0153] All experiments were performed in the open source VLSI full-flow tool OpenROAD-flow-scripts (ORFS). ORFS is a fully autonomous RTL to GDSII flow for rapid architecture and design space exploration, early prediction of QoR quality, and detailed physical design implementation. A variety of platform-, design-, and tool-specific variables are provided in the ORFS flow, enabling finer control and user coverage at each stage of the flow.

[0154] The hardware environment relied on by the experiment is configured as a platform running Ubuntu 22.04.3 system, with a processor core of Intel(R) Core(TM) i5-13600K@5.1GHz and equipped with 128G running memory capacity. In addition, the OpenROAD software version used in the experiment is v2.0-10644-g3187676d8. Python3.9.12, pymoo 0.4.0 and scikit-learn 0.22.2 are used to build a multi-objective Bayesian optimization framework, and the automatic pruning mechanism is implemented by shap 0.45.0.

[0155] The experiment optimized the 20 tool parameters shown in Table 2, taking into account the front-end and back-end stages such as Synthesis, Floorplan, Placement, CTS, and Routing. For Synthesis, the synthesis strategy is considered: area / speed, which is determined by the ABC_AREA parameter. For floorplan, focus on area-related parameters, such as CORE_UTILIZATION, to adjust the core utilization. In the Placement stage, focus on optimizations in timing, congestion, routability, etc., such as GPL_TIMING_DRIVEN specifies whether the placer should use timing optimization-driven layout. Routing focuses on routing resources, such as _FR_LAYER_ADJUST to adjust the layer resources of global routing.

[0156] Table 2 EDA tool parameters

[0157]

[0158] In order to obtain the PPA indicator representing the quality of chip design, the minimum clock cycle, total power and total area of ​​the standard cell are calculated as a percentage relative to the baseline. The baseline results here are obtained using the default parameter values ​​determined by the OpenROAD tool.

[0159] Generally speaking, there are some conflicts in the PPA indicator. In order to comprehensively compare different algorithms, Hypervolume, maximum performance improvement (MPI1), maximum power improvement (MPI2), maximum area improvement (MAI), maximum performance power improvement (MPPI) and maximum performance area improvement (MPAI) are used. MPI1, MPI2 and MAI are the maximum improvements in minimum clock cycle, power consumption and area respectively, which are used to measure the effect of a single goal. MPPI is the maximum improvement of the product of minimum clock cycle and minimum power consumption, and MPAI is the maximum improvement of the product of minimum clock cycle and minimum area, which is used to measure the effect of combining two goals. HV performance,power 、HV performance,area 、HVarea,power They represent performance power HV, performance area HV, and power area HV, respectively. These indicators can evaluate the ability to explore the target subspace. Hypervolume is used to measure the effect of combining all objectives, so that the comparison of various situations is covered. The Hypervolume indicator evaluates the quality of the solution set by measuring the hypervolume occupied by the Pareto optimal solution set. The hypervolume is the volume of the spatial region defined by the boundary of the Pareto optimal solution set. Let is an approximation of the Pareto front in the m-dimensional performance space, and is given by a reference point that usually represents the worst case Hypervolume Defined as

[0160]

[0161] in yes The i-th solution in , ≤ is the objective dominating relation operator, is a Dirac delta function, if z∈H(P f ) is equal to 1, otherwise it is equal to 0. The higher the Hypervolume, The closer to the true Pareto frontier, the more high-quality chip designs are found. The reference point required for calculating Hypervolume is set to [150, 150, 150].

[0162] The specific experiments are as follows:

[0163] The proposed DGPSPMBO algorithm is compared with the multi-objective Bayesian optimization work BO applied in the field of EDA parameter tuning.

[0164] The experimental hyperparameters are set as follows: using the same reference point, parameters, and number of VLSI process runs for each algorithm, the number of initial samples is set to 50, the number of Bayesian optimization process iterations is set to 100, the threshold of the important contribution area is set to 95%, and the stability threshold h is set to 5.

[0165] Tables 3, 4, and 5 show the comparison of DGPSPMBO with the existing methods BO and REMOTune on the aes, bp_fe_top, and jpeg benchmarks. The experimental results show that in all benchmarks, DGPSPMBO achieves better Hypervolume, or HV, than BO and REMOTune. In aes, bp_fe_top, and jpeg, the HV values ​​of the DGPSPMBO method are 6.17%, 13.76%, and 5.77% higher than BO, and 1.61%, 2.12%, and 3.21% higher than REMOTune, respectively.

[0166] In MAI, MPI1, MPI2, MPAI, MPPI, HV performance,power 、HV performance,area 、HV area,power It performs better than BO in terms of evaluation indicators and other indicators, and is also better than REMOTune in most indicators, which shows that DGPSPMBO also performs well in exploring the target subspace.

[0167] At the same time, experimental results show that DGPSPMBO significantly saves running time compared with sequentially optimized BO, saving 49.20%, 53.41%, and 14.05% of running time on aes, bp_fe_top, and jpeg respectively, and is also slightly better than REMOTune.

[0168] Table 3 Comparison of EDA tool parameter adjustment methods on aes Benchmark

[0169]

[0170] Table 4 Comparison of EDA tool parameter adjustment methods on bp_fe_top Benchmark

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[0172]

[0173] Table 5 Comparison of EDA tool parameter adjustment methods on jpeg Benchmark

[0174]

[0175] Table 6 shows the experimental results on the large-scale BlackParrot benchmark. The experimental results show that the HV value of the DGPSPMBO method is 6.63% higher than that of the BO method and 4.5% higher than that of REMOTune.

[0176] Table 6 Comparison of EDA tool parameter adjustment methods on BlackParrot Benchmark In summary, DGPSPMBO benefits from parameter space pruning and can explore more valuable spaces. The diversity-guided Bayesian optimization framework is also extended to parallel optimization, and the search of parameter space is more comprehensive, so that DGPSPMBO obtains better Hypervolume and less running time than other methods. This shows that the proposed DGPSPMBO method can quickly and accurately find a better Pareto optimal set.

[0177] In the algorithm of the present invention, the importance of parameters is quantified by using the interpretable AI method of SHAP value in parameter space pruning, and the values ​​of the correlation length of the covariance determined by the finite difference sequential likelihood ratio test and the GP sequential likelihood ratio test and the automatic correlation can also be used to screen the most contributing parameters. For the strategy of extending the multi-objective Bayesian optimization guided by diversity to parallelization, there are alternatives such as multi-objective trust region Bayesian optimization and expanding the existing acquisition function (such as q-EI).

[0178] The present invention uses explainable AI technology to quantify the impact of parameters on optimization goals, selects important parameters to ensure that optimization is focused on the most effective parameter dimensions, and improves the accuracy of the search. At the same time, a parallel optimization strategy that considers the diversity of parameter space and PPA indicators (performance, power, area) is introduced, and a batch selection mechanism is used to guide exploration in combination with hypervolume improvement indicators. More exploration is performed within a limited running time, making the exploration more complete, so that many EDA tool parameter combinations that can achieve high-quality chip design can be found quickly and accurately.

[0179] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for automatic tuning of EDA tool parameters based on Bayesian optimization, characterized in that: include: Set up process library files, hardware description language code and constraint files for chip design, and configure the parameter space composed of EDA tool parameters; Input the process library file, the hardware description language code of the chip design, the constraint file and the parameter space into DGPSPMBO; The DGPSPMBO outputs chip layout design according to a diversity-guided multi-objective Bayesian optimization framework.

2. The method for automatic tuning of EDA tool parameters based on Bayesian optimization according to claim 1, characterized in that: After setting the process library file, the hardware description language code and constraint file of the chip design, and configuring the parameter space formed by the EDA tool parameters, the method further includes pruning the parameter space to reduce the dimension of the parameter space, specifically: Use SHAP to explain the proxy model and obtain the average absolute value of SHAP for each tool parameter in all samples; Calculate the importance value of each parameter; Setting contribution thresholds; Calculating the contribution value of each parameter according to the importance value; If the contribution value of the current parameter in multiple iterations exceeds the contribution threshold, the current parameter is marked as an important parameter.

3. The method for automatic tuning of EDA tool parameters based on Bayesian optimization according to claim 2, characterized in that: The SHAP interpretation proxy model is used to obtain the SHAP average absolute value of each tool parameter in all samples, including: SHAP's KernelExplainer is used to explain the output of the proxy model and obtain the SHAP average absolute value of each tool parameter k in all samples [SHAP performance , SHAP area SHAP power ] k , used to measure the contribution of each parameter to the PPA index, where the parameter dimension k∈{1,…d}; For PPA indicator j, given the model's predicted value f j (x) and a sample tool parameter vector x = (x1, x2, …, x d ), each parameter x k SHAP value φ k (x) is calculated by the following formula: Where N is the set of all tool parameters {1,2,…,d}; S is a subset of N that does not include parameter k; f j (S) is the model prediction value of target j on parameter subset S; f j (S∪{k}) is the model prediction of target j after adding parameter k to subset S; |S| is the size of subset S, and |N| is the total number of parameters; For the three objectives of performance, area, and power, the tool parameter k is calculated as the SHAP mean absolute value of all samples in the following way: Where n is the number of samples, x i is the instrument parameter vector of the ith sample; |φ k (x i )| j It is the SHAP absolute value of the kth parameter of the ith sample on indicator j, that is, the contribution of tool parameter k to the prediction result of indicator j.

4. The method for automatically tuning EDA tool parameters based on Bayesian optimization according to claim 2, characterized in that: Calculating the importance value of each parameter includes: The average impact of the SHAP value on all PPA metrics is calculated to quantify the overall importance of each parameter on the metric result:

5. The method for automatic tuning of EDA tool parameters based on Bayesian optimization according to claim 2, characterized in that: Calculating the contribution value of each parameter according to the importance value includes: In each iteration, the importance of each input parameter to the PPA indicator is calculated. k ; Calculate the contribution rate of each parameter based on the importance value k , and sort the parameters according to their contribution rate: Where d is the number of parameters in the original parameter space; Determine which parameters fall within the important contribution area, that is, start accumulating from the parameter i with the highest contribution rate, Not greater than the preset value, indicating that parameters i to j, sorted by contribution rate, fall into the important contribution area.

6. The method for automatically tuning EDA tool parameters based on Bayesian optimization according to claim 1, characterized in that: The DGPSPMBO outputs chip layout design based on a diversity-guided multi-objective Bayesian optimization framework, including: The Gaussian process is used to train the proxy model of the objective function; The Pareto front is used to approximate the frontier of the mean function of the Gaussian process extension; A batch selection strategy is adopted to obtain batch points with uniform distribution and hypervolume around the target area according to the output of the Pareto front approximation process.

7. The method for automatically tuning EDA tool parameters based on Bayesian optimization according to claim 6, characterized in that: The use of the Gaussian process model to train the objective function of the proxy model includes: The prior of the Gaussian process is the mean function and kernel function For the characteristics; For a given input variable x, the prior distribution of the Gaussian process is expressed as Use the mean function m(x)=0 and the Matern kernel function to capture various function properties; Train the Gaussian process posterior to improve the prior model by maximizing the log-marginal likelihood logp(y|x,θ) on the available dataset {X, Y}, where θ represents the parameters of the kernel function; The posterior distribution of the Gaussian process is The output is in the form of, where the mean function is μ(x)=m(x)+kK -1 Y, and the covariance function Σ(x)=k(x,x)-kK -1 k T , where k = k(x,X) and K = k(X,X).

8. The method for automatically tuning EDA tool parameters based on Bayesian optimization according to claim 6, characterized in that: The method of using the Pareto front to approximate the frontier of the mean function of the Gaussian process extension includes: Use local optimization methods to obtain a local Pareto optimal solution x for each sample i ; Cover various Pareto frontier areas and explore different optimization directions; Extract x i A first-order approximation of the surrounding Pareto frontier is obtained, and a dense set of solutions is obtained, resulting in a large Pareto optimal region around a single point in the Pareto set.

9. The method for automatic tuning of EDA tool parameters based on Bayesian optimization according to claim 5, characterized in that: The batch selection strategy is used to obtain batch points with uniform distribution and super volume around the target area according to the output of the Pareto front approximation process, including: The selection strategy is expressed as: Where X B ={x1,…,x b } is a set of b samples in a batch, is the current Pareto frontier, for each region Function δ i (.) is defined as belonging to the region From X B Multiple elements x j ; Using a greedy approach, select a point x1 with the largest hypervolume improvement, add x1 to the batch, and Add to current Pareto front Search for the next point with the largest hypervolume improvement, where the current point does not belong to the same region as x1; Repeat the iteration while avoiding all areas of the selected points until all areas are covered; If more points are still needed for the current batch, the counter of the covered region is reset and the same process is repeated to obtain a batch of points {x1, …, x2} that are uniformly distributed around the region and have the highest hypervolume. b }.

10. An EDA tool parameter automatic tuning system based on Bayesian optimization, characterized in that: include: Parameter configuration module, used to set process library files, hardware description language code and constraint files for chip design, and configure the parameter space composed of EDA tool parameters; A data transmission module, used for inputting the process library file, the hardware description language code of the chip design, the constraint file and the parameter space into DGPSPMBO; The data processing module is used for the DGPSPMBO to output the chip layout design according to the diversity-guided multi-objective Bayesian optimization framework.

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