Simulated IC netlist layout collaborative optimization method and system based on reinforcement learning algorithm

Abstract

The invention discloses an analog IC netlist layout collaborative optimization method and system based on a reinforcement learning algorithm, and the method comprises the steps: generating an initial netlist of an analog IC, and inputting the initial netlist into a pre-built simulation platform; generating an analog IC circuit layout according to the initial netlist of the analog IC, and performing simulation through a simulation platform; the reinforcement learning agent builds a graph neural network to execute an optimization task based on a pre-built analog IC netlist multilateral heterogeneous graph, generates an optimized analog IC netlist and sends the optimized analog IC netlist to the simulation platform; a new analog IC circuit layout is generated according to the optimized netlist of the analog IC, the simulation platform simulates the optimized netlist of the analog IC and the new analog IC circuit layout, and the analog IC circuit layout is further optimized through a reinforcement learning agent; and continuously interactively optimizing the reinforcement learning agent and the simulation platform until a final parameter combination meeting the performance index is obtained. According to the invention, the efficiency and performance of circuit optimization are greatly improved.

Description

Technical Field

[0001] The present invention relates to the field of EDA (electronic design automation), and in particular to a method for collaboratively optimizing analog IC netlist layout based on a reinforcement learning algorithm. Background Art

[0002] With the rapid development of integrated circuit technology, the core position of analog IC (integrated circuit) in the fields of communication, medical treatment, automotive electronics and consumer electronics has become increasingly prominent. The performance of analog IC often directly determines the quality and reliability of the entire system, so its design process has extremely high requirements for the accuracy and efficiency of parameter optimization. In the traditional analog IC design process, the generation and optimization of circuit size mainly rely on the experience of design engineers or heuristic algorithms. However, the experience-driven optimization method not only requires designers to have rich professional knowledge and practical experience, but is also easily affected by human factors, and has the disadvantages of strong subjectivity, low repeatability and difficulty in large-scale promotion. Although the heuristic algorithm can achieve a certain degree of parameter optimization, its essence is based on the rule preset of local search, lacks a global perspective, and has limited processing capabilities for complex multi-objective optimization tasks. At the deep submicron process node, the nonlinear effects and parasitic parameters of the device further increase the design difficulty, making the traditional method face major bottlenecks in optimization efficiency and optimization effect, and it is difficult to meet the needs of modern analog IC for high-performance and high-precision design.

[0003] At the same time, with the development of machine learning and artificial intelligence technology, a large number of data-driven circuit design and optimization methods have emerged. However, the premise of such methods is that a large amount of high-quality annotated data is needed as a training set, and the strong correlation and complexity between analog IC layout and netlist make manual annotation an extremely time-consuming and error-prone process, which is not only inefficient, but also may introduce human differences and affect the training effect of the model. Especially in layout and wiring collaborative design, the coordinates, dimensions and associated information annotation of devices often involve multiple levels and multiple data types. It is difficult to meet actual production needs by manually completing these tasks alone. Therefore, how to effectively combine intelligent algorithms in circuit optimization, and at the same time develop efficient layout netlist data annotation methods to achieve high-performance parameter optimization and rapid generation of large-scale data sets has become a key issue that needs to be urgently solved in the current analog IC design field. Summary of the invention

[0004] The main purpose of the present invention is to provide an analog IC netlist layout collaborative optimization method and system based on a reinforcement learning algorithm, so as to improve the efficiency and performance of circuit optimization, reduce the dependence on manual participation, and significantly shorten the design cycle.

[0005] The technical solution adopted by the present invention is:

[0006] A method for collaborative optimization of analog IC netlist layout based on a reinforcement learning algorithm is provided, characterized in that it includes the following steps:

[0007] Select a specified type of IC circuit and use an open source circuit schematic editor to generate and export the initial netlist of the analog IC;

[0008] Inputting the initial netlist of the analog IC into a pre-built simulation platform, and inputting the netlist simulation results into a pre-built reinforcement learning agent whose reward function is associated with the performance indicators of the analog IC;

[0009] Generate an analog IC circuit layout based on the initial netlist of the analog IC, simulate it through the simulation platform, and input the layout simulation results into the reinforcement learning agent;

[0010] The reinforcement learning agent builds a graph neural network to perform optimization tasks based on the pre-built analog IC netlist multi-sided heterogeneous graph, generates an optimized analog IC netlist and sends it to the simulation platform; the construction process of the analog IC netlist multi-sided heterogeneous graph is as follows: define different types of nodes of the heterogeneous graph according to the initial netlist of the analog IC, extract corresponding node features according to different node types, generate nodes of the analog IC netlist heterogeneous graph, node feature matrix and edge type matrix, and finally generate the analog IC netlist multi-sided heterogeneous graph based on signal flow recognition;

[0011] A new analog IC circuit layout is generated according to the optimized analog IC netlist. The simulation platform simulates both the optimized analog IC netlist and the new analog IC circuit layout, and outputs the generated new simulation results to the reinforcement learning agent to further optimize the analog IC circuit layout.

[0012] The reinforcement learning agent and the simulation platform continuously interact and optimize until the final parameter combination that meets the performance indicators is obtained, and the optimized circuit parameters and corresponding netlist files are output for subsequent design and manufacturing.

[0013] Following the above technical solution, the optimization target is determined based on the performance indicators, and combined with the constraints, the two are converted into corresponding parameters and associated with the reward function of the reinforcement learning agent; among which, the performance indicators include gain, bandwidth, phase margin and common mode rejection ratio, and the constraints include specific power consumption, area and size.

[0014] Following the above technical solution, when building a simulation platform, the simulation environment settings are also performed, including simulation mode, simulation temperature, simulation parameters and simulation output item units.

[0015] Following the above technical solution, the analog IC circuit layout is specifically generated based on a heuristic algorithm, including a simulated annealing layout algorithm and an A* routing algorithm. In the layout stage, the layout is optimized through the simulated annealing algorithm and the layout tree; in the routing stage, the path search is performed based on the A* algorithm, and the connection plan between devices is finally generated by gradually exploring the path and selecting the path with the lowest cost.

[0016] In addition to the above technical solution, the A* routing algorithm also dynamically adjusts the strategy according to the complexity of routing to avoid path crossing and blocking, and optimize the signal transmission quality and layout density of the entire layout.

[0017] Following the above technical solution, the reinforcement learning agent interacts repeatedly with the simulation platform, uses the Actor network to output the circuit parameter strategy distribution, uses the Critic network to evaluate the strategy quality, and combines random exploration and goal-oriented optimization strategies to continuously adjust the network weights and gradually converge to the optimal parameters.

[0018] According to the above technical solution, the node types of the heterogeneous graph include m nodes representing MOSFET transistors, c nodes representing capacitors, and v nodes representing voltages, and different parameters are extracted from different types of nodes as node features.

[0019] Following the above technical solution, the transistor size in the analog IC circuit layout is specifically optimized.

[0020] The present invention also provides an analog IC netlist layout collaborative optimization system based on a reinforcement learning algorithm, comprising:

[0021] An open source schematic editor for generating and exporting netlists of analog ICs based on the selected IC type.

[0022] An analog IC circuit layout generator is used to generate an analog IC circuit layout according to an analog IC netlist;

[0023] The analog IC netlist multi-edge heterogeneous graph generator is used to define different types of nodes of the heterogeneous graph according to the analog IC netlist, and extract corresponding node features according to different node types, generate nodes, node feature matrix and edge type matrix of the analog IC netlist heterogeneous graph, and finally generate the analog IC netlist multi-edge heterogeneous graph based on signal flow recognition;

[0024] The simulator is used to pre-build a simulation platform and perform simulation verification, specifically to simulate and verify the netlist of the analog IC, generate netlist simulation results, and to simulate and verify the circuit layout of the analog IC, generate layout simulation results; and the simulator inputs the simulation results into the optimization module;

[0025] The optimization module is used to pre-build a reinforcement learning agent, whose reward function is associated with the performance indicators of the analog IC; the reinforcement learning agent builds a graph neural network to perform optimization tasks based on the acquired netlist simulation results and layout simulation results, and generates optimized analog IC parameters and corresponding netlist files based on the pre-built analog IC netlist multilateral heterogeneous graph; the reinforcement learning agent and the simulation platform continuously interact and optimize until the final parameter combination that meets the performance indicators is obtained, and outputs the optimized circuit parameters and corresponding netlist files for subsequent design and manufacturing.

[0026] Following the above technical solution, the analog IC circuit layout generator specifically generates the analog IC circuit layout based on a heuristic algorithm. The heuristic algorithm includes a simulated annealing layout algorithm and an A* wiring algorithm. In the layout stage, layout optimization is performed through the simulated annealing algorithm and the layout tree; in the wiring stage, path search is performed based on the A* algorithm, and the connection plan between devices is finally generated by gradually exploring the path and selecting the path with the lowest cost.

[0027] The present invention also provides a computer storage medium, which stores a computer program that can be executed by a processor, and the computer program executes the analog IC netlist layout collaborative optimization method based on the reinforcement learning algorithm described in the above technical solution.

[0028] The beneficial effects of the present invention are as follows: the present invention optimizes the generated analog IC circuit layout by introducing a reinforcement learning agent, which does not rely on manual experience and preset rules, and can achieve efficient layout optimization in complex optimization scenarios with multiple objectives and multiple constraints; and through two simulations of the netlist and the layout, the simulation results are used as a component of the feedback obtained by the reinforcement learning agent, and the simulation platform dynamically interacts with the reinforcement learning agent to continuously optimize the layout and narrow the difference between the two simulation results, thereby collaboratively optimizing and improving the integration and performance of the circuit design, ensuring that the circuit layout can effectively reduce the wiring complexity and power consumption while meeting the process constraints, and reduce the impact of parasitic effects on chip performance.

[0029] Furthermore, by constructing a heterogeneous graph through multi-terminal device nodes and signal flow identification, the circuit topology characteristics and signal transmission rules are accurately captured, effectively improving the optimization algorithm's predictive ability and convergence speed for circuit performance; the reinforcement learning agent continuously updates and optimizes the weights of the strategy network and evaluation network through dynamic interaction with the simulation platform, and can automatically learn the optimal design parameters suitable for different circuit topologies and performance requirements.

[0030] Furthermore, the present invention also has significant advantages in circuit layout generation. The layout and wiring optimization strategy based on reinforcement learning can not only automatically optimize the circuit size, but also generate a circuit layout that matches the size optimization. In the layout stage, the simulated annealing algorithm is used to optimize the position of the device to ensure the minimum spacing and reasonable layout between devices; in the wiring stage, the A* algorithm is used to optimize the connection path to ensure the efficiency of signal transmission and reduce signal interference. Compared with traditional heuristic methods, the present invention has stronger global search capabilities and generalization capabilities, greatly improving the efficiency and performance of circuit optimization, while reducing dependence on manual participation, significantly shortening the design cycle, and providing an efficient and intelligent optimization solution for analog IC circuit design.

[0031] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0033] Figure 1A It is a flow chart of a method for collaborative optimization of analog IC netlist layout based on a reinforcement learning algorithm according to an embodiment of the present invention;

[0034] Figure 1B It is a schematic diagram of the framework flow of the analog IC netlist layout collaborative optimization method based on the reinforcement learning algorithm according to an embodiment of the present invention;

[0035] Figure 2 A schematic diagram of constructing a multi-sided heterogeneous graph neural network for simulating an IC netlist according to an embodiment of the present invention;

[0036] Figure 3 A schematic diagram of a layout generated by a layout generator based on a heuristic algorithm according to an embodiment of the present invention;

[0037] Figure 4 Schematic diagram of the interaction between the reinforcement learning agent and the environment in an embodiment of the present invention. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0039] It should be noted that the illustrations provided in the embodiments of the present invention are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout type may also be more complicated.

[0040] In the present invention, it is also necessary to explain that, if the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, if the terms "first" and "second" appear, they are only used for description and distinction purposes, and cannot be understood as indicating or implying relative importance.

[0041] In addition, it should be noted that the features of the various embodiments of the present invention may be combined or combined in part or in whole, and may interact and operate in different ways as will be appreciated by those skilled in the art. Each embodiment may be implemented independently of one another, or in an associated relationship.

[0042] like Figure 1A As shown, the analog IC netlist layout collaborative optimization method based on the reinforcement learning algorithm of the embodiment of the present invention includes the following steps:

[0043] S1. Select a specified type of IC circuit, use an open source circuit schematic editor to generate and export the initial netlist of the analog IC;

[0044] S2, inputting the initial netlist of the analog IC into a pre-built simulation platform, and inputting the netlist simulation results into a pre-built reinforcement learning agent, the reward function of which is associated with the performance index of the analog IC;

[0045] S3, generating an analog IC circuit layout according to the initial netlist of the analog IC, simulating it through a simulation platform, and inputting the layout simulation results into the reinforcement learning agent;

[0046] S4. The reinforcement learning agent builds a graph neural network to perform optimization tasks based on the pre-built analog IC netlist multi-sided heterogeneous graph, generates an optimized analog IC netlist and sends it to the simulation platform; the construction process of the analog IC netlist multi-sided heterogeneous graph is as follows: define different types of nodes of the heterogeneous graph according to the initial netlist of the analog IC, extract corresponding node features according to different node types, generate nodes of the analog IC netlist heterogeneous graph, node feature matrix and edge type matrix, and finally generate the analog IC netlist multi-sided heterogeneous graph based on signal flow recognition;

[0047] S5. Generate a new analog IC circuit layout according to the optimized analog IC netlist. The simulation platform simulates both the optimized analog IC netlist and the new analog IC circuit layout, and outputs the generated new simulation results to the reinforcement learning agent to further optimize the analog IC circuit layout.

[0048] S6. The reinforcement learning agent and the simulation platform continuously interact and optimize until the final parameter combination that meets the performance indicators is obtained, and the optimized circuit parameters and corresponding netlist files are output for subsequent design and manufacturing.

[0049] It can be seen that this embodiment of the present invention optimizes the generated analog IC circuit layout by introducing a reinforcement learning agent, which does not rely on manual experience and preset rules, and can achieve efficient layout optimization in complex optimization scenarios with multiple objectives and multiple constraints; and through two simulations of the netlist and the layout, the simulation results are used as a component of the feedback obtained by the reinforcement learning agent, and the simulation platform and the reinforcement learning agent dynamically interact to continuously optimize the layout and narrow the difference between the two simulation results, thereby collaboratively optimizing and improving the integration and performance of the circuit design, ensuring that the circuit layout can effectively reduce the wiring complexity and power consumption while meeting the process constraints, and reduce the impact of parasitic effects on chip performance.

[0050] When setting up the analog IC netlist simulation platform and the simulation environment, it is necessary to select a process design kit (PDK Process Design Kit) of a specified design process, and select a specified type of circuit, and use the open source circuit schematic editor xschem to generate and export the initial netlist. For example, in the use case of the present invention, the specified PDK is a commercial 130nm PDK, and the specified circuit type is an OTA circuit. It is necessary to select each device in the netlist in the process design library according to the circuit design requirements. For example, in the case of the present invention, including PMOS / NMOS and other types of devices, select each device in the PDK process library. Next, according to the selection of each device and the circuit design requirements, a customized simulation platform is built for a single analog IC netlist. In the use case of the present invention, the gate voltage rating of the device selected for NMOS / PMOS is 5V, and the drain voltage rating is 10.5V. It is suitable for high-voltage circuit design, so the highest bit voltage VDD in the simulation environment is set to 5V. At the same time, for the OTA circuit, four key performance indicators are designed: gain / CMRR / bandwidth / PM (phase margin). In the use case of the present invention, an external circuit for simulation is built and the load capacitor is connected. Through the above steps, the simulation process of the above four key indicators can be fully opened for each circuit parameter solution generated during the optimization process, that is, the simulation platform construction and simulation environment setting of the analog IC netlist are completed.

[0051] The generation of the multi-sided heterogeneous graph of the analog IC netlist based on signal flow recognition is mainly combined with the analog IC netlist to define different types of nodes for the heterogeneous graph. The node types included in the selected case are m (mosfet transistor), c (capacitor), and v (voltage). Different parameters are extracted for different types of nodes as node features. Further explanation is given based on the above rules: in multi-terminal devices, transistors contain 4 ports, and capacitors contain two ports. Each port is defined as a node, and the node type is determined by the device type. In this case, there are 13 node features extracted, which can form a node observation value matrix of 13 nodes. The features extracted from m-type nodes include: id (drain current) / gm (transconductance) / vth (threshold voltage) / vdsat (saturation voltage) / vds (drain-source voltage) / vgs (gate-source voltage) / gds (drain-on conductance), the features extracted from c-type nodes include: capacitance (capacitance value) / w (capacitor width) / l (capacitor length) / m (number of capacitors in parallel), and the features extracted from v-type nodes include the voltage value and current value of the point. The above information is further integrated to complete the establishment of the nodes and node feature matrix of the simulated IC netlist heterogeneous graph.

[0052] The generation of the multi-sided heterogeneous graph of the analog IC netlist based on signal flow recognition is mainly based on the establishment of the nodes and node feature matrix of the heterogeneous graph of the above-mentioned analog IC netlist, and further builds the edges and edge feature matrix of the heterogeneous graph. First, according to the analog IC netlist, the nodes with connection relationships are recorded. For example, in the case selected by the present invention, node 0 is the drain of transistor MM0, and node 6 is the source of transistor MM1. It can be obtained from the netlist that there is a connection relationship between node 0 and node 6, and the signal path connecting the two nodes is net6, so it is necessary to record this edge as [0,6], [6,0]. From this rule, the connection relationship between all nodes can be written. In the OTA circuit selected by the present invention, there are a total of 33 nodes and 48 edges. The above information is further integrated to complete the establishment of the edge set of the heterogeneous graph of the analog IC netlist. Combined with the simulation results, the signal path analysis is performed on each edge in turn to determine whether the path passes a DC signal or an AC information in the AC simulation environment. The two results are numbered separately to establish an edge type matrix. For example, in the case selected in the present invention, 48 edges are judged in turn, the DC signal path is marked as 1, the AC signal path is marked as 0, and an edge type matrix containing 48 0 / 1s is established.

[0053] When building an analog IC circuit layout generator based on a heuristic algorithm, as in the case used in the present invention, an OTA circuit commercial 130nm PDK is used. The present invention uses a heuristic algorithm to generate an analog IC circuit layout, specifically including a simulated annealing layout algorithm and an A* wiring algorithm. First, in the layout stage, the input includes a circuit netlist, device type and size restrictions, design rules (such as minimum spacing, power requirements, etc.), and process parameters (such as device size, gate oxide thickness, etc.) provided in a process design kit (PDK). Based on these inputs, layout optimization is performed by a simulated annealing algorithm and a B-tree (layout tree). A B-tree is a bottom-up tree data structure used to manage the location and layout relationship of devices. In the layout stage, each device is a node in the B-tree, where the characteristics of the node include information such as device type (such as NMOS, PMOS, capacitor, etc.), device size, and location constraints (such as minimum spacing). The simulated annealing algorithm gradually searches for the global optimal layout solution by randomly adjusting the device node position and calculating the cost function. The cost function includes factors such as the minimum spacing between devices, the distribution of power and ground wires, and the compactness of the circuit layout. The output of the layout phase is the final specific location of the device on the chip, and it ensures that all design rules are met. Next, in the routing phase, the input is the optimized device layout, the connection information between nodes (power grid and signal path), and the design rule constraints (such as wiring width, number of wiring layers, path congestion, etc.). The routing algorithm searches for paths based on the A* algorithm, and the cost function of each path comprehensively considers factors such as connection length, wiring density, signal interference, and the minimum distance between devices. In the A algorithm, the starting point and the end point are the device ports that need to be connected, and the heuristic function calculates the estimated cost from the current node to the target node. The A* algorithm gradually explores the path and selects the path with the lowest cost, and finally generates a connection plan between devices. The output of the routing phase is the final connection path, ensuring that each port is connected correctly and the path is optimal, while meeting the process rule requirements (such as minimum width, minimum spacing, shortest path, etc.). In addition, the A* algorithm will dynamically adjust the strategy according to the complexity of the routing to avoid path intersection and blocking, and optimize the signal transmission quality and layout density of the entire layout. By combining simulated annealing layout and A* routing algorithm, the present invention can automatically generate the optimal IC layout, and ensure the rationality and process compatibility of the physical layout while meeting the requirements of electrical performance (such as gain, bandwidth, common mode rejection ratio, phase margin). After the analog IC circuit layout generation part is realized, it is associated with the analog IC netlist simulation platform construction and simulation environment setting in the previous step to ensure that each generated layout can perform correct spice simulation, and the simulation results will be used as a component of the feedback obtained by the reinforcement learning agent.

[0054] When automatically optimizing analog IC netlist circuit parameters, first, determine the optimization goals (such as gain, bandwidth, phase margin, and common mode rejection ratio, etc.) and constraints (such as power consumption, area, sizing legal range, etc.) according to the performance requirements of the analog IC circuit, parameterize these goals and constraints, and set the reward function of the reinforcement learning agent. The reward function mainly consists of three parts: netlist simulation results, layout simulation results, and the difference between the previous and next simulations; then, build a circuit simulation environment based on a real SPICE simulation platform. By coupling the simulation platform with the reinforcement learning framework, the agent can interact with the simulation environment. Two circuit simulations will be performed between each two interactions to obtain circuit performance feedback in the form of a reward function; then, based on SAC (Software Application Programming), the agent can automatically optimize the circuit parameters of the analog IC netlist circuit. First, determine the optimization goals (such as gain, bandwidth, phase margin, and common mode rejection ratio) and constraints (such as power consumption, area, sizing legal range, etc.). Then, parameterize these goals and constraints, and set the reward function of the reinforcement learning agent. The reward function mainly consists of three parts: netlist simulation results, layout simulation results, and the difference between the previous and next simulations; then, build a circuit simulation environment based on a real SPICE simulation platform. By coupling the simulation platform with the reinforcement learning framework, the agent can interact with the simulation environment. Two circuit simulations will be performed between each two interactions to obtain circuit performance feedback in the form of a reward function; then, based on SAC (Software Application Programming), the agent can automatically optimize the circuit parameters of the analog IC netlist circuit. Then, the agent can automatically optimize the circuit parameters of the analog IC netlist circuit. The Actor-Critic algorithm is used to construct a reinforcement learning agent. The agent repeatedly interacts with the simulation platform, uses the Actor network to output the distribution of circuit parameter strategies, and the Critic network to evaluate the strategy quality. It combines random exploration and goal-oriented optimization strategies to continuously adjust the network weights and gradually converge to the optimal parameters. At the same time, a heterogeneous graph neural network with multi-terminal device nodes and signal flow recognition is used to optimize the circuit topology modeling. The network effectively captures the topological characteristics and signal transmission laws of the circuit through a structure containing different types of nodes (such as transistor nodes, power nodes, etc.) and edges (such as DC signal edges, AC signal edges), and extracts the implicit relationship between circuit parameters and performance, further guiding the strategy optimization of the agent. Finally, a new circuit netlist is generated according to the parameter strategy output by the agent and simulated and verified. The verification results are fed back to the reinforcement learning model for continuous optimization until the final parameter combination that meets the performance requirements is obtained, and the optimized circuit parameters and corresponding netlist files are output for subsequent design and manufacturing.

[0055] Among them, for the reward function:

[0056] reward = α * performance_score post-target +β*gap_score post-pre

[0057]

[0058] α and β are weights. Reward needs to ensure that the performance index of the layout meets the standard and the difference with the previous imitation is as small as possible. performance_score post-target This item is a performance indicator, and obviously the larger the better. gap_score post-per This item is the difference between the before and after simulation. We hope that it is as close to 0 as possible. However, the actual performance of the after-imitation cannot exceed the performance of the before-imitation. That is, this item is likely to be negative. We hope that it is close to 0, that is, we hope that this item is as large as possible. The reward for this optimization should be as large as possible.

[0059] The main reason why the present invention selects SAC (a kind of Soft Actor-Critic reinforcement learning algorithm) for transistor parameter optimization algorithm is that it can take into account stability and efficiency. As a reinforcement learning algorithm, SAC has the advantages of stability and efficiency. Compared with traditional algorithms, SAC introduces an entropy regularization term to enable the strategy to maintain a certain randomness during the optimization process, avoiding premature convergence to the local optimal solution, thereby ensuring the breadth of the exploration process. This is especially important for the optimization of transistor size parameters involved in OTA circuit optimization, because circuit performance is affected by many factors. If it falls into the local optimal solution too early, other potential optimal solutions may be missed. Through continuous exploration and optimization, SAC can ensure that the global optimal parameter configuration is found. SAC has excellent convergence, and SAC shows excellent convergence when facing complex high-dimensional continuous action space. It controls the entropy of the strategy through temperature parameters, balancing the exploration and convergence speed, so that the algorithm can converge to the optimal solution more smoothly. In the transistor size optimization of OTA circuits, the complexity and nonlinearity of the parameter space require the algorithm to converge stably and quickly. SAC, with its excellent convergence performance, can effectively avoid the problem of slow convergence or unstable training, and ensure that the best solution is found within a limited number of training steps. SAC can be well combined with graph neural networks, and has a high degree of matching with the problem of dealing with analog circuits. In SAC, graph neural networks (GNNs) are combined, so that the circuit optimization process can more efficiently model the relationship between the components in the circuit. The transistors and other components in the OTA circuit can be regarded as a graph structure. The graph neural network can extract the complex interaction relationship between the components in the circuit through multiple convolutional layers, providing more accurate feedback for the optimization process. This enables SAC to adjust the size parameters of the transistor more efficiently, thereby optimizing the circuit performance. In addition, SAC is a strong algorithm for dealing with continuous action space problems. In the optimization of OTA circuit transistors, the size of the transistor (such as width W and length L) is continuous, and traditional reinforcement learning algorithms may face certain difficulties in dealing with such continuous action spaces. SAC can fine-tune parameters in a continuous space to ensure that every action in the optimization process can effectively improve circuit performance, which is particularly critical for transistor size adjustment in OTA circuits. SAC also has excellent multi-objective optimization capabilities. In OTA circuit optimization, not only the gain needs to be considered, but also multiple performance indicators such as bandwidth, PSRR (power supply rejection ratio), and phase margin need to be optimized simultaneously. SAC can perform well in multi-objective optimization and achieve performance balance by adjusting the weights of different objectives. This enables SAC to ensure that multiple objectives are reasonably optimized when optimizing transistor size, rather than being limited to a single objective. SAC can avoid local optimal solutions and overfitting. SAC's entropy regularization mechanism effectively avoids the risk of falling into local optimal solutions and overfitting too early.The optimization of OTA circuits requires careful adjustments in a wide range of parameter spaces. If the algorithm is too biased towards a fixed solution, it may lead to poor optimization results. SAC's strategy update method can ensure that the algorithm remains sufficiently exploratory during the training process, avoiding this situation and thus improving the robustness of the optimization.

[0060] The present invention introduces a circuit size optimization method based on reinforcement learning, utilizes an innovative design combining a SAC (Soft Actor-Critic) algorithm and a heterogeneous graph neural network, does not rely on artificial experience and preset rules, and can achieve efficient circuit parameter search and optimization in complex optimization scenarios with multiple objectives and multiple constraints. By constructing a heterogeneous graph through multi-terminal device nodes and signal flow identification, the circuit topology characteristics and signal transmission rules are accurately captured, and the prediction ability and convergence speed of the optimization algorithm for circuit performance are effectively improved; the reinforcement learning agent continuously updates and optimizes the weights of the strategy network and the evaluation network through dynamic interaction with the simulation platform, and can automatically learn the optimal design parameters suitable for different circuit topologies and performance requirements. Compared with traditional optimization methods, the present invention also has significant advantages in circuit layout generation. The layout and wiring optimization strategy based on reinforcement learning can not only automatically optimize the circuit size, but also generate a circuit layout that matches the size optimization. In the layout stage, the simulated annealing algorithm is used to optimize the position of the device to ensure the minimum spacing and reasonable layout between the devices; in the wiring stage, the A* algorithm is used to optimize the connection path to ensure the efficiency of signal transmission and reduce signal interference. The integration and performance of circuit design are improved through collaborative optimization, ensuring that the circuit layout can effectively reduce wiring complexity and power consumption while meeting process constraints, and reduce the impact of parasitic effects on chip performance. Compared with traditional heuristic methods, the present invention has stronger global search and generalization capabilities, greatly improving the efficiency and performance of circuit optimization, while reducing dependence on manual participation, significantly shortening the design cycle, and providing an efficient and intelligent optimization solution for analog IC circuit design.

[0061] The size of transistors has a significant impact on circuit performance. The size of transistors (such as width W, length L, and magnification M) directly determines the working characteristics of the circuit, including important performance indicators such as gain, power consumption, bandwidth, and common mode rejection ratio (CMRR). For example, for a common-emitter amplifier circuit, the gain of the circuit is directly determined by the formula: gm*RL / (1+gm*RL). By adjusting the size of the transistor, these performance indicators can be effectively adjusted to meet the design goals. In addition, transistor size adjustment is flexible, and transistor size adjustment is a common and flexible method in circuit design. For example, transistor size optimization can adapt to different process nodes (such as 180nm, 90nm, 45nm, etc.). There are clear differences in the legal range of transistor size at different process nodes. By modifying the width and length of the transistor, the performance of the circuit can be adjusted at different process nodes and under different working conditions, especially in the design optimization process. Reinforcement learning can gradually adjust the transistor size based on actual simulation feedback so that the various performance indicators of the circuit tend to the target.

[0062] Reference Figure 1B , analog IC circuit size optimization method, the input includes the analog IC initial netlist, the circuit size parameters at this time should be the default parameters of the process library device model when drawing the circuit diagram, and the input should also include the performance goals to be completed, which include two parts: circuit performance goals and non-violation device size legalization goals. For example, the current OTA circuit sets four performance indicators as the performance goals of the optimization algorithm, the front and back simulation difference indicators are as close to zero as possible, and the legalization range of the selected device model is added as the optimization goal as follows:

[0063]

[0064] By constructing and extracting feature vectors through the multilateral heterogeneous graph neural network of the simulated IC netlist, the optimal solution for the device size is found through the interaction between the SAC agent and the environment based on the simulation platform, and finally an optimization method for the analog IC circuit size is realized.

[0065] Among them, Gain: Gain, which measures the circuit's ability to amplify signals, is calculated as follows: The differential circuit calculation formula is:

[0066] CMRR: Common mode rejection ratio, which measures the circuit's ability to suppress common mode signals. A higher CMRR means the circuit can effectively suppress common mode noise and improve signal quality. The differential circuit calculation formula is:

[0067]

[0068] PM: Phase margin, which refers to the difference between the system phase and -180° at the crossover frequency of the system open-loop gain. The calculation method of the differential circuit is: 1. Measure the frequency point when the gain is 1 (0db) 2. Find the phase at this frequency point 3. The phase plus 180 is the PM value.

[0069] Bandwidth: Bandwidth is the frequency range in which a circuit can effectively amplify a signal. It is usually defined as the frequency range where the gain drops to -3dB of the maximum gain. The calculation method for the differential circuit is: 1) find the frequency point with maximum gain as the upper limit; 2) find the frequency point with -3db of the gain point as the lower limit; 3) the distance between the upper and lower limits is the bandwidth value.

[0070] Reference Figure 2, the construction of the multi-sided heterogeneous graph neural network of the simulated IC netlist is shown in the figure. For example, the current OTA circuit includes 7 transistors and 1 capacitor. The nodes are divided into three categories, namely m-type nodes (transistors), c-type nodes (capacitors) and v-type nodes (power supplies). For multi-terminal devices such as transistors and capacitors, each port of the device is treated as a separate node, and the node type is the same as the device type, thus obtaining 33 nodes including three types of nodes. Next, the node features of different types of nodes are defined as observation values. The m-type node has 7 features (id / gm / gds / vth / vdsat / vds / vgs), the c-type node has 4 features (capacitance / w / l / m), and the v-type node has 2 features (v / i). Therefore, a 33*13 feature matrix is ​​constructed. Each row of the matrix is ​​a node, and each row has 13 parameters, including the feature values ​​of the three types of nodes. Next, a heterogeneous edge and edge feature matrix is ​​constructed for the current OTA circuit, and the connection relationship contained in the initial netlist is read. Taking the specific case selected by the present invention as an example, in the circuit structure of this case, there are nodes 0 and 6. Among them, node 0 is the drain of transistor MM0, and node 6 is the source of transistor MM1. Through in-depth analysis and interpretation of the analog IC netlist, it can be clearly known that there is a specific connection relationship between node 0 and node 6. Further exploration shows that the signal path formed by the connection of the two nodes is marked as net6. This signal path is of great significance in the signal transmission and function realization of the circuit. In view of the importance of this connection relationship in circuit analysis, it needs to be recorded. Specifically, the edge to be recorded is presented in the form of a node pair, namely [0,6] and [6,0]. This recording method can clearly reflect the bidirectional connection characteristics between the two nodes, and provide accurate data support for subsequent circuit topology analysis, fault diagnosis and other related circuit research work. According to this rule, the connection relationship between all nodes contained in the initial netlist is read, a total of 48. After completing the record of the node connection relationship in the analog IC netlist, it is necessary to carry out further in-depth analysis in combination with the corresponding simulation results. Specifically, a detailed signal path analysis is performed for each recorded edge. This analysis process is carried out in an AC (alternating current) simulation environment, aiming to accurately determine whether the signal path corresponding to each edge passes through a DC signal or an AC information. In order to clearly distinguish and manage these two different types of signal paths, they will be assigned specific numbers respectively. For the two different results of the DC signal path and the AC signal path, this numbering method can facilitate subsequent data processing and analysis. On this basis, an edge type matrix is ​​to be established, which will serve as an important data structure for storing and displaying the signal type information of each edge. Taking the case selected by the present invention as an example, in this specific case, there are a total of 48 edges.These 48 edges need to be carefully judged one by one. In the judgment process, if a DC signal passes through the signal path of an edge, it is marked as 1; if an AC signal passes through the signal path of an edge, it is marked as 0. In this way, an edge type matrix containing 48 elements (0 or 1) can be constructed. This edge type matrix can comprehensively and intuitively reflect the signal type characteristics of all edges in the AC simulation environment, providing key data basis for subsequent in-depth research on the performance, working status and possible problems of the circuit under different signal types, which helps to further optimize the workflow related to circuit design and analysis.

[0071] refer to Figure 3 , the layout is generated for an OTA circuit containing 7 transistors and 1 capacitor. The circuit netlist is consistent with the netlist in the previous question, including 7 transistors (m-type nodes), 1 capacitor (c-type node), and the corresponding power supply (v-type node). The PDK used is a commercial 130nm PDK, which provides multiple level definitions, covering process constraints from metal layers to ground layers, isolation layers, etc. During the layout generation process, the number of layers and the definitions of each layer are strictly carried out according to the requirements of the PDK. The layout generation process follows a series of heuristic algorithms. During the layout process, the present invention automatically extracts the matching constraint relationship of each device in the circuit to ensure that the generated layout meets the performance requirements and design rules of the circuit. Specifically, the system automatically identifies and extracts the matching constraint relationship by analyzing the relative position and electrical characteristics between transistors and other devices in the netlist. For example, in the present invention, there is a specific matching relationship between transistor M0 and transistor M1, transistor M2 and transistor M4, that is, their size, layout and electrical performance need to meet certain constraints, such as the relative matching of width-to-length ratio (W / L), to ensure the consistency of key performance indicators such as gain and CMRR of the circuit. In the wiring stage, the A* algorithm is used to plan the connection between transistors, between transistors and capacitors, and between power supplies and other parts of the circuit. By dynamically adjusting the wiring path and the connection sequence, the signal transmission path is optimized to ensure the reliability of signal transmission in the circuit and minimize noise interference. At this stage, according to the metal layer design rules of PDK, it is also ensured that the connection width, spacing, etc. meet the design rules to avoid short circuits and excessive resistance losses.

[0072] refer to Figure 4 ,The optimization of analog IC circuit size is achieved in the context of the interaction between the intelligent agent (SAC agent) and the specific environment built based on the simulation platform. In order to ensure the scientificity and effectiveness of the simulation platform, the ngspice simulator is selected as its important component. The ngspice simulator has the characteristics of high precision and wide applicability, and can accurately simulate the operating state of the circuit under different conditions.

[0073] At the same time, the present invention also specially builds a powerful simulation result analyzer. The main task of this analyzer is to conduct a comprehensive and in-depth analysis of the simulation results of the four circuit performances in the netlist simulation and layout simulation steps. These four circuit performances cover key indicators such as signal gain, frequency response, power consumption and noise. Through the detailed analysis of these indicators by the analyzer, reliable data support and decision-making basis can be provided for the optimization of circuit size, thereby further improving the performance and reliability of analog IC circuits. It is implemented in the interaction between the SAC agent and the environment based on the simulation platform. The ngspice simulator is selected as an important part of the simulation platform, and a simulation result analyzer is built to analyze the simulation results of the four circuit performances, and finally the performance results are obtained. The current reward is calculated according to the reward formula: reward = α*performance_score post-target +β*gap_score post-pre

[0074]

[0075] α and β are weights, and the calculation results are passed into the agent as input.

[0076] Based on the advanced SAC (Soft Actor-Critic) algorithm, a reinforcement learning agent is constructed, which plays a core role in the entire optimization process. It interacts repeatedly and deeply with the simulation platform, which is a key link in achieving circuit optimization. In this process, the Actor network in the agent is responsible for outputting the policy distribution of circuit parameters, while the Critic network accurately evaluates the policy quality and provides a basis for parameter adjustment. At the same time, the agent cleverly combines random exploration and goal-oriented optimization strategies. Random exploration explores possible hidden better solutions; the goal-oriented optimization strategy ensures that the optimization always moves towards the goal of meeting performance requirements. Through the synergy of these two strategies, the agent continuously fine-tunes the network weights, and in this step-by-step iterative process, the parameters gradually converge to the optimal state. In addition, in order to further optimize the circuit, a heterogeneous graph neural network with multi-terminal device nodes and signal flow recognition is used to model the circuit topology. This network has a unique structure, which contains various types of nodes, such as transistor nodes, power supply nodes, etc. At the same time, there are also DC signal edges, AC signal edges and other types of edges, which together constitute a complete information transmission network. Through this unique structure, heterogeneous graph neural networks can effectively capture the complex topological characteristics and signal transmission rules of circuits. Moreover, it can also dig out the deeply hidden implicit relationships between circuit parameters and performance. These valuable information further provides powerful guidance for the strategy optimization of the intelligent agent. Finally, a new circuit netlist is generated based on the parameter strategy output by the intelligent agent, and then the pre-simulation performance is verified. The layout is generated by the analog circuit layout generator, and the post-simulation performance is verified. The two verification results are fed back to the reinforcement learning model to form a closed loop of continuous optimization. In this cycle, the model is continuously adjusted and improved until the final parameter combination that fully meets the performance requirements is obtained. At this point, the optimized circuit parameters, corresponding netlist files, and layout files can be output. These achievements will provide a solid foundation for subsequent circuit design and manufacturing, ensuring the high quality and efficiency of the entire design and manufacturing process.

[0077] In order to implement the optimization method of the above method embodiment, the present invention also provides an analog IC netlist layout collaborative optimization system based on a reinforcement learning algorithm, comprising:

[0078] An open source schematic editor for generating and exporting netlists of analog ICs based on the selected IC type.

[0079] An analog IC circuit layout generator is used to generate an analog IC circuit layout according to an analog IC netlist;

[0080] The analog IC netlist multi-edge heterogeneous graph generator is used to define different types of nodes of the heterogeneous graph according to the analog IC netlist, and extract corresponding node features according to different node types, generate nodes, node feature matrix and edge type matrix of the analog IC netlist heterogeneous graph, and finally generate the analog IC netlist multi-edge heterogeneous graph based on signal flow recognition;

[0081] The simulator is used to pre-build a simulation platform and perform simulation verification, specifically to simulate and verify the netlist of the analog IC, generate netlist simulation results, and to simulate and verify the circuit layout of the analog IC, generate layout simulation results; and the simulator inputs the simulation results into the optimization module;

[0082] The optimization module is used to pre-build a reinforcement learning agent, whose reward function is associated with the performance indicators of the analog IC; the reinforcement learning agent builds a graph neural network to perform optimization tasks based on the acquired netlist simulation results and layout simulation results, and generates optimized analog IC parameters and corresponding netlist files based on the pre-built analog IC netlist multilateral heterogeneous graph; the reinforcement learning agent and the simulation platform continuously interact and optimize until the final parameter combination that meets the performance indicators is obtained, and outputs the optimized circuit parameters and corresponding netlist files for subsequent design and manufacturing.

[0083] Furthermore, the analog IC circuit layout generator generates the analog IC circuit layout based on a heuristic algorithm. The heuristic algorithm includes a simulated annealing layout algorithm and an A* routing algorithm. In the layout stage, layout optimization is performed through the simulated annealing algorithm and the layout tree. In the routing stage, path search is performed based on the A* algorithm. By gradually exploring the path and selecting the path with the lowest cost, a connection plan between devices is finally generated.

[0084] Each module or structure is mainly used to implement each step of the method embodiment, and will not be described in detail here.

[0085] The present application also provides a computer-readable storage medium, such as a flash memory, a hard disk, a multimedia card, a card-type memory (e.g., SD or DX memory, etc.), a random access memory (RAM), a static random access memory (SRAM), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), a programmable read-only memory (PROM), a magnetic memory, a disk, an optical disk, a server, an App application store, etc., on which a computer program is stored, and the program realizes corresponding functions when executed by a processor. The computer-readable storage medium of this embodiment realizes the method embodiment of the method embodiment based on the reinforcement learning algorithm for the simulation IC netlist layout collaborative optimization method when executed by the processor.

[0086] In summary, the present invention proposes an analog IC size optimization method based on the SAC (Soft Actor-Critic) algorithm, which realizes the automated optimization of device size selection in analog IC design through a reinforcement learning algorithm, and performs collaborative optimization in combination with the layout generation process. This method can significantly improve the optimization efficiency, reduce the time and energy consumption of traditional manual adjustment, and adaptively adjust in multiple iterations to find the optimal size configuration and improve design efficiency. In this process, the algorithm not only takes into account circuit performance indicators (such as bandwidth, gain, CMRR, phase margin, etc.), but also realizes the close coordination of netlist and layout design, ensuring the consistency of size optimization and layout layout, thereby avoiding the negative impact of size adjustment on layout layout.

[0087] Through the SAC algorithm of reinforcement learning, each optimization in the design process is not only based on the feedback of circuit performance, but also combined with the generation of layout and circuit performance, and the optimization results are fed back in real time. This strategy of coordinated optimization of netlist and layout enables the size optimization of the circuit and the layout layout to be adjusted synchronously, ensuring that the optimized circuit meets the performance requirements while the layout layout can be generated smoothly, avoiding the layout conflicts or mismatches caused by size adjustment in the traditional design process.

[0088] This method avoids subjective bias and errors in manual design, ensures the consistency and accuracy of the optimization process, and has strong generalization ability, which can adapt to the design requirements of different circuits. By combining size optimization with layout generation, the present invention provides an efficient and intelligent optimization solution for analog IC design, significantly shortens the design cycle, improves the design quality, and has broad application prospects.

[0089] It should be pointed out that, according to the needs of implementation, the various steps / components described in this application can be split into more steps / components, and two or more steps / components or partial operations of steps / components can be combined into new steps / components to achieve the purpose of the present invention.

[0090] The order of execution of each step in the above embodiment does not mean the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application.

[0091] It should be understood that those skilled in the art can make improvements or changes based on the above description, and all these improvements and changes should fall within the scope of protection of the appended claims of the present invention.

Claims

1. A method for collaborative optimization of analog IC netlist layout based on reinforcement learning algorithm, characterized in that: The following steps are involved: Select a specified type of IC circuit and use an open source circuit schematic editor to generate and export the initial netlist of the analog IC; Inputting the initial netlist of the analog IC into a pre-built simulation platform, and inputting the netlist simulation results into a pre-built reinforcement learning agent whose reward function is associated with the performance indicators of the analog IC; Generate an analog IC circuit layout based on the initial netlist of the analog IC, simulate it through the simulation platform, and input the layout simulation results into the reinforcement learning agent; The reinforcement learning agent builds a graph neural network to perform optimization tasks based on the pre-built analog IC netlist multi-sided heterogeneous graph, generates an optimized analog IC netlist and sends it to the simulation platform; the construction process of the analog IC netlist multi-sided heterogeneous graph is as follows: define different types of nodes of the heterogeneous graph according to the initial netlist of the analog IC, extract corresponding node features according to different node types, generate nodes of the analog IC netlist heterogeneous graph, node feature matrix and edge type matrix, and finally generate the analog IC netlist multi-sided heterogeneous graph based on signal flow recognition; A new analog IC circuit layout is generated according to the optimized analog IC netlist. The simulation platform simulates both the optimized analog IC netlist and the new analog IC circuit layout, and outputs the generated new simulation results to the reinforcement learning agent to further optimize the analog IC circuit layout. The reinforcement learning agent and the simulation platform continuously interact and optimize until the final parameter combination that meets the performance indicators is obtained, and the optimized circuit parameters and corresponding netlist files are output for subsequent design and manufacturing.

2. The method for collaborative optimization of analog IC netlist layout based on reinforcement learning algorithm according to claim 1, characterized in that: The optimization goal is determined based on the performance indicators, and combined with the constraints, the two are converted into corresponding parameters and associated with the reward function of the reinforcement learning agent; among them, the performance indicators include gain, bandwidth, phase margin and common mode rejection ratio, and the constraints include specific power consumption, area and size.

3. The method for collaborative optimization of analog IC netlist layout based on reinforcement learning algorithm according to claim 1, characterized in that: When building a simulation platform, the simulation environment settings are also performed, including simulation mode, simulation temperature, simulation parameters, and simulation output item units.

4. The method for collaborative optimization of analog IC netlist layout based on reinforcement learning algorithm according to claim 1, characterized in that: The analog IC circuit layout is generated based on heuristic algorithms, including simulated annealing layout algorithm and A* routing algorithm. In the layout stage, layout optimization is performed through simulated annealing algorithm and layout tree. In the routing stage, path search is performed based on A* algorithm, and the connection scheme between devices is finally generated by gradually exploring the path and selecting the path with the lowest cost.

5. The method for collaborative optimization of analog IC netlist layout based on reinforcement learning algorithm according to claim 1, characterized in that: The A* routing algorithm also dynamically adjusts the strategy based on the complexity of the routing to avoid path crossing and blocking, and optimize the signal transmission quality and layout density of the entire layout.

6. The method for collaborative optimization of analog IC netlist layout based on reinforcement learning algorithm according to claim 1, characterized in that: The reinforcement learning agent interacts repeatedly with the simulation platform, uses the Actor network to output the circuit parameter policy distribution, uses the Critic network to evaluate the policy quality, and combines random exploration and goal-oriented optimization strategies to continuously adjust the network weights and gradually converge to the optimal parameters.

7. The method for collaborative optimization of analog IC netlist layout based on reinforcement learning algorithm according to claim 1, characterized in that: The node types of the heterogeneous graph include m-nodes representing MOSFET transistors, c-nodes representing capacitors, and v-nodes representing voltages. Different parameters are extracted from different types of nodes as node features.

8. The method for collaborative optimization of analog IC netlist layout based on reinforcement learning algorithm according to any one of claims 1 to 7, characterized in that: Specifically optimize the transistor size in the analog IC circuit layout.

9. An analog IC netlist layout collaborative optimization system based on reinforcement learning algorithm, characterized in that: include: An open source schematic editor for generating and exporting netlists of analog ICs based on the specified type of IC circuit selected; An analog IC circuit layout generator is used to generate an analog IC circuit layout according to an analog IC netlist; The analog IC netlist multi-edge heterogeneous graph generator is used to define different types of nodes of the heterogeneous graph according to the analog IC netlist, and extract corresponding node features according to different node types, generate nodes, node feature matrix and edge type matrix of the analog IC netlist heterogeneous graph, and finally generate the analog IC netlist multi-edge heterogeneous graph based on signal flow recognition; The simulator is used to pre-build a simulation platform and perform simulation verification, specifically to simulate and verify the netlist of the analog IC, generate netlist simulation results, and to simulate and verify the circuit layout of the analog IC, generate layout simulation results; and the simulator inputs the simulation results into the optimization module; An optimization module for pre-building a reinforcement learning agent whose reward function is associated with the performance metric of the analog IC; According to the obtained netlist simulation results and layout simulation results, the reinforcement learning agent builds a graph neural network to perform optimization tasks based on the pre-built analog IC netlist multilateral heterogeneous graph, and generates optimized analog IC parameters and corresponding netlist files; The reinforcement learning agent and the simulation platform continuously interact and optimize until the final parameter combination that meets the performance indicators is obtained, and the optimized circuit parameters and corresponding netlist files are output for subsequent design and manufacturing.

10. The analog IC netlist layout collaborative optimization system based on reinforcement learning algorithm according to claim 9, characterized in that: The analog IC circuit layout generator generates analog IC circuit layouts based on heuristic algorithms. The heuristic algorithms include simulated annealing layout algorithm and A* routing algorithm. In the layout stage, layout optimization is performed through simulated annealing algorithm and layout tree. In the routing stage, path search is performed based on A* algorithm. By gradually exploring the path and selecting the path with the lowest cost, the connection plan between devices is finally generated.

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