Ion trap chip and quantum calculation and quantum simulation device

Abstract

The invention discloses an ion trap chip and a quantum calculation and quantum simulation device, the ion trap chip is connected with more than two linear surface electrode units through a connecting structure, ions trapped above the connecting structure and ions trapped above the linear surface electrode units share a phonon mode for quantum information transmission, and the quantum calculation and the quantum simulation device are integrated. The plurality of linear surface electrode units are connected through the connecting structures, so that the expansion of the ion trap chip is realized, the width of ion lattices trapped by a single linear surface electrode unit is reduced, the stability of the ion lattices is improved, the length of the ion lattices is extended, the scale of the ion lattices trapped by the ion trap chip is improved, and the service life of the ion trap chip is prolonged. And technical support is provided for realizing large-scale quantum calculation and quantum simulation.

Description

Technical Field

[0001] The present application relates to but is not limited to quantum computing and quantum simulation technology, and particularly to an ion trap chip and a quantum computing and quantum simulation device. Background Art

[0002] A quantum computer is a device that uses quantum logic to perform general computations. The basic logic unit of a quantum computer is composed of quantum bits that obey the principles of quantum mechanics. A large number of interacting quantum bits can physically realize a quantum computer. A quantum simulator is a device that uses quantum effects to simulate physical models. A quantum simulator can directly simulate a quantum system using a number of particles similar to that of the original system. Compared with traditional computers, quantum computers and quantum simulators can significantly reduce the computing time when solving certain problems. They have broad application prospects in future basic scientific research, quantum communications and cryptography, artificial intelligence, financial market simulation, and climate change prediction, and therefore have received widespread attention. Using an array of ion quantum bits trapped in a potential well, various high-fidelity quantum logic gate operations can be realized under existing experimental conditions; ion quantum bits have excellent performance in key indicators of quantum computing and quantum simulation performance, such as interaction control, long coherence time, high-fidelity quantum logic gate operations, and quantum error correction, and are one of the most likely platforms for realizing quantum computing and quantum simulation. Trapped ion systems can be divided into Paul wells and Penning wells according to the principle of the well. Among them, the Penning trap uses a strong uniform magnetic field in the axial direction to confine ions in the radial direction, and a quadrupole electric field to confine ions in the axial direction; however, the trapped ions rotate at high speed in space, and it is difficult to perform precise laser manipulation and detection of the ions through the Penning trap. Therefore, the Paul trap with fixed ion positions is more widely used in the fields of quantum computing and quantum simulation. The Paul trap uses a radio frequency electric field to confine ions in the radial direction, and a direct current electric field to confine ions in the axial direction. The lattice distribution of the ions is determined by the determination of the radio frequency electric field and the direct current electric field. At present, the number of quantum bits in the Paul trap is mostly one hundred or dozens, which can realize medium-scale noisy quantum computing or quantum simulation. In order to demonstrate true quantum advantage, the number of operable trapped ions must be greatly increased.

[0003] In summary, how to increase the scale of the ion lattice trapped in the ion trap chip has become a problem to be solved. Summary of the invention

[0004] The following is a summary of the subject matter described in detail in this application. This summary is not intended to limit the scope of the claims.

[0005] The disclosed embodiments provide an ion trap chip and a quantum computing and quantum simulation device, which can increase the scale of trapped ion lattices.

[0006] The embodiment of the present disclosure provides an ion trap chip, comprising: more than two linear surface electrode units and more than one connection structure, wherein the connection structure is used to connect adjacent linear surface electrode units; wherein:

[0007] Each linear surface electrode unit is composed of two or more radio frequency electrodes and non-radio frequency electrode areas distributed on both sides of the radio frequency electrodes. The linear surface electrode unit is used to trap ions above the plane of the linear surface electrode unit itself, and the non-radio frequency electrode area includes one or more direct current electrodes.

[0008] The connection structure is composed of more than two RF electrodes and non-RF electrode areas distributed on both sides of the RF electrodes. The number and arrangement distribution of the RF electrodes and non-RF electrode areas are the same as those of the linear surface electrode unit, wherein the RF electrodes of the connection structure with the same arrangement distribution are connected to the RF electrodes of the linear surface electrode unit, and the non-RF electrode areas of the connection structure and the non-RF electrode areas of the linear surface electrode unit located on both sides of the RF electrodes are arranged on both sides of the RF electrodes of the connection structure in the same arrangement distribution. The connection structure has the ability to trap ions, and the ions trapped above the plane of the connection structure and the ions trapped above the plane of the linear surface electrode unit form a complete ion lattice and share phonon modes for quantum information transmission.

[0009] In an exemplary embodiment, the non-RF electrode area further includes one or more ground electrodes.

[0010] In an exemplary embodiment, the number of the connection structure connecting adjacent linear surface electrode units is one.

[0011] In an exemplary embodiment, the linear surface electrode unit and the axis of the connection structure are both provided with grooves penetrating the substrate for passing light.

[0012] In an exemplary embodiment, the connection structure is a semicircular ring structure.

[0013] In an exemplary embodiment, the two or more linear surface electrode units are arranged in the same direction.

[0014] In an exemplary embodiment, when the two or more linear surface electrode units are arranged in the same direction, the DC electrodes in the non-RF electrode areas outside the surface electrode units are shared by the parts of the two or more adjacent linear surface electrode units close to each other.

[0015] In an exemplary embodiment, the connecting structure is a quarter-circular ring structure.

[0016] In an exemplary embodiment, the width of the groove is equal to a preset value times the width of the lattice that traps the ions.

[0017] In an exemplary embodiment, the width of the groove is greater than or equal to 10 micrometers.

[0018] In an exemplary embodiment, when adjacent linear surface electrode units are connected via a semicircular ring connection structure, the distance between the center lines of two adjacent linear surface electrode units is greater than or equal to 50 micrometers.

[0019] On the other hand, the embodiments of the present disclosure also provide a quantum computing and quantum simulation device, including the above-mentioned ion trap chip.

[0020] The ion trap chip of the disclosed embodiment connects two or more linear surface electrode units through a connecting structure. The ions trapped above the connecting structure share phonon modes with the ions trapped above the linear surface electrode units for quantum information transmission. The ion trap chip is expanded by connecting multiple linear surface electrode units through the connecting structure, which reduces the width of the ion lattice trapped by a single linear surface electrode unit, increases the stability of the ion lattice, and extends the length of the ion lattice, thereby increasing the scale of the ion lattice trapped by the ion trap chip, providing technical support for large-scale quantum computing and quantum simulation.

[0021] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0023] Figure 1 is a schematic diagram of a one-dimensional ion chain in the related art;

[0024] Figure 2 is a schematic diagram of a two-dimensional ionic lattice in the related art;

[0025] Figure 3 is a structural block diagram of the ion trap chip according to an embodiment of the present disclosure;

[0026] Figure 4 A schematic diagram of a linear surface electrode chip well in the related art;

[0027] Figure 5 A schematic diagram of another linear surface electrode chip well in the related art;

[0028] Figure 6 It is a schematic diagram of the structure of the ion trap chip according to an embodiment of the present disclosure;

[0029] Figure 7 It is a cross-sectional view of the ion trap chip according to the embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] The present application describes multiple embodiments, but the description is exemplary rather than restrictive, and it is obvious to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present application. Although many possible feature combinations are shown in the drawings and discussed in the specific embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0031] The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in the present application may also be combined with any conventional features or elements to form a unique invention scheme defined by the claims. Any features or elements of any embodiment may also be combined with features or elements from other invention schemes to form another unique invention scheme defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in the present application may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the attached claims and their equivalents, the embodiments are not subject to other restrictions. In addition, various modifications and changes may be made within the scope of protection of the attached claims.

[0032] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps of the specific order described. As will be understood by those of ordinary skill in the art, other sequences of steps are also possible. Therefore, the specific sequence of the steps set forth in the specification should not be interpreted as a limitation to the claims. In addition, the claims for the method and / or process should not be limited to the steps of performing them in the order written, and those skilled in the art can easily understand that these sequences can be changed and still remain within the spirit and scope of the embodiments of the present application.

[0033] The main purpose of ion trap chip design is to increase the number of operable trapped ions; the main configurations of ion lattices trapped by ion trap chips are as follows: Figure 1 The one-dimensional single-row ion chain and Figure 2The two-dimensional planar ion lattice shown in the figure, both ion lattices are stably trapped in space by direct current electric field and radio frequency electric field. Under normal temperature system, the number of stable trapped one-dimensional or two-dimensional ions is generally in the dozens, mainly limited by background gas collision; under 4 Kelvin (K) low temperature system, the number of one-dimensional ion chain ions can reach 100-200, and the axial trap frequency limits the further increase of the number of ions. The two-dimensional ion lattice increases the number of trapped ions by arranging multiple rows of ions in the width direction, and can usually reach a scale of about 1000 ions. Because the edge ions have large micro-motions, the fidelity of coherent operations will be reduced, and the large-scale two-dimensional ion lattice has poor configuration stability, which limits the expansion of the scale of the two-dimensional ion lattice to increase the number of quantum bits.

[0034] Figure 3 is a structural block diagram of the ion trap chip according to an embodiment of the present disclosure, such as Figure 3 As shown, it includes: more than two linear surface electrode units and more than one connection structure (the figure shows three linear surface electrode units, namely linear surface electrode unit 1, linear surface electrode unit 2 and linear surface electrode unit 3, and adjacent linear surface electrode units are connected by a connection structure), and the connection structure is used to connect adjacent linear surface electrode units; wherein,

[0035] Each linear surface electrode unit is composed of two or more radio frequency electrodes and non-radio frequency electrode areas distributed on both sides of the radio frequency electrodes. The linear surface electrode unit is used to trap ions above the plane of the linear surface electrode unit itself, and the non-radio frequency electrode area includes one or more DC electrodes. Here, the design of the radio frequency electrode and the non-radio frequency electrode area in the linear surface electrode unit can be designed and implemented with reference to the size and distribution of the radio frequency electrode and the non-radio frequency electrode area in the linear surface electrode chip trap in the related art.

[0036] The connection structure is composed of two or more RF electrodes and non-RF electrode areas distributed on both sides of the RF electrodes (the non-RF electrode areas are composed of one or more DC electrodes located in the same area in the connection structure in the figure). The number and arrangement distribution of the RF electrodes and non-RF electrode areas are the same as those of the linear surface electrode unit, wherein the RF electrodes of the connection structure with the same arrangement distribution are connected to the RF electrodes of the linear surface electrode unit, and the non-RF electrode areas of the connection structure and the non-RF electrode areas of the linear surface electrode unit located on both sides of the RF electrodes are arranged on both sides of the RF electrodes of the connection structure with the same arrangement distribution. The connection structure has the ability to trap ions (the voltage of the DC electrodes of the connection structure can be set by numerical simulation methods such as boundary elements or finite elements, so that the connection structure has the ability to trap ions), and the ions trapped above the plane of the connection structure and the ions trapped above the plane of the linear surface electrode unit form a complete ion lattice, sharing phonon modes, which are used for quantum information transmission;

[0037] The disclosed embodiment combines linear surface electrode units by setting a connection structure. The ions trapped by the linear surface electrode units and the connection structure form a complete ion lattice and share phonon modes for transmitting quantum information, thereby achieving the expansion of the ion trap chip, reducing the width of the ion lattice trapped by a single linear surface electrode unit, increasing the stability of the ion lattice, and extending the length of the ion lattice. This increases the scale of the ion lattice trapped by the ion trap chip, and provides technical support for realizing large-scale quantum computing and quantum simulation.

[0038] The connection structure of the embodiment of the present disclosure only needs to meet the following conditions: the trapped ions and the ions trapped by the linear surface electrode units form a complete ion lattice, share phonon modes, and transmit quantum information; it should be noted that whether the above conditions are met can be determined through numerical simulation when designing the connection structure.

[0039] In an exemplary embodiment, the non-RF electrode area of ​​the embodiment of the present disclosure further includes one or more ground electrodes.

[0040] The composition and distribution design of the non-RF electrode area in the embodiment of the present disclosure can be implemented with reference to related technologies.

[0041] It should be noted that although the terms "RF electrode" and "non-RF electrode" are used in the embodiments of the present disclosure, according to the common knowledge of those skilled in the art, RF electrodes can be applied with either RF signals or DC voltage signals, or both can be applied simultaneously; non-RF electrodes can be applied with either RF signals or DC voltage signals, or both can be applied simultaneously; the electrical signals applied to the above-mentioned electrodes in the embodiments of the present disclosure should not be regarded as limitations on the embodiments of the present disclosure. During implementation, those skilled in the art can determine the characteristics of the electrical signals applied to each electrode through numerical simulation and other means to achieve stable confinement of the ion lattice.

[0042] In an exemplary embodiment, the number of connection structures connecting adjacent linear surface electrode units in the embodiment of the present disclosure is one.

[0043] The number of connecting structures of adjacent linear surface electrode units in the embodiment of the present disclosure is one, so adjacent linear surface electrode units will not have a structure in which the two ends of adjacent linear surface electrode units are connected by two connecting structures to form a closed loop. There is only one connecting structure connecting adjacent linear surface electrode units, which provides design support for the expansion of the ion trap chip.

[0044] In an exemplary embodiment, the linear surface electrode unit and the axis of the connection structure of the embodiment of the present disclosure are both provided with grooves (not shown in the figure) penetrating the substrate and used for light to pass through.

[0045] The ion lattice can be trapped even when grooves are not provided in the ion trap chip of the embodiment of the present disclosure. The ion trap with grooves can be incident and irradiated on the ions by the laser perpendicular to the plane of the ion trap chip or at a certain tilt angle. Each linear surface electrode unit of the embodiment of the present disclosure is composed of two or more RF electrodes and non-RF electrode areas distributed on both sides of the RF electrodes, and the connection structure is composed of two or more RF electrodes and non-RF electrode areas distributed on both sides of the RF electrodes; assuming that the two or more RF electrodes of the linear surface electrode unit are the first RF electrode and the second RF electrode, and the two or more RF electrodes of the connection structure are the third RF electrode and the fourth RF electrode, and taking the geometric center of the linear surface electrode unit as the axis, the first RF electrode and the third RF electrode are located on the same side, and the second RF electrode and the fourth RF electrode are located on the same side. In the embodiment of the present disclosure, the first RF electrode and the third RF electrode are connected, and the second RF electrode and the fourth RF electrode are connected. Assuming that the first The first side includes the first non-RF electrode area, the second side includes the second non-RF electrode area, the first side of the second RF electrode includes the third non-RF electrode area, the second side includes the fourth non-RF electrode area, the first side of the third RF electrode includes the fifth non-RF electrode area, the second side includes the sixth non-RF electrode area, the first side of the fourth RF electrode includes the seventh non-RF electrode area, and the second side includes the eighth non-RF electrode area. The first side and the second side are relative positions determined with reference to the same coordinates. The first non-RF electrode area and the fifth non-RF electrode area are arranged in sequence on the same side, the second non-RF electrode area and the sixth non-RF electrode area are arranged in sequence on the same side, the third non-RF electrode area and the seventh non-RF electrode area are arranged in sequence on the same side, and the fourth non-RF electrode area and the eighth non-RF electrode area are arranged in sequence on the same side.

[0046] The above-mentioned ionic lattice in the embodiment of the present disclosure can theoretically be a two-dimensional ionic lattice or a three-dimensional ionic lattice. Due to the influence of the preparation process or other actual parameters, the two-dimensional ionic lattice may show a three-dimensional structure due to deviation.

[0047] When the ion trap chip of the embodiment of the present disclosure includes multiple linear surface electrode units, the linear surface electrode units are connected by a periodic connection structure. In other words, after the composition and structure of the linear surface electrode units and the connection structure are determined, the adjacent linear surface electrode units are periodically connected by the connection structure according to the distribution setting of the ion trap chip.

[0048] In an exemplary embodiment, the linear surface electrode unit of the embodiment of the present disclosure can be implemented by referring to the linear surface electrode chip well design in the related art. Figure 4 and Figure 5 Schematic diagram of a linear surface electrode chip well in the related art, such as Figure 4 and Figure 5As shown, two "six-wire" ion trap chip electrode combinations in the related art are distributed on both sides of the chip in the order of non-RF electrode area, RF electrode, and non-RF electrode area; the size and number of RF electrode and non-RF electrode areas are designed and adjusted by those skilled in the art; in the embodiment of the present disclosure, when the size of the RF electrode and the non-RF electrode area is adjusted, the non-RF electrode area can also be asymmetrically distributed, and similarly, the RF electrode can also be asymmetrically distributed. In the embodiment of the present disclosure, depending on the operation of trapping ions, the inner non-RF electrode area can be Figure 4 The segmented electrode area shown includes multiple DC electrodes, or the outer non-RF electrode area can be Figure 5 The segmented electrode area shown includes multiple DC electrodes; in the linear surface electrode ion trap chip, the non-RF electrode area electrode has the functions of providing axial restraint, rotating the main axis, and compensating for ion micro-motion; it should be noted that the non-RF electrode area electrode and the RF electrode shown in the figure are simplified as rectangles. In actual applications, the size of the non-RF electrode area electrode and / or the RF electrode can be changed as needed to make the structure asymmetric, and the electrode shape can be changed to meet specific task requirements. For example, the RF electrode or the non-RF electrode area electrode can include an arc or broken line structure; other electrodes such as ground electrodes can also be added vertically, but the core goal of the ion trap chip is to use semiconductor or micro-electromechanical system technology or other processing methods to prepare electrodes on a substrate so that the ions are trapped in a space at a certain height above the chip.

[0049] In an exemplary embodiment, the difference between the ion height above the plane of the connection structure of the embodiment of the present disclosure and the ion height above the plane of the linear surface electrode unit should be as small as possible.

[0050] In an exemplary embodiment, the groove of the disclosed embodiment is located directly below the ion chain (the ion chain formed by trapped ions), that is, in the middle of the innermost non-RF electrode area; the width of the groove of the disclosed embodiment is equal to the width of the trapped ion lattice of a preset value to ensure that the light beam passes with as little scattering as possible. In one embodiment, the disclosed embodiment ensures that the laser can address the ions by setting the width of the groove equal to the width of the trapped ion lattice of a preset value. In one embodiment, the width of the groove at the connection structure of the disclosed embodiment can be set according to the needs of the ions to perform addressing operations, and may be a non-constant value (a variable value).

[0051] In an exemplary embodiment, the two or more linear surface electrode units of the embodiment of the present disclosure are arranged in the same direction. Here, when the reference direction is determined to be the horizontal direction, the two or more linear surface electrode units are arranged in the vertical direction.

[0052] In an exemplary embodiment, when two or more linear surface electrode units of the embodiment of the present disclosure are arranged in the same direction, the connection structure is a semicircular ring.

[0053] When the linear surface electrode units of the disclosed embodiment are arranged in the same direction, adjacent linear surface electrode units are connected by a semicircular connection structure. The disclosed embodiment arranges the linear surface electrode units periodically in a longitudinal direction, and after connecting them by a semicircular structure connection, two adjacent linear surface electrode units are connected end to end, and two linear surface electrode units arranged in sequence are connected by two semicircular connection structures to form a U-shaped structure, and three linear surface electrode units arranged in sequence are connected by two semicircular connection structures to form an S-shaped structure; the number of linear surface electrode units in the ion trap chip is greater than three, and they are all connected by a semicircular connection structure to form a serpentine structure; here, serpentine usually refers to a curved shape, similar to the curved body of a snake, and can also be considered as a wavy shape.

[0054] In an exemplary embodiment, when two or more linear surface electrode units of the embodiment of the present disclosure are arranged in the same direction, each linear surface electrode unit includes a complete radio frequency electrode and a non-radio frequency electrode area.

[0055] In an exemplary embodiment, when two or more linear surface electrode units of the embodiment of the present disclosure are arranged in the same direction, the DC electrodes in the non-RF electrode area outside the linear surface electrode units of the adjacent two or more linear surface electrode units close to each other are shared. The embodiment of the present disclosure can save chip size and simplify chip leads by sharing the DC electrodes in the non-RF electrode area.

[0056] In an exemplary embodiment, adjacent linear surface electrode units of the embodiment of the present disclosure are connected by a quarter-circle ring connection structure. Figure 6 FIG. 1 is a schematic diagram of the structure of another ion trap chip according to an embodiment of the present disclosure. Figure 6 As shown, when a quarter-circle connection structure is used to connect the linear surface electrode units, two adjacent linear surface electrode units are connected end to end, and the formed ion trap chip has a structure shaped like a "bow" (or similar to a rectangular pulse).

[0057] In an exemplary embodiment, the connection structure of the embodiment of the present disclosure only needs to meet the following requirements: the ions trapped by the connection structure and the ions trapped by the linear surface electrode units form a complete ion lattice, share phonon modes, and transmit quantum information; the above-mentioned semicircular ring and quarter-circular ring are only embodiments for illustrative purposes, and it can be approximately considered that the linear surface electrode unit is bent into a connection structure according to an arc, which can be a structure similar to a semicircular ring or a quarter-circular ring. When the connection structures of other structures meet the above requirements, they can all be used to implement the ion trap chip of the embodiment of the present disclosure.

[0058] In an exemplary embodiment, the embodiment of the present disclosure determines the shapes of the DC electrode and the RF electrode and the applied potential by simulation according to the ion type, and the simulation method may include boundary element or finite element in the relevant technology. In practical applications, the embodiment of the present disclosure can make the ion center be arranged along the center of the groove (with the deviation as small as possible) and located about tens to hundreds of microns above the surface of the ion trap chip by adjusting the shapes of the DC electrode and the RF electrode and the applied potential combination.

[0059] In an exemplary embodiment, the embodiment of the present disclosure increases the number of trapped ions per unit area of ​​the ion trap chip by setting a groove for passing light, and trapping n rows of ions (n≥1) directly above the groove. The simplified schematic diagram is as follows: Figure 7 As shown, Figure 4 and Figure 5 Similarly, the electrode layout in the accompanying drawings is only a simplified example, indicating that by designing the linear surface electrode unit and the connection structure, multiple rows of ions can form a super-large two-dimensional lattice similar to a snake. The actual electrode layout, shape, size, etc. must be specifically designed according to the needs of the trapped ion lattice; the ion trap chip of the embodiment of the present disclosure deforms the electrodes of the surface electrode ion trap in the related art so that the ions form the required two-dimensional configuration above the chip; wherein, the width of the RF electrode and the DC (or grounding) electrode in the embodiment of the present disclosure (the width of the RF electrode perpendicular to the ion chain, the width of the DC (or grounding) electrode perpendicular to or along the ion chain) is generally greater than or equal to 5 microns, the gap between two adjacent electrodes (adjacent RF electrodes and DC (or grounding) electrodes, adjacent DC (or grounding) electrodes and DC (or grounding) electrodes) is generally greater than or equal to 2 microns, and the groove width is generally greater than or equal to 10 microns; Figure 7 Only simplified shapes of the non-RF electrode area electrodes and RF electrodes are given. In practical applications, the number, size and shape of the electrodes should be adjusted as needed to form a potential field that meets the needs. The grooves can stably trap n rows of ions (n>=1), and the group spacing of each n row of ions is generally greater than or equal to 50 microns, thereby forming an ultra-large-scale ion lattice.

[0060] In an exemplary embodiment, the n rows of ions in the ion trap chip in the embodiment of the present disclosure are designed with a spacing of d microns between ions with reference to related technologies, d≥2, allowing the laser to perform independent addressing operations on the ions, and the spacing between ions can be adjusted by electric potential.

[0061] In an exemplary embodiment, the linear surface electrode units of the embodiment of the present disclosure are arranged longitudinally, and when adjacent linear surface electrode units are connected by a semicircular connection structure, considering factors such as the well frequency and the size of the RF electrode, the spacing between the center lines of two adjacent linear surface electrode units is generally greater than or equal to 50 microns (which can also be considered as the geometric center distance between adjacent linear surface electrode units).

[0062] In an exemplary embodiment, if the area of ​​the ion trap chip of the present disclosure is 10 mm*10 mm, then one chip can in principle trap up to 10 5 ~10 6 Ion quantum bits of the order of magnitude.

[0063] In an exemplary embodiment, the embodiment of the present disclosure can refer to the surface electrode chip trap in the related art to prepare the above-mentioned ion trap chip, and the ion trap chip mainly involves a substrate, an electrode, an interlayer dielectric, vias and leads for wiring electrodes in different metal layers, and grooves for passing light, etc.; Figure 7 is a cross-sectional view of the ion trap chip according to an embodiment of the present disclosure, Figure 7 As shown, Figure 7 It is only a brief schematic diagram of the multi-layer structure, and does not draw all the actual electrodes and wiring designs; the ion trap chip of the embodiment of the present disclosure can use silicon wafers, quartz, ceramics, sapphire and other materials as the substrate, the electrodes are made of metal materials such as aluminum (or its alloys), titanium, platinum, gold, etc., silicon oxide, silicon nitride or other insulating materials are used as interlayer dielectrics, dark gray represents electrodes or interlayer leads made of metal materials, light blue represents interlayer dielectrics used to prevent short circuits between different metal layers, where different metal layers are connected by filling metal in vias (Via), and the leads of multi-layer DC electrodes and RF electrodes are made by designing a multi-layer structure of alternating metal materials / interlayer dielectrics, thereby increasing the number of controlled DC electrodes, and at the same time, different DC electrodes can be connected to the same external signal to reduce the number of DC control signals; the substrate / base chip in the embodiment of the present disclosure needs to be manufactured with a groove that is the widest at the bottom and becomes narrower as it goes up, which can be a stepped groove to allow the laser shown in the figure to pass through the chip vertically or at a certain small angle and focus on the ions.

[0064] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those of ordinary skill in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

Claims

1. An ion trap chip, characterized in that: include: Two or more linear surface electrode units and one or more connecting structures, the connecting structures are used to connect adjacent linear surface electrode units; wherein, Each linear surface electrode unit is composed of two or more radio frequency electrodes and non-radio frequency electrode areas distributed on both sides of the radio frequency electrodes. The linear surface electrode unit is used to trap ions above the plane of the linear surface electrode unit itself, and the non-radio frequency electrode area includes one or more direct current electrodes. The connection structure is composed of more than two RF electrodes and non-RF electrode areas distributed on both sides of the RF electrodes. The number and arrangement distribution of the RF electrodes and non-RF electrode areas are the same as those of the linear surface electrode unit, wherein the RF electrodes of the connection structure with the same arrangement distribution are connected to the RF electrodes of the linear surface electrode unit, and the non-RF electrode areas of the connection structure and the non-RF electrode areas of the linear surface electrode unit located on both sides of the RF electrodes are arranged on both sides of the RF electrodes of the connection structure in the same arrangement distribution. The connection structure has the ability to trap ions, and the ions trapped above the plane of the connection structure and the ions trapped above the plane of the linear surface electrode unit form a complete ion lattice and share phonon modes for quantum information transmission.

2. The ion trap chip according to claim 1, characterized in that: The non-RF electrode area also includes one or more ground electrodes.

3. The ion trap chip according to claim 1, characterized in that: The number of the connection structure connecting adjacent linear surface electrode units is one.

4. The ion trap chip according to claim 1, characterized in that: The linear surface electrode unit and the axis of the connection structure are both provided with grooves penetrating the substrate and used for letting light pass.

5. The ion trap chip according to any one of claims 1 to 4, characterized in that: The connection structure is a semicircular ring structure.

6. The ion trap chip according to claim 5, characterized in that: The two or more linear surface electrode units are arranged in the same direction.

7. The ion trap chip according to claim 6, characterized in that: When the two or more linear surface electrode units are arranged in the same direction, the DC electrodes in the non-RF electrode areas outside the linear surface electrode units are shared by the parts of the two or more adjacent linear surface electrode units close to each other.

8. The ion trap chip according to any one of claims 1 to 4, characterized in that: The connecting structure is a quarter-circular ring structure.

9. The ion trap chip according to claim 4, characterized in that: The width of the groove is equal to a preset value times the width of the ion trapping lattice.

10. The ion trap chip according to claim 9, characterized in that: The width of the groove is greater than or equal to 10 micrometers.

11. The ion trap chip according to claim 6, characterized in that: When adjacent linear surface electrode units are connected via a semicircular connection structure, the distance between the center lines of two adjacent linear surface electrode units is greater than or equal to 50 micrometers.

12. A quantum computing and quantum simulation device, characterized in that: Comprising the ion trap chip according to any one of claims 1 to 11.

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